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path: root/common/recipes-kernel/linux/files/0790-drm-amd-dal-Instantiate-Underlay-version-of-Timing-G.patch
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From d37689dccc3eddd13a101bf8739dc0491bd03533 Mon Sep 17 00:00:00 2001
From: David Rokhvarg <David.Rokhvarg@amd.com>
Date: Wed, 10 Feb 2016 15:12:56 -0500
Subject: [PATCH 0790/1110] drm/amd/dal: Instantiate Underlay version of Timing
 Generator and Scaler.

Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/dal/dc/dce110/Makefile         |  3 ++-
 .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 22 ++++++++++++++++++----
 .../amd/dal/dc/dce110/dce110_timing_generator_v.c  | 16 +---------------
 3 files changed, 21 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
index 2d0007b..71aa9d8 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
@@ -8,7 +8,8 @@ dce110_opp_formatter.o dce110_opp_regamma.o dce110_stream_encoder.o \
 dce110_timing_generator.o dce110_transform.o dce110_transform_v.o \
 dce110_transform_gamut.o dce110_transform_scl.o dce110_opp_csc.o\
 dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \
-dce110_resource.o dce110_transform_bit_depth.o dce110_clock_source.o
+dce110_resource.o dce110_transform_bit_depth.o dce110_clock_source.o \
+dce110_timing_generator_v.o
 
 AMD_DAL_DCE110 = $(addprefix $(AMDDALPATH)/dc/dce110/,$(DCE110))
 
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 4fdf1f0..42e7306 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -32,10 +32,12 @@
 #include "include/irq_service_interface.h"
 #include "../virtual/virtual_stream_encoder.h"
 #include "dce110/dce110_timing_generator.h"
+#include "dce110/dce110_timing_generator_v.h"
 #include "dce110/dce110_link_encoder.h"
 #include "dce110/dce110_mem_input.h"
 #include "dce110/dce110_ipp.h"
 #include "dce110/dce110_transform.h"
+#include "dce110/dce110_transform_v.h"
 #include "dce110/dce110_stream_encoder.h"
 #include "dce110/dce110_opp.h"
 #include "dce110/dce110_clock_source.h"
@@ -305,8 +307,14 @@ static struct timing_generator *dce110_timing_generator_create(
 	if (!tg110)
 		return NULL;
 
-	if (dce110_timing_generator_construct(tg110, as, ctx, instance, offsets))
-		return &tg110->base;
+	if (instance == 3) {
+		/* This is the Underlay instance. */
+		if (dce110_timing_generator_v_construct(tg110, as, ctx))
+			return &tg110->base;
+	} else {
+		if (dce110_timing_generator_construct(tg110, as, ctx, instance, offsets))
+			return &tg110->base;
+	}
 
 	BREAK_TO_DEBUGGER();
 	dm_free(ctx, tg110);
@@ -370,8 +378,14 @@ static struct transform *dce110_transform_create(
 	if (!transform)
 		return NULL;
 
-	if (dce110_transform_construct(transform, ctx, inst, offsets))
-		return &transform->base;
+	if (inst == 3) {
+		/* Underlay */
+		if (dce110_transform_v_construct(transform, ctx))
+			return &transform->base;
+	} else {
+		if (dce110_transform_construct(transform, ctx, inst, offsets))
+			return &transform->base;
+	}
 
 	BREAK_TO_DEBUGGER();
 	dm_free(ctx, transform);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
index 722f636..08588f7 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
@@ -36,7 +36,6 @@ static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg)
      */
 
 	uint32_t value;
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 
 	value = dm_read_reg(tg->ctx,
 			mmCRTCV_MASTER_UPDATE_MODE);
@@ -58,7 +57,6 @@ static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg)
 static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg)
 {
 	uint32_t value;
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 
 	value = dm_read_reg(tg->ctx,
 			mmCRTCV_CONTROL);
@@ -126,7 +124,6 @@ static bool dce110_timing_generator_v_blank_crtc(struct timing_generator *tg)
 
 static bool dce110_timing_generator_v_unblank_crtc(struct timing_generator *tg)
 {
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 	uint32_t addr = mmCRTCV_BLANK_CONTROL;
 	uint32_t value = dm_read_reg(tg->ctx, addr);
 
@@ -153,7 +150,6 @@ static bool dce110_timing_generator_v_is_in_vertical_blank(
 	uint32_t addr = 0;
 	uint32_t value = 0;
 	uint32_t field = 0;
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 
 	addr = mmCRTCV_STATUS;
 	value = dm_read_reg(tg->ctx, addr);
@@ -164,8 +160,6 @@ static bool dce110_timing_generator_v_is_in_vertical_blank(
 static bool dce110_timing_generator_v_is_counter_moving(struct timing_generator *tg)
 {
 	uint32_t value;
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
-
 	uint32_t h1 = 0;
 	uint32_t h2 = 0;
 	uint32_t v1 = 0;
@@ -263,7 +257,6 @@ static void dce110_timing_generator_v_program_blanking(
 	uint32_t hsync_offset = timing->h_border_right +
 			timing->h_front_porch;
 	uint32_t h_sync_start = timing->h_addressable + hsync_offset;
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 
 	struct dc_context *ctx = tg->ctx;
 	uint32_t value = 0;
@@ -339,7 +332,6 @@ static void dce110_timing_generator_v_enable_advanced_request(
 	bool enable,
 	const struct dc_crtc_timing *timing)
 {
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 	uint32_t addr = mmCRTCV_START_LINE_CONTROL;
 	uint32_t value = dm_read_reg(tg->ctx, addr);
 
@@ -402,7 +394,6 @@ static void dce110_timing_generator_v_program_blank_color(
 		enum color_space color_space)
 {
 	struct crtc_black_color black_color;
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 	uint32_t addr = mmCRTCV_BLACK_COLOR;
 	uint32_t value = dm_read_reg(tg->ctx, addr);
 
@@ -436,7 +427,7 @@ static void dce110_timing_generator_v_set_overscan_color_black(
 	struct dc_context *ctx = tg->ctx;
 	uint32_t value = 0;
 	uint32_t addr;
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
+
 	/* Overscan Color for YUV display modes:
 	 * to achieve a black color for both the explicit and implicit overscan,
 	 * the overscan color registers should be programmed to: */
@@ -558,7 +549,6 @@ static void dce110_timing_generator_v_set_overscan_color_black(
 static void dce110_tg_v_program_blank_color(struct timing_generator *tg,
 		const struct crtc_black_color *black_color)
 {
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 	uint32_t addr = mmCRTCV_BLACK_COLOR;
 	uint32_t value = dm_read_reg(tg->ctx, addr);
 
@@ -590,7 +580,6 @@ static void dce110_timing_generator_v_set_overscan_color(struct timing_generator
 	struct dc_context *ctx = tg->ctx;
 	uint32_t value = 0;
 	uint32_t addr;
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 
 	set_reg_field_value(
 		value,
@@ -630,7 +619,6 @@ static void dce110_timing_generator_v_set_early_control(
 		uint32_t early_cntl)
 {
 	uint32_t regval;
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 	uint32_t address = mmCRTC_CONTROL;
 
 	regval = dm_read_reg(tg->ctx, address);
@@ -645,7 +633,6 @@ static void dce110_timing_generator_v_get_crtc_positions(
 	int32_t *v_position)
 {
 	uint32_t value;
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 
 	value = dm_read_reg(tg->ctx, mmCRTCV_STATUS_POSITION);
 
@@ -662,7 +649,6 @@ static void dce110_timing_generator_v_get_crtc_positions(
 
 static uint32_t dce110_timing_generator_v_get_vblank_counter(struct timing_generator *tg)
 {
-	struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 	uint32_t addr = mmCRTCV_STATUS_FRAME_COUNT;
 	uint32_t value = dm_read_reg(tg->ctx, addr);
 	uint32_t field = get_reg_field_value(
-- 
2.7.4