blob: e140467a0164f7ddcd8ff1ab76fd24922a0b93ec (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
From 0a4fa31afa57a5ed03f3574771e941ba63d30c79 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Date: Tue, 9 Feb 2016 11:58:59 -0500
Subject: [PATCH 0782/1110] drm/amd/dal: Temporary disable PLL sharing for DCE
10.
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index eea4eec..ec6db8d 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -103,6 +103,16 @@ static bool is_sharable_clk_src(
const struct core_stream *stream)
{
enum clock_source_id id = stream_with_clk_src->clock_source->id;
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+ enum dce_version dce_ver = dal_adapter_service_get_dce_version(
+ stream->sink->link->adapter_srv);
+
+ /* Currently no clocks are shared for DCE 10 until VBIOS behaviour
+ * is verified for this use case
+ */
+ if (dce_ver == DCE_VERSION_10_0)
+ return false;
+#endif
if (stream_with_clk_src->clock_source == NULL)
return false;
@@ -110,10 +120,6 @@ static bool is_sharable_clk_src(
if (id == CLOCK_SOURCE_ID_EXTERNAL)
return false;
- /* Sharing dual link is not working */
- if (stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK ||
- stream_with_clk_src->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
- return false;
if(!is_same_timing(
&stream_with_clk_src->public.timing, &stream->public.timing))
--
2.7.4
|
