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From 6c1d0e9992aea089e866a3fa1e4e6c1cfa08de1a Mon Sep 17 00:00:00 2001
From: Jordan Lazare <Jordan.Lazare@amd.com>
Date: Thu, 28 Jan 2016 14:06:37 -0500
Subject: [PATCH 0746/1110] drm/amd/dal: Use max clocks/safemarks for dce10
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c | 36 +++++++++++++++++++++-
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 8 +++--
drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 6 ++++
3 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
index b76c8ee..75aff2a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
@@ -335,6 +335,39 @@ static void dal_dc_clock_gating_dce100_power_up(struct dc_context *ctx, bool ena
}
}
+/**
+ * Call display_engine_clock_dce80 to perform the Dclk programming.
+ */
+static void set_display_clock(struct validate_context *context)
+{
+ /* Program the display engine clock.
+ * Check DFS bypass mode support or not. DFSbypass feature is only when
+ * BIOS GPU info table reports support. */
+
+ if (/*dal_adapter_service_is_dfs_bypass_enabled()*/ false) {
+ /*TODO: set_display_clock_dfs_bypass(
+ hws,
+ path_set,
+ context->res_ctx.pool.display_clock,
+ context->res_ctx.min_clocks.min_dclk_khz);*/
+ } else
+ dal_display_clock_set_clock(context->res_ctx.pool.display_clock,
+ 681000);
+
+ /* TODO: When changing display engine clock, DMCU WaitLoop must be
+ * reconfigured in order to maintain the same delays within DMCU
+ * programming sequences. */
+
+ /* TODO: Start GTC counter */
+}
+
+
+static void set_displaymarks(
+ const struct dc *dc, struct validate_context *context)
+{
+ /* Do nothing until we have proper bandwitdth calcs */
+}
+
/**************************************************************************/
bool dce100_hw_sequencer_construct(struct dc *dc)
@@ -348,7 +381,8 @@ bool dce100_hw_sequencer_construct(struct dc *dc)
dc->hwss.enable_fe_clock = dce100_enable_fe_clock;
dc->hwss.pipe_control_lock = dce100_pipe_control_lock;
dc->hwss.set_blender_mode = dce100_set_blender_mode;
-
+ dc->hwss.set_display_clock = set_display_clock;
+ dc->hwss.set_displaymarks = set_displaymarks;
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 9158955..2981307 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -1148,8 +1148,8 @@ static void program_bw(struct dc *dc, struct validate_context *context)
/*TODO: when pplib works*/
/*dc_set_clocks_and_clock_state(context);*/
- set_display_clock(context);
- set_displaymarks(dc, context);
+ dc->hwss.set_display_clock(context);
+ dc->hwss.set_displaymarks(dc, context);
}
static void switch_dp_clock_sources(
@@ -1238,7 +1238,7 @@ static enum dc_status apply_ctx_to_hw(
if (DC_OK != status)
return status;
}
- set_displaymarks(dc, context);
+ dc->hwss.set_displaymarks(dc, context);
update_bios_scratch_critical_state(context->res_ctx.pool.adapter_srv,
false);
@@ -1646,6 +1646,8 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.pipe_control_lock = dce110_pipe_control_lock,
.set_blender_mode = dce110_set_blender_mode,
.clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,/*todo*/
+ .set_display_clock = set_display_clock,
+ .set_displaymarks = set_displaymarks,
};
bool dce110_hw_sequencer_construct(struct dc *dc)
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
index bbb39e4..8460dd7 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
@@ -110,6 +110,12 @@ struct hw_sequencer_funcs {
struct dc_context *ctx,
uint8_t controller_id,
uint32_t mode);
+
+ void (*set_displaymarks)(
+ const struct dc *dc,
+ struct validate_context *context);
+
+ void (*set_display_clock)(struct validate_context *context);
};
bool dc_construct_hw_sequencer(
--
2.7.4
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