path: root/common/recipes-kernel/linux/files/0705-drm-amd-dal-IPP-refactoring-part.patch

From a3b2dec5c70efe7ebe3c65f164ad50fda6b51f33 Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Date: Tue, 19 Jan 2016 14:20:03 -0500
Subject: [PATCH 0705/1110] drm/amd/dal: IPP refactoring part.

Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/dal/dc/core/dc_target.c        |  5 ++-
 .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 23 ++++++-----
 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c     | 46 ++++++----------------
 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h     | 16 +++++---
 .../gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c   | 14 ++-----
 .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 34 +++++++++++++++-
 drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  8 ----
 drivers/gpu/drm/amd/dal/dc/inc/ipp.h               | 39 ++++++++++++++++++
 8 files changed, 114 insertions(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
index b8420bf..e7df2e2 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
@@ -26,6 +26,7 @@
 #include "core_types.h"
 #include "hw_sequencer.h"
 #include "resource.h"
+#include "ipp.h"
 
 #define COEFF_RANGE	3
 #define REGAMMA_COEFF_A0	31308
@@ -364,7 +365,7 @@ bool dc_target_set_cursor_attributes(
 		return false;
 	}
 
-	if (true == core_target->ctx->dc->hwss.cursor_set_attributes(ipp, attributes))
+	if (true == ipp->funcs->ipp_cursor_set_attributes(ipp, attributes))
 		return true;
 
 	return false;
@@ -396,7 +397,7 @@ bool dc_target_set_cursor_position(
 	}
 
 
-	if (true == core_target->ctx->dc->hwss.cursor_set_position(ipp, position))
+	if (true == ipp->funcs->ipp_cursor_set_position(ipp, position))
 		return true;
 
 	return false;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 612afe5..59a3bce 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -187,15 +187,15 @@ static bool set_gamma_ramp(
 	if (params->surface_pixel_format == PIXEL_FORMAT_INDEX8 ||
 		params->selected_gamma_lut == GRAPHICS_GAMMA_LUT_LEGACY) {
 		/* do legacy DCP for 256 colors if we are requested to do so */
-		dce110_ipp_set_legacy_input_gamma_ramp(
+		ipp->funcs->ipp_set_legacy_input_gamma_ramp(
 			ipp, ramp, params);
 
-		dce110_ipp_set_legacy_input_gamma_mode(ipp, true);
+		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, true);
 
 		/* set bypass */
-		dce110_ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
+		ipp->funcs->ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
 
-		dce110_ipp_set_degamma(ipp, params, true);
+		ipp->funcs->ipp_set_degamma(ipp, params, true);
 
 		dce110_opp_set_regamma(opp, ramp, params, true);
 	} else if (params->selected_gamma_lut ==
@@ -208,21 +208,21 @@ static bool set_gamma_ramp(
 		}
 
 		/* do legacy DCP for 256 colors if we are requested to do so */
-		dce110_ipp_set_legacy_input_gamma_ramp(
+		ipp->funcs->ipp_set_legacy_input_gamma_ramp(
 			ipp, ramp, params);
 
-		dce110_ipp_set_legacy_input_gamma_mode(ipp, true);
+		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, true);
 
 		/* set bypass */
-		dce110_ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
+		ipp->funcs->ipp_program_prescale(ipp, PIXEL_FORMAT_UNINITIALIZED);
 	} else {
-		dce110_ipp_set_legacy_input_gamma_mode(ipp, false);
+		ipp->funcs->ipp_set_legacy_input_gamma_mode(ipp, false);
 
-		dce110_ipp_program_prescale(ipp, params->surface_pixel_format);
+		ipp->funcs->ipp_program_prescale(ipp, params->surface_pixel_format);
 
 		/* Do degamma step : remove the given gamma value from FB.
 		 * For FP16 or no degamma do by pass */
-		dce110_ipp_set_degamma(ipp, params, false);
+		ipp->funcs->ipp_set_degamma(ipp, params, false);
 
 		dce110_opp_set_regamma(opp, ramp, params, false);
 	}
@@ -1741,6 +1741,7 @@ static void set_mst_bandwidth(struct stream_encoder *stream_enc,
 		avg_time_slots_per_mtp);
 }
 
+
 static const struct hw_sequencer_funcs dce110_funcs = {
 	.apply_ctx_to_hw = apply_ctx_to_hw,
 	.reset_hw_ctx = reset_hw_ctx,
@@ -1748,8 +1749,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
 	.update_plane_address = update_plane_address,
 	.enable_memory_requests = enable_memory_request,
 	.disable_memory_requests = disable_memory_requests,
-	.cursor_set_attributes = dce110_ipp_cursor_set_attributes,
-	.cursor_set_position = dce110_ipp_cursor_set_position,
 	.set_gamma_ramp = set_gamma_ramp,
 	.power_down = power_down,
 	.enable_accelerated_mode = enable_accelerated_mode,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
index f45da2e..a29dc51 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
@@ -31,31 +31,29 @@
 
 #include "dce110_ipp.h"
 
-static const struct dce110_ipp_reg_offsets reg_offsets[] = {
-{
-	.dcp_offset = (mmDCP0_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-},
-{
-	.dcp_offset = (mmDCP1_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-},
-{
-	.dcp_offset = (mmDCP2_CUR_CONTROL - mmDCP0_CUR_CONTROL),
-}
+static struct ipp_funcs funcs = {
+		.ipp_cursor_set_attributes = dce110_ipp_cursor_set_attributes,
+		.ipp_cursor_set_position = dce110_ipp_cursor_set_position,
+		.ipp_program_prescale = dce110_ipp_program_prescale,
+		.ipp_set_degamma = dce110_ipp_set_degamma,
+		.ipp_set_legacy_input_gamma_mode = dce110_ipp_set_legacy_input_gamma_mode,
+		.ipp_set_legacy_input_gamma_ramp = dce110_ipp_set_legacy_input_gamma_ramp,
+		.ipp_set_palette = dce110_ipp_set_palette,
 };
 
 bool dce110_ipp_construct(
 	struct dce110_ipp* ipp,
 	struct dc_context *ctx,
-	uint32_t inst)
+	uint32_t inst,
+	const struct dce110_ipp_reg_offsets *offset)
 {
-	if (inst >= ARRAY_SIZE(reg_offsets))
-		return false;
-
 	ipp->base.ctx = ctx;
 
 	ipp->base.inst = inst;
 
-	ipp->offsets = reg_offsets[inst];
+	ipp->offsets = *offset;
+
+	ipp->base.funcs = &funcs;
 
 	return true;
 }
@@ -65,21 +63,3 @@ void dce110_ipp_destroy(struct input_pixel_processor **ipp)
 	dc_service_free((*ipp)->ctx, TO_DCE110_IPP(*ipp));
 	*ipp = NULL;
 }
-
-struct input_pixel_processor *dce110_ipp_create(
-	struct dc_context *ctx,
-	uint32_t inst)
-{
-	struct dce110_ipp *ipp =
-		dc_service_alloc(ctx, sizeof(struct dce110_ipp));
-
-	if (!ipp)
-		return NULL;
-
-	if (dce110_ipp_construct(ipp, ctx, inst))
-			return &ipp->base;
-
-	BREAK_TO_DEBUGGER();
-	dc_service_free(ctx, ipp);
-	return NULL;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
index 1da42ff..f0e9e7d 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
@@ -44,14 +44,11 @@ struct dce110_ipp {
 bool dce110_ipp_construct(
 	struct dce110_ipp* ipp,
 	struct dc_context *ctx,
-	enum controller_id id);
+	enum controller_id id,
+	const struct dce110_ipp_reg_offsets *offset);
 
 void dce110_ipp_destroy(struct input_pixel_processor **ipp);
 
-struct input_pixel_processor *dce110_ipp_create(
-	struct dc_context *ctx,
-	enum controller_id id);
-
 /* CURSOR RELATED */
 bool dce110_ipp_cursor_set_position(
 	struct input_pixel_processor *ipp,
@@ -87,4 +84,13 @@ bool dce110_ipp_set_palette(
 	uint32_t length,
 	enum pixel_format surface_pixel_format);
 
+/*
+ * Helper functions to be resused in other ASICs
+ */
+void dce110_helper_select_lut(struct dce110_ipp *ipp110);
+
+void dce110_helper_program_black_white_offset(
+	struct dce110_ipp *ipp110,
+	enum pixel_format surface_pixel_format);
+
 #endif /*__DC_IPP_DCE110_H__*/
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
index f2e8ef4..b7186b1 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
@@ -76,8 +76,6 @@ static void set_lut_inc(
 	bool is_float,
 	bool is_signed);
 
-static void select_lut(struct dce110_ipp *ipp110);
-
 static void program_black_offsets(
 	struct dce110_ipp *ipp110,
 	struct dev_c_lut16 *offset);
@@ -86,10 +84,6 @@ static void program_white_offsets(
 	struct dce110_ipp *ipp110,
 	struct dev_c_lut16 *offset);
 
-static void program_black_white_offset(
-	struct dce110_ipp *ipp110,
-	enum pixel_format surface_pixel_format);
-
 static void program_lut_gamma(
 	struct dce110_ipp *ipp110,
 	const struct dev_c_lut16 *gamma,
@@ -264,7 +258,7 @@ static void set_lut_inc(
 	dal_write_reg(ipp110->base.ctx, addr, value);
 }
 
-static void select_lut(struct dce110_ipp *ipp110)
+void dce110_helper_select_lut(struct dce110_ipp *ipp110)
 {
 	uint32_t value = 0;
 
@@ -371,7 +365,7 @@ static void program_white_offsets(
 		offset->blue);
 }
 
-static void program_black_white_offset(
+void dce110_helper_program_black_white_offset(
 	struct dce110_ipp *ipp110,
 	enum pixel_format surface_pixel_format)
 {
@@ -482,9 +476,9 @@ static void program_lut_gamma(
 		}
 	}
 
-	program_black_white_offset(ipp110, params->surface_pixel_format);
+	dce110_helper_program_black_white_offset(ipp110, params->surface_pixel_format);
 
-	select_lut(ipp110);
+	dce110_helper_select_lut(ipp110);
 
 	if (params->surface_pixel_format == PIXEL_FORMAT_INDEX8) {
 		addr = DCP_REG(mmDC_LUT_SEQ_COLOR);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 7880ccb..8f04707 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -122,6 +122,19 @@ static const struct dce110_transform_reg_offsets dce110_xfm_offsets[] = {
 }
 };
 
+static const struct dce110_ipp_reg_offsets dce110_ipp_reg_offsets[] = {
+{
+	.dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL),
+},
+{
+	.dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL),
+},
+{
+	.dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL),
+}
+};
+
+
 static struct timing_generator *dce110_timing_generator_create(
 		struct adapter_service *as,
 		struct dc_context *ctx,
@@ -207,6 +220,25 @@ static struct transform *dce110_transform_create(
 	return NULL;
 }
 
+static struct input_pixel_processor *dce110_ipp_create(
+	struct dc_context *ctx,
+	uint32_t inst,
+	const struct dce110_ipp_reg_offsets *offsets)
+{
+	struct dce110_ipp *ipp =
+		dc_service_alloc(ctx, sizeof(struct dce110_ipp));
+
+	if (!ipp)
+		return NULL;
+
+	if (dce110_ipp_construct(ipp, ctx, inst, offsets))
+		return &ipp->base;
+
+	BREAK_TO_DEBUGGER();
+	dc_service_free(ctx, ipp);
+	return NULL;
+}
+
 bool dce110_construct_resource_pool(
 	struct adapter_service *adapter_serv,
 	struct dc *dc,
@@ -293,7 +325,7 @@ bool dce110_construct_resource_pool(
 			goto controller_create_fail;
 		}
 
-		pool->ipps[i] = dce110_ipp_create(ctx, i);
+		pool->ipps[i] = dce110_ipp_create(ctx, i, &dce110_ipp_reg_offsets[i]);
 		if (pool->ipps[i] == NULL) {
 			BREAK_TO_DEBUGGER();
 			dal_error(
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
index a5ccb5e..59ed137 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
@@ -51,14 +51,6 @@ struct hw_sequencer_funcs {
 
 	bool (*transform_power_up)(struct transform *xfm);
 
-	bool (*cursor_set_attributes)(
-				struct input_pixel_processor *ipp,
-				const struct dc_cursor_attributes *attributes);
-
-	bool (*cursor_set_position)(
-				struct input_pixel_processor *ipp,
-				const struct dc_cursor_position *position);
-
 	bool (*set_gamma_ramp)(
 					struct input_pixel_processor *ipp,
 					struct output_pixel_processor *opp,
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
index 602b4cb..20bb785 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/ipp.h
@@ -41,6 +41,7 @@
 struct input_pixel_processor {
 	struct  dc_context *ctx;
 	uint32_t inst;
+	struct ipp_funcs *funcs;
 };
 
 enum wide_gamut_degamma_mode {
@@ -63,4 +64,42 @@ struct dcp_video_matrix {
 	int32_t value[MAXTRIX_COEFFICIENTS_NUMBER];
 };
 
+struct ipp_funcs {
+
+	/* CURSOR RELATED */
+	bool (*ipp_cursor_set_position)(
+		struct input_pixel_processor *ipp,
+		const struct dc_cursor_position *position);
+
+	bool (*ipp_cursor_set_attributes)(
+		struct input_pixel_processor *ipp,
+		const struct dc_cursor_attributes *attributes);
+
+	/* DEGAMMA RELATED */
+	bool (*ipp_set_degamma)(
+		struct input_pixel_processor *ipp,
+		const struct gamma_parameters *params,
+		bool force_bypass);
+
+	void (*ipp_program_prescale)(
+		struct input_pixel_processor *ipp,
+		enum pixel_format pixel_format);
+
+	void (*ipp_set_legacy_input_gamma_mode)(
+			struct input_pixel_processor *ipp,
+			bool is_legacy);
+
+	bool (*ipp_set_legacy_input_gamma_ramp)(
+		struct input_pixel_processor *ipp,
+		const struct gamma_ramp *gamma_ramp,
+		const struct gamma_parameters *params);
+
+	bool (*ipp_set_palette)(
+		struct input_pixel_processor *ipp,
+		const struct dev_c_lut *palette,
+		uint32_t start,
+		uint32_t length,
+		enum pixel_format surface_pixel_format);
+};
+
 #endif /* __DAL_IPP_H__ */
-- 
2.7.4