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From 91e820d9c69db1a828a4b1d2d563085639806a48 Mon Sep 17 00:00:00 2001
From: Yongqiang Sun <yongqiang.sun@amd.com>
Date: Tue, 22 Dec 2015 13:53:24 -0500
Subject: [PATCH 0645/1110] drm/amd/dal: Swap enable_stream and enable_link
call sequence.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 6 +++---
drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 1 -
drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 1 -
drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c | 11 +++++------
drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h | 1 -
5 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
index 9b8f536..12c214f 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
@@ -932,7 +932,6 @@ static enum dc_status enable_link_dp(struct core_stream *stream)
dp_enable_link_phy(
stream->sink->link,
stream->signal,
- stream->stream_enc->id,
&link_settings);
panel_mode = dp_get_panel_mode(link);
@@ -1264,12 +1263,13 @@ void core_link_enable_stream(
{
struct dc *dc = stream->ctx->dc;
- dc->hwss.enable_stream(stream);
-
if (DC_OK != enable_link(stream)) {
BREAK_TO_DEBUGGER();
return;
}
+
+ dc->hwss.enable_stream(stream);
+
if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
allocate_mst_payload(stream);
}
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
index 2852440..c0390e1 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
@@ -1075,7 +1075,6 @@ bool dp_hbr_verify_link_cap(
dp_enable_link_phy(
link,
link->public.connector_signal,
- ENGINE_ID_UNKNOWN,
cur);
if (skip_link_training)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
index a1617bc..5ed0380 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
@@ -55,7 +55,6 @@ void dp_receiver_power_ctrl(struct core_link *link, bool on)
void dp_enable_link_phy(
struct core_link *link,
enum signal_type signal,
- enum engine_id engine,
const struct link_settings *link_settings)
{
if (signal == SIGNAL_TYPE_DISPLAY_PORT)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
index 08711c2..8fc8258 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
@@ -1396,7 +1396,7 @@ void dce110_link_encoder_enable_tmds_output(
/* Enable the PHY */
cntl.action = TRANSMITTER_CONTROL_ENABLE;
- cntl.engine_id = enc->transmitter;
+ cntl.engine_id = ENGINE_ID_UNKNOWN;
cntl.transmitter = enc110->base.transmitter;
cntl.pll_id = clock_source;
cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
@@ -1437,7 +1437,7 @@ void dce110_link_encoder_enable_dual_link_tmds_output(
/* Enable the PHY */
cntl.action = TRANSMITTER_CONTROL_ENABLE;
- cntl.engine_id = enc->transmitter;
+ cntl.engine_id = ENGINE_ID_UNKNOWN;
cntl.transmitter = enc110->base.transmitter;
cntl.pll_id = clock_source;
cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
@@ -1472,7 +1472,6 @@ void dce110_link_encoder_enable_dp_output(
struct dc_context *ctx = enc110->base.ctx;
struct bp_transmitter_control cntl = { 0 };
enum bp_result result;
- enum engine_id engine = enc->transmitter;
if (enc110->base.connector.id == CONNECTOR_ID_EDP) {
/* power up eDP panel */
@@ -1496,7 +1495,7 @@ void dce110_link_encoder_enable_dp_output(
configure_encoder(enc110, link_settings);
cntl.action = TRANSMITTER_CONTROL_ENABLE;
- cntl.engine_id = engine;
+ cntl.engine_id = ENGINE_ID_UNKNOWN;
cntl.transmitter = enc110->base.transmitter;
cntl.pll_id = clock_source;
cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
@@ -1532,7 +1531,7 @@ void dce110_link_encoder_enable_dp_mst_output(
struct dc_context *ctx = enc110->base.ctx;
struct bp_transmitter_control cntl = { 0 };
enum bp_result result;
- enum engine_id engine = enc->transmitter;
+
/* Enable the PHY */
/* number_of_lanes is used for pixel clock adjust,
@@ -1542,7 +1541,7 @@ void dce110_link_encoder_enable_dp_mst_output(
configure_encoder(enc110, link_settings);
cntl.action = TRANSMITTER_CONTROL_ENABLE;
- cntl.engine_id = engine;
+ cntl.engine_id = ENGINE_ID_UNKNOWN;
cntl.transmitter = enc110->base.transmitter;
cntl.pll_id = clock_source;
cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
index 28d9d04..d9a48c0 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h
@@ -43,7 +43,6 @@ enum dc_status core_link_write_dpcd(
void dp_enable_link_phy(
struct core_link *link,
enum signal_type signal,
- enum engine_id engine,
const struct link_settings *link_settings);
void dp_receiver_power_ctrl(struct core_link *link, bool on);
--
2.7.4
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