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From c5a1ee9146c9d2e4212dc85bc71a08b34db60e05 Mon Sep 17 00:00:00 2001
From: Harry Wentland <harry.wentland@amd.com>
Date: Wed, 2 Dec 2015 11:41:18 -0500
Subject: [PATCH 0565/1110] drm/amd/dal: Move enabling of stream & link to
dc_link
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 68 ++++++++++++++++++++++
drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 5 +-
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 65 ++-------------------
drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 4 ++
drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 9 +++
5 files changed, 90 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
index d8bf8e9..f29aea7 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
@@ -1090,3 +1090,71 @@ void core_link_resume(struct core_link *link)
DELAY_ON_CONNECT_IN_MS,
DELAY_ON_DISCONNECT_IN_MS);
}
+
+
+static enum dc_status allocate_mst_payload(struct core_stream *stream)
+{
+ struct core_link *link = stream->sink->link;
+ struct link_encoder *link_encoder = link->link_enc;
+ struct stream_encoder *stream_encoder = stream->stream_enc;
+ struct dp_mst_stream_allocation_table table = {0};
+ struct fixed31_32 avg_time_slots_per_mtp;
+ uint8_t cur_stream_payload_idx;
+ struct dc *dc = stream->ctx->dc;
+
+ /* enable_link_dp_mst already check link->enabled_stream_count
+ * and stream is in link->stream[]. This is called during set mode,
+ * stream_enc is available.
+ */
+
+ /* get calculate VC payload for stream: stream_alloc */
+ dc_helpers_dp_mst_write_payload_allocation_table(
+ stream->ctx,
+ &stream->public,
+ &table,
+ true);
+
+ /* program DP source TX for payload */
+ dc->hwss.update_mst_stream_allocation_table(
+ link_encoder,
+ &table);
+
+ /* send down message */
+ dc_helpers_dp_mst_poll_for_allocation_change_trigger(
+ stream->ctx,
+ &stream->public);
+
+ dc_helpers_dp_mst_send_payload_allocation(
+ stream->ctx,
+ &stream->public,
+ true);
+
+ /* slot X.Y for only current stream */
+ cur_stream_payload_idx = table.cur_stream_payload_idx;
+ avg_time_slots_per_mtp = dal_fixed31_32_from_fraction(
+ table.stream_allocations[cur_stream_payload_idx].pbn,
+ table.stream_allocations[cur_stream_payload_idx].pbn_per_slot);
+
+ dc->hwss.set_mst_bandwidth(
+ stream_encoder,
+ avg_time_slots_per_mtp);
+
+ return DC_OK;
+
+}
+
+void core_link_enable_stream(
+ struct core_link *link,
+ struct core_stream *stream)
+{
+ struct dc *dc = stream->ctx->dc;
+
+ dc->hwss.enable_stream(stream);
+
+ if (DC_OK != core_link_enable(stream)) {
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+ if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+ allocate_mst_payload(stream);
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
index 2913d5c..4c9eae4 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
@@ -9,6 +9,10 @@
#include "include/connector_interface.h"
#include "hw_sequencer.h"
#include "include/ddc_service_interface.h"
+#include "dc_helpers.h"
+#include "dce110/dce110_link_encoder.h"
+#include "dce110/dce110_stream_encoder.h"
+
enum dc_status core_link_read_dpcd(
struct core_link* link,
@@ -191,4 +195,3 @@ void dp_set_hw_test_pattern(
link->ctx->dc->hwss.encoder_set_dp_phy_pattern(encoder, &pattern_param);
}
-
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 1d289ba..fa71095 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -774,56 +774,6 @@ static enum color_space get_output_color_space(
return color_space;
}
-static enum dc_status allocate_mst_payload(struct core_stream *stream)
-{
- struct core_link *link = stream->sink->link;
- struct link_encoder *link_encoder = link->link_enc;
- struct stream_encoder *stream_encoder = stream->stream_enc;
- struct dp_mst_stream_allocation_table table = {0};
- struct fixed31_32 avg_time_slots_per_mtp;
- uint8_t cur_stream_payload_idx;
-
- /* enable_link_dp_mst already check link->enabled_stream_count
- * and stream is in link->stream[]. This is called during set mode,
- * stream_enc is available.
- */
-
- /* get calculate VC payload for stream: stream_alloc */
- dc_helpers_dp_mst_write_payload_allocation_table(
- stream->ctx,
- &stream->public,
- &table,
- true);
-
- /* program DP source TX for payload */
- dce110_link_encoder_update_mst_stream_allocation_table(
- link_encoder,
- &table);
-
- /* send down message */
- dc_helpers_dp_mst_poll_for_allocation_change_trigger(
- stream->ctx,
- &stream->public);
-
- dc_helpers_dp_mst_send_payload_allocation(
- stream->ctx,
- &stream->public,
- true);
-
- /* slot X.Y for only current stream */
- cur_stream_payload_idx = table.cur_stream_payload_idx;
- avg_time_slots_per_mtp = dal_fixed31_32_from_fraction(
- table.stream_allocations[cur_stream_payload_idx].pbn,
- table.stream_allocations[cur_stream_payload_idx].pbn_per_slot);
-
- dce110_stream_encoder_set_mst_bandwidth(
- stream_encoder,
- avg_time_slots_per_mtp);
-
- return DC_OK;
-
-}
-
static enum dc_status deallocate_mst_payload(struct core_stream *stream)
{
struct core_link *link = stream->sink->link;
@@ -991,15 +941,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx,
color_space);
if (timing_changed) {
- enable_stream(stream);
-
- if (DC_OK != core_link_enable(stream)) {
- BREAK_TO_DEBUGGER();
- return DC_ERROR_UNEXPECTED;
- }
- if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
- allocate_mst_payload(stream);
-
+ core_link_enable_stream(stream->sink->link, stream);
}
if (dc_is_dp_signal(stream->signal))
@@ -1854,7 +1796,10 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.validate_bandwidth = dce110_validate_bandwidth,
.enable_display_pipe_clock_gating = dce110_enable_display_pipe_clock_gating,
.enable_display_power_gating = dce110_enable_display_power_gating,
- .program_bw = dce110_program_bw
+ .program_bw = dce110_program_bw,
+ .enable_stream = enable_stream,
+ .update_mst_stream_allocation_table = dce110_link_encoder_update_mst_stream_allocation_table,
+ .set_mst_bandwidth = dce110_stream_encoder_set_mst_bandwidth
};
bool dce110_hw_sequencer_construct(struct dc *dc)
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
index bea3c36..299b13e 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
@@ -244,6 +244,10 @@ enum dc_status dc_link_validate_mode_timing(
void core_link_resume(struct core_link *link);
+void core_link_enable_stream(
+ struct core_link *link,
+ struct core_stream *stream);
+
/********** DAL Core*********************/
#include "display_clock_interface.h"
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
index 3114fbd..0502c4d 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
@@ -154,7 +154,16 @@ struct hw_sequencer_funcs {
void (*program_bw)(
struct dc *dc,
struct validate_context *context);
+ void (*enable_stream)(
+ struct core_stream *stream);
+ void (*update_mst_stream_allocation_table)(
+ struct link_encoder *enc,
+ const struct dp_mst_stream_allocation_table *table);
+
+ void (*set_mst_bandwidth)(
+ struct stream_encoder *enc,
+ struct fixed31_32 avg_time_slots_per_mtp);
};
bool dc_construct_hw_sequencer(
--
2.7.4
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