path: root/common/recipes-kernel/linux/files/0537-drm-amd-dal-keep-streams-in-public-target.patch

From 2e9920f97abd7b84fadfb4b2e741ec6fba266bfb Mon Sep 17 00:00:00 2001
From: Mykola Lysenko <Mykola.Lysenko@amd.com>
Date: Mon, 30 Nov 2015 15:08:32 +0800
Subject: [PATCH 0537/1110] drm/amd/dal: keep streams in public target

In order to remove copy of the same information from core_target

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/dal/dc/core/dc.c               | 25 +++++---
 drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      | 22 ++++---
 drivers/gpu/drm/amd/dal/dc/core/dc_target.c        | 60 +++++++++++--------
 .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 64 ++++++++++++---------
 .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 67 +++++++++++++---------
 drivers/gpu/drm/amd/dal/dc/inc/core_types.h        |  2 -
 6 files changed, 141 insertions(+), 99 deletions(-)

diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index e13ce4e..286bdde 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -690,12 +690,13 @@ const struct dc_target *dc_get_target_on_irq_source(
 		break;
 	default:
 		dal_error("%s: invalid irq source: %d\n!",__func__, src);
-		goto fail;
+		return NULL;
 	}
 
 	for (i = 0; i < dc->current_context.target_count; i++) {
-		const struct core_target *target =
-				dc->current_context.targets[i];
+		struct core_target *target = dc->current_context.targets[i];
+
+		struct dc_target *dc_target;
 
 		if (NULL == target) {
 			dal_error("%s: 'dc_target' is NULL for irq source: %d\n!",
@@ -703,14 +704,18 @@ const struct dc_target *dc_get_target_on_irq_source(
 			continue;
 		}
 
-		for (j = 0; j < target->stream_count; j++) {
-			const uint8_t controller_idx =
-					target->streams[j]->controller_idx;
+		dc_target = &target->public;
+
+		for (j = 0; j < target->public.stream_count; j++) {
+			const struct core_stream *stream =
+				DC_STREAM_TO_CORE(dc_target->streams[j]);
+			const uint8_t controller_idx = stream->controller_idx;
+
 			if (controller_idx == crtc_idx)
-				return &target->public;
+				return dc_target;
 		}
 	}
-fail:
+
 	return NULL;
 }
 
@@ -749,6 +754,7 @@ void dc_print_sync_report(
 {
 	uint32_t i;
 	const struct core_target *core_target;
+	const struct core_stream *core_stream;
 	struct dc_context *dc_ctx = dc->ctx;
 	struct dc_target_sync_report *target_sync_report;
 	struct dc_sync_report sync_report = { 0 };
@@ -767,9 +773,10 @@ void dc_print_sync_report(
 
 		core_target = dc->current_context.targets[i];
 		target_sync_report = &sync_report.trg_reports[i];
+		core_stream = DC_STREAM_TO_CORE(core_target->public.streams[0]);
 
 		dc->hwss.get_crtc_positions(
-			core_target->streams[0]->tg,
+			core_stream->tg,
 			&target_sync_report->h_count,
 			&target_sync_report->v_count);
 
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index e5b1d02..f1f7347 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -88,12 +88,15 @@ struct clock_source *find_used_clk_src_for_sharing(
 	uint8_t i, j;
 	for (i = 0; i < context->target_count; i++) {
 		struct core_target *target = context->targets[i];
-		for (j = 0; j < target->stream_count; j++)
-		{
-			if (target->streams[j]->clock_source == NULL)
+		for (j = 0; j < target->public.stream_count; j++) {
+			struct core_stream *clock_source_stream =
+				DC_STREAM_TO_CORE(target->public.streams[j]);
+
+			if (clock_source_stream->clock_source == NULL)
 				continue;
-			if (is_sharable_clk_src(target->streams[j], stream))
-				return target->streams[j]->clock_source;
+
+			if (is_sharable_clk_src(clock_source_stream, stream))
+				return clock_source_stream->clock_source;
 		}
 	}
 
@@ -363,9 +366,12 @@ void build_scaling_params_for_context(
 		if (context->target_flags[i].unchanged)
 			continue;
 		for (j = 0; j < target->status.surface_count; j++) {
-			const struct dc_surface *surface = target->status.surfaces[j];
-			for (k = 0; k < target->stream_count; k++) {
-				struct core_stream *stream = target->streams[k];
+			const struct dc_surface *surface =
+				target->status.surfaces[j];
+			for (k = 0; k < target->public.stream_count; k++) {
+				struct core_stream *stream =
+					DC_STREAM_TO_CORE(
+						target->public.streams[k]);
 
 				build_scaling_params(surface, stream);
 			}
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
index 1a8d8d6..6e89050 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
@@ -52,13 +52,11 @@ static void construct(
 {
 	uint8_t i;
 	for (i = 0; i < stream_count; i++) {
-		target->streams[i] = DC_STREAM_TO_CORE(dc_streams[i]);
 		target->public.streams[i] = dc_streams[i];
 		dc_stream_retain(dc_streams[i]);
 	}
 
 	target->ctx = ctx;
-	target->stream_count = stream_count;
 	target->public.stream_count = stream_count;
 }
 
@@ -68,11 +66,12 @@ static void destruct(struct core_target *core_target)
 
 	for (i = 0; i < core_target->status.surface_count; i++) {
 		dc_surface_release(core_target->status.surfaces[i]);
-		core_target->status.surfaces[i] = 0;
+		core_target->status.surfaces[i] = NULL;
 	}
-	for (i = 0; i < core_target->stream_count; i++) {
-		dc_stream_release(&core_target->streams[i]->public);
-		core_target->streams[i] = 0;
+	for (i = 0; i < core_target->public.stream_count; i++) {
+		dc_stream_release(
+			(struct dc_stream *)core_target->public.streams[i]);
+		core_target->public.streams[i] = NULL;
 	}
 }
 
@@ -222,8 +221,10 @@ bool dc_commit_surfaces_to_target(
 	}
 
 	for (i = 0; i < surface_count; i++)
-		for (j = 0; j < target->stream_count; j++)
-			build_scaling_params(surfaces[i], target->streams[j]);
+		for (j = 0; j < target->public.stream_count; j++)
+			build_scaling_params(
+				surfaces[i],
+				DC_STREAM_TO_CORE(target->public.streams[j]));
 
 	if (dc->hwss.validate_bandwidth(dc, &dc->current_context) != DC_OK) {
 		BREAK_TO_DEBUGGER();
@@ -247,8 +248,8 @@ bool dc_commit_surfaces_to_target(
 		dc_surface_retain(surface);
 
 		program_gamma(dc->ctx, surface,
-				target->streams[0]->ipp,
-				target->streams[0]->opp);
+			DC_STREAM_TO_CORE(target->public.streams[0])->ipp,
+			DC_STREAM_TO_CORE(target->public.streams[0])->opp);
 
 		dc->hwss.set_plane_config(
 			core_surface,
@@ -277,8 +278,8 @@ bool dc_target_is_connected_to_sink(
 {
 	struct core_target *target = DC_TARGET_TO_CORE(dc_target);
 	uint8_t i;
-	for (i = 0; i < target->stream_count; i++) {
-		if (&target->streams[i]->sink->public == dc_sink)
+	for (i = 0; i < target->public.stream_count; i++) {
+		if (target->public.streams[i]->sink == dc_sink)
 			return true;
 	}
 	return false;
@@ -288,9 +289,11 @@ void dc_target_enable_memory_requests(struct dc_target *target)
 {
 	uint8_t i;
 	struct core_target *core_target = DC_TARGET_TO_CORE(target);
-	for (i = 0; i < core_target->stream_count; i++) {
-	struct timing_generator *tg = core_target->streams[i]->tg;
-		if (false == core_target->ctx->dc->hwss.enable_memory_requests(tg)) {
+	for (i = 0; i < core_target->public.stream_count; i++) {
+		struct timing_generator *tg =
+			DC_STREAM_TO_CORE(core_target->public.streams[i])->tg;
+
+		if (!core_target->ctx->dc->hwss.enable_memory_requests(tg)) {
 			dal_error("DC: failed to unblank crtc!\n");
 			BREAK_TO_DEBUGGER();
 		}
@@ -301,8 +304,9 @@ void dc_target_disable_memory_requests(struct dc_target *target)
 {
 	uint8_t i;
 	struct core_target *core_target = DC_TARGET_TO_CORE(target);
-	for (i = 0; i < core_target->stream_count; i++) {
-	struct timing_generator *tg = core_target->streams[i]->tg;
+	for (i = 0; i < core_target->public.stream_count; i++) {
+	struct timing_generator *tg =
+		DC_STREAM_TO_CORE(core_target->public.streams[i])->tg;
 
 		if (NULL == tg) {
 			dal_error("DC: timing generator is NULL!\n");
@@ -334,7 +338,7 @@ bool dc_target_set_cursor_attributes(
 	}
 
 	core_target = DC_TARGET_TO_CORE(dc_target);
-	ipp = core_target->streams[0]->ipp;
+	ipp = DC_STREAM_TO_CORE(core_target->public.streams[0])->ipp;
 
 	if (NULL == ipp) {
 		dal_error("DC: input pixel processor is NULL!\n");
@@ -365,7 +369,7 @@ bool dc_target_set_cursor_position(
 	}
 
 	core_target = DC_TARGET_TO_CORE(dc_target);
-	ipp = core_target->streams[0]->ipp;
+	ipp = DC_STREAM_TO_CORE(core_target->public.streams[0])->ipp;
 
 	if (NULL == ipp) {
 		dal_error("DC: input pixel processor is NULL!\n");
@@ -383,14 +387,17 @@ bool dc_target_set_cursor_position(
 uint8_t dc_target_get_link_index(const struct dc_target *dc_target)
 {
 	const struct core_target *target = CONST_DC_TARGET_TO_CORE(dc_target);
+	const struct core_sink *sink =
+		DC_SINK_TO_CORE(target->public.streams[0]->sink);
 
-	return target->streams[0]->sink->link->link_index;
+	return sink->link->link_index;
 }
 
 uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target)
 {
 	struct core_target *core_target = DC_TARGET_TO_CORE(dc_target);
-	struct timing_generator *tg = core_target->streams[0]->tg;
+	struct timing_generator *tg =
+		DC_STREAM_TO_CORE(core_target->public.streams[0])->tg;
 
 	return core_target->ctx->dc->hwss.get_vblank_counter(tg);
 }
@@ -402,7 +409,9 @@ enum dc_irq_source dc_target_get_irq_src(
 
 	/* #TODO - Remove the assumption that the controller is always in the
 	 * first stream of a core target */
-	uint8_t controller_idx = core_target->streams[0]->controller_idx;
+	struct core_stream *stream =
+		DC_STREAM_TO_CORE(core_target->public.streams[0]);
+	uint8_t controller_idx = stream->controller_idx;
 
 	/* Get controller id */
 	enum controller_id crtc_id = controller_idx + 1;
@@ -434,10 +443,11 @@ void dc_target_log(
 			"core_target 0x%x: surface_count=%d, stream_count=%d",
 			core_target,
 			core_target->status.surface_count,
-			core_target->stream_count);
+			core_target->public.stream_count);
 
-	for (i = 0; i < core_target->stream_count; i++) {
-		const struct core_stream *core_stream = core_target->streams[i];
+	for (i = 0; i < core_target->public.stream_count; i++) {
+		const struct core_stream *core_stream =
+			DC_STREAM_TO_CORE(core_target->public.streams[i]);
 
 		dal_logger_write(dal_logger,
 			log_major,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index cbe27a4..29e7b80 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -1010,7 +1010,7 @@ static void power_down_encoders(struct validate_context *context)
 
 	for (i = 0; i < context->target_count; i++) {
 		target = context->targets[i];
-		stream = target->streams[0];
+		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
 		core_link_disable(stream);
 	}
 }
@@ -1023,7 +1023,7 @@ static void power_down_controllers(struct validate_context *context)
 
 	for (i = 0; i < context->target_count; i++) {
 		target = context->targets[i];
-		stream = target->streams[0];
+		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
 
 		dce110_timing_generator_disable_crtc(stream->tg);
 	}
@@ -1037,7 +1037,7 @@ static void power_down_clock_sources(struct validate_context *context)
 
 	for (i = 0; i < context->target_count; i++) {
 		target = context->targets[i];
-		stream = target->streams[0];
+		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
 
 		if (false == dal_clock_source_power_down_pll(
 				stream->clock_source,
@@ -1074,7 +1074,7 @@ static void disable_vga_and_power_gate_all_controllers(
 
 	for (i = 0; i < context->target_count; i++) {
 		target = context->targets[i];
-		stream = target->streams[0];
+		stream = DC_STREAM_TO_CORE(target->public.streams[0]);
 		tg = stream->tg;
 		ctx = stream->ctx;
 		controller_id = stream->controller_idx;
@@ -1257,8 +1257,9 @@ static void set_displaymarks(
 	for (i = 0; i < target_count; i++) {
 		struct core_target *target = context->targets[i];
 
-		for (j = 0; j < target->stream_count; j++) {
-			struct core_stream *stream = target->streams[j];
+		for (j = 0; j < target->public.stream_count; j++) {
+			struct core_stream *stream =
+				DC_STREAM_TO_CORE(target->public.streams[j]);
 
 			dce110_mem_input_program_display_marks(
 				stream->mi,
@@ -1285,8 +1286,9 @@ static void set_safe_displaymarks(struct validate_context *context)
 	for (i = 0; i < target_count; i++) {
 		struct core_target *target = context->targets[i];
 
-		for (j = 0; j < target->stream_count; j++) {
-			struct core_stream *stream = target->streams[j];
+		for (j = 0; j < target->public.stream_count; j++) {
+			struct core_stream *stream =
+				DC_STREAM_TO_CORE(target->public.streams[j]);
 
 			dce110_mem_input_program_safe_display_marks(stream->mi);
 		}
@@ -1348,8 +1350,9 @@ static void switch_dp_clock_sources(
 	uint8_t i, j;
 	for (i = 0; i < val_context->target_count; i++) {
 		struct core_target *target = val_context->targets[i];
-		for (j = 0; j < target->stream_count; j++) {
-			struct core_stream *stream = target->streams[j];
+		for (j = 0; j < target->public.stream_count; j++) {
+			struct core_stream *stream =
+				DC_STREAM_TO_CORE(target->public.streams[j]);
 
 			if (dc_is_dp_signal(stream->signal)) {
 				struct clock_source *clk_src =
@@ -1556,15 +1559,17 @@ static bool set_plane_config(
 	struct core_surface *surface,
 	struct core_target *target)
 {
+	const struct core_stream *core_stream =
+		DC_STREAM_TO_CORE(target->public.streams[0]);
 	const struct dc_crtc_timing *dc_crtc_timing =
-			&target->streams[0]->public.timing;
-	struct mem_input *mi = target->streams[0]->mi;
-	struct input_pixel_processor *ipp = target->streams[0]->ipp;
-	struct timing_generator *tg = target->streams[0]->tg;
-	struct transform *xfm = target->streams[0]->xfm;
-	struct output_pixel_processor *opp = target->streams[0]->opp;
-	struct dc_context *ctx = target->streams[0]->ctx;
-	uint8_t controller_idx = target->streams[0]->controller_idx;
+			&target->public.streams[0]->timing;
+	struct mem_input *mi = core_stream->mi;
+	struct input_pixel_processor *ipp = core_stream->ipp;
+	struct timing_generator *tg = core_stream->tg;
+	struct transform *xfm = core_stream->xfm;
+	struct output_pixel_processor *opp = core_stream->opp;
+	struct dc_context *ctx = core_stream->ctx;
+	uint8_t controller_idx = core_stream->controller_idx;
 
 	/* TODO: Clean up change, possibly change to use same type */
 	enum color_space input_color_space =
@@ -1590,14 +1595,14 @@ static bool set_plane_config(
 	set_default_colors(
 			ipp,
 			opp,
-			target->streams[0]->format,
+			core_stream->format,
 			input_color_space,
 			get_output_color_space(dc_crtc_timing),
 			dc_crtc_timing->display_color_depth);
 
 	/* program Scaler */
 	program_scaler(
-		controller_idx, tg, xfm, surface, target->streams[0]);
+		controller_idx, tg, xfm, surface, core_stream);
 
 	set_blender_mode(
 			ctx,
@@ -1634,9 +1639,11 @@ static bool update_plane_address(
 	const struct core_surface *surface,
 	struct core_target *target)
 {
-	struct dc_context *ctx = target->streams[0]->ctx;
-	struct mem_input *mi = target->streams[0]->mi;
-	uint8_t controller_id = target->streams[0]->controller_idx;
+	const struct core_stream *core_stream =
+		DC_STREAM_TO_CORE(target->public.streams[0]);
+	struct dc_context *ctx = core_stream->ctx;
+	struct mem_input *mi = core_stream->mi;
+	uint8_t controller_id = core_stream->controller_idx;
 
 	/* TODO: crtc should be per surface, NOT per-target */
 	pipe_control_lock(
@@ -1688,17 +1695,18 @@ static void reset_hw_ctx(struct dc *dc,
 	uint8_t i;
 	/* look up the targets that have been removed since last commit */
 	for (i = 0; i < dc->current_context.target_count; i++) {
-		uint8_t controller_idx = dc->current_context.targets[i]->
-						streams[0]->controller_idx;
+		const struct core_target *core_target =
+			dc->current_context.targets[i];
+		struct core_stream *core_stream =
+			DC_STREAM_TO_CORE(core_target->public.streams[0]);
+		uint8_t controller_idx = core_stream->controller_idx;
 
 		if (context->res_ctx.controller_ctx[controller_idx].stream &&
 				!context->res_ctx.controller_ctx[controller_idx]
 				.flags.timing_changed)
 			continue;
 
-		reset_single_stream_hw_ctx(
-			dc->current_context.targets[i]->streams[0],
-			&dc->current_context);
+		reset_single_stream_hw_ctx(core_stream, &dc->current_context);
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 126ebd2..de71d39 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -876,35 +876,43 @@ static enum dc_status map_resources(
 	/* mark resources used for targets that are already active */
 	for (i = 0; i < context->target_count; i++) {
 		struct core_target *target = context->targets[i];
-		if (context->target_flags[i].unchanged)
-			for (j = 0; j < target->stream_count; j++) {
-				struct core_stream *stream = target->streams[j];
-				attach_stream_to_controller(
-						&context->res_ctx,
-						stream);
-
-				set_stream_engine_in_use(
-						&context->res_ctx,
-						stream->stream_enc);
-
-				reference_clock_source(
-						&context->res_ctx,
-						stream->clock_source);
-
-				if (stream->audio) {
-					set_audio_in_use(&context->res_ctx,
-							stream->audio);
-				}
+
+		if (!context->target_flags[i].unchanged)
+			continue;
+
+		for (j = 0; j < target->public.stream_count; j++) {
+			struct core_stream *stream =
+				DC_STREAM_TO_CORE(target->public.streams[j]);
+
+			attach_stream_to_controller(
+				&context->res_ctx,
+				stream);
+
+			set_stream_engine_in_use(
+				&context->res_ctx,
+				stream->stream_enc);
+
+			reference_clock_source(
+				&context->res_ctx,
+				stream->clock_source);
+
+			if (stream->audio) {
+				set_audio_in_use(&context->res_ctx,
+					stream->audio);
 			}
+		}
 	}
 
 	/* acquire new resources */
 	for (i = 0; i < context->target_count; i++) {
 		struct core_target *target = context->targets[i];
+
 		if (context->target_flags[i].unchanged)
 			continue;
-		for (j = 0; j < target->stream_count; j++) {
-			struct core_stream *stream = target->streams[j];
+
+		for (j = 0; j < target->public.stream_count; j++) {
+			struct core_stream *stream =
+				DC_STREAM_TO_CORE(target->public.streams[j]);
 			struct core_stream *curr_stream;
 
 			if (!assign_first_free_controller(
@@ -1103,9 +1111,11 @@ static enum dc_status validate_mapped_resource(
 		struct core_target *target = context->targets[i];
 		if (context->target_flags[i].unchanged)
 			continue;
-		for (j = 0; j < target->stream_count; j++) {
-			struct core_stream *stream = target->streams[j];
+		for (j = 0; j < target->public.stream_count; j++) {
+			struct core_stream *stream =
+				DC_STREAM_TO_CORE(target->public.streams[j]);
 			struct core_link *link = stream->sink->link;
+
 			status = build_stream_hw_param(stream);
 
 			if (status != DC_OK)
@@ -1152,8 +1162,9 @@ enum dc_status dce110_validate_bandwidth(
 
 	for (i = 0; i < context->target_count; i++) {
 		struct core_target *target = context->targets[i];
-		for (j = 0; j < target->stream_count; j++) {
-			struct core_stream *stream = target->streams[j];
+		for (j = 0; j < target->public.stream_count; j++) {
+			struct core_stream *stream =
+				DC_STREAM_TO_CORE(target->public.streams[j]);
 			struct bw_calcs_input_single_display *disp = &context->
 				bw_mode_data.displays_data[number_of_displays];
 
@@ -1241,8 +1252,10 @@ static void set_target_unchanged(
 	uint8_t i;
 	struct core_target *target = context->targets[target_idx];
 	context->target_flags[target_idx].unchanged = true;
-	for (i = 0; i < target->stream_count; i++) {
-		uint8_t index = target->streams[i]->controller_idx;
+	for (i = 0; i < target->public.stream_count; i++) {
+		struct core_stream *core_stream =
+			DC_STREAM_TO_CORE(target->public.streams[i]);
+		uint8_t index = core_stream->controller_idx;
 		context->res_ctx.controller_ctx[index].flags.unchanged = true;
 	}
 }
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
index f18034c..b636a9c 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
@@ -46,8 +46,6 @@ struct core_target {
 	struct dc_target public;
 	struct dc_target_status status;
 
-	struct core_stream *streams[MAX_STREAMS];
-	uint8_t stream_count;
 	struct dc_context *ctx;
 };
 
-- 
2.7.4