From ed13095ec0b70870f9654f89939c73e8551746f4 Mon Sep 17 00:00:00 2001 From: Eric Yang Date: Mon, 17 Jul 2017 10:22:05 -0400 Subject: [PATCH 0625/4131] drm/amd/display: properly turn off unused mpc before front end programming MPCC_OPP_ID must be programmed to 0xf to properly turn off the mpcc. However the software state of the mpcc must keep track of the opp that the mpcc is attached to for reset to properly happen. This is kinda hacky right now, but a good solution may involve a lot of work. Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index d714422..cadc940 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1572,17 +1572,24 @@ static void dcn10_apply_ctx_for_surface( if ((!pipe_ctx->surface && old_pipe_ctx->surface) || (!pipe_ctx->stream && old_pipe_ctx->stream)) { struct mpcc_cfg mpcc_cfg; + int opp_id_cached = old_pipe_ctx->mpcc->opp_id; if (!old_pipe_ctx->top_pipe) { ASSERT(0); continue; } - mpcc_cfg.opp_id = old_pipe_ctx->mpcc->opp_id; + mpcc_cfg.opp_id = 0xf; mpcc_cfg.top_dpp_id = 0xf; mpcc_cfg.bot_mpcc_id = 0xf; mpcc_cfg.top_of_tree = !old_pipe_ctx->top_pipe; old_pipe_ctx->mpcc->funcs->set(old_pipe_ctx->mpcc, &mpcc_cfg); + /* + * the mpcc is the only thing that keeps track of the mpcc + * mapping for reset front end right now. Might need some + * rework. + */ + old_pipe_ctx->mpcc->opp_id = opp_id_cached; old_pipe_ctx->top_pipe = NULL; old_pipe_ctx->bottom_pipe = NULL; -- 2.7.4