From c53e0596eda73b050066bfe39fddbb59bd62a483 Mon Sep 17 00:00:00 2001 From: Eric Yang Date: Wed, 12 Jul 2017 18:38:04 -0400 Subject: [PATCH 0615/4131] drm/amd/display: fix mpo exit hang Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 82a96de..dbf9cea 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -500,8 +500,10 @@ static void reset_front_end( HUBP_CLOCK_ENABLE, 0); REG_UPDATE(DPP_CONTROL[fe_idx], DPP_CLOCK_ENABLE, 0); - REG_UPDATE(OPP_PIPE_CONTROL[opp_id], - OPP_PIPE_CLOCK_EN, 0); + + if (mpcc_cfg.top_of_tree) + REG_UPDATE(OPP_PIPE_CONTROL[opp_id], + OPP_PIPE_CLOCK_EN, 0); xfm->funcs->transform_reset(xfm); @@ -1584,7 +1586,7 @@ static void dcn10_apply_ctx_for_surface( int i; /* reset unused mpcc */ - /*for (i = 0; i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *old_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; @@ -1593,7 +1595,12 @@ static void dcn10_apply_ctx_for_surface( || (!pipe_ctx->stream && old_pipe_ctx->stream)) { struct mpcc_cfg mpcc_cfg; - mpcc_cfg.opp_id = 0xf; + if (!old_pipe_ctx->top_pipe) { + ASSERT(0); + continue; + } + + mpcc_cfg.opp_id = old_pipe_ctx->mpcc->opp_id; mpcc_cfg.top_dpp_id = 0xf; mpcc_cfg.bot_mpcc_id = 0xf; mpcc_cfg.top_of_tree = !old_pipe_ctx->top_pipe; @@ -1607,7 +1614,7 @@ static void dcn10_apply_ctx_for_surface( "Reset mpcc for pipe %d\n", old_pipe_ctx->pipe_idx); } - }*/ + } if (!surface) return; -- 2.7.4