From f80274b6e96d9a30220dcb1967bb80e10c6b5e22 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 28 Jun 2017 16:31:58 -0400 Subject: [PATCH 0570/4131] drm/amd/display: Rename DCN mem input specific function prefixes to min. Also updated relevant registers. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 96 ++++++++++------------ .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 93 +++++++++++++-------- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 6 +- 3 files changed, 104 insertions(+), 91 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c index a58993a..b7ecfad 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c @@ -38,7 +38,7 @@ #define FN(reg_name, field_name) \ mi->mi_shift->field_name, mi->mi_mask->field_name -static void dcn_mi_set_blank(struct mem_input *mem_input, bool blank) +static void min10_set_blank(struct mem_input *mem_input, bool blank) { struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); uint32_t blank_en = blank ? 1 : 0; @@ -48,7 +48,7 @@ static void dcn_mi_set_blank(struct mem_input *mem_input, bool blank) HUBP_TTU_DISABLE, blank_en); } -static void vready_workaround(struct mem_input *mem_input, +static void min10_vready_workaround(struct mem_input *mem_input, struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) { uint32_t value = 0; @@ -71,7 +71,7 @@ static void vready_workaround(struct mem_input *mem_input, REG_WRITE(HUBPREQ_DEBUG_DB, value); } -static void program_tiling( +static void min10_program_tiling( struct dcn10_mem_input *mi, const union dc_tiling_info *info, const enum surface_pixel_format pixel_format) @@ -91,7 +91,7 @@ static void program_tiling( PIPE_ALIGNED, info->gfx9.pipe_aligned); } -static void program_size_and_rotation( +static void min10_program_size_and_rotation( struct dcn10_mem_input *mi, enum dc_rotation_angle rotation, enum surface_pixel_format format, @@ -153,7 +153,7 @@ static void program_size_and_rotation( H_MIRROR_EN, mirror); } -static void program_pixel_format( +static void min10_program_pixel_format( struct dcn10_mem_input *mi, enum surface_pixel_format format) { @@ -229,7 +229,7 @@ static void program_pixel_format( /* don't see the need of program the xbar in DCN 1.0 */ } -static bool mem_input_program_surface_flip_and_addr( +static bool min10_program_surface_flip_and_addr( struct mem_input *mem_input, const struct dc_plane_address *address, bool flip_immediate) @@ -369,7 +369,7 @@ static bool mem_input_program_surface_flip_and_addr( return true; } -static void dcc_control(struct mem_input *mem_input, bool enable, +static void min10_dcc_control(struct mem_input *mem_input, bool enable, bool independent_64b_blks) { uint32_t dcc_en = enable ? 1 : 0; @@ -381,13 +381,7 @@ static void dcc_control(struct mem_input *mem_input, bool enable, PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); } -static void program_control(struct dcn10_mem_input *mi, - struct dc_plane_dcc_param *dcc) -{ - dcc_control(&mi->base, dcc->enable, dcc->grph.independent_64b_blks); -} - -static void mem_input_program_surface_config( +static void min10_program_surface_config( struct mem_input *mem_input, enum surface_pixel_format format, union dc_tiling_info *tiling_info, @@ -398,14 +392,14 @@ static void mem_input_program_surface_config( { struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); - program_control(mi, dcc); - program_tiling(mi, tiling_info, format); - program_size_and_rotation( + min10_dcc_control(mem_input, dcc->enable, dcc->grph.independent_64b_blks); + min10_program_tiling(mi, tiling_info, format); + min10_program_size_and_rotation( mi, rotation, format, plane_size, dcc, horizontal_mirror); - program_pixel_format(mi, format); + min10_program_pixel_format(mi, format); } -static void program_requestor( +static void min10_program_requestor( struct mem_input *mem_input, struct _vcs_dpi_display_rq_regs_st *rq_regs) { @@ -440,7 +434,7 @@ static void program_requestor( } -static void program_deadline( +static void min10_program_deadline( struct mem_input *mem_input, struct _vcs_dpi_display_dlg_regs_st *dlg_attr, struct _vcs_dpi_display_ttu_regs_st *ttu_attr) @@ -552,7 +546,7 @@ static void program_deadline( ttu_attr->refcyc_per_req_delivery_pre_c); } -static void mem_input_setup( +static void min10_setup( struct mem_input *mem_input, struct _vcs_dpi_display_dlg_regs_st *dlg_attr, struct _vcs_dpi_display_ttu_regs_st *ttu_attr, @@ -562,9 +556,9 @@ static void mem_input_setup( /* otg is locked when this func is called. Register are double buffered. * disable the requestors is not needed */ - program_requestor(mem_input, rq_regs); - program_deadline(mem_input, dlg_attr, ttu_attr); - vready_workaround(mem_input, pipe_dest); + min10_program_requestor(mem_input, rq_regs); + min10_program_deadline(mem_input, dlg_attr, ttu_attr); + min10_vready_workaround(mem_input, pipe_dest); } static uint32_t convert_and_clamp( @@ -582,7 +576,7 @@ static uint32_t convert_and_clamp( return ret_val; } -static void program_watermarks( +static void min10_program_watermarks( struct mem_input *mem_input, struct dcn_watermark_set *watermarks, unsigned int refclk_mhz) @@ -811,7 +805,7 @@ static void program_watermarks( #endif } -static void mem_input_program_display_marks( +static void min10_program_display_marks( struct mem_input *mem_input, struct dce_watermarks nbp, struct dce_watermarks stutter, @@ -823,14 +817,14 @@ static void mem_input_program_display_marks( */ } -bool mem_input_is_flip_pending(struct mem_input *mem_input) +static bool min10_is_flip_pending(struct mem_input *mem_input) { - uint32_t update_pending = 0; + uint32_t flip_pending = 0; struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); struct dc_plane_address earliest_inuse_address; REG_GET(DCSURF_FLIP_CONTROL, - SURFACE_UPDATE_PENDING, &update_pending); + SURFACE_FLIP_PENDING, &flip_pending); REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); @@ -838,7 +832,7 @@ bool mem_input_is_flip_pending(struct mem_input *mem_input) REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); - if (update_pending) + if (flip_pending) return true; if (earliest_inuse_address.grph.addr.quad_part != mem_input->request_address.grph.addr.quad_part) @@ -848,7 +842,7 @@ bool mem_input_is_flip_pending(struct mem_input *mem_input) return false; } -static void mem_input_update_dchub( +static void min10_update_dchub( struct mem_input *mem_input, struct dchub_init_data *dh_data) { @@ -911,7 +905,7 @@ struct vm_system_aperture_param { PHYSICAL_ADDRESS_LOC sys_high; }; -static void read_vm_system_aperture_settings(struct dcn10_mem_input *mi, +static void min10_read_vm_system_aperture_settings(struct dcn10_mem_input *mi, struct vm_system_aperture_param *apt) { PHYSICAL_ADDRESS_LOC physical_page_number; @@ -934,7 +928,7 @@ static void read_vm_system_aperture_settings(struct dcn10_mem_input *mi, apt->sys_high.quad_part = (int64_t)logical_addr_high << 18; } -static void set_vm_system_aperture_settings(struct dcn10_mem_input *mi, +static void min10_set_vm_system_aperture_settings(struct dcn10_mem_input *mi, struct vm_system_aperture_param *apt) { PHYSICAL_ADDRESS_LOC mc_vm_apt_default; @@ -970,7 +964,7 @@ struct vm_context0_param { }; /* Temporary read settings, future will get values from kmd directly */ -static void read_vm_context0_settings(struct dcn10_mem_input *mi, +static void min10_read_vm_context0_settings(struct dcn10_mem_input *mi, struct vm_context0_param *vm0) { PHYSICAL_ADDRESS_LOC fb_base; @@ -1013,7 +1007,7 @@ static void read_vm_context0_settings(struct dcn10_mem_input *mi, vm0->pte_base.quad_part -= fb_offset.quad_part; } -static void set_vm_context0_settings(struct dcn10_mem_input *mi, +static void min10_set_vm_context0_settings(struct dcn10_mem_input *mi, const struct vm_context0_param *vm0) { /* pte base */ @@ -1042,7 +1036,7 @@ static void set_vm_context0_settings(struct dcn10_mem_input *mi, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part); } -void dcn_mem_input_program_pte_vm(struct mem_input *mem_input, +static void min10_program_pte_vm(struct mem_input *mem_input, enum surface_pixel_format format, union dc_tiling_info *tiling_info, enum dc_rotation_angle rotation) @@ -1052,11 +1046,11 @@ void dcn_mem_input_program_pte_vm(struct mem_input *mem_input, struct vm_context0_param vm0 = { { { 0 } } }; - read_vm_system_aperture_settings(mi, &apt); - read_vm_context0_settings(mi, &vm0); + min10_read_vm_system_aperture_settings(mi, &apt); + min10_read_vm_context0_settings(mi, &vm0); - set_vm_system_aperture_settings(mi, &apt); - set_vm_context0_settings(mi, &vm0); + min10_set_vm_system_aperture_settings(mi, &apt); + min10_set_vm_context0_settings(mi, &vm0); /* control: enable VM PTE*/ REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, @@ -1065,20 +1059,18 @@ void dcn_mem_input_program_pte_vm(struct mem_input *mem_input, } static struct mem_input_funcs dcn10_mem_input_funcs = { - .mem_input_program_display_marks = mem_input_program_display_marks, - .allocate_mem_input = NULL, - .free_mem_input = NULL, + .mem_input_program_display_marks = min10_program_display_marks, .mem_input_program_surface_flip_and_addr = - mem_input_program_surface_flip_and_addr, + min10_program_surface_flip_and_addr, .mem_input_program_surface_config = - mem_input_program_surface_config, - .mem_input_is_flip_pending = mem_input_is_flip_pending, - .mem_input_setup = mem_input_setup, - .program_watermarks = program_watermarks, - .mem_input_update_dchub = mem_input_update_dchub, - .mem_input_program_pte_vm = dcn_mem_input_program_pte_vm, - .set_blank = dcn_mi_set_blank, - .dcc_control = dcc_control, + min10_program_surface_config, + .mem_input_is_flip_pending = min10_is_flip_pending, + .mem_input_setup = min10_setup, + .program_watermarks = min10_program_watermarks, + .mem_input_update_dchub = min10_update_dchub, + .mem_input_program_pte_vm = min10_program_pte_vm, + .set_blank = min10_set_blank, + .dcc_control = min10_dcc_control, }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h index 9e2f1bb..c3f18bd 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h @@ -31,7 +31,7 @@ container_of(mi, struct dcn10_mem_input, base) -#define MI_DCN10_REG_LIST(id)\ +#define MI_REG_LIST_DCN(id)\ SRI(DCHUBP_CNTL, HUBP, id),\ SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ @@ -93,27 +93,7 @@ SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\ SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\ SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\ SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\ - SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\ - SR(DCHUBBUB_SDPIF_FB_TOP),\ - SR(DCHUBBUB_SDPIF_FB_BASE),\ - SR(DCHUBBUB_SDPIF_FB_OFFSET),\ - SR(DCHUBBUB_SDPIF_AGP_BASE),\ - SR(DCHUBBUB_SDPIF_AGP_BOT),\ - SR(DCHUBBUB_SDPIF_AGP_TOP),\ SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\ SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\ @@ -152,6 +132,29 @@ MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) +#define MI_REG_LIST_DCN10(id)\ + MI_REG_LIST_DCN(id),\ + SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\ + SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\ + SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\ + SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\ + SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\ + SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\ + SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\ + SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\ + SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\ + SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\ + SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\ + SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\ + SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\ + SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\ + SR(DCHUBBUB_SDPIF_FB_TOP),\ + SR(DCHUBBUB_SDPIF_FB_BASE),\ + SR(DCHUBBUB_SDPIF_FB_OFFSET),\ + SR(DCHUBBUB_SDPIF_AGP_BASE),\ + SR(DCHUBBUB_SDPIF_AGP_BOT),\ + SR(DCHUBBUB_SDPIF_AGP_TOP) + struct dcn_mi_registers { uint32_t DCHUBP_CNTL; uint32_t HUBPREQ_DEBUG_DB; @@ -229,12 +232,20 @@ struct dcn_mi_registers { uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB; uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB; uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; + uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; + uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; uint32_t DCHUBBUB_SDPIF_FB_TOP; uint32_t DCHUBBUB_SDPIF_FB_BASE; uint32_t DCHUBBUB_SDPIF_FB_OFFSET; uint32_t DCHUBBUB_SDPIF_AGP_BASE; uint32_t DCHUBBUB_SDPIF_AGP_BOT; uint32_t DCHUBBUB_SDPIF_AGP_TOP; + uint32_t DCN_VM_FB_LOCATION_TOP; + uint32_t DCN_VM_FB_LOCATION_BASE; + uint32_t DCN_VM_FB_OFFSET; + uint32_t DCN_VM_AGP_BASE; + uint32_t DCN_VM_AGP_BOT; + uint32_t DCN_VM_AGP_TOP; uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A; uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A; uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A; @@ -278,7 +289,7 @@ struct dcn_mi_registers { #define MI_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix -#define MI_DCN10_MASK_SH_LIST(mask_sh)\ +#define MI_MASK_SH_LIST_DCN(mask_sh)\ MI_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ MI_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\ @@ -299,7 +310,7 @@ struct dcn_mi_registers { MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\ MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_PENDING, mask_sh),\ + MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\ MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\ MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\ @@ -382,6 +393,17 @@ struct dcn_mi_registers { MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ + MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ + MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\ + MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh),\ + MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh),\ + MI_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh),\ + MI_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh),\ + MI_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh),\ + MI_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh) + +#define MI_MASK_SH_LIST_DCN10(mask_sh)\ + MI_MASK_SH_LIST_DCN(mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\ @@ -390,11 +412,6 @@ struct dcn_mi_registers { MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ @@ -405,12 +422,9 @@ struct dcn_mi_registers { MI_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh),\ MI_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh),\ MI_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh),\ - MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh),\ - MI_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh),\ - MI_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh),\ - MI_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh),\ - MI_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh),\ - MI_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh),\ + MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ + MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ + MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ /* todo: get these from GVM instead of reading registers ourselves */\ MI_SF(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ MI_SF(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ @@ -444,7 +458,7 @@ struct dcn_mi_registers { type SURFACE_PIXEL_FORMAT;\ type SURFACE_FLIP_TYPE;\ type SURFACE_UPDATE_LOCK;\ - type SURFACE_UPDATE_PENDING;\ + type SURFACE_FLIP_PENDING;\ type PRIMARY_SURFACE_ADDRESS_HIGH;\ type PRIMARY_SURFACE_ADDRESS;\ type SECONDARY_SURFACE_ADDRESS_HIGH;\ @@ -543,12 +557,20 @@ struct dcn_mi_registers { type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\ type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\ type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\ + type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\ + type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\ type SDPIF_FB_TOP;\ type SDPIF_FB_BASE;\ type SDPIF_FB_OFFSET;\ type SDPIF_AGP_BASE;\ type SDPIF_AGP_BOT;\ type SDPIF_AGP_TOP;\ + type FB_TOP;\ + type FB_BASE;\ + type FB_OFFSET;\ + type AGP_BASE;\ + type AGP_BOT;\ + type AGP_TOP;\ type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\ type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\ type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\ @@ -589,5 +611,4 @@ bool dcn10_mem_input_construct( const struct dcn_mi_shift *mi_shift, const struct dcn_mi_mask *mi_mask); - #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index a0dd75d..b0888a8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -374,7 +374,7 @@ static const struct bios_registers bios_regs = { #define mi_regs(id)\ [id] = {\ - MI_DCN10_REG_LIST(id)\ + MI_REG_LIST_DCN10(id)\ } @@ -386,11 +386,11 @@ static const struct dcn_mi_registers mi_regs[] = { }; static const struct dcn_mi_shift mi_shift = { - MI_DCN10_MASK_SH_LIST(__SHIFT) + MI_MASK_SH_LIST_DCN10(__SHIFT) }; static const struct dcn_mi_mask mi_mask = { - MI_DCN10_MASK_SH_LIST(_MASK) + MI_MASK_SH_LIST_DCN10(_MASK) }; #define clk_src_regs(index, pllid)\ -- 2.7.4