From bdabcadfa39f2b8772276d3ba5d852a3a8cad74f Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 14 Mar 2017 12:30:29 -0400 Subject: [PATCH 0287/4131] drm/amd/display: remove dc_pre_update_surfaces_to_stream from dc use Signed-off-by: Dmytro Laktyushkin Acked-by: Harry Wentland Reviewed-by: Dmytro Laktyushkin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 115 ++------------------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 45 -------- .../drm/amd/display/dc/dce110/dce110_resource.c | 48 +++++++-- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 - 6 files changed, 54 insertions(+), 169 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 26f227d..6409d4d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -900,106 +900,7 @@ bool dc_pre_update_surfaces_to_stream( uint8_t new_surface_count, const struct dc_stream *dc_stream) { - int i, j; - struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_stream_status *stream_status = NULL; - struct validate_context *context; - bool ret = true; - - pre_surface_trace(dc, new_surfaces, new_surface_count); - - if (core_dc->current_context->stream_count == 0) - return false; - - /* Cannot commit surface to a stream that is not commited */ - for (i = 0; i < core_dc->current_context->stream_count; i++) - if (dc_stream == &core_dc->current_context->streams[i]->public) - break; - - if (i == core_dc->current_context->stream_count) - return false; - - stream_status = &core_dc->current_context->stream_status[i]; - - if (new_surface_count == stream_status->surface_count) { - bool skip_pre = true; - - for (i = 0; i < stream_status->surface_count; i++) { - struct dc_surface temp_surf = { 0 }; - - temp_surf = *stream_status->surfaces[i]; - temp_surf.clip_rect = new_surfaces[i]->clip_rect; - temp_surf.dst_rect.x = new_surfaces[i]->dst_rect.x; - temp_surf.dst_rect.y = new_surfaces[i]->dst_rect.y; - - if (memcmp(&temp_surf, new_surfaces[i], sizeof(temp_surf)) != 0) { - skip_pre = false; - break; - } - } - - if (skip_pre) - return true; - } - - context = dm_alloc(sizeof(struct validate_context)); - - if (!context) { - dm_error("%s: failed to create validate ctx\n", __func__); - ret = false; - goto val_ctx_fail; - } - - resource_validate_ctx_copy_construct(core_dc->current_context, context); - - dm_logger_write(core_dc->ctx->logger, LOG_DC, - "%s: commit %d surfaces to stream 0x%x\n", - __func__, - new_surface_count, - dc_stream); - - if (!resource_attach_surfaces_to_context( - new_surfaces, new_surface_count, dc_stream, context)) { - BREAK_TO_DEBUGGER(); - ret = false; - goto unexpected_fail; - } - - for (i = 0; i < new_surface_count; i++) - for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { - if (context->res_ctx.pipe_ctx[j].surface != - DC_SURFACE_TO_CORE(new_surfaces[i])) - continue; - - resource_build_scaling_params(&context->res_ctx.pipe_ctx[j]); - } - - if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { - BREAK_TO_DEBUGGER(); - ret = false; - goto unexpected_fail; - } - - core_dc->hwss.set_bandwidth(core_dc, context, false); - - for (i = 0; i < new_surface_count; i++) - for (j = 0; j < context->res_ctx.pool->pipe_count; j++) { - if (context->res_ctx.pipe_ctx[j].surface != - DC_SURFACE_TO_CORE(new_surfaces[i])) - continue; - - core_dc->hwss.prepare_pipe_for_context( - core_dc, - &context->res_ctx.pipe_ctx[j], - context); - } - -unexpected_fail: - resource_validate_ctx_destruct(context); - dm_free(context); -val_ctx_fail: - - return ret; + return true; } bool dc_post_update_surfaces_to_stream(struct dc *dc) @@ -1050,10 +951,6 @@ bool dc_commit_surfaces_to_stream( struct dc_scaling_info scaling_info[MAX_SURFACES]; int i; - if (!dc_pre_update_surfaces_to_stream( - dc, new_surfaces, new_surface_count, dc_stream)) - return false; - memset(updates, 0, sizeof(updates)); memset(flip_addr, 0, sizeof(flip_addr)); memset(plane_info, 0, sizeof(plane_info)); @@ -1423,10 +1320,12 @@ void dc_update_surfaces_and_stream(struct dc *dc, *(srf_updates[i].hdr_static_metadata); } - if (update_type == UPDATE_TYPE_FULL && - !core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { - BREAK_TO_DEBUGGER(); - return; + if (update_type == UPDATE_TYPE_FULL) { + if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) { + BREAK_TO_DEBUGGER(); + return; + } else + core_dc->hwss.set_bandwidth(core_dc, context, false); } if (!surface_count) /* reset */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index ad37d0e..6700d6b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -900,10 +900,11 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( * that has no surface attached yet */ static struct pipe_ctx *acquire_free_pipe_for_stream( - struct resource_context *res_ctx, + struct validate_context *context, const struct dc_stream *dc_stream) { int i; + struct resource_context *res_ctx = &context->res_ctx; struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct pipe_ctx *head_pipe = NULL; @@ -934,7 +935,7 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( if(!res_ctx->pool->funcs->acquire_idle_pipe_for_layer) return NULL; - return res_ctx->pool->funcs->acquire_idle_pipe_for_layer(res_ctx, stream); + return res_ctx->pool->funcs->acquire_idle_pipe_for_layer(context, stream); } @@ -1001,8 +1002,7 @@ bool resource_attach_surfaces_to_context( tail_pipe = NULL; for (i = 0; i < surface_count; i++) { struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]); - struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( - &context->res_ctx, dc_stream); + struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream(context, dc_stream); if (!free_pipe) { stream_status->surfaces[i] = NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index cb7a673e..e5e52c7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -2094,50 +2094,6 @@ static void init_hw(struct core_dc *dc) } } -static void dce110_power_on_pipe_if_needed( - struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) -{ - struct pipe_ctx *old_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; - struct dc_bios *dcb = dc->ctx->dc_bios; - struct tg_color black_color = {0}; - - if (!old_pipe_ctx->stream && pipe_ctx->stream) { - dc->hwss.enable_display_power_gating( - dc, - pipe_ctx->pipe_idx, - dcb, PIPE_GATING_CONTROL_DISABLE); - - /* - * This is for powering on underlay, so crtc does not - * need to be enabled - */ - - pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg, - &pipe_ctx->stream->public.timing, - false); - - pipe_ctx->tg->funcs->enable_advanced_request( - pipe_ctx->tg, - true, - &pipe_ctx->stream->public.timing); - - pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi, - pipe_ctx->stream->public.timing.h_total, - pipe_ctx->stream->public.timing.v_total, - pipe_ctx->stream->public.timing.pix_clk_khz, - context->stream_count); - - /* TODO unhardcode*/ - color_space_to_black_color(dc, - COLOR_SPACE_YCBCR601, &black_color); - pipe_ctx->tg->funcs->set_blank_color( - pipe_ctx->tg, - &black_color); - } -} - static void fill_display_configs( const struct validate_context *context, struct dm_pp_display_configuration *pp_display_cfg) @@ -2481,7 +2437,6 @@ static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe) static const struct hw_sequencer_funcs dce110_funcs = { .init_hw = init_hw, .apply_ctx_to_hw = dce110_apply_ctx_to_hw, - .prepare_pipe_for_context = dce110_power_on_pipe_if_needed, .apply_ctx_for_surface = dce110_apply_ctx_for_surface, .set_plane_config = set_plane_config, .update_plane_addr = update_plane_addr, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index b9d0b5e..e300203 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1111,16 +1111,17 @@ enum dc_status dce110_validate_guaranteed( return result; } -static struct pipe_ctx *dce110_acquire_idle_pipe_for_layer( - struct resource_context *res_ctx, +static struct pipe_ctx *dce110_acquire_underlay( + struct validate_context *context, struct core_stream *stream) { + struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); + struct resource_context *res_ctx = &context->res_ctx; unsigned int underlay_idx = res_ctx->pool->underlay_pipe_index; struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; - if (res_ctx->pipe_ctx[underlay_idx].stream) { + if (res_ctx->pipe_ctx[underlay_idx].stream) return NULL; - } pipe_ctx->tg = res_ctx->pool->timing_generators[underlay_idx]; pipe_ctx->mi = res_ctx->pool->mis[underlay_idx]; @@ -1132,8 +1133,43 @@ static struct pipe_ctx *dce110_acquire_idle_pipe_for_layer( pipe_ctx->stream = stream; - return pipe_ctx; + if (!dc->current_context->res_ctx.pipe_ctx[underlay_idx].stream) { + struct tg_color black_color = {0}; + struct dc_bios *dcb = dc->ctx->dc_bios; + + dc->hwss.enable_display_power_gating( + dc, + pipe_ctx->pipe_idx, + dcb, PIPE_GATING_CONTROL_DISABLE); + + /* + * This is for powering on underlay, so crtc does not + * need to be enabled + */ + + pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg, + &stream->public.timing, + false); + + pipe_ctx->tg->funcs->enable_advanced_request( + pipe_ctx->tg, + true, + &stream->public.timing); + + pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi, + stream->public.timing.h_total, + stream->public.timing.v_total, + stream->public.timing.pix_clk_khz, + context->stream_count); + + color_space_to_black_color(dc, + COLOR_SPACE_YCBCR601, &black_color); + pipe_ctx->tg->funcs->set_blank_color( + pipe_ctx->tg, + &black_color); + } + return pipe_ctx; } static void dce110_destroy_resource_pool(struct resource_pool **pool) @@ -1152,7 +1188,7 @@ static const struct resource_funcs dce110_res_pool_funcs = { .validate_with_context = dce110_validate_with_context, .validate_guaranteed = dce110_validate_guaranteed, .validate_bandwidth = dce110_validate_bandwidth, - .acquire_idle_pipe_for_layer = dce110_acquire_idle_pipe_for_layer, + .acquire_idle_pipe_for_layer = dce110_acquire_underlay, .build_bit_depth_reduction_params = dce110_resource_build_bit_depth_reduction_params }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index faec229..7f3c6da 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -210,7 +210,7 @@ struct resource_funcs { struct validate_context *context); struct pipe_ctx *(*acquire_idle_pipe_for_layer)( - struct resource_context *res_ctx, + struct validate_context *context, struct core_stream *stream); void (*build_bit_depth_reduction_params)( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 98a04cd..bcb2672 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -57,11 +57,6 @@ struct hw_sequencer_funcs { void (*reset_hw_ctx_wrap)( struct core_dc *dc, struct validate_context *context); - void (*prepare_pipe_for_context)( - struct core_dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context); - void (*apply_ctx_for_surface)( struct core_dc *dc, struct core_surface *surface, -- 2.7.4