From 0e2f792c9b2feea587fd068e98c6204efc20619e Mon Sep 17 00:00:00 2001 From: Jordan Lazare Date: Wed, 16 Mar 2016 13:44:46 -0400 Subject: [PATCH 0974/1110] drm/amd/dal: Filter HDMI@4k60 for dce10 Refactor code to use hdmi pixel clock maximums per dce Signed-off-by: Jordan Lazare Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dc/dce100/Makefile | 2 +- .../drm/amd/dal/dc/dce100/dce100_link_encoder.c | 89 ++++++++++++++++++++++ .../drm/amd/dal/dc/dce100/dce100_link_encoder.h | 42 ++++++++++ .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 9 +-- .../drm/amd/dal/dc/dce110/dce110_link_encoder.c | 32 +++----- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 5 -- .../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 5 -- .../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c | 5 ++ drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 5 -- drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 7 -- drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h | 4 +- 11 files changed, 153 insertions(+), 52 deletions(-) create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/Makefile b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile index 656c38e..5fb7e7b 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce100/Makefile +++ b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile @@ -2,7 +2,7 @@ # Makefile for the 'controller' sub-component of DAL. # It provides the control and status of HW CRTC block. -DCE100 = dce100_resource.o dce100_hw_sequencer.o +DCE100 = dce100_resource.o dce100_hw_sequencer.o dce100_link_encoder.o AMD_DAL_DCE100 = $(addprefix $(AMDDALPATH)/dc/dce100/,$(DCE100)) diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c new file mode 100644 index 0000000..5f294ee --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c @@ -0,0 +1,89 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "core_types.h" +#include "dce100_link_encoder.h" +#include "stream_encoder.h" +#include "../dce110/dce110_link_encoder.h" +#include "i2caux_interface.h" + +/* TODO: change to dce80 header file */ +#include "dce/dce_10_0_d.h" +#include "dce/dce_10_0_sh_mask.h" +#include "dce/dce_10_0_enum.h" + +#define LINK_REG(reg)\ + (enc110->link_regs->reg) + +#define DCE10_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 300000 + + +static struct link_encoder_funcs dce100_lnk_enc_funcs = { + .validate_output_with_stream = + dce110_link_encoder_validate_output_with_stream, + .hw_init = dce110_link_encoder_hw_init, + .setup = dce110_link_encoder_setup, + .enable_tmds_output = dce110_link_encoder_enable_tmds_output, + .enable_dp_output = dce110_link_encoder_enable_dp_output, + .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output, + .disable_output = dce110_link_encoder_disable_output, + .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, + .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern, + .update_mst_stream_allocation_table = + dce110_link_encoder_update_mst_stream_allocation_table, + .set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level, + .backlight_control = dce110_link_encoder_edp_backlight_control, + .power_control = dce110_link_encoder_edp_power_control, + .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, + .destroy = dce110_link_encoder_destroy +}; + +bool dce100_link_encoder_construct( + struct dce110_link_encoder *enc110, + const struct encoder_init_data *init_data, + const struct dce110_link_enc_registers *link_regs, + const struct dce110_link_enc_aux_registers *aux_regs, + const struct dce110_link_enc_bl_registers *bl_regs) +{ + dce110_link_encoder_construct( + enc110, + init_data, + link_regs, + aux_regs, + bl_regs); + + enc110->base.funcs = &dce100_lnk_enc_funcs; + + enc110->base.features.flags.bits.IS_HBR3_CAPABLE = false; + enc110->base.features.flags.bits.IS_TPS4_CAPABLE = false; + + enc110->base.features.max_hdmi_pixel_clock = + DCE10_UNIPHY_MAX_PIXEL_CLK_IN_KHZ; + enc110->base.features.max_deep_color = COLOR_DEPTH_121212; + enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212; + + return true; +} diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h new file mode 100644 index 0000000..ae0712f --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h @@ -0,0 +1,42 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_LINK_ENCODER__DCE100_H__ +#define __DC_LINK_ENCODER__DCE100_H__ + +#include "link_encoder.h" +#include "../dce110/dce110_link_encoder.h" + +#define TO_DCE100_LINK_ENC(link_encoder)\ + container_of(link_encoder, struct dce100_link_encoder, base) + +bool dce100_link_encoder_construct( + struct dce110_link_encoder *enc110, + const struct encoder_init_data *init_data, + const struct dce110_link_enc_registers *link_regs, + const struct dce110_link_enc_aux_registers *aux_regs, + const struct dce110_link_enc_bl_registers *bl_regs); + +#endif /* __DC_LINK_ENCODER__DCE100_H__ */ diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c index a4dba58..5185e91 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c @@ -39,6 +39,7 @@ #include "dce110/dce110_mem_input_v.h" #include "dce110/dce110_ipp.h" #include "dce110/dce110_transform.h" +#include "dce100/dce100_link_encoder.h" #include "dce110/dce110_stream_encoder.h" #include "dce110/dce110_opp.h" #include "dce110/dce110_clock_source.h" @@ -442,7 +443,7 @@ struct link_encoder *dce100_link_encoder_create( if (!enc110) return NULL; - if (dce110_link_encoder_construct( + if (dce100_link_encoder_construct( enc110, enc_init_data, &link_enc_regs[enc_init_data->transmitter], @@ -683,11 +684,6 @@ static void get_pixel_clock_parameters( static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) { - /*TODO: unhardcode*/ - pipe_ctx->max_tmds_clk_from_edid_in_mhz = 0; - pipe_ctx->max_hdmi_deep_color = COLOR_DEPTH_121212; - pipe_ctx->max_hdmi_pixel_clock = 600000; - get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params); pipe_ctx->clock_source->funcs->get_pix_clk_dividers( pipe_ctx->clock_source, @@ -741,7 +737,6 @@ static enum dc_status validate_mapped_resource( return DC_FAIL_ENC_VALIDATE; /* TODO: validate audio ASIC caps, encoder */ - status = dc_link_validate_mode_timing(stream->sink, link, &stream->public.timing); diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c index 0e5588a..8da3e4d 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c +++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c @@ -929,20 +929,13 @@ static bool validate_dvi_output( static bool validate_hdmi_output( const struct dce110_link_encoder *enc110, - const struct dc_crtc_timing *crtc_timing, - uint32_t max_tmds_clk_from_edid_in_mhz, - enum dc_color_depth max_hdmi_deep_color, - uint32_t max_hdmi_pixel_clock) + const struct dc_crtc_timing *crtc_timing) { - enum dc_color_depth max_deep_color = max_hdmi_deep_color; + enum dc_color_depth max_deep_color = + enc110->base.features.max_hdmi_deep_color; /* expressed in KHz */ uint32_t pixel_clock = 0; - /*TODO: unhardcode*/ - max_tmds_clk_from_edid_in_mhz = 0; - max_hdmi_deep_color = COLOR_DEPTH_121212; - max_hdmi_pixel_clock = 600000; - if (max_deep_color > enc110->base.features.max_deep_color) max_deep_color = enc110->base.features.max_deep_color; @@ -972,12 +965,8 @@ static bool validate_hdmi_output( break; } - if (max_tmds_clk_from_edid_in_mhz > 0) - if (pixel_clock > max_tmds_clk_from_edid_in_mhz * 1000) - return false; - if ((pixel_clock == 0) || - (pixel_clock > max_hdmi_pixel_clock) || + (pixel_clock > enc110->base.features.max_hdmi_pixel_clock) || (pixel_clock > enc110->base.features.max_pixel_clock)) return false; @@ -1081,7 +1070,12 @@ bool dce110_link_encoder_construct( enc110->base.features.flags.bits.IS_AUDIO_CAPABLE = true; enc110->base.features.max_pixel_clock = - DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ; + MAX_ENCODER_CLK; + + enc110->base.features.max_hdmi_pixel_clock = + DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ; + enc110->base.features.max_deep_color = COLOR_DEPTH_121212; + enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212; /* set the flag to indicate whether driver poll the I2C data pin * while doing the DP sink detect @@ -1156,7 +1150,6 @@ bool dce110_link_encoder_construct( /* test pattern 3 support */ enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true; - enc110->base.features.max_deep_color = COLOR_DEPTH_121212; enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE = dal_adapter_service_is_feature_supported( @@ -1188,10 +1181,7 @@ bool dce110_link_encoder_validate_output_with_stream( case SIGNAL_TYPE_HDMI_TYPE_A: is_valid = validate_hdmi_output( enc110, - &stream->public.timing, - pipe_ctx->max_tmds_clk_from_edid_in_mhz, - pipe_ctx->max_hdmi_deep_color, - pipe_ctx->max_hdmi_pixel_clock); + &stream->public.timing); break; case SIGNAL_TYPE_RGB: is_valid = validate_rgb_output( diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c index b8fc445..ccf6bd8 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c @@ -630,11 +630,6 @@ static void get_pixel_clock_parameters( static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) { - /*TODO: unhardcode*/ - pipe_ctx->max_tmds_clk_from_edid_in_mhz = 0; - pipe_ctx->max_hdmi_deep_color = COLOR_DEPTH_121212; - pipe_ctx->max_hdmi_pixel_clock = 600000; - get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params); pipe_ctx->clock_source->funcs->get_pix_clk_dividers( pipe_ctx->clock_source, diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c index 420b8ca..7b3dee1 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c @@ -723,11 +723,6 @@ static void get_pixel_clock_parameters( static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) { - /*TODO: unhardcode*/ - pipe_ctx->max_tmds_clk_from_edid_in_mhz = 0; - pipe_ctx->max_hdmi_deep_color = COLOR_DEPTH_121212; - pipe_ctx->max_hdmi_pixel_clock = 600000; - get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params); pipe_ctx->clock_source->funcs->get_pix_clk_dividers( pipe_ctx->clock_source, diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c index e25fca2..4615c34 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c +++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c @@ -239,6 +239,11 @@ bool dce80_link_encoder_construct( enc110->base.features.max_pixel_clock = DCE8_UNIPHY_MAX_PIXEL_CLK_IN_KHZ; + enc110->base.features.max_hdmi_pixel_clock = + DCE8_UNIPHY_MAX_PIXEL_CLK_IN_KHZ; + enc110->base.features.max_deep_color = COLOR_DEPTH_121212; + enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212; + /* set the flag to indicate whether driver poll the I2C data pin * while doing the DP sink detect */ diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c index 311f5fa..56487fd 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c @@ -641,11 +641,6 @@ static void get_pixel_clock_parameters( static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) { - /*TODO: unhardcode*/ - pipe_ctx->max_tmds_clk_from_edid_in_mhz = 0; - pipe_ctx->max_hdmi_deep_color = COLOR_DEPTH_121212; - pipe_ctx->max_hdmi_pixel_clock = 600000; - get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->pix_clk_params); pipe_ctx->clock_source->funcs->get_pix_clk_dividers( pipe_ctx->clock_source, diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h index 4ec6192..14b62ab 100644 --- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h @@ -303,13 +303,6 @@ struct pipe_ctx { enum signal_type signal; - /* timing validation (HDMI only) */ - uint32_t max_tmds_clk_from_edid_in_mhz; - /* maximum supported deep color depth for HDMI */ - enum dc_color_depth max_hdmi_deep_color; - /* maximum supported pixel clock for HDMI */ - uint32_t max_hdmi_pixel_clock; - struct pixel_clk_params pix_clk_params; struct pll_settings pll_settings; diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h index 24d318d..115ef54 100644 --- a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h @@ -60,8 +60,10 @@ struct encoder_feature_support { } flags; /* maximum supported deep color depth */ enum dc_color_depth max_deep_color; + enum dc_color_depth max_hdmi_deep_color; /* maximum supported clock */ - uint32_t max_pixel_clock; + unsigned int max_pixel_clock; + unsigned int max_hdmi_pixel_clock; }; struct link_enc_status { -- 2.7.4