From a8dbea4b89559bc636b7f78c23a61738a3b87ee5 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 22 Jan 2016 10:58:47 -0500 Subject: [PATCH 0728/1110] drm/amd/dal: OPP refactoring Signed-off-by: Andrey Grodzovsky Acked-by: Harry Wentland --- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 77 +++++++++++++++++- .../gpu/drm/amd/dal/dc/dce100/dce100_resource.h | 1 + .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 19 ++--- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c | 93 +++++++--------------- drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h | 11 +-- .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 55 ++++++++++++- drivers/gpu/drm/amd/dal/dc/inc/opp.h | 42 ++++++++++ 7 files changed, 214 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c index 5e43d4d..2bf66c6 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c @@ -276,6 +276,38 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = { stream_enc_regs(2) }; +#define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03 + +static const struct dce110_opp_reg_offsets dce100_opp_reg_offsets[] = { +{ + .fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT_CONTROL), + .dcfe_offset = (mmCRTC0_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE), + .dcp_offset = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), +}, +{ .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmCRTC1_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE), + .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmCRTC2_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE), + .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ + .fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmCRTC3_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE), + .dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmCRTC4_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE), + .dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmCRTC5_DCFE_MEM_PWR_CTRL - DCFE_MEM_PWR_CTRL_REG_BASE), + .dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +} +}; + + static struct timing_generator *dce100_timing_generator_create( struct adapter_service *as, struct dc_context *ctx, @@ -405,8 +437,47 @@ struct link_encoder *dce100_link_encoder_create( return NULL; } + +struct output_pixel_processor *dce100_opp_create( + struct dc_context *ctx, + uint32_t inst, + const struct dce110_opp_reg_offsets *offset) +{ + struct dce110_opp *opp = + dc_service_alloc(ctx, sizeof(struct dce110_opp)); + + if (!opp) + return NULL; + + if (dce110_opp_construct(opp, + ctx, inst, offset)) + return &opp->base; + + BREAK_TO_DEBUGGER(); + dc_service_free(ctx, opp); + return NULL; +} + + +void dce100_opp_destroy(struct output_pixel_processor **opp) +{ + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_dx); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_oem); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_1025); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_256); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coordinates_x); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_regamma); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_resulted); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_oem); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_user); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)); + *opp = NULL; +} + bool dce100_construct_resource_pool( struct adapter_service *adapter_serv, + uint8_t num_virtual_links, struct dc *dc, struct resource_pool *pool) { @@ -518,7 +589,7 @@ bool dce100_construct_resource_pool( pool->transforms[i], pool->scaler_filter); - pool->opps[i] = dce110_opp_create(ctx, i); + pool->opps[i] = dce100_opp_create(ctx, i, &dce100_opp_reg_offsets[i]); if (pool->opps[i] == NULL) { BREAK_TO_DEBUGGER(); dal_error( @@ -583,7 +654,7 @@ audio_create_fail: controller_create_fail: for (i = 0; i < pool->controller_count; i++) { if (pool->opps[i] != NULL) - dce110_opp_destroy(&pool->opps[i]); + dce100_opp_destroy(&pool->opps[i]); if (pool->transforms[i] != NULL) dce100_transform_destroy(&pool->transforms[i]); @@ -625,7 +696,7 @@ void dce100_destruct_resource_pool(struct resource_pool *pool) for (i = 0; i < pool->controller_count; i++) { if (pool->opps[i] != NULL) - dce110_opp_destroy(&pool->opps[i]); + dce100_opp_destroy(&pool->opps[i]); if (pool->transforms[i] != NULL) dce100_transform_destroy(&pool->transforms[i]); diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h index 1ae3ecc..a70bfee 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h @@ -16,6 +16,7 @@ struct dc_validation_set; bool dce100_construct_resource_pool( struct adapter_service *adapter_serv, + uint8_t num_virtual_links, struct dc *dc, struct resource_pool *pool); diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c index 674e795..1fc4c07 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c @@ -182,7 +182,8 @@ static bool set_gamma_ramp( const struct gamma_parameters *params) { /*Power on LUT memory*/ - dce110_opp_power_on_regamma_lut(opp, true); + opp->funcs->opp_power_on_regamma_lut(opp, true); + if (params->surface_pixel_format == PIXEL_FORMAT_INDEX8 || params->selected_gamma_lut == GRAPHICS_GAMMA_LUT_LEGACY) { @@ -197,10 +198,10 @@ static bool set_gamma_ramp( ipp->funcs->ipp_set_degamma(ipp, params, true); - dce110_opp_set_regamma(opp, ramp, params, true); + opp->funcs->opp_set_regamma(opp, ramp, params, true); } else if (params->selected_gamma_lut == GRAPHICS_GAMMA_LUT_LEGACY_AND_REGAMMA) { - if (!dce110_opp_map_legacy_and_regamma_hw_to_x_user( + if (!opp->funcs->opp_map_legacy_and_regamma_hw_to_x_user( opp, ramp, params)) { BREAK_TO_DEBUGGER(); /* invalid parameters or bug */ @@ -224,11 +225,11 @@ static bool set_gamma_ramp( * For FP16 or no degamma do by pass */ ipp->funcs->ipp_set_degamma(ipp, params, false); - dce110_opp_set_regamma(opp, ramp, params, false); + opp->funcs->opp_set_regamma(opp, ramp, params, false); } /*re-enable low power mode for LUT memory*/ - dce110_opp_power_on_regamma_lut(opp, false); + opp->funcs->opp_power_on_regamma_lut(opp, false); return true; } @@ -299,11 +300,11 @@ static void program_fmt( /* dithering is affected by , hence should be * programmed afterwards */ - dce110_opp_program_bit_depth_reduction( + opp->funcs->opp_program_bit_depth_reduction( opp, fmt_bit_depth); - dce110_opp_program_clamping_and_pixel_encoding( + opp->funcs->opp_program_clamping_and_pixel_encoding( opp, clamping); @@ -840,7 +841,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx, return DC_ERROR_UNEXPECTED; } - dce110_opp_set_dyn_expansion( + opp->funcs->opp_set_dyn_expansion( opp, COLOR_SPACE_YCBCR601, stream->public.timing.display_color_depth, @@ -1411,7 +1412,7 @@ static void set_default_colors( build_params-> line_buffer_params[path_id][plane_id].depth);*/ - dce110_opp_set_csc_default(opp, &default_adjust); + opp->funcs->opp_set_csc_default(opp, &default_adjust); } static void program_scaler( diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c index 3fd12eb..5003c89 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c +++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c @@ -31,43 +31,11 @@ #include "dce110_opp.h" -#define FROM_OPP(opp)\ - container_of(opp, struct dce110_opp, base) - enum { MAX_LUT_ENTRY = 256, MAX_NUMBER_OF_ENTRIES = 256 }; -static const struct dce110_opp_reg_offsets reg_offsets[] = { -{ - .fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ - .fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -}, -{ .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL), - .dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), - .dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), -} -}; - static void build_evenly_distributed_points( struct gamma_pixel *points, uint32_t numberof_points, @@ -115,18 +83,30 @@ static void build_evenly_distributed_points( /* Constructor, Destructor */ /*****************************************/ +struct opp_funcs funcs = { + .opp_map_legacy_and_regamma_hw_to_x_user = dce110_opp_map_legacy_and_regamma_hw_to_x_user, + .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut, + .opp_program_bit_depth_reduction = dce110_opp_program_bit_depth_reduction, + .opp_program_clamping_and_pixel_encoding = dce110_opp_program_clamping_and_pixel_encoding, + .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment, + .opp_set_csc_default = dce110_opp_set_csc_default, + .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion, + .opp_set_regamma = dce110_opp_set_regamma +}; + bool dce110_opp_construct(struct dce110_opp *opp110, struct dc_context *ctx, - uint32_t inst) + uint32_t inst, + const struct dce110_opp_reg_offsets *offsets) { - if (inst >= ARRAY_SIZE(reg_offsets)) - return false; + + opp110->base.funcs = &funcs; opp110->base.ctx = ctx; opp110->base.inst = inst; - opp110->offsets = reg_offsets[inst]; + opp110->offsets = *offsets; opp110->regamma.hw_points_num = 128; opp110->regamma.coordinates_x = NULL; @@ -274,36 +254,17 @@ failure_1: void dce110_opp_destroy(struct output_pixel_processor **opp) { - dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.coeff128_dx); - dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.coeff128_oem); - dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.coeff128); - dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.axis_x_1025); - dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.axis_x_256); - dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.coordinates_x); - dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.rgb_regamma); - dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.rgb_resulted); - dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.rgb_oem); - dc_service_free((*opp)->ctx, FROM_OPP(*opp)->regamma.rgb_user); - dc_service_free((*opp)->ctx, FROM_OPP(*opp)); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_dx); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128_oem); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coeff128); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_1025); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.axis_x_256); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.coordinates_x); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_regamma); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_resulted); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_oem); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)->regamma.rgb_user); + dc_service_free((*opp)->ctx, FROM_DCE11_OPP(*opp)); *opp = NULL; } -struct output_pixel_processor *dce110_opp_create( - struct dc_context *ctx, - uint32_t inst) -{ - struct dce110_opp *opp = - dc_service_alloc(ctx, sizeof(struct dce110_opp)); - - if (!opp) - return NULL; - - if (dce110_opp_construct(opp, - ctx, inst)) - return &opp->base; - - BREAK_TO_DEBUGGER(); - dc_service_free(ctx, opp); - return NULL; -} - diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h index 71fe624..f9b828c 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h +++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h @@ -28,6 +28,10 @@ #include "dc_types.h" #include "inc/opp.h" + +#define FROM_DCE11_OPP(opp)\ + container_of(opp, struct dce110_opp, base) + enum dce110_opp_reg_type { DCE110_OPP_REG_DCP = 0, DCE110_OPP_REG_DCFE, @@ -89,14 +93,11 @@ struct dce110_opp { bool dce110_opp_construct(struct dce110_opp *opp110, struct dc_context *ctx, - uint32_t inst); + uint32_t inst, + const struct dce110_opp_reg_offsets *offsets); void dce110_opp_destroy(struct output_pixel_processor **opp); -struct output_pixel_processor *dce110_opp_create( - struct dc_context *ctx, - uint32_t inst); - /* REGAMMA RELATED */ void dce110_opp_power_on_regamma_lut( struct output_pixel_processor *opp, diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c index d2970f8..44558d5 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c @@ -240,6 +240,38 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = { stream_enc_regs(2) }; + +/* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */ +static const struct dce110_opp_reg_offsets dce110_opp_reg_offsets[] = { +{ + .fmt_offset = (mmFMT0_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), + .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ .fmt_offset = (mmFMT1_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), + .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ .fmt_offset = (mmFMT2_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmDCFE2_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), + .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ + .fmt_offset = (mmFMT3_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmDCFE3_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), + .dcp_offset = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ .fmt_offset = (mmFMT4_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmDCFE4_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), + .dcp_offset = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +}, +{ .fmt_offset = (mmFMT5_FMT_CONTROL - mmFMT0_FMT_CONTROL), + .dcfe_offset = (mmDCFE5_DCFE_MEM_PWR_CTRL - mmDCFE0_DCFE_MEM_PWR_CTRL), + .dcp_offset = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), +} +}; + + static struct timing_generator *dce110_timing_generator_create( struct adapter_service *as, struct dc_context *ctx, @@ -374,6 +406,27 @@ void dce110_link_encoder_destroy(struct link_encoder **enc) *enc = NULL; } + +static struct output_pixel_processor *dce110_opp_create( + struct dc_context *ctx, + uint32_t inst, + const struct dce110_opp_reg_offsets *offsets) +{ + struct dce110_opp *opp = + dc_service_alloc(ctx, sizeof(struct dce110_opp)); + + if (!opp) + return NULL; + + if (dce110_opp_construct(opp, + ctx, inst, offsets)) + return &opp->base; + + BREAK_TO_DEBUGGER(); + dc_service_free(ctx, opp); + return NULL; +} + bool dce110_construct_resource_pool( struct adapter_service *adapter_serv, uint8_t num_virtual_links, @@ -485,7 +538,7 @@ bool dce110_construct_resource_pool( pool->transforms[i], pool->scaler_filter); - pool->opps[i] = dce110_opp_create(ctx, i); + pool->opps[i] = dce110_opp_create(ctx, i, &dce110_opp_reg_offsets[i]); if (pool->opps[i] == NULL) { BREAK_TO_DEBUGGER(); dal_error( diff --git a/drivers/gpu/drm/amd/dal/dc/inc/opp.h b/drivers/gpu/drm/amd/dal/dc/inc/opp.h index 3293e3b..543848a 100644 --- a/drivers/gpu/drm/amd/dal/dc/inc/opp.h +++ b/drivers/gpu/drm/amd/dal/dc/inc/opp.h @@ -195,6 +195,7 @@ enum opp_regamma { struct output_pixel_processor { struct dc_context *ctx; uint32_t inst; + struct opp_funcs *funcs; }; enum fmt_stereo_action { @@ -203,4 +204,45 @@ enum fmt_stereo_action { FMT_STEREO_ACTION_UPDATE_POLARITY }; +struct opp_funcs { + void (*opp_power_on_regamma_lut)( + struct output_pixel_processor *opp, + bool power_on); + + bool (*opp_set_regamma)( + struct output_pixel_processor *opp, + const struct gamma_ramp *ramp, + const struct gamma_parameters *params, + bool force_bypass); + + bool (*opp_map_legacy_and_regamma_hw_to_x_user)( + struct output_pixel_processor *opp, + const struct gamma_ramp *gamma_ramp, + const struct gamma_parameters *params); + + void (*opp_set_csc_adjustment)( + struct output_pixel_processor *opp, + const struct grph_csc_adjustment *adjust); + + void (*opp_set_csc_default)( + struct output_pixel_processor *opp, + const struct default_adjustment *default_adjust); + + /* FORMATTER RELATED */ + void (*opp_program_bit_depth_reduction)( + struct output_pixel_processor *opp, + const struct bit_depth_reduction_params *params); + + void (*opp_program_clamping_and_pixel_encoding)( + struct output_pixel_processor *opp, + const struct clamping_and_pixel_encoding_params *params); + + + void (*opp_set_dyn_expansion)( + struct output_pixel_processor *opp, + enum color_space color_sp, + enum dc_color_depth color_dpth, + enum signal_type signal); +}; + #endif -- 2.7.4