From 7f26858f4a6c4bfca0f6b2ec08db493c270825a4 Mon Sep 17 00:00:00 2001 From: Chris Park Date: Tue, 5 Jan 2016 16:37:46 -0500 Subject: [PATCH 0662/1110] amdgpu/dce8: Update IP tables to enable DAL on bonaire and hawaii Update IP tables for bonaire and hawaii to enable DAL rather than the legacy dce8 code. Signed-off-by: Chris Park --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +- drivers/gpu/drm/amd/amdgpu/cik.c | 161 +++++++++++++++++++++++++++++ 2 files changed, 167 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7e24cdb..a38ac17 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1388,10 +1388,14 @@ static int amdgpu_resume(struct amdgpu_device *adev) */ bool amdgpu_device_has_dal_support(struct amdgpu_device *adev) { - switch(adev->asic_type) { - case CHIP_CARRIZO: +#if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE8_0) + case CHIP_BONAIRE: + case CHIP_HAWAII: + return true; +#endif #if defined(CONFIG_DRM_AMD_DAL) && defined(CONFIG_DRM_AMD_DAL_DCE11_0) + case CHIP_CARRIZO: return true; #endif default: diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 009598b..7efe693 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -65,6 +65,7 @@ #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" +#include "amdgpu_dm.h" #include "amdgpu_amdkfd.h" #include "amdgpu_powerplay.h" @@ -1626,6 +1627,76 @@ static uint32_t cik_get_rev_id(struct amdgpu_device *adev) >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; } +#if defined(CONFIG_DRM_AMD_DAL_DCE8_0) +static const struct amdgpu_ip_block_version bonaire_ip_blocks_dal[] = +{ + /* ORDER MATTERS! */ + { + .type = AMD_IP_BLOCK_TYPE_COMMON, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &cik_common_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_GMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &gmc_v7_0_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_IH, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_ih_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_SMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &amdgpu_pp_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &amdgpu_dm_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_GFX, + .major = 7, + .minor = 2, + .rev = 0, + .funcs = &gfx_v7_0_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_SDMA, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_sdma_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_UVD, + .major = 4, + .minor = 2, + .rev = 0, + .funcs = &uvd_v4_2_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_VCE, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vce_v2_0_ip_funcs, + }, +}; +#endif + static const struct amdgpu_ip_block_version bonaire_ip_blocks[] = { /* ORDER MATTERS! */ @@ -1694,6 +1765,76 @@ static const struct amdgpu_ip_block_version bonaire_ip_blocks[] = }, }; +#if defined(CONFIG_DRM_AMD_DAL_DCE8_0) +static const struct amdgpu_ip_block_version hawaii_ip_blocks_dal[] = +{ + /* ORDER MATTERS! */ + { + .type = AMD_IP_BLOCK_TYPE_COMMON, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &cik_common_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_GMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &gmc_v7_0_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_IH, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_ih_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_SMC, + .major = 7, + .minor = 0, + .rev = 0, + .funcs = &amdgpu_pp_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 8, + .minor = 0, + .rev = 0, + .funcs = &amdgpu_dm_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_GFX, + .major = 7, + .minor = 3, + .rev = 0, + .funcs = &gfx_v7_0_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_SDMA, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &cik_sdma_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_UVD, + .major = 4, + .minor = 2, + .rev = 0, + .funcs = &uvd_v4_2_ip_funcs, + }, + { + .type = AMD_IP_BLOCK_TYPE_VCE, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vce_v2_0_ip_funcs, + }, +}; +#endif + static const struct amdgpu_ip_block_version hawaii_ip_blocks[] = { /* ORDER MATTERS! */ @@ -1970,12 +2111,32 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_BONAIRE: +#if defined(CONFIG_DRM_AMD_DAL_DCE8_0) + if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) { + adev->ip_blocks = bonaire_ip_blocks_dal; + adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks_dal); + } else { + adev->ip_blocks = bonaire_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks); + } +#else adev->ip_blocks = bonaire_ip_blocks; adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks); +#endif break; case CHIP_HAWAII: +#if defined(CONFIG_DRM_AMD_DAL_DCE8_0) + if (amdgpu_dal && amdgpu_device_has_dal_support(adev)) { + adev->ip_blocks = hawaii_ip_blocks_dal; + adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks_dal); + } else { + adev->ip_blocks = hawaii_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks); + } +#else adev->ip_blocks = hawaii_ip_blocks; adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks); +#endif break; case CHIP_KAVERI: adev->ip_blocks = kaveri_ip_blocks; -- 2.7.4