From 3b98862c1d08b4230b91f9eb7e8c4aa1292b0cfe Mon Sep 17 00:00:00 2001 From: Chris Park Date: Thu, 26 Nov 2015 15:36:48 -0500 Subject: [PATCH 0530/1110] drm/amd/dal: Clean up Stream Encoder Remove AFMT Memory Power State Programming. Refactor Setup. Signed-off-by: Harry Wentland Acked-by: Harry Wentland --- drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 7 - .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 27 +- .../drm/amd/dal/dc/dce110/dce110_stream_encoder.c | 353 +++++++++------------ .../drm/amd/dal/dc/dce110/dce110_stream_encoder.h | 33 +- drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 5 - 5 files changed, 165 insertions(+), 260 deletions(-) diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c index 5a59f38..ec85e87 100644 --- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c @@ -1014,8 +1014,6 @@ enum dc_status core_link_enable(struct core_stream *stream) } if (stream->audio) { - stream->ctx->dc->hwss.set_afmt_memory_power_state( - stream->ctx, stream->stream_enc->id, true); /* notify audio driver for audio modes of monitor */ dal_audio_enable_azalia_audio_jack_presence(stream->audio, stream->stream_enc->id); @@ -1054,11 +1052,6 @@ enum dc_status core_link_disable(struct core_stream *stream) stream->sink->link->link_enc, stream->signal)) status = DC_ERROR_UNEXPECTED; - if (stream->audio) { - dc->hwss.set_afmt_memory_power_state( - stream->ctx, stream->stream_enc->id, false); - } - return status; } diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c index cf893c3..cbe27a4 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c @@ -696,13 +696,11 @@ static void disable_stream(struct core_stream *stream) if (dc_is_hdmi_signal(stream->signal)) dce110_stream_encoder_stop_hdmi_info_packets( - stream->stream_enc->ctx, - stream->stream_enc->id); + stream->stream_enc); if (dc_is_dp_signal(stream->signal)) dce110_stream_encoder_stop_dp_info_packets( - stream->stream_enc->ctx, - stream->stream_enc->id); + stream->stream_enc); if (stream->audio) { /* mute audio */ @@ -822,7 +820,6 @@ static enum dc_status allocate_mst_payload(struct core_stream *stream) dce110_stream_encoder_set_mst_bandwidth( stream_encoder, - stream_encoder->id, avg_time_slots_per_mtp); return DC_OK; @@ -845,7 +842,6 @@ static enum dc_status deallocate_mst_payload(struct core_stream *stream) /* slot X.Y */ dce110_stream_encoder_set_mst_bandwidth( stream_encoder, - stream_encoder->id, avg_time_slots_per_mtp); /* TODO: which component is responsible for remove payload table? */ @@ -941,16 +937,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx, stream->sink->link->link_enc, stream->signal); - if (!dc_is_dp_signal(stream->signal)) - if (ENCODER_RESULT_OK != dce110_stream_encoder_setup( - stream->stream_enc, - &stream->public.timing, - stream->signal, - stream->audio != NULL)) { - BREAK_TO_DEBUGGER(); - return DC_ERROR_UNEXPECTED; - } - if (dc_is_dp_signal(stream->signal)) dce110_stream_encoder_dp_set_stream_attribute( stream->stream_enc, @@ -959,12 +945,15 @@ static enum dc_status apply_single_controller_ctx_to_hw(uint8_t controller_idx, if (dc_is_hdmi_signal(stream->signal)) dce110_stream_encoder_hdmi_set_stream_attribute( stream->stream_enc, - &stream->public.timing); + &stream->public.timing, + stream->audio != NULL); if (dc_is_dvi_signal(stream->signal)) dce110_stream_encoder_dvi_set_stream_attribute( stream->stream_enc, - &stream->public.timing); + &stream->public.timing, + (stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? + true : false); if (stream->audio != NULL) { if (AUDIO_RESULT_OK != dal_audio_setup( @@ -1842,8 +1831,6 @@ static const struct hw_sequencer_funcs dce110_funcs = { .destruct_resource_pool = dce110_destruct_resource_pool, .validate_with_context = dce110_validate_with_context, .validate_bandwidth = dce110_validate_bandwidth, - .set_afmt_memory_power_state = - dce110_stream_encoder_set_afmt_memory_power_state, .enable_display_pipe_clock_gating = dce110_enable_display_pipe_clock_gating, .enable_display_power_gating = dce110_enable_display_power_gating, .program_bw = dce110_program_bw diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c index ac1a948..95dbc35 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c +++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c @@ -60,9 +60,9 @@ static void construct( static void update_avi_info_packet( struct stream_encoder *enc, - enum engine_id engine, const struct encoder_info_packet *info_packet) { + enum engine_id engine = enc->id; const int32_t offset = fe_engine_offsets[engine]; uint32_t regval; uint32_t addr; @@ -165,10 +165,10 @@ static void update_avi_info_packet( static void update_generic_info_packet( struct stream_encoder *enc, - enum engine_id engine, uint32_t packet_index, const struct encoder_info_packet *info_packet) { + enum engine_id engine = enc->id; uint32_t addr; uint32_t regval; /* choose which generic packet to use */ @@ -267,10 +267,10 @@ static void update_generic_info_packet( static void update_hdmi_info_packet( struct stream_encoder *enc, - enum engine_id engine, uint32_t packet_index, const struct encoder_info_packet *info_packet) { + enum engine_id engine = enc->id; uint32_t cont, send, line; uint32_t addr = fe_engine_offsets[engine]; uint32_t regval; @@ -278,7 +278,6 @@ static void update_hdmi_info_packet( if (info_packet->valid) { update_generic_info_packet( enc, - engine, packet_index, info_packet); @@ -372,10 +371,10 @@ static void update_hdmi_info_packet( static void update_dp_info_packet( struct stream_encoder *enc, - enum engine_id engine, uint32_t packet_index, const struct encoder_info_packet *info_packet) { + enum engine_id engine = enc->id; const uint32_t addr = mmDP_SEC_CNTL + fe_engine_offsets[engine]; uint32_t value; @@ -383,7 +382,6 @@ static void update_dp_info_packet( if (info_packet->valid) update_generic_info_packet( enc, - engine, packet_index, info_packet); @@ -445,10 +443,11 @@ static void update_dp_info_packet( } static void dp_steer_fifo_reset( - struct dc_context *ctx, - enum engine_id engine, + struct stream_encoder *enc, bool reset) { + struct dc_context *ctx = enc->ctx; + enum engine_id engine = enc->id; const uint32_t addr = mmDP_STEER_FIFO + fe_engine_offsets[engine]; uint32_t value = dal_read_reg(ctx, addr); @@ -459,9 +458,9 @@ static void dp_steer_fifo_reset( } static void unblank_dp_output( - struct stream_encoder *enc, - enum engine_id engine) + struct stream_encoder *enc) { + enum engine_id engine = enc->id; uint32_t addr; uint32_t value; @@ -472,7 +471,7 @@ static void unblank_dp_output( dal_write_reg(enc->ctx, addr, value); /* switch DP encoder to CRTC data */ - dp_steer_fifo_reset(enc->ctx, engine, false); + dp_steer_fifo_reset(enc, false); /* wait 100us for DIG/DP logic to prime * (i.e. a few video lines) */ @@ -497,10 +496,10 @@ static void unblank_dp_output( static void setup_vid_stream( struct stream_encoder *enc, - enum engine_id engine, uint32_t m_vid, uint32_t n_vid) { + enum engine_id engine = enc->id; uint32_t addr; uint32_t value; @@ -530,11 +529,11 @@ static void setup_vid_stream( static void set_tmds_stream_attributes( struct stream_encoder *enc, - enum engine_id engine, const struct dc_crtc_timing *timing, bool is_dvi ) { + enum engine_id engine = enc->id; uint32_t addr = mmDIG_FE_CNTL + fe_engine_offsets[engine]; uint32_t value = dal_read_reg(enc->ctx, addr); @@ -572,9 +571,9 @@ static void set_tmds_stream_attributes( static void set_dp_stream_attributes( struct stream_encoder *enc, - enum engine_id engine, const struct dc_crtc_timing *timing) { + enum engine_id engine = enc->id; const uint32_t addr = mmDP_PIXEL_FORMAT + fe_engine_offsets[engine]; uint32_t value = dal_read_reg(enc->ctx, addr); @@ -660,9 +659,9 @@ static void set_dp_stream_attributes( static void setup_hdmi( struct stream_encoder *enc, - enum engine_id engine, const struct dc_crtc_timing *timing) { + enum engine_id engine = enc->id; uint32_t output_pixel_clock = timing->pix_clk_khz; uint32_t value; uint32_t addr; @@ -830,40 +829,147 @@ void dce110_stream_encoder_destroy(struct stream_encoder **enc) *enc = NULL; } -/* - * @brief - * Associate digital encoder with specified output transmitter - * and configure to output signal. - * Encoder will be activated later in enable_output() - */ -enum encoder_result dce110_stream_encoder_setup( +/* setup stream encoder in dp mode */ +void dce110_stream_encoder_dp_set_stream_attribute( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing) +{ + set_dp_stream_attributes(enc, crtc_timing); +} + +/* setup stream encoder in hdmi mode */ +void dce110_stream_encoder_hdmi_set_stream_attribute( struct stream_encoder *enc, struct dc_crtc_timing *crtc_timing, - enum signal_type signal, bool enable_audio) { - struct bp_encoder_control cntl; + struct bp_encoder_control cntl = {0}; cntl.action = ENCODER_CONTROL_SETUP; cntl.engine_id = enc->id; - cntl.signal = signal; + cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; cntl.enable_dp_audio = enable_audio; cntl.pixel_clock = crtc_timing->pix_clk_khz; - cntl.lanes_number = (signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? + cntl.lanes_number = LANE_COUNT_FOUR; + cntl.color_depth = crtc_timing->display_color_depth; + + if (dal_bios_parser_encoder_control( + enc->bp, &cntl) != BP_RESULT_OK) + return; + + + set_tmds_stream_attributes(enc, crtc_timing, false); + + /* setup HDMI engine */ + setup_hdmi(enc, crtc_timing); +} + +/* setup stream encoder in dvi mode */ +void dce110_stream_encoder_dvi_set_stream_attribute( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + bool is_dual_link) +{ + struct bp_encoder_control cntl = {0}; + + cntl.action = ENCODER_CONTROL_SETUP; + cntl.engine_id = enc->id; + cntl.signal = is_dual_link ? + SIGNAL_TYPE_DVI_DUAL_LINK : + SIGNAL_TYPE_DVI_SINGLE_LINK; + cntl.enable_dp_audio = false; + cntl.pixel_clock = crtc_timing->pix_clk_khz; + cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; cntl.color_depth = crtc_timing->display_color_depth; if (dal_bios_parser_encoder_control( enc->bp, &cntl) != BP_RESULT_OK) - return ENCODER_RESULT_ERROR; + return; - return ENCODER_RESULT_OK; + set_tmds_stream_attributes(enc, crtc_timing, true); +} + +void dce110_stream_encoder_set_mst_bandwidth( + struct stream_encoder *enc, + struct fixed31_32 avg_time_slots_per_mtp) +{ + uint32_t x = dal_fixed31_32_floor( + avg_time_slots_per_mtp); + + uint32_t y = dal_fixed31_32_ceil( + dal_fixed31_32_shl( + dal_fixed31_32_sub_int( + avg_time_slots_per_mtp, + x), + 26)); + enum engine_id engine = enc->id; + + { + const uint32_t addr = mmDP_MSE_RATE_CNTL + + fe_engine_offsets[engine]; + uint32_t value = dal_read_reg(enc->ctx, addr); + + set_reg_field_value( + value, + x, + DP_MSE_RATE_CNTL, + DP_MSE_RATE_X); + + set_reg_field_value( + value, + y, + DP_MSE_RATE_CNTL, + DP_MSE_RATE_Y); + + dal_write_reg(enc->ctx, addr, value); + } + + /* wait for update to be completed on the link */ + /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ + /* is reset to 0 (not pending) */ + { + const uint32_t addr = mmDP_MSE_RATE_UPDATE + + fe_engine_offsets[engine]; + uint32_t value, field; + uint32_t retries = 0; + + do { + value = dal_read_reg(enc->ctx, addr); + + field = get_reg_field_value( + value, + DP_MSE_RATE_UPDATE, + DP_MSE_RATE_UPDATE_PENDING); + + if (!(field & + DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK)) + break; + + dc_service_delay_in_microseconds(enc->ctx, 10); + + ++retries; + } while (retries < DP_MST_UPDATE_MAX_RETRY); + } +} + +void dce110_stream_encoder_update_hdmi_info_packets( + struct stream_encoder *enc, + const struct encoder_info_frame *info_frame) +{ + update_avi_info_packet( + enc, + &info_frame->avi); + update_hdmi_info_packet(enc, 0, &info_frame->vendor); + update_hdmi_info_packet(enc, 1, &info_frame->gamut); + update_hdmi_info_packet(enc, 2, &info_frame->spd); } void dce110_stream_encoder_stop_hdmi_info_packets( - struct dc_context *ctx, - enum engine_id engine) + struct stream_encoder *enc) { + struct dc_context *ctx = enc->ctx; + enum engine_id engine = enc->id; uint32_t addr = 0; uint32_t value = 0; uint32_t offset = fe_engine_offsets[engine]; @@ -962,12 +1068,19 @@ void dce110_stream_encoder_stop_hdmi_info_packets( dal_write_reg(ctx, addr, value); } +void dce110_stream_encoder_update_dp_info_packets( + struct stream_encoder *enc, + const struct encoder_info_frame *info_frame) +{ + update_dp_info_packet(enc, 0, &info_frame->vsc); +} void dce110_stream_encoder_stop_dp_info_packets( - struct dc_context *ctx, - enum engine_id engine) + struct stream_encoder *enc) { /* stop generic packets on DP */ + struct dc_context *ctx = enc->ctx; + enum engine_id engine = enc->id; uint32_t offset = fe_engine_offsets[engine]; const uint32_t addr = mmDP_SEC_CNTL + offset; uint32_t value = dal_read_reg(ctx, addr); @@ -994,175 +1107,6 @@ void dce110_stream_encoder_stop_dp_info_packets( dal_write_reg(ctx, addr, value); } -/* setup stream encoder in dp mode */ -void dce110_stream_encoder_dp_set_stream_attribute( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing) -{ - set_dp_stream_attributes(enc, enc->id, crtc_timing); -} - -/* setup stream encoder in hdmi mode */ -void dce110_stream_encoder_hdmi_set_stream_attribute( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing) -{ - set_tmds_stream_attributes(enc, enc->id, crtc_timing, false); - - /* setup HDMI engine */ - setup_hdmi( - enc, enc->id, crtc_timing); -} - -/* setup stream encoder in dvi mode */ -void dce110_stream_encoder_dvi_set_stream_attribute( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing) -{ - set_tmds_stream_attributes(enc, enc->id, crtc_timing, true); -} - -void dce110_stream_encoder_set_mst_bandwidth( - struct stream_encoder *enc, - enum engine_id engine, - struct fixed31_32 avg_time_slots_per_mtp) -{ - uint32_t x = dal_fixed31_32_floor( - avg_time_slots_per_mtp); - - uint32_t y = dal_fixed31_32_ceil( - dal_fixed31_32_shl( - dal_fixed31_32_sub_int( - avg_time_slots_per_mtp, - x), - 26)); - - { - const uint32_t addr = mmDP_MSE_RATE_CNTL + - fe_engine_offsets[engine]; - uint32_t value = dal_read_reg(enc->ctx, addr); - - set_reg_field_value( - value, - x, - DP_MSE_RATE_CNTL, - DP_MSE_RATE_X); - - set_reg_field_value( - value, - y, - DP_MSE_RATE_CNTL, - DP_MSE_RATE_Y); - - dal_write_reg(enc->ctx, addr, value); - } - - /* wait for update to be completed on the link - * i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) - * is reset to 0 (not pending) */ - { - const uint32_t addr = mmDP_MSE_RATE_UPDATE + - fe_engine_offsets[engine]; - uint32_t value, field; - uint32_t retries = 0; - - do { - value = dal_read_reg(enc->ctx, addr); - - field = get_reg_field_value( - value, - DP_MSE_RATE_UPDATE, - DP_MSE_RATE_UPDATE_PENDING); - - if (!(field & - DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK)) - break; - - dc_service_delay_in_microseconds(enc->ctx, 10); - - ++retries; - } while (retries < DP_MST_UPDATE_MAX_RETRY); - } -} - - -/** -* set_afmt_memory_power_state -* -* @brief -* Power up audio formatter memory that is mapped to specified DIG -*/ -void dce110_stream_encoder_set_afmt_memory_power_state( - const struct dc_context *ctx, - enum engine_id id, - bool enable) -{ - uint32_t value; - uint32_t mem_pwr_force; - - value = dal_read_reg(ctx, mmDCO_MEM_PWR_CTRL); - - if (enable) - mem_pwr_force = 0; - else - mem_pwr_force = 3; - - /* force shutdown mode for appropriate AFMT memory */ - switch (id) { - case ENGINE_ID_DIGA: - set_reg_field_value( - value, - mem_pwr_force, - DCO_MEM_PWR_CTRL, - HDMI0_MEM_PWR_FORCE); - break; - case ENGINE_ID_DIGB: - set_reg_field_value( - value, - mem_pwr_force, - DCO_MEM_PWR_CTRL, - HDMI1_MEM_PWR_FORCE); - break; - case ENGINE_ID_DIGC: - set_reg_field_value( - value, - mem_pwr_force, - DCO_MEM_PWR_CTRL, - HDMI2_MEM_PWR_FORCE); - break; - default: - dal_logger_write( - ctx->logger, - LOG_MAJOR_WARNING, - LOG_MINOR_COMPONENT_ENCODER, - "%s: Invalid Engine Id\n", - __func__); - break; - } - - dal_write_reg(ctx, mmDCO_MEM_PWR_CTRL, value); -} - -void dce110_stream_encoder_update_hdmi_info_packets( - struct stream_encoder *enc, - const struct encoder_info_frame *info_frame) -{ - update_avi_info_packet( - enc, - enc->id, - &info_frame->avi); - update_hdmi_info_packet(enc, enc->id, 0, &info_frame->vendor); - update_hdmi_info_packet(enc, enc->id, 1, &info_frame->gamut); - update_hdmi_info_packet(enc, enc->id, 2, &info_frame->spd); -} - -void dce110_stream_encoder_update_dp_info_packets( - struct stream_encoder *enc, - const struct encoder_info_frame *info_frame) -{ - update_dp_info_packet(enc, enc->id, 0, &info_frame->vsc); -} - void dce110_stream_encoder_dp_blank( struct stream_encoder *enc) { @@ -1219,7 +1163,7 @@ void dce110_stream_encoder_dp_blank( * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is * complete, stream status will be stuck in video stream enabled state, * i.e. DP_VID_STREAM_STATUS stuck at 1. */ - dp_steer_fifo_reset(enc->ctx, engine, true); + dp_steer_fifo_reset(enc, true); } /* output video stream to link encoder */ @@ -1243,10 +1187,9 @@ void dce110_stream_encoder_dp_unblank( m_vid = (uint32_t) m_vid_l; - setup_vid_stream(enc, - enc->id, m_vid, n_vid); + setup_vid_stream(enc, m_vid, n_vid); } - unblank_dp_output(enc, enc->id); + unblank_dp_output(enc); } diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h index d4477d1..a520691 100644 --- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h +++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h @@ -38,21 +38,6 @@ struct stream_encoder *dce110_stream_encoder_create( void dce110_stream_encoder_destroy(struct stream_encoder **enc); /***** HW programming ***********/ -enum encoder_result dce110_stream_encoder_setup( - struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing, - enum signal_type signal, - bool enable_audio); - -void dce110_stream_encoder_stop_hdmi_info_packets( - struct dc_context *ctx, - enum engine_id engine); - -void dce110_stream_encoder_stop_dp_info_packets( - struct dc_context *ctx, - enum engine_id engine); - - /* setup stream encoder in dp mode */ void dce110_stream_encoder_dp_set_stream_attribute( struct stream_encoder *enc, @@ -61,32 +46,34 @@ void dce110_stream_encoder_dp_set_stream_attribute( /* setup stream encoder in hdmi mode */ void dce110_stream_encoder_hdmi_set_stream_attribute( struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing); + struct dc_crtc_timing *crtc_timing, + bool enable_audio); /* setup stream encoder in dvi mode */ void dce110_stream_encoder_dvi_set_stream_attribute( struct stream_encoder *enc, - struct dc_crtc_timing *crtc_timing); + struct dc_crtc_timing *crtc_timing, + bool is_dual_link); /* set throttling for DP MST */ void dce110_stream_encoder_set_mst_bandwidth( struct stream_encoder *enc, - enum engine_id engine, struct fixed31_32 avg_time_slots_per_mtp); -void dce110_stream_encoder_set_afmt_memory_power_state( - const struct dc_context *ctx, - enum engine_id id, - bool enable); - void dce110_stream_encoder_update_hdmi_info_packets( struct stream_encoder *enc, const struct encoder_info_frame *info_frame); +void dce110_stream_encoder_stop_hdmi_info_packets( + struct stream_encoder *enc); + void dce110_stream_encoder_update_dp_info_packets( struct stream_encoder *enc, const struct encoder_info_frame *info_frame); +void dce110_stream_encoder_stop_dp_info_packets( + struct stream_encoder *enc); + /* output blank/idle stream to link encoder */ void dce110_stream_encoder_dp_blank( struct stream_encoder *enc); diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h index 2c5738f..99a0458 100644 --- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h @@ -134,11 +134,6 @@ struct hw_sequencer_funcs { struct bios_parser *bp, enum pipe_gating_control power_gating); - void (*set_afmt_memory_power_state)( - const struct dc_context *ctx, - enum engine_id id, - bool enable); - /* resource management and validation*/ bool (*construct_resource_pool)( struct adapter_service *adapter_serv, -- 2.7.4