diff options
Diffstat (limited to 'meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/1369-Revert-drm-amdgpu-unify-MQD-programming-sequence.patch')
-rw-r--r-- | meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/1369-Revert-drm-amdgpu-unify-MQD-programming-sequence.patch | 162 |
1 files changed, 0 insertions, 162 deletions
diff --git a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/1369-Revert-drm-amdgpu-unify-MQD-programming-sequence.patch b/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/1369-Revert-drm-amdgpu-unify-MQD-programming-sequence.patch deleted file mode 100644 index 160dc394..00000000 --- a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/1369-Revert-drm-amdgpu-unify-MQD-programming-sequence.patch +++ /dev/null @@ -1,162 +0,0 @@ -From a88528d6ba15ae123d9bacb61b867de388eddb10 Mon Sep 17 00:00:00 2001 -From: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> -Date: Thu, 18 Oct 2018 18:11:54 +0530 -Subject: [PATCH 1369/4131] Revert "drm/amdgpu: unify MQD programming sequence - for kfd and amdgpu v2" - revert the change of kgd_hqd_load - api(amd-staging-hybrid-4.11 also did in such way): - - drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c - - drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c - -Change-Id: Ic461b67578c97a9cc3ef424b4561f2dbbdb1b368 -Signed-off-by: Evan Quan <evan.quan@amd.com> -Signed-off-by: Chaudhary Amit Kumar <chaudharyamit.kumar@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 51 +++++++++++++++++++++-- - drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 51 ++++++++++++++++++++--- - 2 files changed, 93 insertions(+), 9 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c -index f6acf48..e283d31 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c -@@ -29,7 +29,6 @@ - #include "cikd.h" - #include "cik_sdma.h" - #include "amdgpu_ucode.h" --#include "gfx_v7_0.h" - #include "gca/gfx_7_2_d.h" - #include "gca/gfx_7_2_enum.h" - #include "gca/gfx_7_2_sh_mask.h" -@@ -299,12 +298,56 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - m = get_mqd(mqd); - - is_wptr_shadow_valid = !get_user(wptr_shadow, wptr); -- if (is_wptr_shadow_valid) -- m->cp_hqd_pq_wptr = wptr_shadow; - - acquire_queue(kgd, pipe_id, queue_id); - -- gfx_v7_0_mqd_commit(adev, m); -+ WREG32(mmCP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo); -+ WREG32(mmCP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi); -+ WREG32(mmCP_MQD_CONTROL, m->cp_mqd_control); -+ -+ WREG32(mmCP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo); -+ WREG32(mmCP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi); -+ WREG32(mmCP_HQD_PQ_CONTROL, m->cp_hqd_pq_control); -+ -+ WREG32(mmCP_HQD_IB_CONTROL, m->cp_hqd_ib_control); -+ WREG32(mmCP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo); -+ WREG32(mmCP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi); -+ -+ WREG32(mmCP_HQD_IB_RPTR, m->cp_hqd_ib_rptr); -+ -+ WREG32(mmCP_HQD_PERSISTENT_STATE, m->cp_hqd_persistent_state); -+ WREG32(mmCP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd); -+ WREG32(mmCP_HQD_MSG_TYPE, m->cp_hqd_msg_type); -+ -+ WREG32(mmCP_HQD_ATOMIC0_PREOP_LO, m->cp_hqd_atomic0_preop_lo); -+ WREG32(mmCP_HQD_ATOMIC0_PREOP_HI, m->cp_hqd_atomic0_preop_hi); -+ WREG32(mmCP_HQD_ATOMIC1_PREOP_LO, m->cp_hqd_atomic1_preop_lo); -+ WREG32(mmCP_HQD_ATOMIC1_PREOP_HI, m->cp_hqd_atomic1_preop_hi); -+ -+ WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, m->cp_hqd_pq_rptr_report_addr_lo); -+ WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, -+ m->cp_hqd_pq_rptr_report_addr_hi); -+ -+ WREG32(mmCP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr); -+ -+ WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, m->cp_hqd_pq_wptr_poll_addr_lo); -+ WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, m->cp_hqd_pq_wptr_poll_addr_hi); -+ -+ WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, m->cp_hqd_pq_doorbell_control); -+ -+ WREG32(mmCP_HQD_VMID, m->cp_hqd_vmid); -+ -+ WREG32(mmCP_HQD_QUANTUM, m->cp_hqd_quantum); -+ -+ WREG32(mmCP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority); -+ WREG32(mmCP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority); -+ -+ WREG32(mmCP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr); -+ -+ if (is_wptr_shadow_valid) -+ WREG32(mmCP_HQD_PQ_WPTR, wptr_shadow); -+ -+ WREG32(mmCP_HQD_ACTIVE, m->cp_hqd_active); - release_queue(kgd); - - return 0; -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c -index 133d066..e00fadd 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c -@@ -28,7 +28,6 @@ - #include "amdgpu.h" - #include "amdgpu_amdkfd.h" - #include "amdgpu_ucode.h" --#include "gfx_v8_0.h" - #include "gca/gfx_8_0_sh_mask.h" - #include "gca/gfx_8_0_d.h" - #include "gca/gfx_8_0_enum.h" -@@ -253,11 +252,53 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - m = get_mqd(mqd); - - valid_wptr = copy_from_user(&shadow_wptr, wptr, sizeof(shadow_wptr)); -- if (valid_wptr == 0) -- m->cp_hqd_pq_wptr = shadow_wptr; -- - acquire_queue(kgd, pipe_id, queue_id); -- gfx_v8_0_mqd_commit(adev, mqd); -+ -+ WREG32(mmCP_MQD_CONTROL, m->cp_mqd_control); -+ WREG32(mmCP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo); -+ WREG32(mmCP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi); -+ -+ WREG32(mmCP_HQD_VMID, m->cp_hqd_vmid); -+ WREG32(mmCP_HQD_PERSISTENT_STATE, m->cp_hqd_persistent_state); -+ WREG32(mmCP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority); -+ WREG32(mmCP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority); -+ WREG32(mmCP_HQD_QUANTUM, m->cp_hqd_quantum); -+ WREG32(mmCP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo); -+ WREG32(mmCP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi); -+ WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, m->cp_hqd_pq_rptr_report_addr_lo); -+ WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, -+ m->cp_hqd_pq_rptr_report_addr_hi); -+ -+ if (valid_wptr > 0) -+ WREG32(mmCP_HQD_PQ_WPTR, shadow_wptr); -+ -+ WREG32(mmCP_HQD_PQ_CONTROL, m->cp_hqd_pq_control); -+ WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, m->cp_hqd_pq_doorbell_control); -+ -+ WREG32(mmCP_HQD_EOP_BASE_ADDR, m->cp_hqd_eop_base_addr_lo); -+ WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, m->cp_hqd_eop_base_addr_hi); -+ WREG32(mmCP_HQD_EOP_CONTROL, m->cp_hqd_eop_control); -+ WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr); -+ WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr); -+ WREG32(mmCP_HQD_EOP_EVENTS, m->cp_hqd_eop_done_events); -+ -+ WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO, m->cp_hqd_ctx_save_base_addr_lo); -+ WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI, m->cp_hqd_ctx_save_base_addr_hi); -+ WREG32(mmCP_HQD_CTX_SAVE_CONTROL, m->cp_hqd_ctx_save_control); -+ WREG32(mmCP_HQD_CNTL_STACK_OFFSET, m->cp_hqd_cntl_stack_offset); -+ WREG32(mmCP_HQD_CNTL_STACK_SIZE, m->cp_hqd_cntl_stack_size); -+ WREG32(mmCP_HQD_WG_STATE_OFFSET, m->cp_hqd_wg_state_offset); -+ WREG32(mmCP_HQD_CTX_SAVE_SIZE, m->cp_hqd_ctx_save_size); -+ -+ WREG32(mmCP_HQD_IB_CONTROL, m->cp_hqd_ib_control); -+ -+ WREG32(mmCP_HQD_DEQUEUE_REQUEST, m->cp_hqd_dequeue_request); -+ WREG32(mmCP_HQD_ERROR, m->cp_hqd_error); -+ WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem); -+ WREG32(mmCP_HQD_EOP_DONES, m->cp_hqd_eop_dones); -+ -+ WREG32(mmCP_HQD_ACTIVE, m->cp_hqd_active); -+ - release_queue(kgd); - - return 0; --- -2.7.4 - |