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Diffstat (limited to 'meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/1035-drm-amd-display-clean-up-cm-register-programming-fun.patch')
-rw-r--r--meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/1035-drm-amd-display-clean-up-cm-register-programming-fun.patch549
1 files changed, 0 insertions, 549 deletions
diff --git a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/1035-drm-amd-display-clean-up-cm-register-programming-fun.patch b/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/1035-drm-amd-display-clean-up-cm-register-programming-fun.patch
deleted file mode 100644
index a53cb438..00000000
--- a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/1035-drm-amd-display-clean-up-cm-register-programming-fun.patch
+++ /dev/null
@@ -1,549 +0,0 @@
-From 22feab47e4328f49310903b2342dbad9d912f1d9 Mon Sep 17 00:00:00 2001
-From: Yue Hin Lau <Yuehin.Lau@amd.com>
-Date: Tue, 29 Aug 2017 15:01:06 -0400
-Subject: [PATCH 1035/4131] drm/amd/display: clean up cm register programming
- functions
-
-Change-Id: If760306ec97cfc9bca228f7170e81ac0ad44d833
-Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
-Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
----
- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 120 ----------
- .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 251 +++++++--------------
- 2 files changed, 76 insertions(+), 295 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
-index 7179305..4bbd3b4 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
-@@ -44,10 +44,6 @@
- #define TF_REG_LIST_DCN(id) \
- SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
- SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
-- SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
-- SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
-- SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
-- SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
- SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
- SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
- SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
-@@ -79,10 +75,6 @@
- SRI(OBUF_CONTROL, DSCL, id), \
- SRI(CM_ICSC_CONTROL, CM, id), \
- SRI(CM_ICSC_C11_C12, CM, id), \
-- SRI(CM_ICSC_C13_C14, CM, id), \
-- SRI(CM_ICSC_C21_C22, CM, id), \
-- SRI(CM_ICSC_C23_C24, CM, id), \
-- SRI(CM_ICSC_C31_C32, CM, id), \
- SRI(CM_ICSC_C33_C34, CM, id), \
- SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
- SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
-@@ -127,23 +119,11 @@
- #define TF_REG_LIST_DCN10(id) \
- TF_REG_LIST_DCN(id), \
- SRI(CM_COMA_C11_C12, CM, id),\
-- SRI(CM_COMA_C13_C14, CM, id),\
-- SRI(CM_COMA_C21_C22, CM, id),\
-- SRI(CM_COMA_C23_C24, CM, id),\
-- SRI(CM_COMA_C31_C32, CM, id),\
- SRI(CM_COMA_C33_C34, CM, id),\
- SRI(CM_COMB_C11_C12, CM, id),\
-- SRI(CM_COMB_C13_C14, CM, id),\
-- SRI(CM_COMB_C21_C22, CM, id),\
-- SRI(CM_COMB_C23_C24, CM, id),\
-- SRI(CM_COMB_C31_C32, CM, id),\
- SRI(CM_COMB_C33_C34, CM, id),\
- SRI(CM_OCSC_CONTROL, CM, id), \
- SRI(CM_OCSC_C11_C12, CM, id), \
-- SRI(CM_OCSC_C13_C14, CM, id), \
-- SRI(CM_OCSC_C21_C22, CM, id), \
-- SRI(CM_OCSC_C23_C24, CM, id), \
-- SRI(CM_OCSC_C31_C32, CM, id), \
- SRI(CM_OCSC_C33_C34, CM, id), \
- SRI(CM_MEM_PWR_CTRL, CM, id), \
- SRI(CM_RGAM_LUT_DATA, CM, id), \
-@@ -189,14 +169,6 @@
- TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
- TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
- TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
-- TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
-- TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
-- TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
-- TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
-- TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
-- TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
-- TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
-- TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
- TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
- TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
- TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
-@@ -264,14 +236,6 @@
- TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
- TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
- TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
-- TF_SF(CM0_CM_ICSC_C13_C14, CM_ICSC_C13, mask_sh), \
-- TF_SF(CM0_CM_ICSC_C13_C14, CM_ICSC_C14, mask_sh), \
-- TF_SF(CM0_CM_ICSC_C21_C22, CM_ICSC_C21, mask_sh), \
-- TF_SF(CM0_CM_ICSC_C21_C22, CM_ICSC_C22, mask_sh), \
-- TF_SF(CM0_CM_ICSC_C23_C24, CM_ICSC_C23, mask_sh), \
-- TF_SF(CM0_CM_ICSC_C23_C24, CM_ICSC_C24, mask_sh), \
-- TF_SF(CM0_CM_ICSC_C31_C32, CM_ICSC_C31, mask_sh), \
-- TF_SF(CM0_CM_ICSC_C31_C32, CM_ICSC_C32, mask_sh), \
- TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
- TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
- TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \
-@@ -349,39 +313,15 @@
- TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\
- TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\
- TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\
-- TF_SF(CM0_CM_COMA_C13_C14, CM_COMA_C13, mask_sh),\
-- TF_SF(CM0_CM_COMA_C13_C14, CM_COMA_C14, mask_sh),\
-- TF_SF(CM0_CM_COMA_C21_C22, CM_COMA_C21, mask_sh),\
-- TF_SF(CM0_CM_COMA_C21_C22, CM_COMA_C22, mask_sh),\
-- TF_SF(CM0_CM_COMA_C23_C24, CM_COMA_C23, mask_sh),\
-- TF_SF(CM0_CM_COMA_C23_C24, CM_COMA_C24, mask_sh),\
-- TF_SF(CM0_CM_COMA_C31_C32, CM_COMA_C31, mask_sh),\
-- TF_SF(CM0_CM_COMA_C31_C32, CM_COMA_C32, mask_sh),\
- TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\
- TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\
- TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\
- TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\
-- TF_SF(CM0_CM_COMB_C13_C14, CM_COMB_C13, mask_sh),\
-- TF_SF(CM0_CM_COMB_C13_C14, CM_COMB_C14, mask_sh),\
-- TF_SF(CM0_CM_COMB_C21_C22, CM_COMB_C21, mask_sh),\
-- TF_SF(CM0_CM_COMB_C21_C22, CM_COMB_C22, mask_sh),\
-- TF_SF(CM0_CM_COMB_C23_C24, CM_COMB_C23, mask_sh),\
-- TF_SF(CM0_CM_COMB_C23_C24, CM_COMB_C24, mask_sh),\
-- TF_SF(CM0_CM_COMB_C31_C32, CM_COMB_C31, mask_sh),\
- TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\
-- TF_SF(CM0_CM_COMB_C31_C32, CM_COMB_C32, mask_sh),\
- TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\
- TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
- TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \
- TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
-- TF_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C13, mask_sh), \
-- TF_SF(CM0_CM_OCSC_C13_C14, CM_OCSC_C14, mask_sh), \
-- TF_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C21, mask_sh), \
-- TF_SF(CM0_CM_OCSC_C21_C22, CM_OCSC_C22, mask_sh), \
-- TF_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C23, mask_sh), \
-- TF_SF(CM0_CM_OCSC_C23_C24, CM_OCSC_C24, mask_sh), \
-- TF_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C31, mask_sh), \
-- TF_SF(CM0_CM_OCSC_C31_C32, CM_OCSC_C32, mask_sh), \
- TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
- TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
- TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
-@@ -532,51 +472,19 @@
- type CM_GAMUT_REMAP_MODE; \
- type CM_GAMUT_REMAP_C11; \
- type CM_GAMUT_REMAP_C12; \
-- type CM_GAMUT_REMAP_C13; \
-- type CM_GAMUT_REMAP_C14; \
-- type CM_GAMUT_REMAP_C21; \
-- type CM_GAMUT_REMAP_C22; \
-- type CM_GAMUT_REMAP_C23; \
-- type CM_GAMUT_REMAP_C24; \
-- type CM_GAMUT_REMAP_C31; \
-- type CM_GAMUT_REMAP_C32; \
- type CM_GAMUT_REMAP_C33; \
- type CM_GAMUT_REMAP_C34; \
- type CM_COMA_C11; \
- type CM_COMA_C12; \
-- type CM_COMA_C13; \
-- type CM_COMA_C14; \
-- type CM_COMA_C21; \
-- type CM_COMA_C22; \
-- type CM_COMA_C23; \
-- type CM_COMA_C24; \
-- type CM_COMA_C31; \
-- type CM_COMA_C32; \
- type CM_COMA_C33; \
- type CM_COMA_C34; \
- type CM_COMB_C11; \
- type CM_COMB_C12; \
-- type CM_COMB_C13; \
-- type CM_COMB_C14; \
-- type CM_COMB_C21; \
-- type CM_COMB_C22; \
-- type CM_COMB_C23; \
-- type CM_COMB_C24; \
-- type CM_COMB_C31; \
-- type CM_COMB_C32; \
- type CM_COMB_C33; \
- type CM_COMB_C34; \
- type CM_OCSC_MODE; \
- type CM_OCSC_C11; \
- type CM_OCSC_C12; \
-- type CM_OCSC_C13; \
-- type CM_OCSC_C14; \
-- type CM_OCSC_C21; \
-- type CM_OCSC_C22; \
-- type CM_OCSC_C23; \
-- type CM_OCSC_C24; \
-- type CM_OCSC_C31; \
-- type CM_OCSC_C32; \
- type CM_OCSC_C33; \
- type CM_OCSC_C34; \
- type RGAM_MEM_PWR_FORCE; \
-@@ -1008,14 +916,6 @@
- type CM_ICSC_MODE; \
- type CM_ICSC_C11; \
- type CM_ICSC_C12; \
-- type CM_ICSC_C13; \
-- type CM_ICSC_C14; \
-- type CM_ICSC_C21; \
-- type CM_ICSC_C22; \
-- type CM_ICSC_C23; \
-- type CM_ICSC_C24; \
-- type CM_ICSC_C31; \
-- type CM_ICSC_C32; \
- type CM_ICSC_C33; \
- type CM_ICSC_C34; \
- type CM_DGAM_RAMB_EXP_REGION_START_B; \
-@@ -1146,29 +1046,13 @@ struct dcn_dpp_registers {
- uint32_t RECOUT_SIZE;
- uint32_t CM_GAMUT_REMAP_CONTROL;
- uint32_t CM_GAMUT_REMAP_C11_C12;
-- uint32_t CM_GAMUT_REMAP_C13_C14;
-- uint32_t CM_GAMUT_REMAP_C21_C22;
-- uint32_t CM_GAMUT_REMAP_C23_C24;
-- uint32_t CM_GAMUT_REMAP_C31_C32;
- uint32_t CM_GAMUT_REMAP_C33_C34;
- uint32_t CM_COMA_C11_C12;
-- uint32_t CM_COMA_C13_C14;
-- uint32_t CM_COMA_C21_C22;
-- uint32_t CM_COMA_C23_C24;
-- uint32_t CM_COMA_C31_C32;
- uint32_t CM_COMA_C33_C34;
- uint32_t CM_COMB_C11_C12;
-- uint32_t CM_COMB_C13_C14;
-- uint32_t CM_COMB_C21_C22;
-- uint32_t CM_COMB_C23_C24;
-- uint32_t CM_COMB_C31_C32;
- uint32_t CM_COMB_C33_C34;
- uint32_t CM_OCSC_CONTROL;
- uint32_t CM_OCSC_C11_C12;
-- uint32_t CM_OCSC_C13_C14;
-- uint32_t CM_OCSC_C21_C22;
-- uint32_t CM_OCSC_C23_C24;
-- uint32_t CM_OCSC_C31_C32;
- uint32_t CM_OCSC_C33_C34;
- uint32_t CM_MEM_PWR_CTRL;
- uint32_t CM_RGAM_LUT_DATA;
-@@ -1317,10 +1201,6 @@ struct dcn_dpp_registers {
- uint32_t CM_SHAPER_LUT_DATA;
- uint32_t CM_ICSC_CONTROL;
- uint32_t CM_ICSC_C11_C12;
-- uint32_t CM_ICSC_C13_C14;
-- uint32_t CM_ICSC_C21_C22;
-- uint32_t CM_ICSC_C23_C24;
-- uint32_t CM_ICSC_C31_C32;
- uint32_t CM_ICSC_C33_C34;
- uint32_t CM_DGAM_RAMB_START_CNTL_B;
- uint32_t CM_DGAM_RAMB_START_CNTL_G;
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
-index 01b1c0e..d698fcc 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
-@@ -50,7 +50,7 @@
-
- struct dcn10_input_csc_matrix {
- enum dc_color_space color_space;
-- uint32_t regval[12];
-+ uint16_t regval[12];
- };
-
- enum dcn10_coef_filter_type_sel {
-@@ -116,6 +116,38 @@ static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = {
- 0x2568, 0x43ee, 0xdbb2} }
- };
-
-+static void dpp_cm_program_color_registers(
-+ struct dcn10_dpp *xfm,
-+ const uint16_t *regval,
-+ uint32_t cm_reg_start,
-+ uint32_t cm_reg_end)
-+{
-+ uint32_t reg_region_cur;
-+ unsigned int i = 0;
-+
-+#undef REG
-+#define REG(reg) reg
-+
-+ for (reg_region_cur = cm_reg_start;
-+ reg_region_cur <= cm_reg_end;
-+ reg_region_cur++) {
-+
-+ const uint16_t *regval0 = &(regval[2 * i]);
-+ const uint16_t *regval1 = &(regval[(2 * i) + 1]);
-+
-+ REG_SET_2(reg_region_cur, 0,
-+ CM_GAMUT_REMAP_C11, *regval0,
-+ CM_GAMUT_REMAP_C12, *regval1);
-+
-+ i++;
-+ }
-+
-+#undef REG
-+#define REG(reg)\
-+ xfm->tf_regs->reg
-+
-+}
-+
- static void program_gamut_remap(
- struct dcn10_dpp *xfm,
- const uint16_t *regval,
-@@ -145,79 +177,27 @@ static void program_gamut_remap(
-
- if (select == GAMUT_REMAP_COEFF) {
-
-- REG_SET_2(CM_GAMUT_REMAP_C11_C12, 0,
-- CM_GAMUT_REMAP_C11, regval[0],
-- CM_GAMUT_REMAP_C12, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_GAMUT_REMAP_C13_C14, 0,
-- CM_GAMUT_REMAP_C13, regval[0],
-- CM_GAMUT_REMAP_C14, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_GAMUT_REMAP_C21_C22, 0,
-- CM_GAMUT_REMAP_C21, regval[0],
-- CM_GAMUT_REMAP_C22, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_GAMUT_REMAP_C23_C24, 0,
-- CM_GAMUT_REMAP_C23, regval[0],
-- CM_GAMUT_REMAP_C24, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_GAMUT_REMAP_C31_C32, 0,
-- CM_GAMUT_REMAP_C31, regval[0],
-- CM_GAMUT_REMAP_C32, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_GAMUT_REMAP_C33_C34, 0,
-- CM_GAMUT_REMAP_C33, regval[0],
-- CM_GAMUT_REMAP_C34, regval[1]);
-+ dpp_cm_program_color_registers(
-+ xfm,
-+ regval,
-+ REG(CM_GAMUT_REMAP_C11_C12),
-+ REG(CM_GAMUT_REMAP_C33_C34));
-
- } else if (select == GAMUT_REMAP_COMA_COEFF) {
-- REG_SET_2(CM_COMA_C11_C12, 0,
-- CM_COMA_C11, regval[0],
-- CM_COMA_C12, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_COMA_C13_C14, 0,
-- CM_COMA_C13, regval[0],
-- CM_COMA_C14, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_COMA_C21_C22, 0,
-- CM_COMA_C21, regval[0],
-- CM_COMA_C22, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_COMA_C23_C24, 0,
-- CM_COMA_C23, regval[0],
-- CM_COMA_C24, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_COMA_C31_C32, 0,
-- CM_COMA_C31, regval[0],
-- CM_COMA_C32, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_COMA_C33_C34, 0,
-- CM_COMA_C33, regval[0],
-- CM_COMA_C34, regval[1]);
-+
-+ dpp_cm_program_color_registers(
-+ xfm,
-+ regval,
-+ REG(CM_COMA_C11_C12),
-+ REG(CM_COMA_C33_C34));
-
- } else {
-- REG_SET_2(CM_COMB_C11_C12, 0,
-- CM_COMB_C11, regval[0],
-- CM_COMB_C12, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_COMB_C13_C14, 0,
-- CM_COMB_C13, regval[0],
-- CM_COMB_C14, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_COMB_C21_C22, 0,
-- CM_COMB_C21, regval[0],
-- CM_COMB_C22, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_COMB_C23_C24, 0,
-- CM_COMB_C23, regval[0],
-- CM_COMB_C24, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_COMB_C31_C32, 0,
-- CM_COMB_C31, regval[0],
-- CM_COMB_C32, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_COMB_C33_C34, 0,
-- CM_COMB_C33, regval[0],
-- CM_COMB_C34, regval[1]);
-+
-+ dpp_cm_program_color_registers(
-+ xfm,
-+ regval,
-+ REG(CM_COMB_C11_C12),
-+ REG(CM_COMB_C33_C34));
- }
-
- REG_SET(
-@@ -312,59 +292,20 @@ static void dcn10_dpp_cm_program_color_matrix(
- }
-
- if (mode == 4) {
-- /*R*/
-- REG_SET_2(CM_OCSC_C11_C12, 0,
-- CM_OCSC_C11, tbl_entry->regval[0],
-- CM_OCSC_C12, tbl_entry->regval[1]);
--
-- REG_SET_2(CM_OCSC_C13_C14, 0,
-- CM_OCSC_C13, tbl_entry->regval[2],
-- CM_OCSC_C14, tbl_entry->regval[3]);
--
-- /*G*/
-- REG_SET_2(CM_OCSC_C21_C22, 0,
-- CM_OCSC_C21, tbl_entry->regval[4],
-- CM_OCSC_C22, tbl_entry->regval[5]);
--
-- REG_SET_2(CM_OCSC_C23_C24, 0,
-- CM_OCSC_C23, tbl_entry->regval[6],
-- CM_OCSC_C24, tbl_entry->regval[7]);
--
-- /*B*/
-- REG_SET_2(CM_OCSC_C31_C32, 0,
-- CM_OCSC_C31, tbl_entry->regval[8],
-- CM_OCSC_C32, tbl_entry->regval[9]);
--
-- REG_SET_2(CM_OCSC_C33_C34, 0,
-- CM_OCSC_C33, tbl_entry->regval[10],
-- CM_OCSC_C34, tbl_entry->regval[11]);
-+
-+ dpp_cm_program_color_registers(
-+ xfm,
-+ tbl_entry->regval,
-+ REG(CM_OCSC_C11_C12),
-+ REG(CM_OCSC_C33_C34));
-+
- } else {
-- /*R*/
-- REG_SET_2(CM_COMB_C11_C12, 0,
-- CM_COMB_C11, tbl_entry->regval[0],
-- CM_COMB_C12, tbl_entry->regval[1]);
--
-- REG_SET_2(CM_COMB_C13_C14, 0,
-- CM_COMB_C13, tbl_entry->regval[2],
-- CM_COMB_C14, tbl_entry->regval[3]);
--
-- /*G*/
-- REG_SET_2(CM_COMB_C21_C22, 0,
-- CM_COMB_C21, tbl_entry->regval[4],
-- CM_COMB_C22, tbl_entry->regval[5]);
--
-- REG_SET_2(CM_COMB_C23_C24, 0,
-- CM_COMB_C23, tbl_entry->regval[6],
-- CM_COMB_C24, tbl_entry->regval[7]);
--
-- /*B*/
-- REG_SET_2(CM_COMB_C31_C32, 0,
-- CM_COMB_C31, tbl_entry->regval[8],
-- CM_COMB_C32, tbl_entry->regval[9]);
--
-- REG_SET_2(CM_COMB_C33_C34, 0,
-- CM_COMB_C33, tbl_entry->regval[10],
-- CM_COMB_C34, tbl_entry->regval[11]);
-+
-+ dpp_cm_program_color_registers(
-+ xfm,
-+ tbl_entry->regval,
-+ REG(CM_COMB_C11_C12),
-+ REG(CM_COMB_C33_C34));
- }
- }
-
-@@ -602,7 +543,7 @@ void ippn10_program_input_csc(
- struct dcn10_dpp *xfm = TO_DCN10_DPP(xfm_base);
- int i;
- int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
-- const uint32_t *regval = NULL;
-+ const uint16_t *regval = NULL;
- uint32_t selection = 1;
-
- if (select == INPUT_CSC_SELECT_BYPASS) {
-@@ -627,59 +568,19 @@ void ippn10_program_input_csc(
- CM_ICSC_MODE, selection);
-
- if (select == INPUT_CSC_SELECT_ICSC) {
-- /*R*/
-- REG_SET_2(CM_ICSC_C11_C12, 0,
-- CM_ICSC_C11, regval[0],
-- CM_ICSC_C12, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_ICSC_C13_C14, 0,
-- CM_ICSC_C13, regval[0],
-- CM_ICSC_C14, regval[1]);
-- /*G*/
-- regval += 2;
-- REG_SET_2(CM_ICSC_C21_C22, 0,
-- CM_ICSC_C21, regval[0],
-- CM_ICSC_C22, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_ICSC_C23_C24, 0,
-- CM_ICSC_C23, regval[0],
-- CM_ICSC_C24, regval[1]);
-- /*B*/
-- regval += 2;
-- REG_SET_2(CM_ICSC_C31_C32, 0,
-- CM_ICSC_C31, regval[0],
-- CM_ICSC_C32, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_ICSC_C33_C34, 0,
-- CM_ICSC_C33, regval[0],
-- CM_ICSC_C34, regval[1]);
-+
-+ dpp_cm_program_color_registers(
-+ xfm,
-+ regval,
-+ REG(CM_ICSC_C11_C12),
-+ REG(CM_ICSC_C33_C34));
- } else {
-- /*R*/
-- REG_SET_2(CM_COMA_C11_C12, 0,
-- CM_COMA_C11, regval[0],
-- CM_COMA_C12, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_COMA_C13_C14, 0,
-- CM_COMA_C13, regval[0],
-- CM_COMA_C14, regval[1]);
-- /*G*/
-- regval += 2;
-- REG_SET_2(CM_COMA_C21_C22, 0,
-- CM_COMA_C21, regval[0],
-- CM_COMA_C22, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_COMA_C23_C24, 0,
-- CM_COMA_C23, regval[0],
-- CM_COMA_C24, regval[1]);
-- /*B*/
-- regval += 2;
-- REG_SET_2(CM_COMA_C31_C32, 0,
-- CM_COMA_C31, regval[0],
-- CM_COMA_C32, regval[1]);
-- regval += 2;
-- REG_SET_2(CM_COMA_C33_C34, 0,
-- CM_COMA_C33, regval[0],
-- CM_COMA_C34, regval[1]);
-+
-+ dpp_cm_program_color_registers(
-+ xfm,
-+ regval,
-+ REG(CM_COMA_C11_C12),
-+ REG(CM_COMA_C33_C34));
- }
- }
-
---
-2.7.4
-