diff options
Diffstat (limited to 'meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0968-drm-amd-display-Flattening-core_dc-to-dc.patch')
| -rw-r--r-- | meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0968-drm-amd-display-Flattening-core_dc-to-dc.patch | 3926 |
1 files changed, 0 insertions, 3926 deletions
diff --git a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0968-drm-amd-display-Flattening-core_dc-to-dc.patch b/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0968-drm-amd-display-Flattening-core_dc-to-dc.patch deleted file mode 100644 index 1fca09ae..00000000 --- a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0968-drm-amd-display-Flattening-core_dc-to-dc.patch +++ /dev/null @@ -1,3926 +0,0 @@ -From 09c21685f623819b9ff84876ff01e9167409c325 Mon Sep 17 00:00:00 2001 -From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> -Date: Tue, 1 Aug 2017 15:00:25 -0400 -Subject: [PATCH 0968/4131] drm/amd/display: Flattening core_dc to dc - --Flattening core_dc to dc - -Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> -Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> - - Conflicts: - drivers/gpu/drm/amd/display/dc/dc.h - drivers/gpu/drm/amd/display/dc/inc/core_dc.h - -Change-Id: I79c50941417c9be663323c08c389bfdca871368b ---- - drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 73 +++++---- - drivers/gpu/drm/amd/display/dc/core/dc.c | 164 ++++++++++----------- - drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 20 +-- - .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 3 +- - drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 ++- - drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 1 - - drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +- - drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 22 +-- - drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 14 +- - drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 10 +- - drivers/gpu/drm/amd/display/dc/dc.h | 75 ++++++++-- - .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 5 +- - drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 10 +- - drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 4 +- - drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 +- - .../amd/display/dc/dce100/dce100_hw_sequencer.c | 9 +- - .../amd/display/dc/dce100/dce100_hw_sequencer.h | 6 +- - .../drm/amd/display/dc/dce100/dce100_resource.c | 22 +-- - .../drm/amd/display/dc/dce100/dce100_resource.h | 4 +- - .../amd/display/dc/dce110/dce110_hw_sequencer.c | 72 ++++----- - .../amd/display/dc/dce110/dce110_hw_sequencer.h | 12 +- - .../drm/amd/display/dc/dce110/dce110_resource.c | 26 ++-- - .../drm/amd/display/dc/dce110/dce110_resource.h | 4 +- - .../amd/display/dc/dce112/dce112_hw_sequencer.c | 5 +- - .../amd/display/dc/dce112/dce112_hw_sequencer.h | 4 +- - .../drm/amd/display/dc/dce112/dce112_resource.c | 26 ++-- - .../drm/amd/display/dc/dce112/dce112_resource.h | 10 +- - .../amd/display/dc/dce120/dce120_hw_sequencer.c | 5 +- - .../amd/display/dc/dce120/dce120_hw_sequencer.h | 4 +- - .../drm/amd/display/dc/dce120/dce120_resource.c | 18 +-- - .../drm/amd/display/dc/dce120/dce120_resource.h | 4 +- - .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 5 +- - .../drm/amd/display/dc/dce80/dce80_hw_sequencer.h | 4 +- - .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 46 +++--- - .../gpu/drm/amd/display/dc/dce80/dce80_resource.h | 8 +- - drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c | 1 - - .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 108 +++++++------- - .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 4 +- - .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 34 ++--- - .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.h | 4 +- - drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 59 -------- - drivers/gpu/drm/amd/display/dc/inc/core_types.h | 8 +- - drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 2 +- - drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 12 +- - drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 1 + - drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 50 ++++--- - drivers/gpu/drm/amd/display/dc/inc/resource.h | 15 +- - .../amd/display/dc/irq/dce110/irq_service_dce110.c | 6 +- - .../amd/display/dc/irq/dce80/irq_service_dce80.c | 1 - - .../gpu/drm/amd/display/include/logger_interface.h | 10 +- - .../drm/amd/display/modules/freesync/freesync.c | 11 +- - 51 files changed, 512 insertions(+), 532 deletions(-) - delete mode 100644 drivers/gpu/drm/amd/display/dc/inc/core_dc.h - -diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c -index 6fb1b9a..f0dfd3c 100644 ---- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c -+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c -@@ -27,7 +27,6 @@ - #include "dcn_calcs.h" - #include "dcn_calc_auto.h" - #include "dc.h" --#include "core_dc.h" - #include "dal_asic_id.h" - - #include "resource.h" -@@ -399,7 +398,7 @@ static void pipe_ctx_to_e2e_pipe_params ( - } - - static void dcn_bw_calc_rq_dlg_ttu( -- const struct core_dc *dc, -+ const struct dc *dc, - const struct dcn_bw_internal_vars *v, - struct pipe_ctx *pipe, - int in_idx) -@@ -674,45 +673,45 @@ static void calc_wm_sets_and_perf_params( - context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a; - } - --static bool dcn_bw_apply_registry_override(struct core_dc *dc) -+static bool dcn_bw_apply_registry_override(struct dc *dc) - { - bool updated = false; - - kernel_fpu_begin(); -- if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->public.debug.sr_exit_time_ns -- && dc->public.debug.sr_exit_time_ns) { -+ if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns -+ && dc->debug.sr_exit_time_ns) { - updated = true; -- dc->dcn_soc->sr_exit_time = dc->public.debug.sr_exit_time_ns / 1000.0; -+ dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0; - } - - if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000) -- != dc->public.debug.sr_enter_plus_exit_time_ns -- && dc->public.debug.sr_enter_plus_exit_time_ns) { -+ != dc->debug.sr_enter_plus_exit_time_ns -+ && dc->debug.sr_enter_plus_exit_time_ns) { - updated = true; - dc->dcn_soc->sr_enter_plus_exit_time = -- dc->public.debug.sr_enter_plus_exit_time_ns / 1000.0; -+ dc->debug.sr_enter_plus_exit_time_ns / 1000.0; - } - -- if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->public.debug.urgent_latency_ns -- && dc->public.debug.urgent_latency_ns) { -+ if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns -+ && dc->debug.urgent_latency_ns) { - updated = true; -- dc->dcn_soc->urgent_latency = dc->public.debug.urgent_latency_ns / 1000.0; -+ dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0; - } - - if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000) -- != dc->public.debug.percent_of_ideal_drambw -- && dc->public.debug.percent_of_ideal_drambw) { -+ != dc->debug.percent_of_ideal_drambw -+ && dc->debug.percent_of_ideal_drambw) { - updated = true; - dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency = -- dc->public.debug.percent_of_ideal_drambw; -+ dc->debug.percent_of_ideal_drambw; - } - - if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000) -- != dc->public.debug.dram_clock_change_latency_ns -- && dc->public.debug.dram_clock_change_latency_ns) { -+ != dc->debug.dram_clock_change_latency_ns -+ && dc->debug.dram_clock_change_latency_ns) { - updated = true; - dc->dcn_soc->dram_clock_change_latency = -- dc->public.debug.dram_clock_change_latency_ns / 1000.0; -+ dc->debug.dram_clock_change_latency_ns / 1000.0; - } - kernel_fpu_end(); - -@@ -720,7 +719,7 @@ static bool dcn_bw_apply_registry_override(struct core_dc *dc) - } - - bool dcn_validate_bandwidth( -- const struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - const struct resource_pool *pool = dc->res_pool; -@@ -730,8 +729,8 @@ bool dcn_validate_bandwidth( - bool bw_limit_pass; - float bw_limit; - -- if (dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public))) -- dcn_bw_sync_calcs_and_dml(DC_TO_CORE(&dc->public)); -+ if (dcn_bw_apply_registry_override(dc)) -+ dcn_bw_sync_calcs_and_dml(dc); - - memset(v, 0, sizeof(*v)); - kernel_fpu_begin(); -@@ -850,7 +849,7 @@ bool dcn_validate_bandwidth( - v->phyclk_per_state[1] = v->phyclkv_mid0p72; - v->phyclk_per_state[0] = v->phyclkv_min0p65; - -- if (dc->public.debug.disable_pipe_split) { -+ if (dc->debug.disable_pipe_split) { - v->max_dispclk[0] = v->max_dppclk_vmin0p65; - } - -@@ -982,15 +981,15 @@ bool dcn_validate_bandwidth( - mode_support_and_system_configuration(v); - - if (v->voltage_level == 0 && -- (dc->public.debug.sr_exit_time_dpm0_ns -- || dc->public.debug.sr_enter_plus_exit_time_dpm0_ns)) { -- struct core_dc *dc_core = DC_TO_CORE(&dc->public); -+ (dc->debug.sr_exit_time_dpm0_ns -+ || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) { -+ struct dc *dc_core = dc; - -- if (dc->public.debug.sr_enter_plus_exit_time_dpm0_ns) -+ if (dc->debug.sr_enter_plus_exit_time_dpm0_ns) - v->sr_enter_plus_exit_time = -- dc->public.debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; -- if (dc->public.debug.sr_exit_time_dpm0_ns) -- v->sr_exit_time = dc->public.debug.sr_exit_time_dpm0_ns / 1000.0f; -+ dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f; -+ if (dc->debug.sr_exit_time_dpm0_ns) -+ v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f; - dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; - dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time; - mode_support_and_system_configuration(v); -@@ -1020,7 +1019,7 @@ bool dcn_validate_bandwidth( - context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000); - context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000); - context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000); -- if (dc->public.debug.max_disp_clk == true) -+ if (dc->debug.max_disp_clk == true) - context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000); - context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2; - -@@ -1109,13 +1108,13 @@ bool dcn_validate_bandwidth( - - input_idx++; - } -- if (dc->public.debug.use_dml_wm) -+ if (dc->debug.use_dml_wm) - dcn_dml_wm_override(v, (struct display_mode_lib *) - &dc->dml, context, pool); - } - - if (v->voltage_level == 0) { -- struct core_dc *dc_core = DC_TO_CORE(&dc->public); -+ struct dc *dc_core = dc; - - dc_core->dml.soc.sr_enter_plus_exit_time_us = - dc_core->dcn_soc->sr_enter_plus_exit_time; -@@ -1138,7 +1137,7 @@ bool dcn_validate_bandwidth( - } - - unsigned int dcn_find_normalized_clock_vdd_Level( -- const struct core_dc *dc, -+ const struct dc *dc, - enum dm_pp_clock_type clocks_type, - int clocks_in_khz) - { -@@ -1228,7 +1227,7 @@ unsigned int dcn_find_normalized_clock_vdd_Level( - } - - unsigned int dcn_find_dcfclk_suits_all( -- const struct core_dc *dc, -+ const struct dc *dc, - struct clocks_value *clocks) - { - unsigned vdd_level, vdd_level_temp; -@@ -1270,7 +1269,7 @@ unsigned int dcn_find_dcfclk_suits_all( - return dcf_clk; - } - --void dcn_bw_update_from_pplib(struct core_dc *dc) -+void dcn_bw_update_from_pplib(struct dc *dc) - { - struct dc_context *ctx = dc->ctx; - struct dm_pp_clock_levels_with_voltage clks = {0}; -@@ -1310,7 +1309,7 @@ void dcn_bw_update_from_pplib(struct core_dc *dc) - kernel_fpu_end(); - } - --void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc) -+void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) - { - struct dm_pp_wm_sets_with_clock_ranges_soc15 clk_ranges = {0}; - int max_fclk_khz, nom_fclk_khz, min_fclk_khz, max_dcfclk_khz, -@@ -1388,7 +1387,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc) - dm_pp_notify_wm_clock_changes_soc15(dc->ctx, &clk_ranges); - } - --void dcn_bw_sync_calcs_and_dml(struct core_dc *dc) -+void dcn_bw_sync_calcs_and_dml(struct dc *dc) - { - kernel_fpu_begin(); - dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c -index 9a588a3..4a543dd 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c -@@ -35,7 +35,6 @@ - #include "clock_source.h" - #include "dc_bios_types.h" - --#include "dce_calcs.h" - #include "bios_parser_interface.h" - #include "include/irq_service_interface.h" - #include "transform.h" -@@ -52,7 +51,7 @@ - /******************************************************************************* - * Private functions - ******************************************************************************/ --static void destroy_links(struct core_dc *dc) -+static void destroy_links(struct dc *dc) - { - uint32_t i; - -@@ -63,7 +62,7 @@ static void destroy_links(struct core_dc *dc) - } - - static bool create_links( -- struct core_dc *dc, -+ struct dc *dc, - uint32_t num_virtual_links) - { - int i; -@@ -153,7 +152,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, - int vmin, int vmax) - { - /* TODO: Support multiple streams */ -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct dc_stream_state *stream = streams[0]; - int i = 0; - bool ret = false; -@@ -179,7 +178,7 @@ static bool stream_get_crtc_position(struct dc *dc, - unsigned int *v_pos, unsigned int *nom_v_pos) - { - /* TODO: Support multiple streams */ -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct dc_stream_state *stream = streams[0]; - int i = 0; - bool ret = false; -@@ -202,7 +201,7 @@ static bool stream_get_crtc_position(struct dc *dc, - - static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - int i = 0; - bool ret = false; - struct pipe_ctx *pipes; -@@ -220,7 +219,7 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) - - static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - int i = 0; - bool ret = false; - struct pipe_ctx *pipes; -@@ -245,7 +244,7 @@ static void set_static_screen_events(struct dc *dc, - int num_streams, - const struct dc_static_screen_events *events) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - int i = 0; - int j = 0; - struct pipe_ctx *pipes_affected[MAX_PIPES]; -@@ -270,7 +269,7 @@ static void set_drive_settings(struct dc *dc, - struct link_training_settings *lt_settings, - const struct dc_link *link) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - int i; - - for (i = 0; i < core_dc->link_count; i++) { -@@ -288,7 +287,7 @@ static void perform_link_training(struct dc *dc, - struct dc_link_settings *link_setting, - bool skip_video_pattern) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - int i; - - for (i = 0; i < core_dc->link_count; i++) -@@ -369,48 +368,48 @@ void set_dither_option(struct dc_stream_state *stream, - opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); - } - --static void allocate_dc_stream_funcs(struct core_dc *core_dc) -+static void allocate_dc_stream_funcs(struct dc *core_dc) - { - if (core_dc->hwss.set_drr != NULL) { -- core_dc->public.stream_funcs.adjust_vmin_vmax = -+ core_dc->stream_funcs.adjust_vmin_vmax = - stream_adjust_vmin_vmax; - } - -- core_dc->public.stream_funcs.set_static_screen_events = -+ core_dc->stream_funcs.set_static_screen_events = - set_static_screen_events; - -- core_dc->public.stream_funcs.get_crtc_position = -+ core_dc->stream_funcs.get_crtc_position = - stream_get_crtc_position; - -- core_dc->public.stream_funcs.set_gamut_remap = -+ core_dc->stream_funcs.set_gamut_remap = - set_gamut_remap; - -- core_dc->public.stream_funcs.program_csc_matrix = -+ core_dc->stream_funcs.program_csc_matrix = - program_csc_matrix; - -- core_dc->public.stream_funcs.set_dither_option = -+ core_dc->stream_funcs.set_dither_option = - set_dither_option; - -- core_dc->public.link_funcs.set_drive_settings = -+ core_dc->link_funcs.set_drive_settings = - set_drive_settings; - -- core_dc->public.link_funcs.perform_link_training = -+ core_dc->link_funcs.perform_link_training = - perform_link_training; - -- core_dc->public.link_funcs.set_preferred_link_settings = -+ core_dc->link_funcs.set_preferred_link_settings = - set_preferred_link_settings; - -- core_dc->public.link_funcs.enable_hpd = -+ core_dc->link_funcs.enable_hpd = - enable_hpd; - -- core_dc->public.link_funcs.disable_hpd = -+ core_dc->link_funcs.disable_hpd = - disable_hpd; - -- core_dc->public.link_funcs.set_test_pattern = -+ core_dc->link_funcs.set_test_pattern = - set_test_pattern; - } - --static void destruct(struct core_dc *dc) -+static void destruct(struct dc *dc) - { - dc_release_validate_context(dc->current_context); - dc->current_context = NULL; -@@ -446,10 +445,11 @@ static void destruct(struct core_dc *dc) - - dm_free(dc->dcn_ip); - dc->dcn_ip = NULL; -+ - #endif - } - --static bool construct(struct core_dc *dc, -+static bool construct(struct dc *dc, - const struct dc_init_data *init_params) - { - struct dal_logger *logger; -@@ -508,7 +508,7 @@ static bool construct(struct core_dc *dc, - - dc_ctx->cgs_device = init_params->cgs_device; - dc_ctx->driver_context = init_params->driver; -- dc_ctx->dc = &dc->public; -+ dc_ctx->dc = dc; - dc_ctx->asic_id = init_params->asic_id; - - /* Create logger */ -@@ -621,7 +621,7 @@ void ProgramPixelDurationV(unsigned int pixelClockInKHz ) - - struct dc *dc_create(const struct dc_init_data *init_params) - { -- struct core_dc *core_dc = dm_alloc(sizeof(*core_dc)); -+ struct dc *core_dc = dm_alloc(sizeof(*core_dc)); - unsigned int full_pipe_count; - - if (NULL == core_dc) -@@ -636,23 +636,23 @@ struct dc *dc_create(const struct dc_init_data *init_params) - full_pipe_count = core_dc->res_pool->pipe_count; - if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE) - full_pipe_count--; -- core_dc->public.caps.max_streams = min( -+ core_dc->caps.max_streams = min( - full_pipe_count, - core_dc->res_pool->stream_enc_count); - -- core_dc->public.caps.max_links = core_dc->link_count; -- core_dc->public.caps.max_audios = core_dc->res_pool->audio_count; -+ core_dc->caps.max_links = core_dc->link_count; -+ core_dc->caps.max_audios = core_dc->res_pool->audio_count; - -- core_dc->public.config = init_params->flags; -+ core_dc->config = init_params->flags; - - dm_logger_write(core_dc->ctx->logger, LOG_DC, - "Display Core initialized\n"); - - - /* TODO: missing feature to be enabled */ -- core_dc->public.debug.disable_dfs_bypass = true; -+ core_dc->debug.disable_dfs_bypass = true; - -- return &core_dc->public; -+ return core_dc; - - construct_fail: - dm_free(core_dc); -@@ -663,14 +663,14 @@ struct dc *dc_create(const struct dc_init_data *init_params) - - void dc_destroy(struct dc **dc) - { -- struct core_dc *core_dc = DC_TO_CORE(*dc); -+ struct dc *core_dc = *dc; - destruct(core_dc); - dm_free(core_dc); - *dc = NULL; - } - - static bool is_validation_required( -- const struct core_dc *dc, -+ const struct dc *dc, - const struct dc_validation_set set[], - int set_count) - { -@@ -705,7 +705,7 @@ static bool is_validation_required( - } - - static bool validate_streams ( -- const struct dc *dc, -+ struct dc *dc, - const struct dc_validation_set set[], - int set_count) - { -@@ -719,7 +719,7 @@ static bool validate_streams ( - } - - static bool validate_surfaces( -- const struct dc *dc, -+ struct dc *dc, - const struct dc_validation_set set[], - int set_count) - { -@@ -734,11 +734,11 @@ static bool validate_surfaces( - } - - struct validate_context *dc_get_validate_context( -- const struct dc *dc, -+ struct dc *dc, - const struct dc_validation_set set[], - uint8_t set_count) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - enum dc_status result = DC_ERROR_UNEXPECTED; - struct validate_context *context; - -@@ -773,11 +773,11 @@ struct validate_context *dc_get_validate_context( - } - - bool dc_validate_resources( -- const struct dc *dc, -+ struct dc *dc, - const struct dc_validation_set set[], - uint8_t set_count) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - enum dc_status result = DC_ERROR_UNEXPECTED; - struct validate_context *context; - -@@ -811,10 +811,10 @@ bool dc_validate_resources( - } - - bool dc_validate_guaranteed( -- const struct dc *dc, -+ struct dc *dc, - struct dc_stream_state *stream) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - enum dc_status result = DC_ERROR_UNEXPECTED; - struct validate_context *context; - -@@ -844,7 +844,7 @@ bool dc_validate_guaranteed( - } - - static void program_timing_sync( -- struct core_dc *core_dc, -+ struct dc *core_dc, - struct validate_context *ctx) - { - int i, j; -@@ -918,7 +918,7 @@ static void program_timing_sync( - } - - static bool context_changed( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - uint8_t i; -@@ -935,7 +935,7 @@ static bool context_changed( - } - - static bool streams_changed( -- struct core_dc *dc, -+ struct dc *dc, - struct dc_stream_state *streams[], - uint8_t stream_count) - { -@@ -961,7 +961,7 @@ bool dc_enable_stereo( - bool ret = true; - int i, j; - struct pipe_ctx *pipe; -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - - #ifdef ENABLE_FBC - struct compressor *fbc_compressor = core_dc->fbc_compressor; -@@ -996,7 +996,7 @@ bool dc_enable_stereo( - */ - static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct dc_bios *dcb = core_dc->ctx->dc_bios; - enum dc_status result = DC_ERROR_UNEXPECTED; - struct pipe_ctx *pipe; -@@ -1064,7 +1064,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c - bool dc_commit_context(struct dc *dc, struct validate_context *context) - { - enum dc_status result = DC_ERROR_UNEXPECTED; -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - int i; - - if (false == context_changed(core_dc, context)) -@@ -1092,7 +1092,7 @@ bool dc_commit_streams( - struct dc_stream_state *streams[], - uint8_t stream_count) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - enum dc_status result = DC_ERROR_UNEXPECTED; - struct validate_context *context; - struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } }; -@@ -1158,7 +1158,7 @@ bool dc_commit_streams( - bool dc_post_update_surfaces_to_stream(struct dc *dc) - { - int i; -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct validate_context *context = core_dc->current_context; - - post_surface_trace(dc); -@@ -1375,7 +1375,7 @@ static enum surface_update_type get_scaling_info_update_type( - } - - static enum surface_update_type det_surface_update( -- const struct core_dc *dc, -+ const struct dc *dc, - const struct dc_surface_update *u, - int surface_index) - { -@@ -1410,7 +1410,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( - struct dc_stream_update *stream_update, - const struct dc_stream_status *stream_status) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - int i; - enum surface_update_type overall_type = UPDATE_TYPE_FAST; - -@@ -1456,7 +1456,7 @@ void dc_update_planes_and_stream(struct dc *dc, - struct dc_stream_state *stream, - struct dc_stream_update *stream_update) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct validate_context *context; - int i, j; - enum surface_update_type update_type; -@@ -1781,29 +1781,29 @@ void dc_update_planes_and_stream(struct dc *dc, - DC_ERROR("Failed to allocate new validate context!\n"); - } - --uint8_t dc_get_current_stream_count(const struct dc *dc) -+uint8_t dc_get_current_stream_count(struct dc *dc) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - return core_dc->current_context->stream_count; - } - --struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i) -+struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - if (i < core_dc->current_context->stream_count) - return core_dc->current_context->streams[i]; - return NULL; - } - --struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index) -+struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - return core_dc->links[link_index]; - } - --struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe) -+struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) { - return core_dc->res_pool->dwbc[(int)pipe]; - } else { -@@ -1814,20 +1814,20 @@ struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe) - const struct graphics_object_id dc_get_link_id_at_index( - struct dc *dc, uint32_t link_index) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - return core_dc->links[link_index]->link_id; - } - - enum dc_irq_source dc_get_hpd_irq_source_at_index( - struct dc *dc, uint32_t link_index) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - return core_dc->links[link_index]->irq_source_hpd; - } - - const struct audio **dc_get_audios(struct dc *dc) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - return (const struct audio **)core_dc->res_pool->audios; - } - -@@ -1837,7 +1837,7 @@ void dc_flip_plane_addrs( - struct dc_flip_addrs flip_addrs[], - uint32_t count) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - int i, j; - - for (i = 0; i < count; i++) { -@@ -1862,24 +1862,24 @@ enum dc_irq_source dc_interrupt_to_irq_source( - uint32_t src_id, - uint32_t ext_id) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id); - } - --void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable) -+void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable) - { -- struct core_dc *core_dc; -+ struct dc *core_dc; - - if (dc == NULL) - return; -- core_dc = DC_TO_CORE(dc); -+ core_dc = dc; - - dal_irq_service_set(core_dc->res_pool->irqs, src, enable); - } - - void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - dal_irq_service_ack(core_dc->res_pool->irqs, src); - } - -@@ -1888,7 +1888,7 @@ void dc_set_power_state( - enum dc_acpi_cm_power_state power_state, - enum dc_video_power_state video_power_state) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - atomic_t ref_count; - - core_dc->previous_power_state = core_dc->current_power_state; -@@ -1921,9 +1921,9 @@ void dc_set_power_state( - - } - --void dc_resume(const struct dc *dc) -+void dc_resume(struct dc *dc) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - - uint32_t i; - -@@ -1938,7 +1938,7 @@ bool dc_read_aux_dpcd( - uint8_t *data, - uint32_t size) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - - struct dc_link *link = core_dc->links[link_index]; - enum ddc_result r = dal_ddc_service_read_dpcd_data( -@@ -1958,7 +1958,7 @@ bool dc_write_aux_dpcd( - const uint8_t *data, - uint32_t size) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct dc_link *link = core_dc->links[link_index]; - - enum ddc_result r = dal_ddc_service_write_dpcd_data( -@@ -1979,7 +1979,7 @@ bool dc_read_aux_i2c( - uint8_t *data, - uint32_t size) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - - struct dc_link *link = core_dc->links[link_index]; - enum ddc_result r = dal_ddc_service_read_dpcd_data( -@@ -2000,7 +2000,7 @@ bool dc_write_aux_i2c( - const uint8_t *data, - uint32_t size) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct dc_link *link = core_dc->links[link_index]; - - enum ddc_result r = dal_ddc_service_write_dpcd_data( -@@ -2022,7 +2022,7 @@ bool dc_query_ddc_data( - uint8_t *read_buf, - uint32_t read_size) { - -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - - struct dc_link *link = core_dc->links[link_index]; - -@@ -2042,7 +2042,7 @@ bool dc_submit_i2c( - uint32_t link_index, - struct i2c_command *cmd) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - - struct dc_link *link = core_dc->links[link_index]; - struct ddc_service *ddc = link->ddc; -@@ -2161,7 +2161,7 @@ void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) - bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) - { - int i; -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct mem_input *mi = NULL; - - for (i = 0; i < core_dc->res_pool->pipe_count; i++) { -@@ -2187,7 +2187,7 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) - - void dc_log_hw_state(struct dc *dc) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - - if (core_dc->hwss.log_hw_state) - core_dc->hwss.log_hw_state(core_dc); -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c -index 21af3bc..d74eed8 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c -@@ -37,12 +37,12 @@ - } while (0) - - void pre_surface_trace( -- const struct dc *dc, -+ struct dc *dc, - const struct dc_plane_state *const *plane_states, - int surface_count) - { - int i; -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct dal_logger *logger = core_dc->ctx->logger; - - for (i = 0; i < surface_count; i++) { -@@ -158,12 +158,12 @@ void pre_surface_trace( - } - - void update_surface_trace( -- const struct dc *dc, -+ struct dc *dc, - const struct dc_surface_update *updates, - int surface_count) - { - int i; -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct dal_logger *logger = core_dc->ctx->logger; - - for (i = 0; i < surface_count; i++) { -@@ -279,9 +279,9 @@ void update_surface_trace( - SURFACE_TRACE("\n"); - } - --void post_surface_trace(const struct dc *dc) -+void post_surface_trace(struct dc *dc) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct dal_logger *logger = core_dc->ctx->logger; - - SURFACE_TRACE("post surface process.\n"); -@@ -289,11 +289,11 @@ void post_surface_trace(const struct dc *dc) - } - - void context_timing_trace( -- const struct dc *dc, -+ struct dc *dc, - struct resource_context *res_ctx) - { - int i; -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct dal_logger *logger = core_dc->ctx->logger; - int h_pos[MAX_PIPES], v_pos[MAX_PIPES]; - struct crtc_position position; -@@ -328,11 +328,11 @@ void context_timing_trace( - } - - void context_clock_trace( -- const struct dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - #if defined(CONFIG_DRM_AMD_DC_DCN1_0) -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct dal_logger *logger = core_dc->ctx->logger; - - CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n" -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c -index 7b1f249..71993d5 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c -@@ -25,7 +25,6 @@ - - #include "dm_services.h" - #include "core_types.h" --#include "core_dc.h" - #include "timing_generator.h" - #include "hw_sequencer.h" - -@@ -55,7 +54,7 @@ static const struct tg_color black_color_format[] = { - }; - - void color_space_to_black_color( -- const struct core_dc *dc, -+ const struct dc *dc, - enum dc_color_space colorspace, - struct tg_color *black_color) - { -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c -index b858fec..1888bf4 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c -@@ -26,14 +26,13 @@ - #include "dm_services.h" - #include "dm_helpers.h" - #include "dc.h" --#include "core_dc.h" - #include "grph_object_id.h" - #include "gpio_service_interface.h" - #include "core_status.h" - #include "dc_link_dp.h" - #include "dc_link_ddc.h" - #include "link_hwss.h" --#include "stream_encoder.h" -+ - #include "link_encoder.h" - #include "hw_sequencer.h" - #include "resource.h" -@@ -1392,7 +1391,7 @@ enum dc_status dc_link_validate_mode_timing( - bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, - uint32_t frame_ramp, const struct dc_stream_state *stream) - { -- struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); -+ struct dc *core_dc = link->ctx->dc; - struct abm *abm = core_dc->res_pool->abm; - unsigned int controller_id = 0; - int i; -@@ -1431,7 +1430,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, - - bool dc_link_set_abm_disable(const struct dc_link *link) - { -- struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); -+ struct dc *core_dc = link->ctx->dc; - struct abm *abm = core_dc->res_pool->abm; - - if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL)) -@@ -1445,7 +1444,7 @@ bool dc_link_set_abm_disable(const struct dc_link *link) - - bool dc_link_set_psr_enable(const struct dc_link *link, bool enable) - { -- struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); -+ struct dc *core_dc = link->ctx->dc; - struct dmcu *dmcu = core_dc->res_pool->dmcu; - - if (dmcu != NULL && link->psr_enabled) -@@ -1456,7 +1455,7 @@ bool dc_link_set_psr_enable(const struct dc_link *link, bool enable) - - bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state) - { -- struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); -+ struct dc *core_dc = link->ctx->dc; - struct dmcu *dmcu = core_dc->res_pool->dmcu; - - if (dmcu != NULL && link->psr_enabled) -@@ -1469,7 +1468,7 @@ bool dc_link_setup_psr(struct dc_link *link, - const struct dc_stream_state *stream, struct psr_config *psr_config, - struct psr_context *psr_context) - { -- struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); -+ struct dc *core_dc = link->ctx->dc; - struct dmcu *dmcu = core_dc->res_pool->dmcu; - int i; - -@@ -1874,7 +1873,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) - - void core_link_enable_stream(struct pipe_ctx *pipe_ctx) - { -- struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); -+ struct dc *core_dc = pipe_ctx->stream->ctx->dc; - - enum dc_status status = enable_link(pipe_ctx); - -@@ -1907,7 +1906,7 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx) - - void core_link_disable_stream(struct pipe_ctx *pipe_ctx) - { -- struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); -+ struct dc *core_dc = pipe_ctx->stream->ctx->dc; - - if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) - deallocate_mst_payload(pipe_ctx); -@@ -1919,7 +1918,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx) - - void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) - { -- struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc); -+ struct dc *core_dc = pipe_ctx->stream->ctx->dc; - - if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) - return; -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c -index 9d5fe65..0144c98 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c -@@ -10,7 +10,6 @@ - #include "core_status.h" - #include "dpcd_defs.h" - --#include "core_dc.h" - #include "resource.h" - - /* maximum pre emphasis level allowed for each voltage swing level*/ -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c -index d19c663..da880bd 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c -@@ -3,7 +3,7 @@ - - #include "dm_services.h" - #include "dc.h" --#include "inc/core_dc.h" -+#include "inc/core_types.h" - #include "include/ddc_service_types.h" - #include "include/i2caux_interface.h" - #include "link_hwss.h" -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c -index f6fb19a..e3cf519 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c -@@ -92,7 +92,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) - } - - struct resource_pool *dc_create_resource_pool( -- struct core_dc *dc, -+ struct dc *dc, - int num_virtual_links, - enum dce_version dc_version, - struct hw_asic_id asic_id) -@@ -153,7 +153,7 @@ struct resource_pool *dc_create_resource_pool( - return res_pool; - } - --void dc_destroy_resource_pool(struct core_dc *dc) -+void dc_destroy_resource_pool(struct dc *dc) - { - if (dc) { - if (dc->res_pool) -@@ -193,7 +193,7 @@ static void update_num_audio( - - bool resource_construct( - unsigned int num_virtual_links, -- struct core_dc *dc, -+ struct dc *dc, - struct resource_pool *pool, - const struct resource_create_funcs *create_funcs) - { -@@ -892,7 +892,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) - - - enum dc_status resource_build_scaling_params_for_context( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context) - { - int i; -@@ -1438,7 +1438,7 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream) - } - - enum dc_status resource_map_pool_resources( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context, - struct validate_context *old_context) - { -@@ -2316,7 +2316,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) - } - - enum dc_status resource_map_clock_resources( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context, - struct validate_context *old_context) - { -@@ -2343,7 +2343,7 @@ enum dc_status resource_map_clock_resources( - else { - pipe_ctx->clock_source = NULL; - -- if (!dc->public.config.disable_disp_pll_sharing) -+ if (!dc->config.disable_disp_pll_sharing) - resource_find_used_clk_src_for_sharing( - &context->res_ctx, - pipe_ctx); -@@ -2515,9 +2515,9 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, - fmt_bit_depth->pixel_encoding = pixel_encoding; - } - --bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream) -+bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - struct dc_context *dc_ctx = core_dc->ctx; - struct dc_link *link = stream->sink->link; - struct timing_generator *tg = core_dc->res_pool->timing_generators[0]; -@@ -2547,9 +2547,9 @@ bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream) - return res == DC_OK; - } - --bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state) -+bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - - /* TODO For now validates pixel format only */ - if (core_dc->res_pool->funcs->validate_plane) -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c -index 47e407d..5e4f7f0 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c -@@ -144,7 +144,7 @@ struct dc_stream_status *dc_stream_get_status( - struct dc_stream_state *stream) - { - uint8_t i; -- struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); -+ struct dc *dc = stream->ctx->dc; - - for (i = 0; i < dc->current_context->stream_count; i++) { - if (stream == dc->current_context->streams[i]) { -@@ -163,7 +163,7 @@ bool dc_stream_set_cursor_attributes( - const struct dc_cursor_attributes *attributes) - { - int i; -- struct core_dc *core_dc; -+ struct dc *core_dc; - struct resource_context *res_ctx; - - if (NULL == stream) { -@@ -175,7 +175,7 @@ bool dc_stream_set_cursor_attributes( - return false; - } - -- core_dc = DC_TO_CORE(stream->ctx->dc); -+ core_dc = stream->ctx->dc; - res_ctx = &core_dc->current_context->res_ctx; - - for (i = 0; i < MAX_PIPES; i++) { -@@ -198,7 +198,7 @@ bool dc_stream_set_cursor_position( - const struct dc_cursor_position *position) - { - int i; -- struct core_dc *core_dc; -+ struct dc *core_dc; - struct resource_context *res_ctx; - - if (NULL == stream) { -@@ -211,7 +211,7 @@ bool dc_stream_set_cursor_position( - return false; - } - -- core_dc = DC_TO_CORE(stream->ctx->dc); -+ core_dc = stream->ctx->dc; - res_ctx = &core_dc->current_context->res_ctx; - - for (i = 0; i < MAX_PIPES; i++) { -@@ -246,7 +246,7 @@ bool dc_stream_set_cursor_position( - uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) - { - uint8_t i; -- struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); -+ struct dc *core_dc = stream->ctx->dc; - struct resource_context *res_ctx = - &core_dc->current_context->res_ctx; - -@@ -270,7 +270,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, - { - uint8_t i; - bool ret = false; -- struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); -+ struct dc *core_dc = stream->ctx->dc; - struct resource_context *res_ctx = - &core_dc->current_context->res_ctx; - -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c -index da19c7f..0b6410f 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c -@@ -28,7 +28,7 @@ - #include "dc.h" - - /* DC core (private) */ --#include "core_dc.h" -+#include "core_types.h" - #include "transform.h" - - /******************************************************************************* -@@ -64,9 +64,9 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state, - /*register_flip_interrupt(surface);*/ - } - --struct dc_plane_state *dc_create_plane_state(const struct dc *dc) -+struct dc_plane_state *dc_create_plane_state(struct dc *dc) - { -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - - struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state)); - -@@ -91,7 +91,7 @@ const struct dc_plane_status *dc_plane_get_status( - const struct dc_plane_state *plane_state) - { - const struct dc_plane_status *plane_status; -- struct core_dc *core_dc; -+ struct dc *core_dc; - int i; - - if (!plane_state || -@@ -102,7 +102,7 @@ const struct dc_plane_status *dc_plane_get_status( - } - - plane_status = &plane_state->status; -- core_dc = DC_TO_CORE(plane_state->ctx->dc); -+ core_dc = plane_state->ctx->dc; - - if (core_dc->current_context == NULL) - return NULL; -diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h -index dcad0d9..a34c26f 100644 ---- a/drivers/gpu/drm/amd/display/dc/dc.h -+++ b/drivers/gpu/drm/amd/display/dc/dc.h -@@ -34,14 +34,19 @@ - #include "grph_object_ctrl_defs.h" - #include <inc/hw/opp.h> - -+#include "inc/hw_sequencer.h" -+#include "dml/display_mode_lib.h" -+ -+ -+ - #define MAX_SURFACES 3 - #define MAX_STREAMS 6 - #define MAX_SINKS_PER_LINK 4 - -+ - /******************************************************************************* - * Display Core Interfaces - ******************************************************************************/ -- - struct dc_caps { - uint32_t max_streams; - uint32_t max_links; -@@ -186,7 +191,9 @@ struct dc_debug { - bool disable_psr; - bool force_abm_enable; - }; -- -+struct validate_context; -+struct resource_pool; -+struct dce_hwseq; - struct dc { - struct dc_caps caps; - struct dc_cap_funcs cap_funcs; -@@ -194,6 +201,44 @@ struct dc { - struct dc_link_funcs link_funcs; - struct dc_config config; - struct dc_debug debug; -+ -+ struct dc_context *ctx; -+ -+ uint8_t link_count; -+ struct dc_link *links[MAX_PIPES * 2]; -+ -+ struct validate_context *current_context; -+ struct resource_pool *res_pool; -+ -+ /*Power State*/ -+ enum dc_video_power_state previous_power_state; -+ enum dc_video_power_state current_power_state; -+ -+ /* Display Engine Clock levels */ -+ struct dm_pp_clock_levels sclk_lvls; -+ -+ /* Inputs into BW and WM calculations. */ -+ struct bw_calcs_dceip *bw_dceip; -+ struct bw_calcs_vbios *bw_vbios; -+#ifdef CONFIG_DRM_AMD_DC_DCN1_0 -+ struct dcn_soc_bounding_box *dcn_soc; -+ struct dcn_ip_params *dcn_ip; -+ struct display_mode_lib dml; -+#endif -+ -+ /* HW functions */ -+ struct hw_sequencer_funcs hwss; -+ struct dce_hwseq *hwseq; -+ -+ /* temp store of dm_pp_display_configuration -+ * to compare to see if display config changed -+ */ -+ struct dm_pp_display_configuration prev_display_config; -+ -+ /* FBC compressor */ -+#ifdef ENABLE_FBC -+ struct compressor *fbc_compressor; -+#endif - }; - - enum frame_buffer_mode { -@@ -384,7 +429,7 @@ struct dc_surface_update { - /* - * Create a new surface with default parameters; - */ --struct dc_plane_state *dc_create_plane_state(const struct dc *dc); -+struct dc_plane_state *dc_create_plane_state(struct dc *dc); - const struct dc_plane_status *dc_plane_get_status( - const struct dc_plane_state *plane_state); - -@@ -570,8 +615,8 @@ void dc_stream_log( - struct dal_logger *dc_logger, - enum dc_log_type log_type); - --uint8_t dc_get_current_stream_count(const struct dc *dc); --struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i); -+uint8_t dc_get_current_stream_count(struct dc *dc); -+struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); - - /* - * Return the current frame counter. -@@ -597,9 +642,9 @@ struct dc_validation_set { - uint8_t plane_count; - }; - --bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream); -+bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); - --bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state); -+bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); - /* - * This function takes a set of resources and checks that they are cofunctional. - * -@@ -607,12 +652,12 @@ bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_s - * No hardware is programmed for call. Only validation is done. - */ - struct validate_context *dc_get_validate_context( -- const struct dc *dc, -+ struct dc *dc, - const struct dc_validation_set set[], - uint8_t set_count); - - bool dc_validate_resources( -- const struct dc *dc, -+ struct dc *dc, - const struct dc_validation_set set[], - uint8_t set_count); - -@@ -625,7 +670,7 @@ bool dc_validate_resources( - */ - - bool dc_validate_guaranteed( -- const struct dc *dc, -+ struct dc *dc, - struct dc_stream_state *stream); - - void dc_resource_validate_ctx_copy_construct( -@@ -776,7 +821,7 @@ struct dc_link { - - /* Private to DC core */ - -- const struct core_dc *dc; -+ const struct dc *dc; - - struct dc_context *ctx; - -@@ -807,9 +852,9 @@ const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); - * boot time. They cannot be created or destroyed. - * Use dc_get_caps() to get number of links. - */ --struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index); -+struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); - --struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe); -+struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe); - - /* Return id of physical connector represented by a dc_link at link_index.*/ - const struct graphics_object_id dc_get_link_id_at_index( -@@ -960,7 +1005,7 @@ enum dc_irq_source dc_interrupt_to_irq_source( - struct dc *dc, - uint32_t src_id, - uint32_t ext_id); --void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable); -+void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); - void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); - enum dc_irq_source dc_get_hpd_irq_source_at_index( - struct dc *dc, uint32_t link_index); -@@ -973,7 +1018,7 @@ void dc_set_power_state( - struct dc *dc, - enum dc_acpi_cm_power_state power_state, - enum dc_video_power_state video_power_state); --void dc_resume(const struct dc *dc); -+void dc_resume(struct dc *dc); - - /* - * DPCD access interfaces -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c -index 922af2d..0654fe3 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c -@@ -34,7 +34,6 @@ - - #include "dce_clock_source.h" - --#include "core_dc.h" - #include "reg_helper.h" - - #define REG(reg)\ -@@ -609,7 +608,7 @@ static uint32_t dce110_get_pll_pixel_rate_in_hz( - struct pll_settings *pll_settings) - { - uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; -- struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc); -+ struct dc *dc_core = cs->ctx->dc; - struct validate_context *context = dc_core->current_context; - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; - -@@ -624,7 +623,7 @@ static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll( - struct pll_settings *pll_settings) - { - uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; -- struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc); -+ struct dc *dc_core = cs->ctx->dc; - struct validate_context *context = dc_core->current_context; - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; - -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c -index 7bb2eaf..9d67340 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c -@@ -29,14 +29,12 @@ - #include "fixed32_32.h" - #include "bios_parser_interface.h" - #include "dc.h" --#include "core_dc.h" - #include "dce_abm.h" - #include "dmcu.h" - #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - #include "dcn_calcs.h" --#include "core_dc.h" - #endif -- -+#include "core_types.h" - - - #define TO_DCE_CLOCKS(clocks)\ -@@ -368,7 +366,7 @@ static int dce_psr_set_clock( - { - struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); - struct dc_context *ctx = clk_dce->base.ctx; -- struct core_dc *core_dc = DC_TO_CORE(ctx->dc); -+ struct dc *core_dc = ctx->dc; - struct dmcu *dmcu = core_dc->res_pool->dmcu; - int actual_clk_khz = requested_clk_khz; - -@@ -385,7 +383,7 @@ static int dce112_set_clock( - struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk); - struct bp_set_dce_clock_parameters dce_clk_params; - struct dc_bios *bp = clk->ctx->dc_bios; -- struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); -+ struct dc *core_dc = clk->ctx->dc; - struct abm *abm = core_dc->res_pool->abm; - struct dmcu *dmcu = core_dc->res_pool->dmcu; - int actual_clock = requested_clk_khz; -@@ -621,7 +619,7 @@ static bool dce_apply_clock_voltage_request( - if (send_request) { - #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (clk->ctx->dce_version >= DCN_VERSION_1_0) { -- struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); -+ struct dc *core_dc = clk->ctx->dc; - /*use dcfclk request voltage*/ - clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; - clock_voltage_req.clocks_in_khz = -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c -index 4894e17..d2e66b1 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c -@@ -26,7 +26,7 @@ - #include "dce_hwseq.h" - #include "reg_helper.h" - #include "hw_sequencer.h" --#include "core_dc.h" -+#include "core_types.h" - - #define CTX \ - hws->ctx -@@ -44,7 +44,7 @@ void dce_enable_fe_clock(struct dce_hwseq *hws, - DCFE_CLOCK_ENABLE, enable); - } - --void dce_pipe_control_lock(struct core_dc *dc, -+void dce_pipe_control_lock(struct dc *dc, - struct pipe_ctx *pipe, - bool lock) - { -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h -index 9a97d8e..3a1eb6a 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h -@@ -528,7 +528,7 @@ enum blnd_mode { - void dce_enable_fe_clock(struct dce_hwseq *hwss, - unsigned int inst, bool enable); - --void dce_pipe_control_lock(struct core_dc *dc, -+void dce_pipe_control_lock(struct dc *dc, - struct pipe_ctx *pipe, - bool lock); - -diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c -index c638f47..b7e51c5 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c -@@ -24,7 +24,6 @@ - */ - #include "dm_services.h" - #include "dc.h" --#include "core_dc.h" - #include "core_types.h" - #include "hw_sequencer.h" - #include "dce100_hw_sequencer.h" -@@ -71,7 +70,7 @@ static const struct dce100_hw_seq_reg_offsets reg_offsets[] = { - /***************************PIPE_CONTROL***********************************/ - - static bool dce100_enable_display_power_gating( -- struct core_dc *dc, -+ struct dc *dc, - uint8_t controller_id, - struct dc_bios *dcb, - enum pipe_gating_control power_gating) -@@ -107,7 +106,7 @@ static bool dce100_enable_display_power_gating( - } - - static void dce100_pplib_apply_display_requirements( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; -@@ -127,7 +126,7 @@ static void dce100_pplib_apply_display_requirements( - } - - void dce100_set_bandwidth( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context, - bool decrease_allowed) - { -@@ -143,7 +142,7 @@ void dce100_set_bandwidth( - - /**************************************************************************/ - --bool dce100_hw_sequencer_construct(struct core_dc *dc) -+bool dce100_hw_sequencer_construct(struct dc *dc) - { - dce110_hw_sequencer_construct(dc); - -diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h -index 24433f0..c04aa15 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h -+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h -@@ -28,13 +28,13 @@ - - #include "core_types.h" - --struct core_dc; -+struct dc; - struct validate_context; - --bool dce100_hw_sequencer_construct(struct core_dc *dc); -+bool dce100_hw_sequencer_construct(struct dc *dc); - - void dce100_set_bandwidth( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context, - bool decrease_allowed); - -diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c -index 46f0c71..b2b0363 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c -@@ -652,7 +652,7 @@ static void destruct(struct dce110_resource_pool *pool) - } - - static enum dc_status build_mapped_resource( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context, - struct validate_context *old_context) - { -@@ -688,7 +688,7 @@ static enum dc_status build_mapped_resource( - } - - bool dce100_validate_bandwidth( -- const struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - /* TODO implement when needed but for now hardcode max value*/ -@@ -720,7 +720,7 @@ static bool dce100_validate_surface_sets( - } - - enum dc_status dce100_validate_with_context( -- const struct core_dc *dc, -+ struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *context, -@@ -764,7 +764,7 @@ enum dc_status dce100_validate_with_context( - } - - enum dc_status dce100_validate_guaranteed( -- const struct core_dc *dc, -+ struct dc *dc, - struct dc_stream_state *dc_stream, - struct validate_context *context) - { -@@ -784,7 +784,7 @@ enum dc_status dce100_validate_guaranteed( - - if (result == DC_OK) { - validate_guaranteed_copy_streams( -- context, dc->public.caps.max_streams); -+ context, dc->caps.max_streams); - result = resource_build_scaling_params_for_context(dc, context); - } - -@@ -824,7 +824,7 @@ static const struct resource_funcs dce100_res_pool_funcs = { - - static bool construct( - uint8_t num_virtual_links, -- struct core_dc *dc, -+ struct dc *dc, - struct dce110_resource_pool *pool) - { - unsigned int i; -@@ -909,9 +909,9 @@ static bool construct( - *************************************************/ - pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; - pool->base.pipe_count = res_cap.num_timing_generator; -- dc->public.caps.max_downscale_ratio = 200; -- dc->public.caps.i2c_speed_in_khz = 40; -- dc->public.caps.max_cursor_size = 128; -+ dc->caps.max_downscale_ratio = 200; -+ dc->caps.i2c_speed_in_khz = 40; -+ dc->caps.max_cursor_size = 128; - - for (i = 0; i < pool->base.pipe_count; i++) { - pool->base.timing_generators[i] = -@@ -958,7 +958,7 @@ static bool construct( - } - } - -- dc->public.caps.max_planes = pool->base.pipe_count; -+ dc->caps.max_planes = pool->base.pipe_count; - - if (!resource_construct(num_virtual_links, dc, &pool->base, - &res_create_funcs)) -@@ -978,7 +978,7 @@ static bool construct( - - struct resource_pool *dce100_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc) -+ struct dc *dc) - { - struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); -diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h -index edc50ca..ca7b2b7 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h -+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h -@@ -8,13 +8,13 @@ - #ifndef DCE100_RESOURCE_H_ - #define DCE100_RESOURCE_H_ - --struct core_dc; -+struct dc; - struct resource_pool; - struct dc_validation_set; - - struct resource_pool *dce100_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc); -+ struct dc *dc); - - enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state); - -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c -index ef987ac..8f43d6d 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c -@@ -164,7 +164,7 @@ static void enable_display_pipe_clock_gating( - } - - static bool dce110_enable_display_power_gating( -- struct core_dc *dc, -+ struct dc *dc, - uint8_t controller_id, - struct dc_bios *dcb, - enum pipe_gating_control power_gating) -@@ -944,7 +944,7 @@ static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, - } - } - --static void program_scaler(const struct core_dc *dc, -+static void program_scaler(const struct dc *dc, - const struct pipe_ctx *pipe_ctx) - { - struct tg_color color = {0}; -@@ -955,7 +955,7 @@ static void program_scaler(const struct core_dc *dc, - return; - #endif - -- if (dc->public.debug.surface_visual_confirm) -+ if (dc->debug.surface_visual_confirm) - get_surface_visual_confirm_color(pipe_ctx, &color); - else - color_space_to_black_color(dc, -@@ -979,7 +979,7 @@ static void program_scaler(const struct core_dc *dc, - static enum dc_status dce110_prog_pixclk_crtc_otg( - struct pipe_ctx *pipe_ctx, - struct validate_context *context, -- struct core_dc *dc) -+ struct dc *dc) - { - struct dc_stream_state *stream = pipe_ctx->stream; - struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. -@@ -1035,7 +1035,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( - static enum dc_status apply_single_controller_ctx_to_hw( - struct pipe_ctx *pipe_ctx, - struct validate_context *context, -- struct core_dc *dc) -+ struct dc *dc) - { - struct dc_stream_state *stream = pipe_ctx->stream; - struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. -@@ -1141,7 +1141,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( - - /******************************************************************************/ - --static void power_down_encoders(struct core_dc *dc) -+static void power_down_encoders(struct dc *dc) - { - int i; - -@@ -1151,7 +1151,7 @@ static void power_down_encoders(struct core_dc *dc) - } - } - --static void power_down_controllers(struct core_dc *dc) -+static void power_down_controllers(struct dc *dc) - { - int i; - -@@ -1161,7 +1161,7 @@ static void power_down_controllers(struct core_dc *dc) - } - } - --static void power_down_clock_sources(struct core_dc *dc) -+static void power_down_clock_sources(struct dc *dc) - { - int i; - -@@ -1176,7 +1176,7 @@ static void power_down_clock_sources(struct core_dc *dc) - } - } - --static void power_down_all_hw_blocks(struct core_dc *dc) -+static void power_down_all_hw_blocks(struct dc *dc) - { - power_down_encoders(dc); - -@@ -1191,7 +1191,7 @@ static void power_down_all_hw_blocks(struct core_dc *dc) - } - - static void disable_vga_and_power_gate_all_controllers( -- struct core_dc *dc) -+ struct dc *dc) - { - int i; - struct timing_generator *tg; -@@ -1219,7 +1219,7 @@ static void disable_vga_and_power_gate_all_controllers( - * 3. Enable power gating for controller - * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) - */ --void dce110_enable_accelerated_mode(struct core_dc *dc) -+void dce110_enable_accelerated_mode(struct dc *dc) - { - power_down_all_hw_blocks(dc); - -@@ -1245,7 +1245,7 @@ static uint32_t compute_pstate_blackout_duration( - } - - void dce110_set_displaymarks( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context) - { - uint8_t i, num_pipes; -@@ -1311,7 +1311,7 @@ static void set_safe_displaymarks( - } - - static void switch_dp_clock_sources( -- const struct core_dc *dc, -+ const struct dc *dc, - struct resource_context *res_ctx) - { - uint8_t i; -@@ -1403,7 +1403,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, - * may read PLL register to get pixel clock - */ - static uint32_t get_max_pixel_clock_for_all_paths( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context, - bool pre_mode_set) - { -@@ -1444,7 +1444,7 @@ static uint32_t get_max_pixel_clock_for_all_paths( - * etc support for dcn1.0 - */ - static void apply_min_clocks( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context, - enum dm_pp_clocks_state *clocks_state, - bool pre_mode_set) -@@ -1533,7 +1533,7 @@ static void apply_min_clocks( - /* - * Check if FBC can be enabled - */ --static enum dc_status validate_fbc(struct core_dc *dc, -+static enum dc_status validate_fbc(struct dc *dc, - struct validate_context *context) - { - struct pipe_ctx *pipe_ctx = -@@ -1563,7 +1563,7 @@ static enum dc_status validate_fbc(struct core_dc *dc, - /* - * Enable FBC - */ --static enum dc_status enable_fbc(struct core_dc *dc, -+static enum dc_status enable_fbc(struct dc *dc, - struct validate_context *context) - { - enum dc_status status = validate_fbc(dc, context); -@@ -1592,7 +1592,7 @@ static enum dc_status enable_fbc(struct core_dc *dc, - #endif - - static enum dc_status apply_ctx_to_hw_fpga( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - enum dc_status status = DC_ERROR_UNEXPECTED; -@@ -1622,7 +1622,7 @@ static enum dc_status apply_ctx_to_hw_fpga( - } - - static void dce110_reset_hw_ctx_wrap( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - int i; -@@ -1667,7 +1667,7 @@ static void dce110_reset_hw_ctx_wrap( - - - enum dc_status dce110_apply_ctx_to_hw( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - struct dc_bios *dcb = dc->ctx->dc_bios; -@@ -1960,7 +1960,7 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) - * -------------------------------------------------| - * - ******************************************************************************/ --static void program_surface_visibility(const struct core_dc *dc, -+static void program_surface_visibility(const struct dc *dc, - struct pipe_ctx *pipe_ctx) - { - enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; -@@ -2033,7 +2033,7 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx) - * TODO REMOVE, USE UPDATE INSTEAD - */ - static void set_plane_config( -- const struct core_dc *dc, -+ const struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct resource_context *res_ctx) - { -@@ -2112,7 +2112,7 @@ static void set_plane_config( - if (mi->funcs->set_blank) - mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); - -- if (dc->public.config.gpu_vm_support) -+ if (dc->config.gpu_vm_support) - mi->funcs->mem_input_program_pte_vm( - pipe_ctx->plane_res.mi, - plane_state->format, -@@ -2120,7 +2120,7 @@ static void set_plane_config( - plane_state->rotation); - } - --static void update_plane_addr(const struct core_dc *dc, -+static void update_plane_addr(const struct dc *dc, - struct pipe_ctx *pipe_ctx) - { - struct dc_plane_state *plane_state = pipe_ctx->plane_state; -@@ -2158,7 +2158,7 @@ void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) - } - } - --void dce110_power_down(struct core_dc *dc) -+void dce110_power_down(struct dc *dc) - { - power_down_all_hw_blocks(dc); - disable_vga_and_power_gate_all_controllers(dc); -@@ -2203,7 +2203,7 @@ static bool wait_for_reset_trigger_to_occur( - - /* Enable timing synchronization for a group of Timing Generators. */ - static void dce110_enable_timing_synchronization( -- struct core_dc *dc, -+ struct dc *dc, - int group_index, - int group_size, - struct pipe_ctx *grouped_pipes[]) -@@ -2252,7 +2252,7 @@ static void dce110_enable_timing_synchronization( - DC_SYNC_INFO("GSL: Set-up complete.\n"); - } - --static void init_hw(struct core_dc *dc) -+static void init_hw(struct dc *dc) - { - int i; - struct dc_bios *bp; -@@ -2389,7 +2389,7 @@ uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) - } - - static int determine_sclk_from_bounding_box( -- const struct core_dc *dc, -+ const struct dc *dc, - int required_sclk) - { - int i; -@@ -2415,7 +2415,7 @@ static int determine_sclk_from_bounding_box( - } - - static void pplib_apply_display_requirements( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; -@@ -2469,7 +2469,7 @@ static void pplib_apply_display_requirements( - } - - static void dce110_set_bandwidth( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context, - bool decrease_allowed) - { -@@ -2486,7 +2486,7 @@ static void dce110_set_bandwidth( - } - - static void dce110_program_front_end_for_pipe( -- struct core_dc *dc, struct pipe_ctx *pipe_ctx) -+ struct dc *dc, struct pipe_ctx *pipe_ctx) - { - struct mem_input *mi = pipe_ctx->plane_res.mi; - struct pipe_ctx *old_pipe = NULL; -@@ -2567,7 +2567,7 @@ static void dce110_program_front_end_for_pipe( - if (mi->funcs->set_blank) - mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); - -- if (dc->public.config.gpu_vm_support) -+ if (dc->config.gpu_vm_support) - mi->funcs->mem_input_program_pte_vm( - pipe_ctx->plane_res.mi, - plane_state->format, -@@ -2613,7 +2613,7 @@ static void dce110_program_front_end_for_pipe( - } - - static void dce110_apply_ctx_for_surface( -- struct core_dc *dc, -+ struct dc *dc, - const struct dc_stream_state *stream, - int num_planes, - struct validate_context *context) -@@ -2643,7 +2643,7 @@ static void dce110_apply_ctx_for_surface( - } - } - --static void dce110_power_down_fe(struct core_dc *dc, int fe_idx) -+static void dce110_power_down_fe(struct dc *dc, int fe_idx) - { - /* Do not power down fe when stream is active on dce*/ - if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream) -@@ -2657,7 +2657,7 @@ static void dce110_power_down_fe(struct core_dc *dc, int fe_idx) - } - - static void dce110_wait_for_mpcc_disconnect( -- struct core_dc *dc, -+ struct dc *dc, - struct resource_pool *res_pool, - struct pipe_ctx *pipe_ctx) - { -@@ -2719,7 +2719,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { - .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect - }; - --bool dce110_hw_sequencer_construct(struct core_dc *dc) -+bool dce110_hw_sequencer_construct(struct dc *dc) - { - dc->hwss = dce110_funcs; - -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h -index 89782ca..d710f6e6 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h -+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h -@@ -29,20 +29,20 @@ - #include "core_types.h" - - #define GAMMA_HW_POINTS_NUM 256 --struct core_dc; -+struct dc; - struct validate_context; - struct dm_pp_display_configuration; - --bool dce110_hw_sequencer_construct(struct core_dc *dc); -+bool dce110_hw_sequencer_construct(struct dc *dc); - - enum dc_status dce110_apply_ctx_to_hw( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context); - - void dce110_set_display_clock(struct validate_context *context); - - void dce110_set_displaymarks( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context); - - void dce110_enable_stream(struct pipe_ctx *pipe_ctx); -@@ -55,9 +55,9 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, - void dce110_update_info_frame(struct pipe_ctx *pipe_ctx); - - void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); --void dce110_enable_accelerated_mode(struct core_dc *dc); -+void dce110_enable_accelerated_mode(struct dc *dc); - --void dce110_power_down(struct core_dc *dc); -+void dce110_power_down(struct dc *dc); - - void dce110_update_pending_status(struct pipe_ctx *pipe_ctx); - -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c -index 56be84c..2154c2e 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c -@@ -772,7 +772,7 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne - } - - static enum dc_status build_mapped_resource( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context, - struct validate_context *old_context) - { -@@ -814,7 +814,7 @@ static enum dc_status build_mapped_resource( - } - - static bool dce110_validate_bandwidth( -- const struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - bool result = false; -@@ -928,7 +928,7 @@ static bool dce110_validate_surface_sets( - } - - static enum dc_status dce110_validate_with_context( -- const struct core_dc *dc, -+ struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *context, -@@ -972,7 +972,7 @@ static enum dc_status dce110_validate_with_context( - } - - static enum dc_status dce110_validate_guaranteed( -- const struct core_dc *dc, -+ struct dc *dc, - struct dc_stream_state *dc_stream, - struct validate_context *context) - { -@@ -992,7 +992,7 @@ static enum dc_status dce110_validate_guaranteed( - - if (result == DC_OK) { - validate_guaranteed_copy_streams( -- context, dc->public.caps.max_streams); -+ context, dc->caps.max_streams); - result = resource_build_scaling_params_for_context(dc, context); - } - -@@ -1008,7 +1008,7 @@ static struct pipe_ctx *dce110_acquire_underlay( - const struct resource_pool *pool, - struct dc_stream_state *stream) - { -- struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); -+ struct dc *dc = stream->ctx->dc; - struct resource_context *res_ctx = &context->res_ctx; - unsigned int underlay_idx = pool->underlay_pipe_index; - struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx]; -@@ -1117,7 +1117,7 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) - return true; - } - --static void bw_calcs_data_update_from_pplib(struct core_dc *dc) -+static void bw_calcs_data_update_from_pplib(struct dc *dc) - { - struct dm_pp_clock_levels clks = {0}; - -@@ -1184,7 +1184,7 @@ const struct resource_caps *dce110_resource_cap( - - static bool construct( - uint8_t num_virtual_links, -- struct core_dc *dc, -+ struct dc *dc, - struct dce110_resource_pool *pool, - struct hw_asic_id asic_id) - { -@@ -1206,9 +1206,9 @@ static bool construct( - pool->base.pipe_count = pool->base.res_cap->num_timing_generator; - pool->base.underlay_pipe_index = pool->base.pipe_count; - -- dc->public.caps.max_downscale_ratio = 150; -- dc->public.caps.i2c_speed_in_khz = 100; -- dc->public.caps.max_cursor_size = 128; -+ dc->caps.max_downscale_ratio = 150; -+ dc->caps.i2c_speed_in_khz = 100; -+ dc->caps.max_cursor_size = 128; - - /************************************************* - * Create resources * -@@ -1351,7 +1351,7 @@ static bool construct( - if (!dce110_hw_sequencer_construct(dc)) - goto res_create_fail; - -- dc->public.caps.max_planes = pool->base.pipe_count; -+ dc->caps.max_planes = pool->base.pipe_count; - - bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); - -@@ -1366,7 +1366,7 @@ static bool construct( - - struct resource_pool *dce110_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc, -+ struct dc *dc, - struct hw_asic_id asic_id) - { - struct dce110_resource_pool *pool = -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h -index 8e2e85d..5bb692d 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h -+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h -@@ -28,7 +28,7 @@ - - #include "core_types.h" - --struct core_dc; -+struct dc; - struct resource_pool; - - #define TO_DCE110_RES_POOL(pool)\ -@@ -42,7 +42,7 @@ enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx); - - struct resource_pool *dce110_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc, -+ struct dc *dc, - struct hw_asic_id asic_id); - - #endif /* __DC_RESOURCE_DCE110_H__ */ -diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c -index 204f613..8816e09 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c -@@ -25,7 +25,6 @@ - - #include "dm_services.h" - #include "dc.h" --#include "core_dc.h" - #include "core_types.h" - #include "dce112_hw_sequencer.h" - -@@ -112,7 +111,7 @@ static void dce112_init_pte(struct dc_context *ctx) - } - - static bool dce112_enable_display_power_gating( -- struct core_dc *dc, -+ struct dc *dc, - uint8_t controller_id, - struct dc_bios *dcb, - enum pipe_gating_control power_gating) -@@ -153,7 +152,7 @@ static bool dce112_enable_display_power_gating( - return false; - } - --bool dce112_hw_sequencer_construct(struct core_dc *dc) -+bool dce112_hw_sequencer_construct(struct dc *dc) - { - /* All registers used by dce11.2 match those in dce11 in offset and - * structure -diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h -index d96c582..37bd60c 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h -+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h -@@ -28,9 +28,9 @@ - - #include "core_types.h" - --struct core_dc; -+struct dc; - --bool dce112_hw_sequencer_construct(struct core_dc *dc); -+bool dce112_hw_sequencer_construct(struct dc *dc); - - #endif /* __DC_HWSS_DCE112_H__ */ - -diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c -index d6e58a25..89a8dfa 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c -@@ -723,7 +723,7 @@ static struct clock_source *find_matching_pll( - } - - static enum dc_status build_mapped_resource( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context, - struct validate_context *old_context) - { -@@ -759,7 +759,7 @@ static enum dc_status build_mapped_resource( - } - - bool dce112_validate_bandwidth( -- const struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - bool result = false; -@@ -837,7 +837,7 @@ bool dce112_validate_bandwidth( - } - - enum dc_status resource_map_phy_clock_resources( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context, - struct validate_context *old_context) - { -@@ -904,7 +904,7 @@ static bool dce112_validate_surface_sets( - } - - enum dc_status dce112_validate_with_context( -- const struct core_dc *dc, -+ struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *context, -@@ -948,7 +948,7 @@ enum dc_status dce112_validate_with_context( - } - - enum dc_status dce112_validate_guaranteed( -- const struct core_dc *dc, -+ struct dc *dc, - struct dc_stream_state *stream, - struct validate_context *context) - { -@@ -968,7 +968,7 @@ enum dc_status dce112_validate_guaranteed( - - if (result == DC_OK) { - validate_guaranteed_copy_streams( -- context, dc->public.caps.max_streams); -+ context, dc->caps.max_streams); - result = resource_build_scaling_params_for_context(dc, context); - } - -@@ -997,7 +997,7 @@ static const struct resource_funcs dce112_res_pool_funcs = { - .validate_plane = dce100_validate_plane - }; - --static void bw_calcs_data_update_from_pplib(struct core_dc *dc) -+static void bw_calcs_data_update_from_pplib(struct dc *dc) - { - struct dm_pp_clock_levels_with_latency eng_clks = {0}; - struct dm_pp_clock_levels_with_latency mem_clks = {0}; -@@ -1153,7 +1153,7 @@ const struct resource_caps *dce112_resource_cap( - - static bool construct( - uint8_t num_virtual_links, -- struct core_dc *dc, -+ struct dc *dc, - struct dce110_resource_pool *pool) - { - unsigned int i; -@@ -1170,9 +1170,9 @@ static bool construct( - *************************************************/ - pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; - pool->base.pipe_count = pool->base.res_cap->num_timing_generator; -- dc->public.caps.max_downscale_ratio = 200; -- dc->public.caps.i2c_speed_in_khz = 100; -- dc->public.caps.max_cursor_size = 128; -+ dc->caps.max_downscale_ratio = 200; -+ dc->caps.i2c_speed_in_khz = 100; -+ dc->caps.max_cursor_size = 128; - - /************************************************* - * Create resources * -@@ -1319,7 +1319,7 @@ static bool construct( - &res_create_funcs)) - goto res_create_fail; - -- dc->public.caps.max_planes = pool->base.pipe_count; -+ dc->caps.max_planes = pool->base.pipe_count; - - /* Create hardware sequencer */ - if (!dce112_hw_sequencer_construct(dc)) -@@ -1338,7 +1338,7 @@ static bool construct( - - struct resource_pool *dce112_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc) -+ struct dc *dc) - { - struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); -diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h -index feef559..69f8f68 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h -+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h -@@ -28,27 +28,27 @@ - - #include "core_types.h" - --struct core_dc; -+struct dc; - struct resource_pool; - - struct resource_pool *dce112_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc); -+ struct dc *dc); - - enum dc_status dce112_validate_with_context( -- const struct core_dc *dc, -+ struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *context, - struct validate_context *old_context); - - enum dc_status dce112_validate_guaranteed( -- const struct core_dc *dc, -+ struct dc *dc, - struct dc_stream_state *dc_stream, - struct validate_context *context); - - bool dce112_validate_bandwidth( -- const struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context); - - -diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c -index 91301b4..d6225f3 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c -@@ -25,7 +25,6 @@ - - #include "dm_services.h" - #include "dc.h" --#include "core_dc.h" - #include "core_types.h" - #include "dce120_hw_sequencer.h" - #include "dce/dce_hwseq.h" -@@ -149,7 +148,7 @@ static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id) - #endif - - static bool dce120_enable_display_power_gating( -- struct core_dc *dc, -+ struct dc *dc, - uint8_t controller_id, - struct dc_bios *dcb, - enum pipe_gating_control power_gating) -@@ -247,7 +246,7 @@ static void dce120_update_dchub( - - - --bool dce120_hw_sequencer_construct(struct core_dc *dc) -+bool dce120_hw_sequencer_construct(struct dc *dc) - { - /* All registers used by dce11.2 match those in dce11 in offset and - * structure -diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h -index 3402413..6448a17 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h -+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h -@@ -28,9 +28,9 @@ - - #include "core_types.h" - --struct core_dc; -+struct dc; - --bool dce120_hw_sequencer_construct(struct core_dc *dc); -+bool dce120_hw_sequencer_construct(struct dc *dc); - - #endif /* __DC_HWSS_DCE112_H__ */ - -diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c -index 562ae22..b8fcdff 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c -@@ -410,7 +410,7 @@ void dce120_clock_source_destroy(struct clock_source **clk_src) - } - - --bool dce120_hw_sequencer_create(struct core_dc *dc) -+bool dce120_hw_sequencer_create(struct dc *dc) - { - /* All registers used by dce11.2 match those in dce11 in offset and - * structure -@@ -704,7 +704,7 @@ static const struct resource_funcs dce120_res_pool_funcs = { - .validate_plane = dce100_validate_plane - }; - --static void bw_calcs_data_update_from_pplib(struct core_dc *dc) -+static void bw_calcs_data_update_from_pplib(struct dc *dc) - { - struct dm_pp_clock_levels_with_latency eng_clks = {0}; - struct dm_pp_clock_levels_with_latency mem_clks = {0}; -@@ -831,7 +831,7 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) - - static bool construct( - uint8_t num_virtual_links, -- struct core_dc *dc, -+ struct dc *dc, - struct dce110_resource_pool *pool) - { - unsigned int i; -@@ -847,10 +847,10 @@ static bool construct( - pool->base.pipe_count = res_cap.num_timing_generator; - pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; - -- dc->public.caps.max_downscale_ratio = 200; -- dc->public.caps.i2c_speed_in_khz = 100; -- dc->public.caps.max_cursor_size = 128; -- dc->public.debug = debug_defaults; -+ dc->caps.max_downscale_ratio = 200; -+ dc->caps.i2c_speed_in_khz = 100; -+ dc->caps.max_cursor_size = 128; -+ dc->debug = debug_defaults; - - /************************************************* - * Create resources * -@@ -982,7 +982,7 @@ static bool construct( - if (!dce120_hw_sequencer_create(dc)) - goto controller_create_fail; - -- dc->public.caps.max_planes = pool->base.pipe_count; -+ dc->caps.max_planes = pool->base.pipe_count; - - bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); - -@@ -1003,7 +1003,7 @@ static bool construct( - - struct resource_pool *dce120_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc) -+ struct dc *dc) - { - struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); -diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h -index 038c78d..3d1f3cf0 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h -+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h -@@ -28,12 +28,12 @@ - - #include "core_types.h" - --struct core_dc; -+struct dc; - struct resource_pool; - - struct resource_pool *dce120_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc); -+ struct dc *dc); - - #endif /* __DC_RESOURCE_DCE120_H__ */ - -diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c -index 4cba80f..28fe382 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c -@@ -25,7 +25,6 @@ - - #include "dm_services.h" - #include "dc.h" --#include "core_dc.h" - #include "core_types.h" - #include "dce80_hw_sequencer.h" - -@@ -72,7 +71,7 @@ static const struct dce80_hw_seq_reg_offsets reg_offsets[] = { - /***************************PIPE_CONTROL***********************************/ - - static bool dce80_enable_display_power_gating( -- struct core_dc *dc, -+ struct dc *dc, - uint8_t controller_id, - struct dc_bios *dcb, - enum pipe_gating_control power_gating) -@@ -107,7 +106,7 @@ static bool dce80_enable_display_power_gating( - return false; - } - --bool dce80_hw_sequencer_construct(struct core_dc *dc) -+bool dce80_hw_sequencer_construct(struct dc *dc) - { - dce110_hw_sequencer_construct(dc); - -diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h -index 7cc203f..9d6dd05 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h -+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h -@@ -28,9 +28,9 @@ - - #include "core_types.h" - --struct core_dc; -+struct dc; - --bool dce80_hw_sequencer_construct(struct core_dc *dc); -+bool dce80_hw_sequencer_construct(struct dc *dc); - - #endif /* __DC_HWSS_DCE80_H__ */ - -diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c -index 132117e..838bfda 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c -@@ -684,7 +684,7 @@ static void destruct(struct dce110_resource_pool *pool) - } - - static enum dc_status build_mapped_resource( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context, - struct validate_context *old_context) - { -@@ -720,7 +720,7 @@ static enum dc_status build_mapped_resource( - } - - bool dce80_validate_bandwidth( -- const struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - /* TODO implement when needed but for now hardcode max value*/ -@@ -752,7 +752,7 @@ static bool dce80_validate_surface_sets( - } - - enum dc_status dce80_validate_with_context( -- const struct core_dc *dc, -+ struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *context, -@@ -795,7 +795,7 @@ enum dc_status dce80_validate_with_context( - } - - enum dc_status dce80_validate_guaranteed( -- const struct core_dc *dc, -+ struct dc *dc, - struct dc_stream_state *dc_stream, - struct validate_context *context) - { -@@ -815,7 +815,7 @@ enum dc_status dce80_validate_guaranteed( - - if (result == DC_OK) { - validate_guaranteed_copy_streams( -- context, dc->public.caps.max_streams); -+ context, dc->caps.max_streams); - result = resource_build_scaling_params_for_context(dc, context); - } - -@@ -845,7 +845,7 @@ static const struct resource_funcs dce80_res_pool_funcs = { - - static bool dce80_construct( - uint8_t num_virtual_links, -- struct core_dc *dc, -+ struct dc *dc, - struct dce110_resource_pool *pool) - { - unsigned int i; -@@ -865,9 +865,9 @@ static bool dce80_construct( - *************************************************/ - pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; - pool->base.pipe_count = res_cap.num_timing_generator; -- dc->public.caps.max_downscale_ratio = 200; -- dc->public.caps.i2c_speed_in_khz = 40; -- dc->public.caps.max_cursor_size = 128; -+ dc->caps.max_downscale_ratio = 200; -+ dc->caps.i2c_speed_in_khz = 40; -+ dc->caps.max_cursor_size = 128; - - /************************************************* - * Create resources * -@@ -974,7 +974,7 @@ static bool dce80_construct( - } - } - -- dc->public.caps.max_planes = pool->base.pipe_count; -+ dc->caps.max_planes = pool->base.pipe_count; - - if (!resource_construct(num_virtual_links, dc, &pool->base, - &res_create_funcs)) -@@ -993,7 +993,7 @@ static bool dce80_construct( - - struct resource_pool *dce80_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc) -+ struct dc *dc) - { - struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); -@@ -1010,7 +1010,7 @@ struct resource_pool *dce80_create_resource_pool( - - static bool dce81_construct( - uint8_t num_virtual_links, -- struct core_dc *dc, -+ struct dc *dc, - struct dce110_resource_pool *pool) - { - unsigned int i; -@@ -1030,9 +1030,9 @@ static bool dce81_construct( - *************************************************/ - pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; - pool->base.pipe_count = res_cap_81.num_timing_generator; -- dc->public.caps.max_downscale_ratio = 200; -- dc->public.caps.i2c_speed_in_khz = 40; -- dc->public.caps.max_cursor_size = 128; -+ dc->caps.max_downscale_ratio = 200; -+ dc->caps.i2c_speed_in_khz = 40; -+ dc->caps.max_cursor_size = 128; - - /************************************************* - * Create resources * -@@ -1139,7 +1139,7 @@ static bool dce81_construct( - } - } - -- dc->public.caps.max_planes = pool->base.pipe_count; -+ dc->caps.max_planes = pool->base.pipe_count; - - if (!resource_construct(num_virtual_links, dc, &pool->base, - &res_create_funcs)) -@@ -1158,7 +1158,7 @@ static bool dce81_construct( - - struct resource_pool *dce81_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc) -+ struct dc *dc) - { - struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); -@@ -1175,7 +1175,7 @@ struct resource_pool *dce81_create_resource_pool( - - static bool dce83_construct( - uint8_t num_virtual_links, -- struct core_dc *dc, -+ struct dc *dc, - struct dce110_resource_pool *pool) - { - unsigned int i; -@@ -1195,9 +1195,9 @@ static bool dce83_construct( - *************************************************/ - pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; - pool->base.pipe_count = res_cap_83.num_timing_generator; -- dc->public.caps.max_downscale_ratio = 200; -- dc->public.caps.i2c_speed_in_khz = 40; -- dc->public.caps.max_cursor_size = 128; -+ dc->caps.max_downscale_ratio = 200; -+ dc->caps.i2c_speed_in_khz = 40; -+ dc->caps.max_cursor_size = 128; - - /************************************************* - * Create resources * -@@ -1300,7 +1300,7 @@ static bool dce83_construct( - } - } - -- dc->public.caps.max_planes = pool->base.pipe_count; -+ dc->caps.max_planes = pool->base.pipe_count; - - if (!resource_construct(num_virtual_links, dc, &pool->base, - &res_create_funcs)) -@@ -1319,7 +1319,7 @@ static bool dce83_construct( - - struct resource_pool *dce83_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc) -+ struct dc *dc) - { - struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); -diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h -index 04f0cfe..eff31ab8 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h -+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.h -@@ -28,20 +28,20 @@ - - #include "core_types.h" - --struct core_dc; -+struct dc; - struct resource_pool; - - struct resource_pool *dce80_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc); -+ struct dc *dc); - - struct resource_pool *dce81_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc); -+ struct dc *dc); - - struct resource_pool *dce83_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc); -+ struct dc *dc); - - #endif /* __DC_RESOURCE_DCE80_H__ */ - -diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c -index 1138612..684241c 100644 ---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c -+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c -@@ -26,7 +26,6 @@ - #if defined(CONFIG_DRM_AMD_DC_DCN1_0) - - #include "reg_helper.h" --#include "core_dc.h" - #include "resource.h" - #include "dwb.h" - #include "dcn10_dwb.h" -diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c -index 184627c..d5d2398 100644 ---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c -@@ -52,7 +52,7 @@ - #define FN(reg_name, field_name) \ - hws->shifts->field_name, hws->masks->field_name - --static void log_mpc_crc(struct core_dc *dc) -+static void log_mpc_crc(struct dc *dc) - { - struct dc_context *dc_ctx = dc->ctx; - struct dce_hwseq *hws = dc->hwseq; -@@ -130,7 +130,7 @@ static void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws, - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); - } - --static void dcn10_log_hubbub_state(struct core_dc *dc) -+static void dcn10_log_hubbub_state(struct dc *dc) - { - struct dc_context *dc_ctx = dc->ctx; - struct dcn_hubbub_wm wm; -@@ -157,7 +157,7 @@ static void dcn10_log_hubbub_state(struct core_dc *dc) - DTN_INFO("\n"); - } - --static void dcn10_log_hw_state(struct core_dc *dc) -+static void dcn10_log_hw_state(struct dc *dc) - { - struct dc_context *dc_ctx = dc->ctx; - struct resource_pool *pool = dc->res_pool; -@@ -273,7 +273,7 @@ static void verify_allow_pstate_change_high( - forced_pstate_allow = true; - - if (should_log_hw_state) { -- dcn10_log_hw_state(DC_TO_CORE(hws->ctx->dc)); -+ dcn10_log_hw_state(hws->ctx->dc); - } - - BREAK_TO_DEBUGGER(); -@@ -746,7 +746,7 @@ static void power_on_plane( - "Un-gated front end for pipe %d\n", plane_id); - } - --static void bios_golden_init(struct core_dc *dc) -+static void bios_golden_init(struct dc *dc) - { - struct dc_bios *bp = dc->ctx->dc_bios; - int i; -@@ -762,7 +762,7 @@ static void bios_golden_init(struct core_dc *dc) - } - } - --static void dcn10_init_hw(struct core_dc *dc) -+static void dcn10_init_hw(struct dc *dc) - { - int i; - struct abm *abm = dc->res_pool->abm; -@@ -773,7 +773,7 @@ static void dcn10_init_hw(struct core_dc *dc) - REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); - REG_WRITE(DIO_MEM_PWR_CTRL, 0); - -- if (!dc->public.debug.disable_clock_gate) { -+ if (!dc->debug.disable_clock_gate) { - /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - -@@ -830,7 +830,7 @@ static void dcn10_init_hw(struct core_dc *dc) - /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); - -- if (!dc->public.debug.disable_clock_gate) { -+ if (!dc->debug.disable_clock_gate) { - /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - -@@ -845,7 +845,7 @@ static void dcn10_init_hw(struct core_dc *dc) - static enum dc_status dcn10_prog_pixclk_crtc_otg( - struct pipe_ctx *pipe_ctx, - struct validate_context *context, -- struct core_dc *dc) -+ struct dc *dc) - { - struct dc_stream_state *stream = pipe_ctx->stream; - enum dc_color_space color_space; -@@ -932,7 +932,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( - } - - static void reset_back_end_for_pipe( -- struct core_dc *dc, -+ struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) - { -@@ -979,7 +979,7 @@ static void reset_back_end_for_pipe( - } - - /* trigger HW to start disconnect plane from stream on the next vsync */ --static void plane_atomic_disconnect(struct core_dc *dc, -+static void plane_atomic_disconnect(struct dc *dc, - int fe_idx) - { - struct mem_input *mi = dc->res_pool->mis[fe_idx]; -@@ -1004,10 +1004,10 @@ static void plane_atomic_disconnect(struct core_dc *dc, - if (opp_id == dc->res_pool->pipe_count) - return; - -- if (dc->public.debug.sanity_checks) -+ if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - mi->funcs->dcc_control(mi, false, false); -- if (dc->public.debug.sanity_checks) -+ if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - - mpc->funcs->remove(mpc, dc->res_pool->opps[opp_id], fe_idx); -@@ -1015,7 +1015,7 @@ static void plane_atomic_disconnect(struct core_dc *dc, - - /* disable HW used by plane. - * note: cannot disable until disconnect is complete */ --static void plane_atomic_disable(struct core_dc *dc, -+static void plane_atomic_disable(struct dc *dc, - int fe_idx) - { - struct dce_hwseq *hws = dc->hwseq; -@@ -1037,7 +1037,7 @@ static void plane_atomic_disable(struct core_dc *dc, - mi->opp_id = 0xf; - mi->mpcc_id = 0xf; - -- if (dc->public.debug.sanity_checks) -+ if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - - REG_UPDATE(HUBP_CLK_CNTL[fe_idx], -@@ -1049,7 +1049,7 @@ static void plane_atomic_disable(struct core_dc *dc, - REG_UPDATE(OPP_PIPE_CONTROL[opp_id], - OPP_PIPE_CLOCK_EN, 0); - -- if (dc->public.debug.sanity_checks) -+ if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - } - -@@ -1057,7 +1057,7 @@ static void plane_atomic_disable(struct core_dc *dc, - * kill power to plane hw - * note: cannot power down until plane is disable - */ --static void plane_atomic_power_down(struct core_dc *dc, int fe_idx) -+static void plane_atomic_power_down(struct dc *dc, int fe_idx) - { - struct dce_hwseq *hws = dc->hwseq; - struct transform *xfm = dc->res_pool->transforms[fe_idx]; -@@ -1072,13 +1072,13 @@ static void plane_atomic_power_down(struct core_dc *dc, int fe_idx) - dm_logger_write(dc->ctx->logger, LOG_DC, - "Power gated front end %d\n", fe_idx); - -- if (dc->public.debug.sanity_checks) -+ if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - } - - - static void reset_front_end( -- struct core_dc *dc, -+ struct dc *dc, - int fe_idx) - { - struct dce_hwseq *hws = dc->hwseq; -@@ -1097,7 +1097,7 @@ static void reset_front_end( - REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1); - tg->funcs->unlock(tg); - -- if (dc->public.debug.sanity_checks) -+ if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(hws); - - if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) -@@ -1112,7 +1112,7 @@ static void reset_front_end( - fe_idx); - } - --static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx) -+static void dcn10_power_down_fe(struct dc *dc, int fe_idx) - { - struct dce_hwseq *hws = dc->hwseq; - struct transform *xfm = dc->res_pool->transforms[fe_idx]; -@@ -1129,12 +1129,12 @@ static void dcn10_power_down_fe(struct core_dc *dc, int fe_idx) - dm_logger_write(dc->ctx->logger, LOG_DC, - "Power gated front end %d\n", fe_idx); - -- if (dc->public.debug.sanity_checks) -+ if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - } - - static void reset_hw_ctx_wrap( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - int i; -@@ -1246,7 +1246,7 @@ static void toggle_watermark_change_req(struct dce_hwseq *hws) - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req); - } - --static void dcn10_update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) -+static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) - { - bool addr_patched = false; - PHYSICAL_ADDRESS_LOC addr; -@@ -1657,7 +1657,7 @@ static bool dcn10_set_output_transfer_func( - } - - static void dcn10_pipe_control_lock( -- struct core_dc *dc, -+ struct dc *dc, - struct pipe_ctx *pipe, - bool lock) - { -@@ -1669,7 +1669,7 @@ static void dcn10_pipe_control_lock( - if (pipe->top_pipe) - return; - -- if (dc->public.debug.sanity_checks) -+ if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - - if (lock) -@@ -1677,7 +1677,7 @@ static void dcn10_pipe_control_lock( - else - pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); - -- if (dc->public.debug.sanity_checks) -+ if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - } - -@@ -1719,7 +1719,7 @@ static bool wait_for_reset_trigger_to_occur( - } - - static void dcn10_enable_timing_synchronization( -- struct core_dc *dc, -+ struct dc *dc, - int group_index, - int group_size, - struct pipe_ctx *grouped_pipes[]) -@@ -1748,7 +1748,7 @@ static void dcn10_enable_timing_synchronization( - } - - static void print_rq_dlg_ttu( -- struct core_dc *core_dc, -+ struct dc *core_dc, - struct pipe_ctx *pipe_ctx) - { - dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS, -@@ -1870,14 +1870,14 @@ static void print_rq_dlg_ttu( - } - - static void dcn10_power_on_fe( -- struct core_dc *dc, -+ struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) - { - struct dc_plane_state *plane_state = pipe_ctx->plane_state; - struct dce_hwseq *hws = dc->hwseq; - -- if (dc->public.debug.sanity_checks) { -+ if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); - } - -@@ -1928,7 +1928,7 @@ static void dcn10_power_on_fe( - print_rq_dlg_ttu(dc, pipe_ctx); - } - -- if (dc->public.debug.sanity_checks) { -+ if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); - } - } -@@ -2084,7 +2084,7 @@ static void dcn10_get_surface_visual_confirm_color( - } - - static void update_dchubp_dpp( -- struct core_dc *dc, -+ struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) - { -@@ -2126,7 +2126,7 @@ static void update_dchubp_dpp( - - size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; - -- if (dc->public.config.gpu_vm_support) -+ if (dc->config.gpu_vm_support) - mi->funcs->mem_input_program_pte_vm( - pipe_ctx->plane_res.mi, - plane_state->format, -@@ -2142,7 +2142,7 @@ static void update_dchubp_dpp( - mpcc_cfg.opp = pipe_ctx->stream_res.opp; - for (top_pipe = pipe_ctx->top_pipe; top_pipe; top_pipe = top_pipe->top_pipe) - mpcc_cfg.z_index++; -- if (dc->public.debug.surface_visual_confirm) -+ if (dc->debug.surface_visual_confirm) - dcn10_get_surface_visual_confirm_color( - pipe_ctx, &mpcc_cfg.black_color); - else -@@ -2187,7 +2187,7 @@ static void update_dchubp_dpp( - - - static void program_all_pipe_in_tree( -- struct core_dc *dc, -+ struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct validate_context *context) - { -@@ -2201,7 +2201,7 @@ static void program_all_pipe_in_tree( - /* watermark is for all pipes */ - program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz); - -- if (dc->public.debug.sanity_checks) { -+ if (dc->debug.sanity_checks) { - /* pstate stuck check after watermark update */ - verify_allow_pstate_change_high(dc->hwseq); - } -@@ -2236,7 +2236,7 @@ static void program_all_pipe_in_tree( - update_dchubp_dpp(dc, pipe_ctx, context); - } - -- if (dc->public.debug.sanity_checks) { -+ if (dc->debug.sanity_checks) { - /* pstate stuck check after each pipe is programmed */ - verify_allow_pstate_change_high(dc->hwseq); - } -@@ -2246,7 +2246,7 @@ static void program_all_pipe_in_tree( - } - - static void dcn10_pplib_apply_display_requirements( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context) - { - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; -@@ -2273,14 +2273,14 @@ static void dcn10_pplib_apply_display_requirements( - } - - static void dcn10_apply_ctx_for_surface( -- struct core_dc *dc, -+ struct dc *dc, - const struct dc_stream_state *stream, - int num_planes, - struct validate_context *context) - { - int i, be_idx; - -- if (dc->public.debug.sanity_checks) -+ if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - - be_idx = -1; -@@ -2351,7 +2351,7 @@ static void dcn10_apply_ctx_for_surface( - "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n", - old_pipe_ctx->mpcc->inst);*/ - -- if (dc->public.debug.sanity_checks) -+ if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - - old_pipe_ctx->top_pipe = NULL; -@@ -2422,18 +2422,18 @@ static void dcn10_apply_ctx_for_surface( - context->bw.dcn.watermarks.d.pte_meta_urgent_ns - ); - -- if (dc->public.debug.sanity_checks) -+ if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - } - - static void dcn10_set_bandwidth( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context, - bool decrease_allowed) - { - struct dm_pp_clock_for_voltage_req clock; - -- if (dc->public.debug.sanity_checks) { -+ if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); - } - -@@ -2488,7 +2488,7 @@ static void dcn10_set_bandwidth( - } - dcn10_pplib_apply_display_requirements(dc, context); - -- if (dc->public.debug.sanity_checks) { -+ if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); - } - -@@ -2541,7 +2541,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, - } - - static void set_plane_config( -- const struct core_dc *dc, -+ const struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct resource_context *res_ctx) - { -@@ -2586,7 +2586,7 @@ static void dcn10_config_stereo_parameters( - return; - } - --static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) -+static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) - { - struct crtc_stereo_flags flags = { 0 }; - struct dc_stream_state *stream = pipe_ctx->stream; -@@ -2607,13 +2607,13 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) - } - - static void dcn10_wait_for_mpcc_disconnect( -- struct core_dc *dc, -+ struct dc *dc, - struct resource_pool *res_pool, - struct pipe_ctx *pipe_ctx) - { - int i; - -- if (dc->public.debug.sanity_checks) { -+ if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); - } - -@@ -2631,14 +2631,14 @@ static void dcn10_wait_for_mpcc_disconnect( - } - } - -- if (dc->public.debug.sanity_checks) { -+ if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); - } - - } - - static bool dcn10_dummy_display_power_gating( -- struct core_dc *dc, -+ struct dc *dc, - uint8_t controller_id, - struct dc_bios *dcb, - enum pipe_gating_control power_gating) -@@ -2652,7 +2652,7 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) - struct timing_generator *tg = pipe_ctx->stream_res.tg; - - if (plane_state->ctx->dc->debug.sanity_checks) { -- struct core_dc *dc = DC_TO_CORE(plane_state->ctx->dc); -+ struct dc *dc = plane_state->ctx->dc; - - verify_allow_pstate_change_high(dc->hwseq); - } -@@ -2716,7 +2716,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { - }; - - --void dcn10_hw_sequencer_construct(struct core_dc *dc) -+void dcn10_hw_sequencer_construct(struct dc *dc) - { - dc->hwss = dcn10_funcs; - } -diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h -index 28218dc..8bb09de 100644 ---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h -+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h -@@ -28,9 +28,9 @@ - - #include "core_types.h" - --struct core_dc; -+struct dc; - --void dcn10_hw_sequencer_construct(struct core_dc *dc); -+void dcn10_hw_sequencer_construct(struct dc *dc); - extern void fill_display_configs( - const struct validate_context *context, - struct dm_pp_display_configuration *pp_display_cfg); -diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c -index c36843d..2d9e88f 100644 ---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c -@@ -825,7 +825,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) - } - - static enum dc_status build_mapped_resource( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context, - struct validate_context *old_context) - { -@@ -872,7 +872,7 @@ static enum dc_status build_mapped_resource( - } - - enum dc_status dcn10_validate_with_context( -- const struct core_dc *dc, -+ struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *context, -@@ -917,7 +917,7 @@ enum dc_status dcn10_validate_with_context( - } - - enum dc_status dcn10_validate_guaranteed( -- const struct core_dc *dc, -+ struct dc *dc, - struct dc_stream_state *dc_stream, - struct validate_context *context) - { -@@ -937,7 +937,7 @@ enum dc_status dcn10_validate_guaranteed( - - if (result == DC_OK) { - validate_guaranteed_copy_streams( -- context, dc->public.caps.max_streams); -+ context, dc->caps.max_streams); - result = resource_build_scaling_params_for_context(dc, context); - } - if (result == DC_OK && !dcn_validate_bandwidth(dc, context)) -@@ -1221,7 +1221,7 @@ static struct resource_funcs dcn10_res_pool_funcs = { - - static bool construct( - uint8_t num_virtual_links, -- struct core_dc *dc, -+ struct dc *dc, - struct dcn10_resource_pool *pool) - { - int i; -@@ -1244,16 +1244,16 @@ static bool construct( - - /* TODO: Hardcode to correct number of functional controllers */ - pool->base.pipe_count = 4; -- dc->public.caps.max_downscale_ratio = 200; -- dc->public.caps.i2c_speed_in_khz = 100; -- dc->public.caps.max_cursor_size = 256; -+ dc->caps.max_downscale_ratio = 200; -+ dc->caps.i2c_speed_in_khz = 100; -+ dc->caps.max_cursor_size = 256; - -- dc->public.caps.max_slave_planes = 1; -+ dc->caps.max_slave_planes = 1; - - if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) -- dc->public.debug = debug_defaults_drv; -+ dc->debug = debug_defaults_drv; - else -- dc->public.debug = debug_defaults_diags; -+ dc->debug = debug_defaults_diags; - - /************************************************* - * Create resources * -@@ -1327,7 +1327,7 @@ static bool construct( - - if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { - dc->dcn_soc->urgent_latency = 3; -- dc->public.debug.disable_dmcu = true; -+ dc->debug.disable_dmcu = true; - dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; - } - -@@ -1347,10 +1347,10 @@ static bool construct( - } - } - -- if (!dc->public.debug.disable_pplib_clock_request) -+ if (!dc->debug.disable_pplib_clock_request) - dcn_bw_update_from_pplib(dc); - dcn_bw_sync_calcs_and_dml(dc); -- if (!dc->public.debug.disable_pplib_wm_range) -+ if (!dc->debug.disable_pplib_wm_range) - dcn_bw_notify_pplib_of_wm_ranges(dc); - - { -@@ -1424,9 +1424,9 @@ static bool construct( - goto res_create_fail; - - dcn10_hw_sequencer_construct(dc); -- dc->public.caps.max_planes = pool->base.pipe_count; -+ dc->caps.max_planes = pool->base.pipe_count; - -- dc->public.cap_funcs = cap_funcs; -+ dc->cap_funcs = cap_funcs; - - return true; - -@@ -1449,7 +1449,7 @@ static bool construct( - - struct resource_pool *dcn10_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc) -+ struct dc *dc) - { - struct dcn10_resource_pool *pool = - dm_alloc(sizeof(struct dcn10_resource_pool)); -diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h -index 5f84dbd..8f71225 100644 ---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h -+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.h -@@ -31,7 +31,7 @@ - #define TO_DCN10_RES_POOL(pool)\ - container_of(pool, struct dcn10_resource_pool, base) - --struct core_dc; -+struct dc; - struct resource_pool; - struct _vcs_dpi_display_pipe_params_st; - -@@ -40,7 +40,7 @@ struct dcn10_resource_pool { - }; - struct resource_pool *dcn10_create_resource_pool( - uint8_t num_virtual_links, -- struct core_dc *dc); -+ struct dc *dc); - - - #endif /* __DC_RESOURCE_DCN10_H__ */ -diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h -deleted file mode 100644 -index 61d7e5a..0000000 ---- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h -+++ /dev/null -@@ -1,59 +0,0 @@ --/* -- * core_dc.h -- * -- * Created on: Nov 13, 2015 -- * Author: yonsun -- */ -- --#ifndef __CORE_DC_H__ --#define __CORE_DC_H__ -- --#include "core_types.h" --#include "hw_sequencer.h" --#include "compressor.h" -- --#define DC_TO_CORE(dc)\ -- container_of(dc, struct core_dc, public) -- --struct core_dc { -- struct dc public; -- struct dc_context *ctx; -- -- uint8_t link_count; -- struct dc_link *links[MAX_PIPES * 2]; -- -- struct validate_context *current_context; -- struct resource_pool *res_pool; -- -- /*Power State*/ -- enum dc_video_power_state previous_power_state; -- enum dc_video_power_state current_power_state; -- -- /* Display Engine Clock levels */ -- struct dm_pp_clock_levels sclk_lvls; -- -- /* Inputs into BW and WM calculations. */ -- struct bw_calcs_dceip *bw_dceip; -- struct bw_calcs_vbios *bw_vbios; --#ifdef CONFIG_DRM_AMD_DC_DCN1_0 -- struct dcn_soc_bounding_box *dcn_soc; -- struct dcn_ip_params *dcn_ip; -- struct display_mode_lib dml; --#endif -- -- /* HW functions */ -- struct hw_sequencer_funcs hwss; -- struct dce_hwseq *hwseq; -- -- /* temp store of dm_pp_display_configuration -- * to compare to see if display config changed -- */ -- struct dm_pp_display_configuration prev_display_config; -- -- /* FBC compressor */ --#ifdef ENABLE_FBC -- struct compressor *fbc_compressor; --#endif --}; -- --#endif /* __CORE_DC_H__ */ -diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h -index 2845402..f8ade55 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h -@@ -52,7 +52,7 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state, - - /************ link *****************/ - struct link_init_data { -- const struct core_dc *dc; -+ const struct dc *dc; - struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ - uint32_t connector_index; /* this will be mapped to the HPD pins */ - uint32_t link_index; /* this is mapped to DAL display_index -@@ -87,19 +87,19 @@ struct resource_funcs { - struct link_encoder *(*link_enc_create)( - const struct encoder_init_data *init); - enum dc_status (*validate_with_context)( -- const struct core_dc *dc, -+ struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *context, - struct validate_context *old_context); - - enum dc_status (*validate_guaranteed)( -- const struct core_dc *dc, -+ struct dc *dc, - struct dc_stream_state *stream, - struct validate_context *context); - - bool (*validate_bandwidth)( -- const struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context); - - struct pipe_ctx *(*acquire_idle_pipe_for_layer)( -diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h -index 36c48f7..6a205b0 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h -@@ -33,7 +33,7 @@ - #include "bw_fixed.h" - - struct pipe_ctx; --struct core_dc; -+struct dc; - struct validate_context; - struct dce_bw_output; - -diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h -index 7e8abcd..58744fe8 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h -@@ -34,7 +34,7 @@ - #include "display_clock.h" - #include "../dml/display_mode_lib.h" - --struct core_dc; -+struct dc; - struct validate_context; - - /******************************************************************************* -@@ -620,16 +620,16 @@ struct dcn_ip_params { - extern const struct dcn_ip_params dcn10_ip_defaults; - - bool dcn_validate_bandwidth( -- const struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context); - - unsigned int dcn_find_dcfclk_suits_all( -- const struct core_dc *dc, -+ const struct dc *dc, - struct clocks_value *clocks); - --void dcn_bw_update_from_pplib(struct core_dc *dc); --void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc); --void dcn_bw_sync_calcs_and_dml(struct core_dc *dc); -+void dcn_bw_update_from_pplib(struct dc *dc); -+void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc); -+void dcn_bw_sync_calcs_and_dml(struct dc *dc); - - #endif /* __DCN_CALCS_H__ */ - -diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h -index a02f18a..f876a11 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h -@@ -30,6 +30,7 @@ - - #include "dml/display_mode_structs.h" - -+struct dchub_init_data; - struct cstate_pstate_watermarks_st { - uint32_t cstate_exit_ns; - uint32_t cstate_enter_plus_exit_ns; -diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h -index 7689e37..c73dca9 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h -@@ -25,8 +25,10 @@ - - #ifndef __DC_HW_SEQUENCER_H__ - #define __DC_HW_SEQUENCER_H__ --#include "core_types.h" --#include "timing_generator.h" -+#include "dc_types.h" -+#include "clock_source.h" -+#include "inc/hw/timing_generator.h" -+#include "core_status.h" - - enum pipe_gating_control { - PIPE_GATING_CONTROL_DISABLE = 0, -@@ -46,25 +48,31 @@ struct dce_hwseq { - struct dce_hwseq_wa wa; - }; - -+struct pipe_ctx; -+struct validate_context; -+struct dchub_init_data; -+struct dc_static_screen_events; -+struct resource_pool; -+struct resource_context; - - struct hw_sequencer_funcs { - -- void (*init_hw)(struct core_dc *dc); -+ void (*init_hw)(struct dc *dc); - - enum dc_status (*apply_ctx_to_hw)( -- struct core_dc *dc, struct validate_context *context); -+ struct dc *dc, struct validate_context *context); - - void (*reset_hw_ctx_wrap)( -- struct core_dc *dc, struct validate_context *context); -+ struct dc *dc, struct validate_context *context); - - void (*apply_ctx_for_surface)( -- struct core_dc *dc, -+ struct dc *dc, - const struct dc_stream_state *stream, - int num_planes, - struct validate_context *context); - - void (*set_plane_config)( -- const struct core_dc *dc, -+ const struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct resource_context *res_ctx); - -@@ -77,7 +85,7 @@ struct hw_sequencer_funcs { - uint16_t *matrix); - - void (*update_plane_addr)( -- const struct core_dc *dc, -+ const struct dc *dc, - struct pipe_ctx *pipe_ctx); - - void (*update_dchub)( -@@ -95,12 +103,12 @@ struct hw_sequencer_funcs { - struct pipe_ctx *pipe_ctx, - const struct dc_stream_state *stream); - -- void (*power_down)(struct core_dc *dc); -+ void (*power_down)(struct dc *dc); - -- void (*enable_accelerated_mode)(struct core_dc *dc); -+ void (*enable_accelerated_mode)(struct dc *dc); - - void (*enable_timing_synchronization)( -- struct core_dc *dc, -+ struct dc *dc, - int group_index, - int group_size, - struct pipe_ctx *grouped_pipes[]); -@@ -110,14 +118,14 @@ struct hw_sequencer_funcs { - bool clock_gating); - - bool (*enable_display_power_gating)( -- struct core_dc *dc, -+ struct dc *dc, - uint8_t controller_id, - struct dc_bios *dcb, - enum pipe_gating_control power_gating); - -- void (*power_down_front_end)(struct core_dc *dc, int fe_idx); -+ void (*power_down_front_end)(struct dc *dc, int fe_idx); - -- void (*power_on_front_end)(struct core_dc *dc, -+ void (*power_on_front_end)(struct dc *dc, - struct pipe_ctx *pipe, - struct validate_context *context); - -@@ -131,12 +139,12 @@ struct hw_sequencer_funcs { - struct dc_link_settings *link_settings); - - void (*pipe_control_lock)( -- struct core_dc *dc, -+ struct dc *dc, - struct pipe_ctx *pipe, - bool lock); - - void (*set_bandwidth)( -- struct core_dc *dc, -+ struct dc *dc, - struct validate_context *context, - bool decrease_allowed); - -@@ -152,23 +160,23 @@ struct hw_sequencer_funcs { - enum dc_status (*prog_pixclk_crtc_otg)( - struct pipe_ctx *pipe_ctx, - struct validate_context *context, -- struct core_dc *dc); -+ struct dc *dc); - - void (*setup_stereo)( - struct pipe_ctx *pipe_ctx, -- struct core_dc *dc); -+ struct dc *dc); - - void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); - -- void (*log_hw_state)(struct core_dc *dc); -+ void (*log_hw_state)(struct dc *dc); - -- void (*wait_for_mpcc_disconnect)(struct core_dc *dc, -+ void (*wait_for_mpcc_disconnect)(struct dc *dc, - struct resource_pool *res_pool, - struct pipe_ctx *pipe_ctx); - }; - - void color_space_to_black_color( -- const struct core_dc *dc, -+ const struct dc *dc, - enum dc_color_space colorspace, - struct tg_color *black_color); - -diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h -index 7f30d99..13218a5 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/resource.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h -@@ -27,7 +27,6 @@ - - #include "core_types.h" - #include "core_status.h" --#include "core_dc.h" - #include "dal_asic_id.h" - - /* TODO unhardcode, 4 for CZ*/ -@@ -67,27 +66,27 @@ struct resource_create_funcs { - - bool resource_construct( - unsigned int num_virtual_links, -- struct core_dc *dc, -+ struct dc *dc, - struct resource_pool *pool, - const struct resource_create_funcs *create_funcs); - - struct resource_pool *dc_create_resource_pool( -- struct core_dc *dc, -+ struct dc *dc, - int num_virtual_links, - enum dce_version dc_version, - struct hw_asic_id asic_id); - --void dc_destroy_resource_pool(struct core_dc *dc); -+void dc_destroy_resource_pool(struct dc *dc); - - enum dc_status resource_map_pool_resources( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context, - struct validate_context *old_context); - - bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); - - enum dc_status resource_build_scaling_params_for_context( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context); - - void resource_build_info_frame(struct pipe_ctx *pipe_ctx); -@@ -148,12 +147,12 @@ void resource_validate_ctx_update_pointer_after_copy( - struct validate_context *dst_ctx); - - enum dc_status resource_map_clock_resources( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context, - struct validate_context *old_context); - - enum dc_status resource_map_phy_clock_resources( -- const struct core_dc *dc, -+ const struct dc *dc, - struct validate_context *context, - struct validate_context *old_context); - -diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c -index 24e47eb..e3a12f3 100644 ---- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c -+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c -@@ -34,8 +34,8 @@ - - #include "ivsrcid/ivsrcid_vislands30.h" - --#include "core_dc.h" -- -+#include "dc.h" -+#include "core_types.h" - static bool hpd_ack( - struct irq_service *irq_service, - const struct irq_source_info *info) -@@ -206,7 +206,7 @@ bool dce110_vblank_set( - bool enable) - { - struct dc_context *dc_ctx = irq_service->ctx; -- struct core_dc *core_dc = DC_TO_CORE(irq_service->ctx->dc); -+ struct dc *core_dc = irq_service->ctx->dc; - enum dc_irq_source dal_irq_src = dc_interrupt_to_irq_source( - irq_service->ctx->dc, - info->src_id, -diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c -index 7e8cb22..f458ef8 100644 ---- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c -+++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c -@@ -36,7 +36,6 @@ - #include "ivsrcid/ivsrcid_vislands30.h" - - #include "dc_types.h" --#include "inc/core_dc.h" - - static bool hpd_ack( - struct irq_service *irq_service, -diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h -index beb7909..93c8556 100644 ---- a/drivers/gpu/drm/amd/display/include/logger_interface.h -+++ b/drivers/gpu/drm/amd/display/include/logger_interface.h -@@ -76,23 +76,23 @@ void logger_write(struct dal_logger *logger, - void *paralist); - - void pre_surface_trace( -- const struct dc *dc, -+ struct dc *dc, - const struct dc_plane_state *const *plane_states, - int surface_count); - - void update_surface_trace( -- const struct dc *dc, -+ struct dc *dc, - const struct dc_surface_update *updates, - int surface_count); - --void post_surface_trace(const struct dc *dc); -+void post_surface_trace(struct dc *dc); - - void context_timing_trace( -- const struct dc *dc, -+ struct dc *dc, - struct resource_context *res_ctx); - - void context_clock_trace( -- const struct dc *dc, -+ struct dc *dc, - struct validate_context *context); - - /* Any function which is empty or have incomplete implementation should be -diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c -index f0a3e43..f49203b 100644 ---- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c -+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c -@@ -27,7 +27,6 @@ - #include "dc.h" - #include "mod_freesync.h" - #include "core_types.h" --#include "core_dc.h" - - #define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32 - -@@ -146,7 +145,7 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) - struct core_freesync *core_freesync = - dm_alloc(sizeof(struct core_freesync)); - -- struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct dc *core_dc = dc; - - struct persistent_data_flag flag; - -@@ -246,7 +245,7 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, - bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - struct dc_stream_state *stream, struct mod_freesync_caps *caps) - { -- struct core_dc *core_dc = NULL; -+ struct dc *core_dc = NULL; - struct core_freesync *core_freesync = NULL; - int persistent_freesync_enable = 0; - struct persistent_data_flag flag; -@@ -257,7 +256,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - return false; - - core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); -- core_dc = DC_TO_CORE(core_freesync->dc); -+ core_dc = core_freesync->dc; - - flag.save_per_edid = true; - flag.save_per_link = false; -@@ -971,14 +970,14 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, - unsigned int stream_index, map_index; - int persistent_data = 0; - struct persistent_data_flag flag; -- struct core_dc *core_dc = NULL; -+ struct dc *core_dc = NULL; - struct core_freesync *core_freesync = NULL; - - if (mod_freesync == NULL) - return false; - - core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); -- core_dc = DC_TO_CORE(core_freesync->dc); -+ core_dc = core_freesync->dc; - - flag.save_per_edid = true; - flag.save_per_link = false; --- -2.7.4 - |