diff options
Diffstat (limited to 'meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0875-drm-amd-powerplay-refine-pp-code-for-raven.patch')
-rw-r--r-- | meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0875-drm-amd-powerplay-refine-pp-code-for-raven.patch | 277 |
1 files changed, 0 insertions, 277 deletions
diff --git a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0875-drm-amd-powerplay-refine-pp-code-for-raven.patch b/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0875-drm-amd-powerplay-refine-pp-code-for-raven.patch deleted file mode 100644 index 38604e80..00000000 --- a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0875-drm-amd-powerplay-refine-pp-code-for-raven.patch +++ /dev/null @@ -1,277 +0,0 @@ -From 87f2165d3a06be0b0d209601777a5c94a83505f2 Mon Sep 17 00:00:00 2001 -From: Rex Zhu <Rex.Zhu@amd.com> -Date: Fri, 25 Aug 2017 15:51:03 +0800 -Subject: [PATCH 0875/4131] drm/amd/powerplay: refine pp code for raven - -delete useless code. - -Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 135 +++---------------------- - 1 file changed, 16 insertions(+), 119 deletions(-) - -diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c -index 2c3e6ba..02c86c9 100644 ---- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c -+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c -@@ -38,20 +38,17 @@ - #include "pp_soc15.h" - - #define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID 5 --#define RAVEN_MINIMUM_ENGINE_CLOCK 800 //8Mhz, the low boundary of engine clock allowed on this chip -+#define RAVEN_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */ - #define SCLK_MIN_DIV_INTV_SHIFT 12 --#define RAVEN_DISPCLK_BYPASS_THRESHOLD 10000 //100mhz -+#define RAVEN_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */ - #define SMC_RAM_END 0x40000 - - static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Rv_Magic; -+ -+ - int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr, - struct pp_display_clock_request *clock_req); - --struct phm_vq_budgeting_record rv_vqtable[] = { -- /* _TBD -- * CUs, SSP low, SSP High, Min Sclk Low, Min Sclk, High, AWD/non-AWD, DCLK, ECLK, Sustainable Sclk, Sustainable CUs */ -- { 8, 0, 45, 0, 0, VQ_DisplayConfig_NoneAWD, 80000, 120000, 4, 0 }, --}; - - static struct rv_power_state *cast_rv_ps(struct pp_hw_power_state *hw_ps) - { -@@ -70,101 +67,24 @@ static const struct rv_power_state *cast_const_rv_ps( - return (struct rv_power_state *)hw_ps; - } - --static int rv_init_vq_budget_table(struct pp_hwmgr *hwmgr) --{ -- uint32_t table_size, i; -- struct phm_vq_budgeting_table *ptable; -- uint32_t num_entries = ARRAY_SIZE(rv_vqtable); -- -- if (hwmgr->dyn_state.vq_budgeting_table != NULL) -- return 0; -- -- table_size = sizeof(struct phm_vq_budgeting_table) + -- sizeof(struct phm_vq_budgeting_record) * (num_entries - 1); -- -- ptable = kzalloc(table_size, GFP_KERNEL); -- if (NULL == ptable) -- return -ENOMEM; -- -- ptable->numEntries = (uint8_t) num_entries; -- -- for (i = 0; i < ptable->numEntries; i++) { -- ptable->entries[i].ulCUs = rv_vqtable[i].ulCUs; -- ptable->entries[i].ulSustainableSOCPowerLimitLow = rv_vqtable[i].ulSustainableSOCPowerLimitLow; -- ptable->entries[i].ulSustainableSOCPowerLimitHigh = rv_vqtable[i].ulSustainableSOCPowerLimitHigh; -- ptable->entries[i].ulMinSclkLow = rv_vqtable[i].ulMinSclkLow; -- ptable->entries[i].ulMinSclkHigh = rv_vqtable[i].ulMinSclkHigh; -- ptable->entries[i].ucDispConfig = rv_vqtable[i].ucDispConfig; -- ptable->entries[i].ulDClk = rv_vqtable[i].ulDClk; -- ptable->entries[i].ulEClk = rv_vqtable[i].ulEClk; -- ptable->entries[i].ulSustainableSclk = rv_vqtable[i].ulSustainableSclk; -- ptable->entries[i].ulSustainableCUs = rv_vqtable[i].ulSustainableCUs; -- } -- -- hwmgr->dyn_state.vq_budgeting_table = ptable; -- -- return 0; --} -- - static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) - { - struct rv_hwmgr *rv_hwmgr = (struct rv_hwmgr *)(hwmgr->backend); -- struct cgs_system_info sys_info = {0}; -- int result; - -- rv_hwmgr->ddi_power_gating_disabled = 0; -- rv_hwmgr->bapm_enabled = 1; - rv_hwmgr->dce_slow_sclk_threshold = 30000; -- rv_hwmgr->disable_driver_thermal_policy = 1; - rv_hwmgr->thermal_auto_throttling_treshold = 0; - rv_hwmgr->is_nb_dpm_enabled = 1; - rv_hwmgr->dpm_flags = 1; -- rv_hwmgr->disable_smu_acp_s3_handshake = 1; -- rv_hwmgr->disable_notify_smu_vpu_recovery = 0; - rv_hwmgr->gfx_off_controled_by_driver = false; - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, -- PHM_PlatformCaps_DynamicM3Arbiter); -- -- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, -- PHM_PlatformCaps_UVDPowerGating); -- -- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, -- PHM_PlatformCaps_UVDDynamicPowerGating); -- -- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, -- PHM_PlatformCaps_VCEPowerGating); -- -- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, -- PHM_PlatformCaps_SamuPowerGating); -- -- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, -- PHM_PlatformCaps_ACP); -- -- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkDeepSleep); - - phm_cap_unset(hwmgr->platform_descriptor.platformCaps, -- PHM_PlatformCaps_GFXDynamicMGPowerGating); -- -- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, - PHM_PlatformCaps_SclkThrottleLowNotification); - -- phm_cap_unset(hwmgr->platform_descriptor.platformCaps, -- PHM_PlatformCaps_DisableVoltageIsland); -- - phm_cap_set(hwmgr->platform_descriptor.platformCaps, -- PHM_PlatformCaps_DynamicUVDState); -- -- sys_info.size = sizeof(struct cgs_system_info); -- sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS; -- result = cgs_query_system_info(hwmgr->device, &sys_info); -- if (!result) { -- if (sys_info.value & AMD_PG_SUPPORT_GFX_DMG) -- phm_cap_set(hwmgr->platform_descriptor.platformCaps, -- PHM_PlatformCaps_GFXDynamicMGPowerGating); -- } -- -+ PHM_PlatformCaps_PowerPlaySupport); - return 0; - } - -@@ -256,14 +176,6 @@ static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input, - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SetMinDeepSleepDcefclk, - clocks.dcefClockInSR / 100); -- /* -- if(!rv_data->isp_tileA_power_gated || !rv_data->isp_tileB_power_gated) { -- if ((hwmgr->ispArbiter.iclk != 0) && (rv_data->ISPActualHardMinFreq != (hwmgr->ispArbiter.iclk / 100) )) { -- smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, -- PPSMC_MSG_SetHardMinIspclkByFreq, hwmgr->ispArbiter.iclk / 100); -- rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->ISPActualHardMinFreq), -- } -- } */ - - if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) != rv_data->vclk_soft_min) || - ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) { -@@ -279,7 +191,7 @@ static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input, - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SetHardMinSocclkByFreq, - hwmgr->gfx_arbiter.sclk_hard_min / 100); -- rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->soc_actual_hard_min_freq); -+ rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->soc_actual_hard_min_freq); - } - - if ((hwmgr->gfx_arbiter.gfxclk != 0) && -@@ -301,6 +213,7 @@ static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input, - return 0; - } - -+ - static int rv_tf_set_num_active_display(struct pp_hwmgr *hwmgr, void *input, - void *output, void *storage, int result) - { -@@ -313,6 +226,7 @@ static int rv_tf_set_num_active_display(struct pp_hwmgr *hwmgr, void *input, - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SetDisplayCount, - num_of_active_displays); -+ - return 0; - } - -@@ -563,9 +477,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr) - return result; - } - -- phm_cap_set(hwmgr->platform_descriptor.platformCaps, -- PHM_PlatformCaps_PowerPlaySupport); -- - rv_populate_clock_table(hwmgr); - - result = rv_get_system_info_data(hwmgr); -@@ -624,8 +535,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr) - - hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; - -- rv_init_vq_budget_table(hwmgr); -- - return result; - } - -@@ -670,11 +579,6 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; - } - -- if (NULL != hwmgr->dyn_state.vq_budgeting_table) { -- kfree(hwmgr->dyn_state.vq_budgeting_table); -- hwmgr->dyn_state.vq_budgeting_table = NULL; -- } -- - kfree(hwmgr->backend); - hwmgr->backend = NULL; - -@@ -711,18 +615,9 @@ static int rv_dpm_get_pp_table_entry_callback( - { - struct rv_power_state *rv_ps = cast_rv_ps(hw_ps); - -- const ATOM_PPLIB_CZ_CLOCK_INFO *rv_clock_info = clock_info; -- -- struct phm_clock_voltage_dependency_table *table = -- hwmgr->dyn_state.vddc_dependency_on_sclk; -- uint8_t clock_info_index = rv_clock_info->index; -- -- if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1)) -- clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1); -- -- rv_ps->levels[index].engine_clock = table->entries[clock_info_index].clk; -- rv_ps->levels[index].vddc_index = (uint8_t)table->entries[clock_info_index].v; -+ rv_ps->levels[index].engine_clock = 0; - -+ rv_ps->levels[index].vddc_index = 0; - rv_ps->level = index + 1; - - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { -@@ -814,12 +709,12 @@ static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_p - ps = cast_const_rv_ps(state); - - level_index = index > ps->level - 1 ? ps->level - 1 : index; -- level->coreClock = ps->levels[level_index].engine_clock; -+ level->coreClock = 30000; - - if (designation == PHM_PerformanceLevelDesignation_PowerContainment) { - for (i = 1; i < ps->level; i++) { - if (ps->levels[i].engine_clock > data->dce_slow_sclk_threshold) { -- level->coreClock = ps->levels[i].engine_clock; -+ level->coreClock = 30000; - break; - } - } -@@ -829,8 +724,9 @@ static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_p - vol_dep_record_index = data->clock_vol_info.vdd_dep_on_fclk->count - 1; - level->memory_clock = - data->clock_vol_info.vdd_dep_on_fclk->entries[vol_dep_record_index].clk; -- } else -+ } else { - level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; -+ } - - level->nonLocalMemoryFreq = 0; - level->nonLocalMemoryWidth = 0; -@@ -1001,7 +897,8 @@ int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr, - - static int rv_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) - { -- return -EINVAL; -+ clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */ -+ return 0; - } - - static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr) --- -2.7.4 - |