diff options
Diffstat (limited to 'meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0708-drm-amd-display-remove-DCN1-guard-as-DCN1-is-already.patch')
-rw-r--r-- | meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0708-drm-amd-display-remove-DCN1-guard-as-DCN1-is-already.patch | 512 |
1 files changed, 0 insertions, 512 deletions
diff --git a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0708-drm-amd-display-remove-DCN1-guard-as-DCN1-is-already.patch b/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0708-drm-amd-display-remove-DCN1-guard-as-DCN1-is-already.patch deleted file mode 100644 index cb41e521..00000000 --- a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0708-drm-amd-display-remove-DCN1-guard-as-DCN1-is-already.patch +++ /dev/null @@ -1,512 +0,0 @@ -From 7bfde81ae863b0a1fd5ea719e36031d9c6130b1e Mon Sep 17 00:00:00 2001 -From: "AMD\\\\\\\\ktsao" <kenny.tsao@amd.com> -Date: Sun, 30 Jul 2017 14:18:36 -0400 -Subject: [PATCH 0708/4131] drm/amd/display: remove DCN1 guard as DCN1 is - already open sourced. - -Signed-off-by: Kenny Tsao <kenny.tsao@amd.com> -Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> -Acked-by: Harry Wentland <Harry.Wentland@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/display/dc/dc.h | 6 -- - drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 91 ++++++++++------------ - .../gpu/drm/amd/display/dc/dce/dce_clock_source.h | 2 - - drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 20 ++--- - .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 15 ++-- - .../drm/amd/display/dc/dce/dce_stream_encoder.h | 6 -- - drivers/gpu/drm/amd/display/dc/dm_services.h | 2 - - drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 - - .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 2 - - drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 2 - - drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 - - drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 2 - - .../drm/amd/display/dc/inc/hw/timing_generator.h | 7 +- - drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4 - - drivers/gpu/drm/amd/display/include/dal_types.h | 3 +- - 15 files changed, 58 insertions(+), 110 deletions(-) - -diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h -index 0918569..d03218d 100644 ---- a/drivers/gpu/drm/amd/display/dc/dc.h -+++ b/drivers/gpu/drm/amd/display/dc/dc.h -@@ -96,13 +96,9 @@ struct dc_surface; - struct validate_context; - - struct dc_cap_funcs { --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - bool (*get_dcc_compression_cap)(const struct dc *dc, - const struct dc_dcc_surface_param *input, - struct dc_surface_dcc_cap *output); --#else -- int i; --#endif - }; - - struct dc_stream_funcs { -@@ -171,7 +167,6 @@ struct dc_debug { - bool disable_stutter; - bool disable_dcc; - bool disable_dfs_bypass; --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - bool disable_dpp_power_gate; - bool disable_hubp_power_gate; - bool disable_pplib_wm_range; -@@ -185,7 +180,6 @@ struct dc_debug { - int percent_of_ideal_drambw; - int dram_clock_change_latency_ns; - int always_scale; --#endif - bool disable_pplib_clock_request; - bool disable_clock_gate; - bool disable_dmcu; -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h -index e0abd2d..59e909e 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h -@@ -54,21 +54,19 @@ - SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ - SR(BIOS_SCRATCH_2) - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) -- #define ABM_DCN10_REG_LIST(id)\ -- ABM_COMMON_REG_LIST_DCE_BASE(), \ -- SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ -- SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ -- SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ -- SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ -- SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ -- SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ -- SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ -- SRI(BL1_PWM_USER_LEVEL, ABM, id), \ -- SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ -- SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ -- NBIO_SR(BIOS_SCRATCH_2) --#endif -+#define ABM_DCN10_REG_LIST(id)\ -+ ABM_COMMON_REG_LIST_DCE_BASE(), \ -+ SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ -+ SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ -+ SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ -+ SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ -+ SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ -+ SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ -+ SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ -+ SRI(BL1_PWM_USER_LEVEL, ABM, id), \ -+ SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ -+ SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ -+ NBIO_SR(BIOS_SCRATCH_2) - - #define ABM_SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix -@@ -120,39 +118,36 @@ - ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ - ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) - -- --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) -- #define ABM_MASK_SH_LIST_DCN10(mask_sh) \ -- ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ -- ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ -- ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ -- ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ -- ABM1_HG_VMAX_SEL, mask_sh), \ -- ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ -- ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ -- ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ -- ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ -- ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ -- ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ -- ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ -- ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ -- ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ -- BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ -- ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ -- BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ -- ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ -- BL1_PWM_USER_LEVEL, mask_sh), \ -- ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ -- ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ -- ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ -- ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ -- ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ -- ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ -- ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ -- ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ -- ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ -- ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) --#endif -+#define ABM_MASK_SH_LIST_DCN10(mask_sh) \ -+ ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ -+ ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ -+ ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ -+ ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ -+ ABM1_HG_VMAX_SEL, mask_sh), \ -+ ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ -+ ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ -+ ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ -+ ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ -+ ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ -+ ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ -+ ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ -+ ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ -+ ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ -+ BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ -+ ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ -+ BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ -+ ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ -+ BL1_PWM_USER_LEVEL, mask_sh), \ -+ ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ -+ ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ -+ ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ -+ ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ -+ ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ -+ ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ -+ ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ -+ ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ -+ ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ -+ ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) - - #define ABM_REG_FIELD_LIST(type) \ - type ABM1_HG_NUM_OF_BINS_SEL; \ -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h -index e8bc98b..fc92388 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h -@@ -55,7 +55,6 @@ - CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ - CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ - SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ - SRII(PHASE, DP_DTO, 0),\ -@@ -74,7 +73,6 @@ - #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ - CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ - CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) --#endif - - #define CS_REG_FIELD_LIST(type) \ - type PLL_REF_DIV_SRC; \ -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h -index c421a02..b85f53c 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h -@@ -48,11 +48,9 @@ - DMCU_COMMON_REG_LIST_DCE_BASE(), \ - SR(DCI_MEM_PWR_STATUS) - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) -- #define DMCU_DCN10_REG_LIST()\ -- DMCU_COMMON_REG_LIST_DCE_BASE(), \ -- SR(DMU_MEM_PWR_CNTL) --#endif -+#define DMCU_DCN10_REG_LIST()\ -+ DMCU_COMMON_REG_LIST_DCE_BASE(), \ -+ SR(DMU_MEM_PWR_CNTL) - - #define DMCU_SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix -@@ -82,12 +80,10 @@ - DMCU_SF(DCI_MEM_PWR_STATUS, \ - DMCU_IRAM_MEM_PWR_STATE, mask_sh) - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) -- #define DMCU_MASK_SH_LIST_DCN10(mask_sh) \ -- DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ -- DMCU_SF(DMU_MEM_PWR_CNTL, \ -- DMCU_IRAM_MEM_PWR_STATE, mask_sh) --#endif -+#define DMCU_MASK_SH_LIST_DCN10(mask_sh) \ -+ DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ -+ DMCU_SF(DMU_MEM_PWR_CNTL, \ -+ DMCU_IRAM_MEM_PWR_STATE, mask_sh) - - #define DMCU_REG_FIELD_LIST(type) \ - type DMCU_IRAM_MEM_PWR_STATE; \ -@@ -211,13 +207,11 @@ struct dmcu *dce_dmcu_create( - const struct dce_dmcu_shift *dmcu_shift, - const struct dce_dmcu_mask *dmcu_mask); - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - struct dmcu *dcn10_dmcu_create( - struct dc_context *ctx, - const struct dce_dmcu_registers *regs, - const struct dce_dmcu_shift *dmcu_shift, - const struct dce_dmcu_mask *dmcu_mask); --#endif - - void dce_dmcu_destroy(struct dmcu **dmcu); - -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h -index a47b075..5f05ca6 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h -@@ -100,15 +100,12 @@ - SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ - SR(DCI_MEM_PWR_STATUS) - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) -- #define LE_DCN10_REG_LIST(id)\ -- LE_COMMON_REG_LIST_BASE(id), \ -- SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ -- SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ -- SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ -- SR(DMU_MEM_PWR_CNTL) --#endif -- -+#define LE_DCN10_REG_LIST(id)\ -+ LE_COMMON_REG_LIST_BASE(id), \ -+ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ -+ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ -+ SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ -+ SR(DMU_MEM_PWR_CNTL) - - struct dce110_link_enc_aux_registers { - uint32_t AUX_CONTROL; -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h -index 0b548cb..ff8ca12 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h -@@ -97,7 +97,6 @@ - SE_COMMON_REG_LIST_DCE_BASE(id), \ - SRI(AFMT_CNTL, DIG, id) - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - #define SE_DCN_REG_LIST(id)\ - SE_COMMON_REG_LIST_BASE(id),\ - SRI(AFMT_CNTL, DIG, id),\ -@@ -112,7 +111,6 @@ - SRI(DP_MSA_TIMING_PARAM3, DP, id), \ - SRI(DP_MSA_TIMING_PARAM4, DP, id), \ - SRI(HDMI_DB_CONTROL, DIG, id) --#endif - - #define SE_SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix -@@ -328,7 +326,6 @@ - SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\ - SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - #define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\ - SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ - SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\ -@@ -368,7 +365,6 @@ - SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ - SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ - SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh) --#endif - - struct dce_stream_encoder_shift { - uint8_t AFMT_GENERIC_INDEX; -@@ -684,7 +680,6 @@ struct dce110_stream_enc_registers { - uint32_t HDMI_ACR_48_0; - uint32_t HDMI_ACR_48_1; - uint32_t TMDS_CNTL; --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - uint32_t DP_DB_CNTL; - uint32_t DP_MSA_MISC; - uint32_t DP_MSA_COLORIMETRY; -@@ -693,7 +688,6 @@ struct dce110_stream_enc_registers { - uint32_t DP_MSA_TIMING_PARAM3; - uint32_t DP_MSA_TIMING_PARAM4; - uint32_t HDMI_DB_CONTROL; --#endif - }; - - struct dce110_stream_encoder { -diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h -index e9bf4c4..a7d661d 100644 ---- a/drivers/gpu/drm/amd/display/dc/dm_services.h -+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h -@@ -75,9 +75,7 @@ - BREAK_TO_DEBUGGER(); \ - } while (0) - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - #include <asm/fpu/api.h> --#endif - - #define dm_alloc(size) kzalloc(size, GFP_KERNEL) - #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL) -diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h -index ab389ab..da52971 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h -@@ -32,9 +32,7 @@ - #include "ddc_service_types.h" - #include "dc_bios_types.h" - #include "mem_input.h" --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - #include "mpc.h" --#endif - - #define MAX_CLOCK_SOURCES 7 - -diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h -index 240ab11..879c3db 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h -@@ -37,13 +37,11 @@ struct clocks_value { - bool dispclk_notify_pplib_done; - bool pixelclk_notify_pplib_done; - bool phyclk_notigy_pplib_done; --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - int dcfclock_in_khz; - int dppclk_in_khz; - int mclk_in_khz; - int phyclk_in_khz; - int common_vdd_level; --#endif - }; - - -diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h -index 1298d30..0f952e5 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h -@@ -122,9 +122,7 @@ struct ipp_funcs { - struct input_pixel_processor *ipp, - const struct pwl_params *params); - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - void (*ipp_destroy)(struct input_pixel_processor **ipp); --#endif - }; - - #endif /* __DAL_IPP_H__ */ -diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h -index a7c89c3..a02f18a 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h -@@ -28,7 +28,6 @@ - #include "dc.h" - #include "include/grph_object_id.h" - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - #include "dml/display_mode_structs.h" - - struct cstate_pstate_watermarks_st { -@@ -49,7 +48,6 @@ struct dcn_watermark_set { - struct dcn_watermarks c; - struct dcn_watermarks d; - }; --#endif - - struct dce_watermarks { - int a_mark; -@@ -76,7 +74,6 @@ struct mem_input { - }; - - struct mem_input_funcs { --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - void (*mem_input_setup)( - struct mem_input *mem_input, - struct _vcs_dpi_display_dlg_regs_st *dlg_regs, -@@ -90,7 +87,6 @@ struct mem_input_funcs { - struct mem_input *mem_input, - const struct rect *viewport, - const struct rect *viewport_c); --#endif - - void (*mem_input_program_display_marks)( - struct mem_input *mem_input, -diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h -index dadd2ad..75adb8f 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h -@@ -27,9 +27,7 @@ - #define __DAL_OPP_H__ - - #include "hw_shared.h" --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - #include "dc_hw_types.h" --#endif - #include "transform.h" - - struct fixed31_32; -diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h -index 2b72d1d..c6ab38c 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h -@@ -91,7 +91,7 @@ enum crtc_state { - CRTC_STATE_VBLANK = 0, - CRTC_STATE_VACTIVE - }; --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) -+ - struct _dlg_otg_param { - int vstartup_start; - int vupdate_offset; -@@ -99,7 +99,6 @@ struct _dlg_otg_param { - int vready_offset; - enum signal_type signal; - }; --#endif - - struct crtc_stereo_flags { - uint8_t PROGRAM_STEREO : 1; -@@ -113,9 +112,7 @@ struct timing_generator { - const struct timing_generator_funcs *funcs; - struct dc_bios *bp; - struct dc_context *ctx; --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - struct _dlg_otg_param dlg_otg_param; --#endif - int inst; - }; - -@@ -176,10 +173,8 @@ struct timing_generator_funcs { - - bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width); - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - void (*program_global_sync)(struct timing_generator *tg); - void (*enable_optc_clock)(struct timing_generator *tg, bool enable); --#endif - void (*program_stereo)(struct timing_generator *tg, - const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); - bool (*is_stereo_left_eye)(struct timing_generator *tg); -diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h -index 3d2ed5c..af9fa66 100644 ---- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h -+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h -@@ -109,18 +109,14 @@ - #define ASIC_REV_IS_STONEY(rev) \ - ((rev >= STONEY_A0) && (rev < CZ_UNKNOWN)) - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - /* DCN1_0 */ - #define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */ - #define RAVEN_A0 0x01 - #define RAVEN_UNKNOWN 0xFF - - #define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN) --#endif - --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - #define FAMILY_RV 142 /* DCN 1*/ --#endif - - /* - * ASIC chip ID -diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h -index 50a2a3e..1bfc191 100644 ---- a/drivers/gpu/drm/amd/display/include/dal_types.h -+++ b/drivers/gpu/drm/amd/display/include/dal_types.h -@@ -39,9 +39,8 @@ enum dce_version { - DCE_VERSION_11_0, - DCE_VERSION_11_2, - DCE_VERSION_12_0, --#if defined(CONFIG_DRM_AMD_DC_DCN1_0) -+ DCE_VERSION_MAX, - DCN_VERSION_1_0, --#endif - DCN_VERSION_MAX - }; - --- -2.7.4 - |