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Diffstat (limited to 'meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0627-drm-amd-display-revert-order-change-of-HUBP-and-MPC-.patch')
-rw-r--r--meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0627-drm-amd-display-revert-order-change-of-HUBP-and-MPC-.patch162
1 files changed, 162 insertions, 0 deletions
diff --git a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0627-drm-amd-display-revert-order-change-of-HUBP-and-MPC-.patch b/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0627-drm-amd-display-revert-order-change-of-HUBP-and-MPC-.patch
new file mode 100644
index 00000000..51d55c15
--- /dev/null
+++ b/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0627-drm-amd-display-revert-order-change-of-HUBP-and-MPC-.patch
@@ -0,0 +1,162 @@
+From 9a1eb005fa9f33dc0945af582a802f4087a516ac Mon Sep 17 00:00:00 2001
+From: Tony Cheng <tony.cheng@amd.com>
+Date: Fri, 14 Jul 2017 13:42:23 -0400
+Subject: [PATCH 0627/4131] drm/amd/display: revert order change of HUBP and
+ MPC disable
+
+- root cause was we disable opp clk in MPC disconnect
+- hubp_blank is not double buffered, so we can't blank until MPC disconnect or we have risk of underflow
+
+Signed-off-by: Tony Cheng <tony.cheng@amd.com>
+Reviewed-by: Eric Yang <eric.yang2@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 --
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 41 +++++++++++++---------
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 5 +++
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 2 ++
+ 4 files changed, 32 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+index 7e1d46f..94d12b5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+@@ -288,7 +288,6 @@ struct dce_hwseq_registers {
+ HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
+ HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, mask_sh), \
+ HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, mask_sh), \
+- HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh), \
+ HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \
+ HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \
+ HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
+@@ -351,7 +350,6 @@ struct dce_hwseq_registers {
+ #define HWSEQ_DCN_REG_FIELD_LIST(type) \
+ type VUPDATE_NO_LOCK_EVENT_CLEAR; \
+ type VUPDATE_NO_LOCK_EVENT_OCCURRED; \
+- type HUBP_NO_OUTSTANDING_REQ; \
+ type HUBP_VTG_SEL; \
+ type HUBP_CLOCK_ENABLE; \
+ type DPP_CLOCK_ENABLE; \
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 8284837..adf3d29 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -436,29 +436,17 @@ static void reset_back_end_for_pipe(
+ pipe_ctx->pipe_idx, pipe_ctx->tg->inst);
+ }
+
+-static void reset_front_end(
++static void plane_atomic_stop(
+ struct core_dc *dc,
+ int fe_idx)
+ {
+- struct dce_hwseq *hws = dc->hwseq;
+ struct mpcc_cfg mpcc_cfg;
+ struct mem_input *mi = dc->res_pool->mis[fe_idx];
+ struct transform *xfm = dc->res_pool->transforms[fe_idx];
+ struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx];
+ struct timing_generator *tg = dc->res_pool->timing_generators[mpcc->opp_id];
+- unsigned int opp_id = mpcc->opp_id;
+-
+- /*Already reset*/
+- if (opp_id == 0xf)
+- return;
+-
+- tg->funcs->lock(tg);
+
+ mi->funcs->dcc_control(mi, false, false);
+- mi->funcs->set_blank(mi, true);
+- REG_WAIT(DCHUBP_CNTL[fe_idx],
+- HUBP_NO_OUTSTANDING_REQ, 1,
+- 1, 200);
+
+ mpcc_cfg.opp_id = 0xf;
+ mpcc_cfg.top_dpp_id = 0xf;
+@@ -466,23 +454,44 @@ static void reset_front_end(
+ mpcc_cfg.top_of_tree = tg->inst == mpcc->inst;
+ mpcc->funcs->set(mpcc, &mpcc_cfg);
+
++ xfm->funcs->transform_reset(xfm);
++}
++
++static void reset_front_end(
++ struct core_dc *dc,
++ int fe_idx)
++{
++ struct dce_hwseq *hws = dc->hwseq;
++ struct mem_input *mi = dc->res_pool->mis[fe_idx];
++ struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx];
++ struct timing_generator *tg = dc->res_pool->timing_generators[mpcc->opp_id];
++ unsigned int opp_id = mpcc->opp_id;
++
++ /*Already reset*/
++ if (opp_id == 0xf)
++ return;
++
++ tg->funcs->lock(tg);
++
++ plane_atomic_stop(dc, fe_idx);
++
+ REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
+ tg->funcs->unlock(tg);
+ REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 20000, 200000);
+
+ mpcc->funcs->wait_for_idle(mpcc);
+
++ mi->funcs->set_blank(mi, true);
++
+ REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
+ HUBP_CLOCK_ENABLE, 0);
+ REG_UPDATE(DPP_CONTROL[fe_idx],
+ DPP_CLOCK_ENABLE, 0);
+
+- if (mpcc_cfg.top_of_tree)
++ if (tg->inst == mpcc->inst)
+ REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
+ OPP_PIPE_CLOCK_EN, 0);
+
+- xfm->funcs->transform_reset(xfm);
+-
+ dm_logger_write(dc->ctx->logger, LOG_DC,
+ "Reset front end %d\n",
+ fe_idx);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+index efa02d1..8054794 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+@@ -46,6 +46,11 @@ static void min10_set_blank(struct mem_input *mem_input, bool blank)
+ REG_UPDATE_2(DCHUBP_CNTL,
+ HUBP_BLANK_EN, blank_en,
+ HUBP_TTU_DISABLE, blank_en);
++
++ if (blank)
++ REG_WAIT(DCHUBP_CNTL,
++ HUBP_NO_OUTSTANDING_REQ, 1,
++ 1, 200);
+ }
+
+ static void min10_vready_workaround(struct mem_input *mem_input,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+index 7efa857..a0a1cef 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+@@ -304,6 +304,7 @@ struct dcn_mi_registers {
+ #define MI_MASK_SH_LIST_DCN(mask_sh)\
+ MI_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
+ MI_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
++ MI_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
+ MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
+ MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
+ MI_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
+@@ -463,6 +464,7 @@ struct dcn_mi_registers {
+ #define DCN_MI_REG_FIELD_LIST(type) \
+ type HUBP_BLANK_EN;\
+ type HUBP_TTU_DISABLE;\
++ type HUBP_NO_OUTSTANDING_REQ;\
+ type NUM_PIPES;\
+ type NUM_BANKS;\
+ type PIPE_INTERLEAVE;\
+--
+2.7.4
+