diff options
Diffstat (limited to 'meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0592-drm-amd-display-Fix-MPO-visual-confirm.patch')
-rw-r--r-- | meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0592-drm-amd-display-Fix-MPO-visual-confirm.patch | 334 |
1 files changed, 0 insertions, 334 deletions
diff --git a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0592-drm-amd-display-Fix-MPO-visual-confirm.patch b/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0592-drm-amd-display-Fix-MPO-visual-confirm.patch deleted file mode 100644 index a807560d..00000000 --- a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0592-drm-amd-display-Fix-MPO-visual-confirm.patch +++ /dev/null @@ -1,334 +0,0 @@ -From 888c5fcf60d37fd1815209394dd144e55f17a1e3 Mon Sep 17 00:00:00 2001 -From: Anthony Koo <Anthony.Koo@amd.com> -Date: Thu, 6 Jul 2017 14:27:49 -0400 -Subject: [PATCH 0592/4131] drm/amd/display: Fix MPO visual confirm - -1. Need to blend non-active area to show visual confirm borders -2. Set number of Visual Confirm lines based on pipe instance -3. Set Different colors representing surface format of bottom most plan - -Signed-off-by: Anthony Koo <anthony.koo@amd.com> -Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> -Acked-by: Harry Wentland <Harry.Wentland@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 6 --- - drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 16 ++++---- - drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 8 ++-- - .../amd/display/dc/dce110/dce110_hw_sequencer.c | 8 +++- - .../drm/amd/display/dc/dce110/dce110_transform_v.c | 4 +- - .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 45 +++++++++++++++++++++- - drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 5 ++- - .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- - .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c | 13 ++++--- - .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h | 1 + - 10 files changed, 77 insertions(+), 31 deletions(-) - -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c -index 6cd1e93..7b1f249 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c -@@ -59,12 +59,6 @@ void color_space_to_black_color( - enum dc_color_space colorspace, - struct tg_color *black_color) - { -- if (dc->public.debug.surface_visual_confirm) { -- *black_color = -- black_color_format[BLACK_COLOR_FORMAT_DEBUG]; -- return; -- } -- - switch (colorspace) { - case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YCBCR709: -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c -index 9202bbe..cb02c7c 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c -@@ -399,11 +399,11 @@ static enum pixel_format convert_pixel_format_to_dalsurface( - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: - case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: -- dal_pixel_format = PIXEL_FORMAT_420BPP12; -+ dal_pixel_format = PIXEL_FORMAT_420BPP8; - break; - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: - case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: -- dal_pixel_format = PIXEL_FORMAT_420BPP15; -+ dal_pixel_format = PIXEL_FORMAT_420BPP10; - break; - case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: - default: -@@ -433,8 +433,8 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) - struct scaler_data *data = &pipe_ctx->scl_data; - struct rect surf_src = surface->src_rect; - struct rect clip = { 0 }; -- int vpc_div = (data->format == PIXEL_FORMAT_420BPP12 -- || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1; -+ int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 -+ || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; - bool pri_split = pipe_ctx->bottom_pipe && - pipe_ctx->bottom_pipe->surface == pipe_ctx->surface; - bool sec_split = pipe_ctx->top_pipe && -@@ -637,8 +637,8 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) - pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz; - pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert; - -- if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12 -- || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP15) { -+ if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP8 -+ || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP10) { - pipe_ctx->scl_data.ratios.horz_c.value /= 2; - pipe_ctx->scl_data.ratios.vert_c.value /= 2; - } -@@ -648,8 +648,8 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r - { - struct scaler_data *data = &pipe_ctx->scl_data; - struct rect src = pipe_ctx->surface->public.src_rect; -- int vpc_div = (data->format == PIXEL_FORMAT_420BPP12 -- || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1; -+ int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 -+ || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; - - - if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 || -diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h -index 94fb930..05f030e 100644 ---- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h -+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h -@@ -214,15 +214,15 @@ enum pixel_format { - PIXEL_FORMAT_ARGB2101010_XRBIAS, - PIXEL_FORMAT_FP16, - /*video*/ -- PIXEL_FORMAT_420BPP12, -- PIXEL_FORMAT_420BPP15, -+ PIXEL_FORMAT_420BPP8, -+ PIXEL_FORMAT_420BPP10, - /*end of pixel format definition*/ - PIXEL_FORMAT_INVALID, - - PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8, - PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16, -- PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP12, -- PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP15, -+ PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8, -+ PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10, - PIXEL_FORMAT_UNKNOWN - }; - -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c -index 8778af7..d3c84dc3 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c -@@ -916,11 +916,15 @@ static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, - /* set boarder color to blue */ - color->color_b_cb = color_value; - break; -- case PIXEL_FORMAT_420BPP12: -- case PIXEL_FORMAT_420BPP15: -+ case PIXEL_FORMAT_420BPP8: - /* set boarder color to green */ - color->color_g_y = color_value; - break; -+ case PIXEL_FORMAT_420BPP10: -+ /* set boarder color to yellow */ -+ color->color_g_y = color_value; -+ color->color_r_cr = color_value; -+ break; - case PIXEL_FORMAT_FP16: - /* set boarder color to white */ - color->color_r_cr = color_value; -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c -index 2896399..8548248 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c -+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c -@@ -59,7 +59,7 @@ static void calculate_viewport( - chroma_viewport->height = luma_viewport->height; - chroma_viewport->width = luma_viewport->width; - -- if (scl_data->format == PIXEL_FORMAT_420BPP12) { -+ if (scl_data->format == PIXEL_FORMAT_420BPP8) { - luma_viewport->height += luma_viewport->height % 2; - luma_viewport->width += luma_viewport->width % 2; - /*for 420 video chroma is 1/4 the area of luma, scaled -@@ -184,7 +184,7 @@ static bool setup_scaling_configuration( - set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE_C); - set_reg_field_value(value, 1, SCLV_MODE, SCL_PSCL_EN_C); - is_scaling_needed = true; -- } else if (data->format != PIXEL_FORMAT_420BPP12) { -+ } else if (data->format != PIXEL_FORMAT_420BPP8) { - set_reg_field_value( - value, - get_reg_field_value(value, SCLV_MODE, SCL_MODE), -diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c -index fb32631..5e27523 100644 ---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c -@@ -1390,6 +1390,42 @@ static bool is_rgb_cspace(enum dc_color_space output_color_space) - } - } - -+static void dcn10_get_surface_visual_confirm_color( -+ const struct pipe_ctx *pipe_ctx, -+ struct tg_color *color) -+{ -+ uint32_t color_value = MAX_TG_COLOR_VALUE; -+ -+ switch (pipe_ctx->scl_data.format) { -+ case PIXEL_FORMAT_ARGB8888: -+ /* set boarder color to red */ -+ color->color_r_cr = color_value; -+ break; -+ -+ case PIXEL_FORMAT_ARGB2101010: -+ /* set boarder color to blue */ -+ color->color_b_cb = color_value; -+ break; -+ case PIXEL_FORMAT_420BPP8: -+ /* set boarder color to green */ -+ color->color_g_y = color_value; -+ break; -+ case PIXEL_FORMAT_420BPP10: -+ /* set boarder color to yellow */ -+ color->color_g_y = color_value; -+ color->color_r_cr = color_value; -+ break; -+ case PIXEL_FORMAT_FP16: -+ /* set boarder color to white */ -+ color->color_r_cr = color_value; -+ color->color_b_cb = color_value; -+ color->color_g_y = color_value; -+ break; -+ default: -+ break; -+ } -+} -+ - static void update_dchubp_dpp( - struct core_dc *dc, - struct pipe_ctx *pipe_ctx, -@@ -1462,8 +1498,13 @@ static void update_dchubp_dpp( - && per_pixel_alpha; - pipe_ctx->mpcc->funcs->set(pipe_ctx->mpcc, &mpcc_cfg); - -- color_space_to_black_color( -- dc, pipe_ctx->stream->public.output_color_space, &black_color); -+ if (dc->public.debug.surface_visual_confirm) { -+ dcn10_get_surface_visual_confirm_color(pipe_ctx, &black_color); -+ } else { -+ color_space_to_black_color( -+ dc, pipe_ctx->stream->public.output_color_space, -+ &black_color); -+ } - pipe_ctx->mpcc->funcs->set_bg_color(pipe_ctx->mpcc, &black_color); - - pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; -diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c -index 7af04bc..1c9d5e9 100644 ---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c -+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c -@@ -25,6 +25,7 @@ - - #include "reg_helper.h" - #include "dcn10_mpc.h" -+#include "dc.h" - - #define REG(reg)\ - mpcc10->mpcc_regs->reg -@@ -85,6 +86,8 @@ static void dcn10_mpcc_set(struct mpcc *mpcc, struct mpcc_cfg *cfg) - BLND_PP_ALPHA : BLND_GLOBAL_ALPHA; - int mpcc_mode = cfg->bot_mpcc_id != 0xf ? - MODE_BLEND : MODE_TOP_ONLY; -+ bool blend_active_only = cfg->top_of_tree && -+ !mpcc->ctx->dc->debug.surface_visual_confirm; - - REG_SET(MPCC_OPP_ID, 0, - MPCC_OPP_ID, cfg->opp_id); -@@ -99,7 +102,7 @@ static void dcn10_mpcc_set(struct mpcc *mpcc, struct mpcc_cfg *cfg) - MPCC_MODE, mpcc_mode, - MPCC_ALPHA_BLND_MODE, alpha_blnd_mode, - MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha, -- MPCC_BLND_ACTIVE_OVERLAP_ONLY, cfg->top_of_tree); -+ MPCC_BLND_ACTIVE_OVERLAP_ONLY, blend_active_only); - - if (cfg->top_of_tree) { - if (cfg->opp_id != 0xf) -diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c -index 66b5d30..75ad37e 100644 ---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c -@@ -465,7 +465,7 @@ static struct transform *dcn10_transform_create( - if (!transform) - return NULL; - -- if (dcn10_transform_construct(transform, ctx, -+ if (dcn10_transform_construct(transform, ctx, inst, - &tf_regs[inst], &tf_shift, &tf_mask)) - return &transform->base; - -diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c -index 92322b7..398af22 100644 ---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c -+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c -@@ -171,8 +171,8 @@ static enum dscl_mode_sel get_dscl_mode( - && data->format <= PIXEL_FORMAT_VIDEO_END) - ycbcr = true; - -- if (data->format == PIXEL_FORMAT_420BPP12 || -- data->format == PIXEL_FORMAT_420BPP15) -+ if (data->format == PIXEL_FORMAT_420BPP8 || -+ data->format == PIXEL_FORMAT_420BPP10) - format420 = true; - - if (data->ratios.horz.value == one -@@ -579,8 +579,8 @@ static enum lb_memory_config find_lb_memory_config(const struct scaler_data *scl - && is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)) - return LB_MEMORY_CONFIG_2; - -- if (scl_data->format == PIXEL_FORMAT_420BPP12 -- || scl_data->format == PIXEL_FORMAT_420BPP15) { -+ if (scl_data->format == PIXEL_FORMAT_420BPP8 -+ || scl_data->format == PIXEL_FORMAT_420BPP10) { - calc_lb_num_partitions( - scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c); - -@@ -675,7 +675,8 @@ static void transform_set_recout( - RECOUT_WIDTH, recout->width, - /* Number of RECOUT vertical lines */ - RECOUT_HEIGHT, recout->height -- - xfm->base.ctx->dc->debug.surface_visual_confirm * 2); -+ - xfm->base.ctx->dc->debug.surface_visual_confirm * 4 * -+ (xfm->base.inst + 1)); - } - - static void transform_set_manual_ratio_init( -@@ -1038,12 +1039,14 @@ static struct transform_funcs dcn10_transform_funcs = { - bool dcn10_transform_construct( - struct dcn10_transform *xfm, - struct dc_context *ctx, -+ uint32_t inst, - const struct dcn_transform_registers *tf_regs, - const struct dcn_transform_shift *tf_shift, - const struct dcn_transform_mask *tf_mask) - { - xfm->base.ctx = ctx; - -+ xfm->base.inst = inst; - xfm->base.funcs = &dcn10_transform_funcs; - - xfm->tf_regs = tf_regs; -diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h -index cd312bd..880a554 100644 ---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h -+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h -@@ -413,6 +413,7 @@ struct dcn10_transform { - - bool dcn10_transform_construct(struct dcn10_transform *xfm110, - struct dc_context *ctx, -+ uint32_t inst, - const struct dcn_transform_registers *tf_regs, - const struct dcn_transform_shift *tf_shift, - const struct dcn_transform_mask *tf_mask); --- -2.7.4 - |