diff options
Diffstat (limited to 'meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0587-drm-amd-display-block-modes-that-require-read-bw-gre.patch')
| -rw-r--r-- | meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0587-drm-amd-display-block-modes-that-require-read-bw-gre.patch | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0587-drm-amd-display-block-modes-that-require-read-bw-gre.patch b/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0587-drm-amd-display-block-modes-that-require-read-bw-gre.patch new file mode 100644 index 00000000..5fc3dc94 --- /dev/null +++ b/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0587-drm-amd-display-block-modes-that-require-read-bw-gre.patch @@ -0,0 +1,74 @@ +From 8835f3cee7752b21a17b32e802d56becd08f0d0b Mon Sep 17 00:00:00 2001 +From: Eric Yang <Eric.Yang2@amd.com> +Date: Tue, 27 Jun 2017 12:09:01 -0400 +Subject: [PATCH 0587/4131] drm/amd/display: block modes that require read bw + greater than 30% + +Signed-off-by: Eric Yang <Eric.Yang2@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 18 +++++++++++++++++- + drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 1 + + 2 files changed, 18 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +index 93384a3..24f8c44 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +@@ -95,6 +95,9 @@ const struct dcn_soc_bounding_box dcn10_soc_defaults = { + .vmm_page_size = 4096, /*bytes*/ + .return_bus_width = 64, /*bytes*/ + .max_request_size = 256, /*bytes*/ ++ ++ /* Depends on user class (client vs embedded, workstation, etc) */ ++ .percent_disp_bw_limit = 0.3f /*%*/ + }; + + const struct dcn_ip_params dcn10_ip_defaults = { +@@ -695,6 +698,8 @@ bool dcn_validate_bandwidth( + struct dcn_bw_internal_vars *v = &context->dcn_bw_vars; + int i, input_idx; + int vesa_sync_start, asic_blank_end, asic_blank_start; ++ bool bw_limit_pass; ++ float bw_limit; + + if (dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public))) + dcn_bw_sync_calcs_and_dml(DC_TO_CORE(&dc->public)); +@@ -1072,8 +1077,19 @@ bool dcn_validate_bandwidth( + dc_core->dml.soc.sr_exit_time_us = dc_core->dcn_soc.sr_exit_time; + } + ++ /* ++ * BW limit is set to prevent display from impacting other system functions ++ */ ++ ++ bw_limit = dc->dcn_soc.percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9; ++ bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit; ++ + kernel_fpu_end(); +- return v->voltage_level != 5; ++ ++ if (bw_limit_pass && v->voltage_level != 5) ++ return true; ++ else ++ return false; + } + + unsigned int dcn_find_normalized_clock_vdd_Level( +diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +index 499bc11..b6cc074 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +@@ -572,6 +572,7 @@ struct dcn_soc_bounding_box { + int vmm_page_size; /*bytes*/ + float dram_clock_change_latency; /*us*/ + int return_bus_width; /*bytes*/ ++ float percent_disp_bw_limit; /*%*/ + }; + extern const struct dcn_soc_bounding_box dcn10_soc_defaults; + +-- +2.7.4 + |