aboutsummaryrefslogtreecommitdiffstats
path: root/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0456-drm-amd-display-fix-flip-register-write-sequence.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0456-drm-amd-display-fix-flip-register-write-sequence.patch')
-rw-r--r--meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0456-drm-amd-display-fix-flip-register-write-sequence.patch178
1 files changed, 0 insertions, 178 deletions
diff --git a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0456-drm-amd-display-fix-flip-register-write-sequence.patch b/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0456-drm-amd-display-fix-flip-register-write-sequence.patch
deleted file mode 100644
index 8a90c7f5..00000000
--- a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0456-drm-amd-display-fix-flip-register-write-sequence.patch
+++ /dev/null
@@ -1,178 +0,0 @@
-From c9eab86a7238e1a783108c357562ddd7eee6acba Mon Sep 17 00:00:00 2001
-From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Date: Thu, 18 May 2017 16:56:45 -0400
-Subject: [PATCH 0456/4131] drm/amd/display: fix flip register write sequence
-
-Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
-Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 56 ++++++++++------------
- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 2 +
- 2 files changed, 28 insertions(+), 30 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
-index a52c614..da2f99d 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
-@@ -237,7 +237,7 @@ static bool mem_input_program_surface_flip_and_addr(
- struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
-
- /* program flip type */
-- REG_UPDATE(DCSURF_FLIP_CONTROL,
-+ REG_SET(DCSURF_FLIP_CONTROL, 0,
- SURFACE_FLIP_TYPE, flip_immediate);
-
- /* HW automatically latch rest of address register on write to
-@@ -258,21 +258,20 @@ static bool mem_input_program_surface_flip_and_addr(
- break;
-
- if (address->grph.meta_addr.quad_part != 0) {
--
-- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
-+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
- PRIMARY_META_SURFACE_ADDRESS_HIGH,
- address->grph.meta_addr.high_part);
-
-- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
-+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
- PRIMARY_META_SURFACE_ADDRESS,
- address->grph.meta_addr.low_part);
- }
-
-- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
-+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
- PRIMARY_SURFACE_ADDRESS_HIGH,
- address->grph.addr.high_part);
-
-- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
-+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
- PRIMARY_SURFACE_ADDRESS,
- address->grph.addr.low_part);
- break;
-@@ -282,40 +281,38 @@ static bool mem_input_program_surface_flip_and_addr(
- break;
-
- if (address->video_progressive.luma_meta_addr.quad_part != 0) {
-+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
-+ PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
-+ address->video_progressive.chroma_meta_addr.high_part);
-
-- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
-+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
-+ PRIMARY_META_SURFACE_ADDRESS_C,
-+ address->video_progressive.chroma_meta_addr.low_part);
-+
-+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
- PRIMARY_META_SURFACE_ADDRESS_HIGH,
- address->video_progressive.luma_meta_addr.high_part);
-
-- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
-+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
- PRIMARY_META_SURFACE_ADDRESS,
- address->video_progressive.luma_meta_addr.low_part);
--
-- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
-- PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
-- address->video_progressive.chroma_meta_addr.high_part);
--
-- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C,
-- PRIMARY_META_SURFACE_ADDRESS_C,
-- address->video_progressive.chroma_meta_addr.low_part);
- }
-
-- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C,
-+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
- PRIMARY_SURFACE_ADDRESS_HIGH_C,
- address->video_progressive.chroma_addr.high_part);
-
-- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_C,
-+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
- PRIMARY_SURFACE_ADDRESS_C,
- address->video_progressive.chroma_addr.low_part);
-
-- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
-+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
- PRIMARY_SURFACE_ADDRESS_HIGH,
- address->video_progressive.luma_addr.high_part);
-
-- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
-+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
- PRIMARY_SURFACE_ADDRESS,
- address->video_progressive.luma_addr.low_part);
--
- break;
- case PLN_ADDR_TYPE_GRPH_STEREO:
- if (address->grph_stereo.left_addr.quad_part == 0)
-@@ -324,39 +321,38 @@ static bool mem_input_program_surface_flip_and_addr(
- break;
- if (address->grph_stereo.right_meta_addr.quad_part != 0) {
-
-- REG_UPDATE(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH,
-+ REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
- SECONDARY_META_SURFACE_ADDRESS_HIGH,
- address->grph_stereo.right_meta_addr.high_part);
-
-- REG_UPDATE(DCSURF_SECONDARY_META_SURFACE_ADDRESS,
-+ REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
- SECONDARY_META_SURFACE_ADDRESS,
- address->grph_stereo.right_meta_addr.low_part);
- }
- if (address->grph_stereo.left_meta_addr.quad_part != 0) {
-
-- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
-+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
- PRIMARY_META_SURFACE_ADDRESS_HIGH,
- address->grph_stereo.left_meta_addr.high_part);
-
-- REG_UPDATE(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
-+ REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
- PRIMARY_META_SURFACE_ADDRESS,
- address->grph_stereo.left_meta_addr.low_part);
- }
-
-- REG_UPDATE(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH,
-+ REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
- SECONDARY_SURFACE_ADDRESS_HIGH,
- address->grph_stereo.right_addr.high_part);
-
-- REG_UPDATE(DCSURF_SECONDARY_SURFACE_ADDRESS,
-+ REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
- SECONDARY_SURFACE_ADDRESS,
- address->grph_stereo.right_addr.low_part);
-
--
-- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
-+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
- PRIMARY_SURFACE_ADDRESS_HIGH,
- address->grph_stereo.left_addr.high_part);
-
-- REG_UPDATE(DCSURF_PRIMARY_SURFACE_ADDRESS,
-+ REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
- PRIMARY_SURFACE_ADDRESS,
- address->grph_stereo.left_addr.low_part);
- break;
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
-index 20bd0f5..48b313b 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
-@@ -282,6 +282,7 @@ struct dcn_mi_registers {
- MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_PENDING, mask_sh),\
-+ MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
- MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
-@@ -414,6 +415,7 @@ struct dcn_mi_registers {
- type H_MIRROR_EN;\
- type SURFACE_PIXEL_FORMAT;\
- type SURFACE_FLIP_TYPE;\
-+ type SURFACE_UPDATE_LOCK;\
- type SURFACE_UPDATE_PENDING;\
- type PRIMARY_SURFACE_ADDRESS_HIGH;\
- type PRIMARY_SURFACE_ADDRESS;\
---
-2.7.4
-