diff options
Diffstat (limited to 'meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0373-drm-amd-display-dce80-100-110-and-112-to-dce-ipp-ref.patch')
-rw-r--r-- | meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0373-drm-amd-display-dce80-100-110-and-112-to-dce-ipp-ref.patch | 1419 |
1 files changed, 0 insertions, 1419 deletions
diff --git a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0373-drm-amd-display-dce80-100-110-and-112-to-dce-ipp-ref.patch b/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0373-drm-amd-display-dce80-100-110-and-112-to-dce-ipp-ref.patch deleted file mode 100644 index 4d58f6f8..00000000 --- a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0373-drm-amd-display-dce80-100-110-and-112-to-dce-ipp-ref.patch +++ /dev/null @@ -1,1419 +0,0 @@ -From 26ea47c0249f28babe37f8bf41fbe05967e09381 Mon Sep 17 00:00:00 2001 -From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> -Date: Mon, 24 Apr 2017 16:30:58 -0400 -Subject: [PATCH 0373/4131] drm/amd/display: dce80, 100, 110 and 112 to dce ipp - refactor - -Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> -Acked-by: Harry Wentland <Harry.Wentland@amd.com> -Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 12 +- - drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h | 24 +- - .../drm/amd/display/dc/dce100/dce100_resource.c | 73 +++--- - drivers/gpu/drm/amd/display/dc/dce110/Makefile | 4 +- - drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c | 63 ------ - drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h | 74 ------ - .../drm/amd/display/dc/dce110/dce110_ipp_cursor.c | 249 --------------------- - .../drm/amd/display/dc/dce110/dce110_ipp_gamma.c | 159 ------------- - .../drm/amd/display/dc/dce110/dce110_resource.c | 70 +++--- - .../drm/amd/display/dc/dce112/dce112_resource.c | 81 +++---- - .../drm/amd/display/dc/dce120/dce120_resource.c | 14 +- - drivers/gpu/drm/amd/display/dc/dce80/Makefile | 2 +- - drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c | 65 ------ - drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h | 45 ---- - .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 84 ++++--- - 15 files changed, 171 insertions(+), 848 deletions(-) - delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c - delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h - delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c - delete mode 100644 drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c - delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c - delete mode 100644 drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h - -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c -index d6bf606..9e8f0a3 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c -@@ -174,7 +174,8 @@ static void dce_ipp_program_input_lut( - struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); - - /* power on LUT memory */ -- REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); -+ if (REG(DCFE_MEM_PWR_CTRL)) -+ REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); - - /* enable all */ - REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); -@@ -199,7 +200,8 @@ static void dce_ipp_program_input_lut( - } - - /* power off LUT memory */ -- REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); -+ if (REG(DCFE_MEM_PWR_CTRL)) -+ REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); - - /* bypass prescale, enable legacy LUT */ - REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); -@@ -250,3 +252,9 @@ void dce_ipp_construct( - ipp_dce->ipp_shift = ipp_shift; - ipp_dce->ipp_mask = ipp_mask; - } -+ -+void dce_ipp_destroy(struct input_pixel_processor **ipp) -+{ -+ dm_free(TO_DCE_IPP(*ipp)); -+ *ipp = NULL; -+} -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h -index 23f25b1..ca04e97 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h -@@ -23,8 +23,8 @@ - * - */ - --#ifndef _DCE_DCE_IPP_H_ --#define _DCE_DCE_IPP_H_ -+#ifndef _DCE_IPP_H_ -+#define _DCE_IPP_H_ - - #include "ipp.h" - -@@ -46,7 +46,6 @@ - SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \ - SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \ - SRI(INPUT_GAMMA_CONTROL, DCP, id), \ -- SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ - SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \ - SRI(DC_LUT_RW_MODE, DCP, id), \ - SRI(DC_LUT_CONTROL, DCP, id), \ -@@ -54,6 +53,14 @@ - SRI(DC_LUT_SEQ_COLOR, DCP, id), \ - SRI(DEGAMMA_CONTROL, DCP, id) - -+#define IPP_DCE100_REG_LIST_DCE_BASE(id) \ -+ IPP_COMMON_REG_LIST_DCE_BASE(id), \ -+ SRI(DCFE_MEM_PWR_CTRL, CRTC, id) -+ -+#define IPP_DCE110_REG_LIST_DCE_BASE(id) \ -+ IPP_COMMON_REG_LIST_DCE_BASE(id), \ -+ SRI(DCFE_MEM_PWR_CTRL, DCFE, id) -+ - #define IPP_SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix - -@@ -85,7 +92,6 @@ - IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \ - IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \ - IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \ -- IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \ - IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \ - IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \ - IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \ -@@ -97,7 +103,11 @@ - IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \ - IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh) - --#define IPP_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ -+#define IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ -+ IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ -+ IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh) -+ -+#define IPP_DCE120_MASK_SH_LIST_SOC_BASE(mask_sh) \ - IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \ - IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \ - IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \ -@@ -223,4 +233,6 @@ void dce_ipp_construct(struct dce_ipp *ipp_dce, - const struct dce_ipp_shift *ipp_shift, - const struct dce_ipp_mask *ipp_mask); - --#endif /* _DCE_DCE_IPP_H_ */ -+void dce_ipp_destroy(struct input_pixel_processor **ipp); -+ -+#endif /* _DCE_IPP_H_ */ -diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c -index 9b36559..f65b785 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c -@@ -37,7 +37,7 @@ - #include "dce/dce_stream_encoder.h" - #include "dce110/dce110_mem_input.h" - #include "dce110/dce110_mem_input_v.h" --#include "dce110/dce110_ipp.h" -+#include "dce/dce_ipp.h" - #include "dce/dce_transform.h" - #include "dce/dce_opp.h" - #include "dce/dce_clocks.h" -@@ -168,30 +168,6 @@ static const struct dce110_mem_input_reg_offsets dce100_mi_reg_offsets[] = { - } - }; - -- --static const struct dce110_ipp_reg_offsets dce100_ipp_reg_offsets[] = { --{ -- .dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL), --} --}; -- -- -- - /* set register offset */ - #define SR(reg_name)\ - .reg_name = mm ## reg_name -@@ -213,6 +189,28 @@ static const struct dce_disp_clk_mask disp_clk_mask = { - CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) - }; - -+#define ipp_regs(id)\ -+[id] = {\ -+ IPP_DCE100_REG_LIST_DCE_BASE(id)\ -+} -+ -+static const struct dce_ipp_registers ipp_regs[] = { -+ ipp_regs(0), -+ ipp_regs(1), -+ ipp_regs(2), -+ ipp_regs(3), -+ ipp_regs(4), -+ ipp_regs(5) -+}; -+ -+static const struct dce_ipp_shift ipp_shift = { -+ IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) -+}; -+ -+static const struct dce_ipp_mask ipp_mask = { -+ IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) -+}; -+ - #define transform_regs(id)\ - [id] = {\ - XFM_COMMON_REG_LIST_DCE100(id)\ -@@ -563,22 +561,18 @@ static struct transform *dce100_transform_create( - } - - static struct input_pixel_processor *dce100_ipp_create( -- struct dc_context *ctx, -- uint32_t inst, -- const struct dce110_ipp_reg_offsets *offsets) -+ struct dc_context *ctx, uint32_t inst) - { -- struct dce110_ipp *ipp = -- dm_alloc(sizeof(struct dce110_ipp)); -+ struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); - -- if (!ipp) -+ if (!ipp) { -+ BREAK_TO_DEBUGGER(); - return NULL; -+ } - -- if (dce110_ipp_construct(ipp, ctx, inst, offsets)) -- return &ipp->base; -- -- BREAK_TO_DEBUGGER(); -- dm_free(ipp); -- return NULL; -+ dce_ipp_construct(ipp, ctx, inst, -+ &ipp_regs[inst], &ipp_shift, &ipp_mask); -+ return &ipp->base; - } - - static const struct encoder_feature_support link_enc_feature = { -@@ -674,7 +668,7 @@ static void destruct(struct dce110_resource_pool *pool) - dce100_transform_destroy(&pool->base.transforms[i]); - - if (pool->base.ipps[i] != NULL) -- dce110_ipp_destroy(&pool->base.ipps[i]); -+ dce_ipp_destroy(&pool->base.ipps[i]); - - if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); -@@ -1005,8 +999,7 @@ static bool construct( - goto res_create_fail; - } - -- pool->base.ipps[i] = dce100_ipp_create(ctx, i, -- &dce100_ipp_reg_offsets[i]); -+ pool->base.ipps[i] = dce100_ipp_create(ctx, i); - if (pool->base.ipps[i] == NULL) { - BREAK_TO_DEBUGGER(); - dm_error( -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/Makefile b/drivers/gpu/drm/amd/display/dc/dce110/Makefile -index 9c42afc..c54bf03 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce110/Makefile -+++ b/drivers/gpu/drm/amd/display/dc/dce110/Makefile -@@ -2,9 +2,7 @@ - # Makefile for the 'controller' sub-component of DAL. - # It provides the control and status of HW CRTC block. - --DCE110 = dce110_ipp.o dce110_ipp_cursor.o \ --dce110_ipp_gamma.o \ --dce110_timing_generator.o \ -+DCE110 = dce110_timing_generator.o \ - dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \ - dce110_resource.o \ - dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \ -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c -deleted file mode 100644 -index 86fa765..0000000 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c -+++ /dev/null -@@ -1,63 +0,0 @@ --/* -- * Copyright 2012-15 Advanced Micro Devices, Inc. -- * -- * Permission is hereby granted, free of charge, to any person obtaining a -- * copy of this software and associated documentation files (the "Software"), -- * to deal in the Software without restriction, including without limitation -- * the rights to use, copy, modify, merge, publish, distribute, sublicense, -- * and/or sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following conditions: -- * -- * The above copyright notice and this permission notice shall be included in -- * all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. -- * -- * Authors: AMD -- * -- */ -- --#include "dm_services.h" --#include "include/logger_interface.h" -- --#include "dce/dce_11_0_d.h" --#include "dce/dce_11_0_sh_mask.h" -- --#include "dce110_ipp.h" -- --static const struct ipp_funcs funcs = { -- .ipp_cursor_set_attributes = dce110_ipp_cursor_set_attributes, -- .ipp_cursor_set_position = dce110_ipp_cursor_set_position, -- .ipp_program_prescale = dce110_ipp_program_prescale, -- .ipp_program_input_lut = dce110_ipp_program_input_lut, -- .ipp_set_degamma = dce110_ipp_set_degamma, --}; -- --bool dce110_ipp_construct( -- struct dce110_ipp* ipp, -- struct dc_context *ctx, -- uint32_t inst, -- const struct dce110_ipp_reg_offsets *offset) --{ -- ipp->base.ctx = ctx; -- -- ipp->base.inst = inst; -- -- ipp->offsets = *offset; -- -- ipp->base.funcs = &funcs; -- -- return true; --} -- --void dce110_ipp_destroy(struct input_pixel_processor **ipp) --{ -- dm_free(TO_DCE110_IPP(*ipp)); -- *ipp = NULL; --} -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h -deleted file mode 100644 -index 8684e6a..0000000 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.h -+++ /dev/null -@@ -1,74 +0,0 @@ --/* -- * Copyright 2012-15 Advanced Micro Devices, Inc. -- * -- * Permission is hereby granted, free of charge, to any person obtaining a -- * copy of this software and associated documentation files (the "Software"), -- * to deal in the Software without restriction, including without limitation -- * the rights to use, copy, modify, merge, publish, distribute, sublicense, -- * and/or sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following conditions: -- * -- * The above copyright notice and this permission notice shall be included in -- * all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. -- * -- * Authors: AMD -- * -- */ -- --#ifndef __DC_IPP_DCE110_H__ --#define __DC_IPP_DCE110_H__ -- --#include "ipp.h" -- --#define TO_DCE110_IPP(input_pixel_processor)\ -- container_of(input_pixel_processor, struct dce110_ipp, base) -- --struct dce110_ipp_reg_offsets { -- uint32_t dcp_offset; --}; -- --struct dce110_ipp { -- struct input_pixel_processor base; -- struct dce110_ipp_reg_offsets offsets; --}; -- --bool dce110_ipp_construct( -- struct dce110_ipp* ipp, -- struct dc_context *ctx, -- enum controller_id id, -- const struct dce110_ipp_reg_offsets *offset); -- --void dce110_ipp_destroy(struct input_pixel_processor **ipp); -- --/* CURSOR RELATED */ --void dce110_ipp_cursor_set_position( -- struct input_pixel_processor *ipp, -- const struct dc_cursor_position *position, -- const struct dc_cursor_mi_param *param); -- --void dce110_ipp_cursor_set_attributes( -- struct input_pixel_processor *ipp, -- const struct dc_cursor_attributes *attributes); -- --/* DEGAMMA RELATED */ --void dce110_ipp_set_degamma( -- struct input_pixel_processor *ipp, -- enum ipp_degamma_mode mode); -- --void dce110_ipp_program_prescale( -- struct input_pixel_processor *ipp, -- struct ipp_prescale_params *params); -- --void dce110_ipp_program_input_lut( -- struct input_pixel_processor *ipp, -- const struct dc_gamma *gamma); -- --#endif /*__DC_IPP_DCE110_H__*/ -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c -deleted file mode 100644 -index f712916..0000000 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_cursor.c -+++ /dev/null -@@ -1,249 +0,0 @@ --/* -- * Copyright 2012-15 Advanced Micro Devices, Inc. -- * -- * Permission is hereby granted, free of charge, to any person obtaining a -- * copy of this software and associated documentation files (the "Software"), -- * to deal in the Software without restriction, including without limitation -- * the rights to use, copy, modify, merge, publish, distribute, sublicense, -- * and/or sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following conditions: -- * -- * The above copyright notice and this permission notice shall be included in -- * all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. -- * -- * Authors: AMD -- * -- */ -- --#include "dm_services.h" --#include "include/logger_interface.h" -- --#include "dce/dce_11_0_d.h" --#include "dce/dce_11_0_sh_mask.h" -- --#include "dce110_ipp.h" -- --#define CURSOR_COLOR_BLACK 0x00000000 --#define CURSOR_COLOR_WHITE 0xFFFFFFFF -- --#define DCP_REG(reg)\ -- (reg + ipp110->offsets.dcp_offset) -- --static void enable( -- struct dce110_ipp *ipp110, -- bool enable); -- --static void lock( -- struct dce110_ipp *ipp110, -- bool enable); -- --static void program_position( -- struct dce110_ipp *ipp110, -- uint32_t x, -- uint32_t y); -- --static bool program_control( -- struct dce110_ipp *ipp110, -- enum dc_cursor_color_format color_format, -- bool enable_magnification, -- bool inverse_transparent_clamping); -- --static void program_hotspot( -- struct dce110_ipp *ipp110, -- uint32_t x, -- uint32_t y); -- --static void program_size( -- struct dce110_ipp *ipp110, -- uint32_t width, -- uint32_t height); -- --static void program_address( -- struct dce110_ipp *ipp110, -- PHYSICAL_ADDRESS_LOC address); -- --void dce110_ipp_cursor_set_position( -- struct input_pixel_processor *ipp, -- const struct dc_cursor_position *position, -- const struct dc_cursor_mi_param *param) --{ -- struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); -- -- /* lock cursor registers */ -- lock(ipp110, true); -- -- /* Flag passed in structure differentiates cursor enable/disable. */ -- /* Update if it differs from cached state. */ -- enable(ipp110, position->enable); -- -- program_position(ipp110, position->x, position->y); -- -- program_hotspot( -- ipp110, -- position->x_hotspot, -- position->y_hotspot); -- -- /* unlock cursor registers */ -- lock(ipp110, false); --} -- --void dce110_ipp_cursor_set_attributes( -- struct input_pixel_processor *ipp, -- const struct dc_cursor_attributes *attributes) --{ -- struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); -- /* Lock cursor registers */ -- lock(ipp110, true); -- -- /* Program cursor control */ -- program_control( -- ipp110, -- attributes->color_format, -- attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, -- attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING); -- -- -- /* -- * Program cursor size -- NOTE: HW spec specifies that HW register -- * stores size as (height - 1, width - 1) -- */ -- program_size(ipp110, attributes->width-1, attributes->height-1); -- -- /* Program cursor surface address */ -- program_address(ipp110, attributes->address); -- -- /* Unlock Cursor registers. */ -- lock(ipp110, false); --} -- --static void enable( -- struct dce110_ipp *ipp110, bool enable) --{ -- uint32_t value = 0; -- uint32_t addr = DCP_REG(mmCUR_CONTROL); -- -- value = dm_read_reg(ipp110->base.ctx, addr); -- set_reg_field_value(value, enable, CUR_CONTROL, CURSOR_EN); -- dm_write_reg(ipp110->base.ctx, addr, value); --} -- --static void lock( -- struct dce110_ipp *ipp110, bool lock) --{ -- uint32_t value = 0; -- uint32_t addr = DCP_REG(mmCUR_UPDATE); -- -- value = dm_read_reg(ipp110->base.ctx, addr); -- set_reg_field_value(value, lock, CUR_UPDATE, CURSOR_UPDATE_LOCK); -- dm_write_reg(ipp110->base.ctx, addr, value); --} -- --static void program_position( -- struct dce110_ipp *ipp110, -- uint32_t x, -- uint32_t y) --{ -- uint32_t value = 0; -- uint32_t addr = DCP_REG(mmCUR_POSITION); -- -- value = dm_read_reg(ipp110->base.ctx, addr); -- set_reg_field_value(value, x, CUR_POSITION, CURSOR_X_POSITION); -- set_reg_field_value(value, y, CUR_POSITION, CURSOR_Y_POSITION); -- dm_write_reg(ipp110->base.ctx, addr, value); --} -- --static bool program_control( -- struct dce110_ipp *ipp110, -- enum dc_cursor_color_format color_format, -- bool enable_magnification, -- bool inverse_transparent_clamping) --{ -- uint32_t value = 0; -- uint32_t addr = DCP_REG(mmCUR_CONTROL); -- uint32_t mode = 0; -- -- switch (color_format) { -- case CURSOR_MODE_MONO: -- mode = 0; -- break; -- case CURSOR_MODE_COLOR_1BIT_AND: -- mode = 1; -- break; -- case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: -- mode = 2; -- break; -- case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: -- mode = 3; -- break; -- default: -- return false; -- } -- -- set_reg_field_value(value, mode, CUR_CONTROL, CURSOR_MODE); -- set_reg_field_value(value, enable_magnification, -- CUR_CONTROL, CURSOR_2X_MAGNIFY); -- set_reg_field_value(value, inverse_transparent_clamping, -- CUR_CONTROL, CUR_INV_TRANS_CLAMP); -- dm_write_reg(ipp110->base.ctx, addr, value); -- -- if (color_format == CURSOR_MODE_MONO) { -- addr = DCP_REG(mmCUR_COLOR1); -- dm_write_reg(ipp110->base.ctx, addr, CURSOR_COLOR_BLACK); -- addr = DCP_REG(mmCUR_COLOR2); -- dm_write_reg(ipp110->base.ctx, addr, CURSOR_COLOR_WHITE); -- } -- return true; --} -- --static void program_hotspot( -- struct dce110_ipp *ipp110, -- uint32_t x, -- uint32_t y) --{ -- uint32_t value = 0; -- uint32_t addr = DCP_REG(mmCUR_HOT_SPOT); -- -- value = dm_read_reg(ipp110->base.ctx, addr); -- set_reg_field_value(value, x, CUR_HOT_SPOT, CURSOR_HOT_SPOT_X); -- set_reg_field_value(value, y, CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y); -- dm_write_reg(ipp110->base.ctx, addr, value); --} -- --static void program_size( -- struct dce110_ipp *ipp110, -- uint32_t width, -- uint32_t height) --{ -- uint32_t value = 0; -- uint32_t addr = DCP_REG(mmCUR_SIZE); -- -- value = dm_read_reg(ipp110->base.ctx, addr); -- set_reg_field_value(value, width, CUR_SIZE, CURSOR_WIDTH); -- set_reg_field_value(value, height, CUR_SIZE, CURSOR_HEIGHT); -- dm_write_reg(ipp110->base.ctx, addr, value); --} -- --static void program_address( -- struct dce110_ipp *ipp110, -- PHYSICAL_ADDRESS_LOC address) --{ -- uint32_t addr = DCP_REG(mmCUR_SURFACE_ADDRESS_HIGH); -- /* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor -- * surface base address in byte. It is 4K byte aligned. -- * The correct way to program cursor surface address is to first write -- * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS */ -- -- dm_write_reg(ipp110->base.ctx, addr, address.high_part); -- -- addr = DCP_REG(mmCUR_SURFACE_ADDRESS); -- dm_write_reg(ipp110->base.ctx, addr, address.low_part); --} -- -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c -deleted file mode 100644 -index 0bcd8a6..0000000 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp_gamma.c -+++ /dev/null -@@ -1,159 +0,0 @@ --/* -- * Copyright 2012-15 Advanced Micro Devices, Inc. -- * -- * Permission is hereby granted, free of charge, to any person obtaining a -- * copy of this software and associated documentation files (the "Software"), -- * to deal in the Software without restriction, including without limitation -- * the rights to use, copy, modify, merge, publish, distribute, sublicense, -- * and/or sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following conditions: -- * -- * The above copyright notice and this permission notice shall be included in -- * all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. -- * -- * Authors: AMD -- * -- */ -- --#include "dm_services.h" --#include "include/logger_interface.h" --#include "include/fixed31_32.h" --#include "basics/conversion.h" -- --#include "dce/dce_11_0_d.h" --#include "dce/dce_11_0_sh_mask.h" -- --#include "dce110_ipp.h" -- --#define DCP_REG(reg)\ -- (mm##reg + ipp110->offsets.dcp_offset) -- --#define DCP_REG_SET_N(reg_name, n, ...) \ -- generic_reg_update_ex(ipp110->base.ctx, \ -- DCP_REG(reg_name), \ -- 0, n, __VA_ARGS__) -- --#define DCP_REG_SET(reg, field1, val1) \ -- DCP_REG_SET_N(reg, 1, FD(reg##__##field1), val1) -- --#define DCP_REG_SET_2(reg, field1, val1, field2, val2) \ -- DCP_REG_SET_N(reg, 2, \ -- FD(reg##__##field1), val1, \ -- FD(reg##__##field2), val2) -- --#define DCP_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \ -- DCP_REG_SET_N(reg, 3, \ -- FD(reg##__##field1), val1, \ -- FD(reg##__##field2), val2, \ -- FD(reg##__##field3), val3) -- --#define DCP_REG_UPDATE_N(reg_name, n, ...) \ -- generic_reg_update_ex(ipp110->base.ctx, \ -- DCP_REG(reg_name), \ -- dm_read_reg(ipp110->base.ctx, DCP_REG(reg_name)), \ -- n, __VA_ARGS__) -- --#define DCP_REG_UPDATE(reg, field, val) \ -- DCP_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) -- -- -- --void dce110_ipp_set_degamma( -- struct input_pixel_processor *ipp, -- enum ipp_degamma_mode mode) --{ -- struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); -- -- uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; -- -- ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || -- mode == IPP_DEGAMMA_MODE_HW_sRGB); -- -- DCP_REG_SET_3( -- DEGAMMA_CONTROL, -- GRPH_DEGAMMA_MODE, degamma_type, -- CURSOR_DEGAMMA_MODE, degamma_type, -- CURSOR2_DEGAMMA_MODE, degamma_type); --} -- --void dce110_ipp_program_prescale( -- struct input_pixel_processor *ipp, -- struct ipp_prescale_params *params) --{ -- struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); -- -- /* set to bypass mode first before change */ -- DCP_REG_UPDATE(PRESCALE_GRPH_CONTROL, -- GRPH_PRESCALE_BYPASS, 1); -- -- DCP_REG_SET_2(PRESCALE_VALUES_GRPH_R, -- GRPH_PRESCALE_SCALE_R, params->scale, -- GRPH_PRESCALE_BIAS_R, params->bias); -- -- DCP_REG_SET_2(PRESCALE_VALUES_GRPH_G, -- GRPH_PRESCALE_SCALE_G, params->scale, -- GRPH_PRESCALE_BIAS_G, params->bias); -- -- DCP_REG_SET_2(PRESCALE_VALUES_GRPH_B, -- GRPH_PRESCALE_SCALE_B, params->scale, -- GRPH_PRESCALE_BIAS_B, params->bias); -- -- if (params->mode != IPP_PRESCALE_MODE_BYPASS) { -- /* If prescale is in use, then legacy lut should be bypassed */ -- DCP_REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 0); -- DCP_REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 1); -- } --} -- --static void dce110_helper_select_lut(struct dce110_ipp *ipp110) --{ -- /* enable all */ -- DCP_REG_SET(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, 0x7); -- -- /* 256 entry mode */ -- DCP_REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); -- -- /* LUT-256, unsigned, integer, new u0.12 format */ -- DCP_REG_SET_3(DC_LUT_CONTROL, -- DC_LUT_DATA_R_FORMAT, 3, -- DC_LUT_DATA_G_FORMAT, 3, -- DC_LUT_DATA_B_FORMAT, 3); -- -- /* start from index 0 */ -- DCP_REG_SET(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, 0); --} -- --void dce110_ipp_program_input_lut( -- struct input_pixel_processor *ipp, -- const struct dc_gamma *gamma) --{ -- int i; -- struct dce110_ipp *ipp110 = TO_DCE110_IPP(ipp); -- -- dce110_helper_select_lut(ipp110); -- -- /* power on LUT memory and give it time to settle */ -- DCP_REG_SET(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 1); -- udelay(10); -- -- for (i = 0; i < INPUT_LUT_ENTRIES; i++) { -- DCP_REG_SET(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->red[i]); -- DCP_REG_SET(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->green[i]); -- DCP_REG_SET(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, gamma->blue[i]); -- } -- -- /* power off LUT memory */ -- DCP_REG_SET(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, 0); -- -- /* bypass prescale, enable legacy LUT */ -- DCP_REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); -- DCP_REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); --} -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c -index b4ab438..8dec9a5 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c -@@ -40,7 +40,7 @@ - #include "dce/dce_stream_encoder.h" - #include "dce110/dce110_mem_input.h" - #include "dce110/dce110_mem_input_v.h" --#include "dce110/dce110_ipp.h" -+#include "dce/dce_ipp.h" - #include "dce/dce_transform.h" - #include "dce110/dce110_transform_v.h" - #include "dce/dce_opp.h" -@@ -157,31 +157,6 @@ static const struct dce110_mem_input_reg_offsets dce110_mi_reg_offsets[] = { - } - }; - -- --static const struct dce110_ipp_reg_offsets dce110_ipp_reg_offsets[] = { --{ -- .dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL), --} --}; -- -- -- -- - /* set register offset */ - #define SR(reg_name)\ - .reg_name = mm ## reg_name -@@ -226,6 +201,25 @@ static const struct dce_abm_mask abm_mask = { - ABM_MASK_SH_LIST_DCE110(_MASK) - }; - -+#define ipp_regs(id)\ -+[id] = {\ -+ IPP_DCE110_REG_LIST_DCE_BASE(id)\ -+} -+ -+static const struct dce_ipp_registers ipp_regs[] = { -+ ipp_regs(0), -+ ipp_regs(1), -+ ipp_regs(2) -+}; -+ -+static const struct dce_ipp_shift ipp_shift = { -+ IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) -+}; -+ -+static const struct dce_ipp_mask ipp_mask = { -+ IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) -+}; -+ - #define transform_regs(id)\ - [id] = {\ - XFM_COMMON_REG_LIST_DCE110(id)\ -@@ -578,22 +572,18 @@ static struct transform *dce110_transform_create( - } - - static struct input_pixel_processor *dce110_ipp_create( -- struct dc_context *ctx, -- uint32_t inst, -- const struct dce110_ipp_reg_offsets *offsets) -+ struct dc_context *ctx, uint32_t inst) - { -- struct dce110_ipp *ipp = -- dm_alloc(sizeof(struct dce110_ipp)); -+ struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); - -- if (!ipp) -+ if (!ipp) { -+ BREAK_TO_DEBUGGER(); - return NULL; -+ } - -- if (dce110_ipp_construct(ipp, ctx, inst, offsets)) -- return &ipp->base; -- -- BREAK_TO_DEBUGGER(); -- dm_free(ipp); -- return NULL; -+ dce_ipp_construct(ipp, ctx, inst, -+ &ipp_regs[inst], &ipp_shift, &ipp_mask); -+ return &ipp->base; - } - - static const struct encoder_feature_support link_enc_feature = { -@@ -705,7 +695,7 @@ static void destruct(struct dce110_resource_pool *pool) - dce110_transform_destroy(&pool->base.transforms[i]); - - if (pool->base.ipps[i] != NULL) -- dce110_ipp_destroy(&pool->base.ipps[i]); -+ dce_ipp_destroy(&pool->base.ipps[i]); - - if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); -@@ -1414,7 +1404,7 @@ static bool construct( - goto res_create_fail; - } - -- pool->base.ipps[i] = dce110_ipp_create(ctx, i, &dce110_ipp_reg_offsets[i]); -+ pool->base.ipps[i] = dce110_ipp_create(ctx, i); - if (pool->base.ipps[i] == NULL) { - BREAK_TO_DEBUGGER(); - dm_error( -diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c -index 0a1ad28..4bf75af 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c -@@ -40,7 +40,7 @@ - #include "dce/dce_stream_encoder.h" - #include "dce/dce_audio.h" - #include "dce/dce_opp.h" --#include "dce110/dce110_ipp.h" -+#include "dce/dce_ipp.h" - #include "dce/dce_clocks.h" - #include "dce/dce_clock_source.h" - -@@ -177,28 +177,6 @@ static const struct dce110_mem_input_reg_offsets dce112_mi_reg_offsets[] = { - } - }; - --static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = { --{ -- .dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL), --} --}; -- -- - /* set register offset */ - #define SR(reg_name)\ - .reg_name = mm ## reg_name -@@ -244,6 +222,28 @@ static const struct dce_abm_mask abm_mask = { - ABM_MASK_SH_LIST_DCE110(_MASK) - }; - -+#define ipp_regs(id)\ -+[id] = {\ -+ IPP_DCE110_REG_LIST_DCE_BASE(id)\ -+} -+ -+static const struct dce_ipp_registers ipp_regs[] = { -+ ipp_regs(0), -+ ipp_regs(1), -+ ipp_regs(2), -+ ipp_regs(3), -+ ipp_regs(4), -+ ipp_regs(5) -+}; -+ -+static const struct dce_ipp_shift ipp_shift = { -+ IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) -+}; -+ -+static const struct dce_ipp_mask ipp_mask = { -+ IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) -+}; -+ - #define transform_regs(id)\ - [id] = {\ - XFM_COMMON_REG_LIST_DCE110(id)\ -@@ -627,29 +627,19 @@ struct link_encoder *dce112_link_encoder_create( - return NULL; - } - --struct input_pixel_processor *dce112_ipp_create( -- struct dc_context *ctx, -- uint32_t inst, -- const struct dce110_ipp_reg_offsets *offset) -+static struct input_pixel_processor *dce112_ipp_create( -+ struct dc_context *ctx, uint32_t inst) - { -- struct dce110_ipp *ipp = -- dm_alloc(sizeof(struct dce110_ipp)); -+ struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); - -- if (!ipp) -+ if (!ipp) { -+ BREAK_TO_DEBUGGER(); - return NULL; -+ } - -- if (dce110_ipp_construct(ipp, ctx, inst, offset)) -- return &ipp->base; -- -- BREAK_TO_DEBUGGER(); -- dm_free(ipp); -- return NULL; --} -- --void dce112_ipp_destroy(struct input_pixel_processor **ipp) --{ -- dm_free(TO_DCE110_IPP(*ipp)); -- *ipp = NULL; -+ dce_ipp_construct(ipp, ctx, inst, -+ &ipp_regs[inst], &ipp_shift, &ipp_mask); -+ return &ipp->base; - } - - struct output_pixel_processor *dce112_opp_create( -@@ -712,7 +702,7 @@ static void destruct(struct dce110_resource_pool *pool) - dce112_transform_destroy(&pool->base.transforms[i]); - - if (pool->base.ipps[i] != NULL) -- dce112_ipp_destroy(&pool->base.ipps[i]); -+ dce_ipp_destroy(&pool->base.ipps[i]); - - if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); -@@ -1370,10 +1360,7 @@ static bool construct( - goto res_create_fail; - } - -- pool->base.ipps[i] = dce112_ipp_create( -- ctx, -- i, -- &ipp_reg_offsets[i]); -+ pool->base.ipps[i] = dce112_ipp_create(ctx, i); - if (pool->base.ipps[i] == NULL) { - BREAK_TO_DEBUGGER(); - dm_error( -diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c -index 207d07b..b6bdd1d 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c -@@ -176,7 +176,7 @@ static const struct dce_abm_mask abm_mask = { - - #define ipp_regs(id)\ - [id] = {\ -- IPP_COMMON_REG_LIST_DCE_BASE(id)\ -+ IPP_DCE110_REG_LIST_DCE_BASE(id)\ - } - - static const struct dce_ipp_registers ipp_regs[] = { -@@ -189,11 +189,11 @@ static const struct dce_ipp_registers ipp_regs[] = { - }; - - static const struct dce_ipp_shift ipp_shift = { -- IPP_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) -+ IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) - }; - - static const struct dce_ipp_mask ipp_mask = { -- IPP_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) -+ IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) - }; - - #define transform_regs(id)\ -@@ -497,12 +497,6 @@ static struct timing_generator *dce120_timing_generator_create( - return NULL; - } - --static void dce120_ipp_destroy(struct input_pixel_processor **ipp) --{ -- dm_free(TO_DCE_IPP(*ipp)); -- *ipp = NULL; --} -- - static void dce120_transform_destroy(struct transform **xfm) - { - dm_free(TO_DCE_TRANSFORM(*xfm)); -@@ -521,7 +515,7 @@ static void destruct(struct dce110_resource_pool *pool) - dce120_transform_destroy(&pool->base.transforms[i]); - - if (pool->base.ipps[i] != NULL) -- dce120_ipp_destroy(&pool->base.ipps[i]); -+ dce_ipp_destroy(&pool->base.ipps[i]); - - if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); -diff --git a/drivers/gpu/drm/amd/display/dc/dce80/Makefile b/drivers/gpu/drm/amd/display/dc/dce80/Makefile -index 8d2c3db..1d54d5f 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce80/Makefile -+++ b/drivers/gpu/drm/amd/display/dc/dce80/Makefile -@@ -2,7 +2,7 @@ - # Makefile for the 'controller' sub-component of DAL. - # It provides the control and status of HW CRTC block. - --DCE80 = dce80_ipp.o dce80_timing_generator.o \ -+DCE80 = dce80_timing_generator.o \ - dce80_compressor.o dce80_mem_input.o dce80_hw_sequencer.o \ - dce80_resource.o - -diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c -deleted file mode 100644 -index c195acb..0000000 ---- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.c -+++ /dev/null -@@ -1,65 +0,0 @@ --/* -- * Copyright 2012-15 Advanced Micro Devices, Inc. -- * -- * Permission is hereby granted, free of charge, to any person obtaining a -- * copy of this software and associated documentation files (the "Software"), -- * to deal in the Software without restriction, including without limitation -- * the rights to use, copy, modify, merge, publish, distribute, sublicense, -- * and/or sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following conditions: -- * -- * The above copyright notice and this permission notice shall be included in -- * all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. -- * -- * Authors: AMD -- * -- */ -- --#include "dm_services.h" --#include "include/logger_interface.h" -- --#include "dce/dce_8_0_d.h" --#include "dce/dce_8_0_sh_mask.h" -- --#include "dce80_ipp.h" -- --#include "dce110/dce110_ipp.h" -- --static const struct ipp_funcs funcs = { -- .ipp_cursor_set_attributes = dce110_ipp_cursor_set_attributes, -- .ipp_cursor_set_position = dce110_ipp_cursor_set_position, -- .ipp_program_prescale = dce110_ipp_program_prescale, -- .ipp_program_input_lut = dce110_ipp_program_input_lut, -- .ipp_set_degamma = dce110_ipp_set_degamma, --}; -- --bool dce80_ipp_construct( -- struct dce110_ipp *ipp, -- struct dc_context *ctx, -- uint32_t inst, -- const struct dce110_ipp_reg_offsets *offset) --{ -- ipp->base.ctx = ctx; -- -- ipp->base.inst = inst; -- -- ipp->offsets = *offset; -- -- ipp->base.funcs = &funcs; -- -- return true; --} -- --void dce80_ipp_destroy(struct input_pixel_processor **ipp) --{ -- dm_free(TO_DCE80_IPP(*ipp)); -- *ipp = NULL; --} -diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h -deleted file mode 100644 -index 06e8598..0000000 ---- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_ipp.h -+++ /dev/null -@@ -1,45 +0,0 @@ --/* -- * Copyright 2012-15 Advanced Micro Devices, Inc. -- * -- * Permission is hereby granted, free of charge, to any person obtaining a -- * copy of this software and associated documentation files (the "Software"), -- * to deal in the Software without restriction, including without limitation -- * the rights to use, copy, modify, merge, publish, distribute, sublicense, -- * and/or sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following conditions: -- * -- * The above copyright notice and this permission notice shall be included in -- * all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. -- * -- * Authors: AMD -- * -- */ -- --#ifndef __DC_IPP_DCE80_H__ --#define __DC_IPP_DCE80_H__ -- --#include "ipp.h" -- --#define TO_DCE80_IPP(input_pixel_processor)\ -- container_of(input_pixel_processor, struct dce110_ipp, base) -- --struct dce110_ipp; --struct dce110_ipp_reg_offsets; -- --bool dce80_ipp_construct( -- struct dce110_ipp *ipp, -- struct dc_context *ctx, -- uint32_t inst, -- const struct dce110_ipp_reg_offsets *offset); -- --void dce80_ipp_destroy(struct input_pixel_processor **ipp); -- --#endif /*__DC_IPP_DCE80_H__*/ -diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c -index ab8cee3..d490929 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c -@@ -41,10 +41,9 @@ - #include "dce/dce_link_encoder.h" - #include "dce/dce_stream_encoder.h" - #include "dce80/dce80_mem_input.h" --#include "dce80/dce80_ipp.h" -+#include "dce/dce_ipp.h" - #include "dce/dce_transform.h" - #include "dce/dce_opp.h" --#include "dce110/dce110_ipp.h" - #include "dce/dce_clocks.h" - #include "dce/dce_clock_source.h" - #include "dce/dce_audio.h" -@@ -187,27 +186,6 @@ static const struct dce110_mem_input_reg_offsets dce80_mi_reg_offsets[] = { - } - }; - --static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = { --{ -- .dcp_offset = (mmDCP0_CUR_CONTROL - mmDCP0_CUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP1_CUR_CONTROL - mmDCP0_CUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP2_CUR_CONTROL - mmDCP0_CUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP3_CUR_CONTROL - mmDCP0_CUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP4_CUR_CONTROL - mmDCP0_CUR_CONTROL), --}, --{ -- .dcp_offset = (mmDCP5_CUR_CONTROL - mmDCP0_CUR_CONTROL), --} --}; -- - /* set register offset */ - #define SR(reg_name)\ - .reg_name = mm ## reg_name -@@ -229,6 +207,28 @@ static const struct dce_disp_clk_mask disp_clk_mask = { - CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) - }; - -+#define ipp_regs(id)\ -+[id] = {\ -+ IPP_COMMON_REG_LIST_DCE_BASE(id)\ -+} -+ -+static const struct dce_ipp_registers ipp_regs[] = { -+ ipp_regs(0), -+ ipp_regs(1), -+ ipp_regs(2), -+ ipp_regs(3), -+ ipp_regs(4), -+ ipp_regs(5) -+}; -+ -+static const struct dce_ipp_shift ipp_shift = { -+ IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) -+}; -+ -+static const struct dce_ipp_mask ipp_mask = { -+ IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) -+}; -+ - #define transform_regs(id)\ - [id] = {\ - XFM_COMMON_REG_LIST_DCE_BASE(id)\ -@@ -592,25 +592,6 @@ static struct transform *dce80_transform_create( - return NULL; - } - --static struct input_pixel_processor *dce80_ipp_create( -- struct dc_context *ctx, -- uint32_t inst, -- const struct dce110_ipp_reg_offsets *offset) --{ -- struct dce110_ipp *ipp = -- dm_alloc(sizeof(struct dce110_ipp)); -- -- if (!ipp) -- return NULL; -- -- if (dce80_ipp_construct(ipp, ctx, inst, offset)) -- return &ipp->base; -- -- BREAK_TO_DEBUGGER(); -- dm_free(ipp); -- return NULL; --} -- - static const struct encoder_feature_support link_enc_feature = { - .max_hdmi_deep_color = COLOR_DEPTH_121212, - .max_hdmi_pixel_clock = 297000, -@@ -673,6 +654,21 @@ void dce80_clock_source_destroy(struct clock_source **clk_src) - *clk_src = NULL; - } - -+static struct input_pixel_processor *dce80_ipp_create( -+ struct dc_context *ctx, uint32_t inst) -+{ -+ struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); -+ -+ if (!ipp) { -+ BREAK_TO_DEBUGGER(); -+ return NULL; -+ } -+ -+ dce_ipp_construct(ipp, ctx, inst, -+ &ipp_regs[inst], &ipp_shift, &ipp_mask); -+ return &ipp->base; -+} -+ - static void destruct(struct dce110_resource_pool *pool) - { - unsigned int i; -@@ -685,7 +681,7 @@ static void destruct(struct dce110_resource_pool *pool) - dce80_transform_destroy(&pool->base.transforms[i]); - - if (pool->base.ipps[i] != NULL) -- dce80_ipp_destroy(&pool->base.ipps[i]); -+ dce_ipp_destroy(&pool->base.ipps[i]); - - if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i])); -@@ -1016,7 +1012,7 @@ static bool construct( - goto res_create_fail; - } - -- pool->base.ipps[i] = dce80_ipp_create(ctx, i, &ipp_reg_offsets[i]); -+ pool->base.ipps[i] = dce80_ipp_create(ctx, i); - if (pool->base.ipps[i] == NULL) { - BREAK_TO_DEBUGGER(); - dm_error("DC: failed to create input pixel processor!\n"); --- -2.7.4 - |