diff options
Diffstat (limited to 'meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0277-drm-amd-display-Enable-DCE12-support.patch')
-rw-r--r-- | meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0277-drm-amd-display-Enable-DCE12-support.patch | 1942 |
1 files changed, 0 insertions, 1942 deletions
diff --git a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0277-drm-amd-display-Enable-DCE12-support.patch b/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0277-drm-amd-display-Enable-DCE12-support.patch deleted file mode 100644 index 46f87929..00000000 --- a/meta-v1000/recipes-kernel/linux/linux-yocto-4.14.71/0277-drm-amd-display-Enable-DCE12-support.patch +++ /dev/null @@ -1,1942 +0,0 @@ -From c36d9218a8c0e37d355dbf266cdadecdacfb925f Mon Sep 17 00:00:00 2001 -From: Alex Deucher <alexander.deucher@amd.com> -Date: Thu, 15 Jun 2017 16:20:24 -0400 -Subject: [PATCH 0277/4131] drm/amd/display: Enable DCE12 support - -This wires DCE12 support into DC and enables it. - -Signed-off-by: Harry Wentland <harry.wentland@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +- - drivers/gpu/drm/amd/display/Kconfig | 7 + - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++- - .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 10 ++ - .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 20 ++- - drivers/gpu/drm/amd/display/dc/Makefile | 4 + - drivers/gpu/drm/amd/display/dc/bios/Makefile | 8 ++ - .../amd/display/dc/bios/bios_parser_interface.c | 14 ++ - drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 117 ++++++++++++++++ - drivers/gpu/drm/amd/display/dc/core/dc.c | 29 ++++ - drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 11 ++ - drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 +++ - drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 ++ - drivers/gpu/drm/amd/display/dc/dc.h | 27 ++++ - drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 46 +++++++ - .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 6 + - drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 149 +++++++++++++++++++++ - drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 20 +++ - drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 8 ++ - .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 14 ++ - drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 35 +++++ - drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 34 +++++ - drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 72 ++++++++++ - .../drm/amd/display/dc/dce/dce_stream_encoder.h | 100 ++++++++++++++ - drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 68 ++++++++++ - .../amd/display/dc/dce110/dce110_hw_sequencer.c | 53 +++++++- - .../drm/amd/display/dc/dce110/dce110_mem_input.c | 3 + - .../display/dc/dce110/dce110_timing_generator.h | 3 + - drivers/gpu/drm/amd/display/dc/dce120/Makefile | 12 ++ - .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 3 + - drivers/gpu/drm/amd/display/dc/dm_services.h | 89 ++++++++++++ - drivers/gpu/drm/amd/display/dc/dm_services_types.h | 27 ++++ - drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 ++ - drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 ++ - drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +- - drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 ++ - drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 ++ - .../gpu/drm/amd/display/dc/inc/bandwidth_calcs.h | 3 + - .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 23 ++++ - drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 + - drivers/gpu/drm/amd/display/dc/irq/Makefile | 12 ++ - drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 3 + - drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4 + - drivers/gpu/drm/amd/display/include/dal_types.h | 3 + - 44 files changed, 1141 insertions(+), 10 deletions(-) - create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/Makefile - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -index 3d8f699..486b3c5 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -@@ -1973,14 +1973,16 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) - #if defined(CONFIG_DRM_AMD_DC) - case CHIP_BONAIRE: - case CHIP_HAWAII: -- return amdgpu_dc != 0; - case CHIP_CARRIZO: - case CHIP_STONEY: - case CHIP_POLARIS11: - case CHIP_POLARIS10: -- return amdgpu_dc != 0; -+ case CHIP_POLARIS12: - case CHIP_TONGA: - case CHIP_FIJI: -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ case CHIP_VEGA10: -+#endif - return amdgpu_dc != 0; - #endif - default: -diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig -index f652cc3..40d6386 100644 ---- a/drivers/gpu/drm/amd/display/Kconfig -+++ b/drivers/gpu/drm/amd/display/Kconfig -@@ -9,6 +9,13 @@ config DRM_AMD_DC - - Will be deprecated when the DC component is upstream. - -+config DRM_AMD_DC_DCE12_0 -+ bool "Vega10 family" -+ depends on DRM_AMD_DC -+ help -+ Choose this option if you want to have -+ VG family for display engine. -+ - config DEBUG_KERNEL_DC - bool "Enable kgdb break in DC" - depends on DRM_AMD_DC -diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c -index 54d8d2c..1d208af 100644 ---- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c -+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c -@@ -888,6 +888,10 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) - struct dc_interrupt_params int_params = {0}; - int r; - int i; -+ unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY; -+ -+ if (adev->asic_type == CHIP_VEGA10) -+ client_id = AMDGPU_IH_CLIENTID_DCE; - - int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; - int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; -@@ -904,7 +908,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) - - /* Use VBLANK interrupt */ - for (i = 1; i <= adev->mode_info.num_crtc; i++) { -- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->crtc_irq); -+ r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); - - if (r) { - DRM_ERROR("Failed to add crtc irq id!\n"); -@@ -927,7 +931,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) - /* Use GRPH_PFLIP interrupt */ - for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; - i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { -- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); -+ r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); - if (r) { - DRM_ERROR("Failed to add page flip irq id!\n"); - return r; -@@ -948,8 +952,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) - } - - /* HPD */ -- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, -- &adev->hpd_irq); -+ r = amdgpu_irq_add_id(adev, client_id, -+ VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); - if (r) { - DRM_ERROR("Failed to add hpd irq id!\n"); - return r; -@@ -1119,6 +1123,9 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) - case CHIP_POLARIS11: - case CHIP_POLARIS10: - case CHIP_POLARIS12: -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ case CHIP_VEGA10: -+#endif - if (dce110_register_irq_handlers(dm->adev)) { - DRM_ERROR("DM: Failed to initialize IRQ\n"); - return -1; -@@ -1317,6 +1324,7 @@ static const struct amdgpu_display_funcs dm_display_funcs = { - - }; - -+ - #if defined(CONFIG_DEBUG_KERNEL_DC) - - static ssize_t s3_debug_store( -@@ -1389,6 +1397,13 @@ static int dm_early_init(void *handle) - adev->mode_info.num_hpd = 6; - adev->mode_info.num_dig = 6; - break; -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ case CHIP_VEGA10: -+ adev->mode_info.num_crtc = 6; -+ adev->mode_info.num_hpd = 6; -+ adev->mode_info.num_dig = 6; -+ break; -+#endif - default: - DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); - return -EINVAL; -diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c -index 1ddc56c..df53092 100644 ---- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c -+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c -@@ -402,6 +402,16 @@ bool dm_pp_notify_wm_clock_changes( - return false; - } - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+bool dm_pp_notify_wm_clock_changes_soc15( -+ const struct dc_context *ctx, -+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) -+{ -+ /* TODO: to be implemented */ -+ return false; -+} -+#endif -+ - bool dm_pp_apply_power_level_change_request( - const struct dc_context *ctx, - struct dm_pp_power_level_change_request *level_change_req) -diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c -index 38d37c2..908cc3d 100644 ---- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c -+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c -@@ -494,7 +494,7 @@ static void fill_plane_attributes_from_fb( - - memset(&surface->tiling_info, 0, sizeof(surface->tiling_info)); - -- /* Fill GFX8 params */ -+ /* Fill GFX params */ - if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) - { - unsigned bankw, bankh, mtaspect, tile_split, num_banks; -@@ -523,6 +523,24 @@ static void fill_plane_attributes_from_fb( - surface->tiling_info.gfx8.pipe_config = - AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); - -+ if (adev->asic_type == CHIP_VEGA10) { -+ /* Fill GFX9 params */ -+ surface->tiling_info.gfx9.num_pipes = -+ adev->gfx.config.gb_addr_config_fields.num_pipes; -+ surface->tiling_info.gfx9.num_banks = -+ adev->gfx.config.gb_addr_config_fields.num_banks; -+ surface->tiling_info.gfx9.pipe_interleave = -+ adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; -+ surface->tiling_info.gfx9.num_shader_engines = -+ adev->gfx.config.gb_addr_config_fields.num_se; -+ surface->tiling_info.gfx9.max_compressed_frags = -+ adev->gfx.config.gb_addr_config_fields.max_compress_frags; -+ surface->tiling_info.gfx9.swizzle = -+ AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); -+ surface->tiling_info.gfx9.shaderEnable = 1; -+ } -+ -+ - surface->plane_size.grph.surface_size.x = 0; - surface->plane_size.grph.surface_size.y = 0; - surface->plane_size.grph.surface_size.width = fb->width; -diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile -index 2df163b..a580cab 100644 ---- a/drivers/gpu/drm/amd/display/dc/Makefile -+++ b/drivers/gpu/drm/amd/display/dc/Makefile -@@ -4,6 +4,10 @@ - - DC_LIBS = basics bios calcs dce gpio i2caux irq virtual - -+ifdef CONFIG_DRM_AMD_DC_DCE12_0 -+DC_LIBS += dce120 -+endif -+ - DC_LIBS += dce112 - DC_LIBS += dce110 - DC_LIBS += dce100 -diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile -index 876614d..7702484 100644 ---- a/drivers/gpu/drm/amd/display/dc/bios/Makefile -+++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile -@@ -4,6 +4,10 @@ - - BIOS = bios_parser.o bios_parser_interface.o bios_parser_helper.o command_table.o command_table_helper.o - -+ifdef CONFIG_DRM_AMD_DC_DCE12_0 -+BIOS += command_table2.o command_table_helper2.o bios_parser2.o -+endif -+ - AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS)) - - AMD_DISPLAY_FILES += $(AMD_DAL_BIOS) -@@ -21,3 +25,7 @@ AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce80/command_table_helper_dce80.o - AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o - - AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper_dce112.o -+ -+ifdef CONFIG_DRM_AMD_DC_DCE12_0 -+AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper2_dce112.o -+endif -diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c -index 42272c3..7fe2a79 100644 ---- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c -+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c -@@ -29,6 +29,10 @@ - #include "bios_parser_interface.h" - #include "bios_parser.h" - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#include "bios_parser2.h" -+#endif -+ - - struct dc_bios *dal_bios_parser_create( - struct bp_init_data *init, -@@ -36,7 +40,17 @@ struct dc_bios *dal_bios_parser_create( - { - struct dc_bios *bios = NULL; - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ bios = firmware_parser_create(init, dce_version); -+ -+ if (bios == NULL) -+ /* TODO: remove dce_version from bios_parser. -+ * cannot remove today because dal enum to bp enum translation is dce specific -+ */ -+ bios = bios_parser_create(init, dce_version); -+#else - bios = bios_parser_create(init, dce_version); -+#endif - - return bios; - } -diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c -index ab8d1e9..aa98762 100644 ---- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c -+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c -@@ -50,6 +50,11 @@ static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asi - return BW_CALCS_VERSION_POLARIS11; - return BW_CALCS_VERSION_INVALID; - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ case FAMILY_AI: -+ return BW_CALCS_VERSION_VEGA10; -+#endif -+ - default: - return BW_CALCS_VERSION_INVALID; - } -@@ -2430,6 +2435,118 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, - dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2; - dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); - break; -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ case BW_CALCS_VERSION_VEGA10: -+ vbios.memory_type = bw_def_hbm; -+ vbios.dram_channel_width_in_bits = 128; -+ vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits; -+ vbios.number_of_dram_banks = 16; -+ vbios.high_yclk = bw_int_to_fixed(2400); -+ vbios.mid_yclk = bw_int_to_fixed(1700); -+ vbios.low_yclk = bw_int_to_fixed(1000); -+ vbios.low_sclk = bw_int_to_fixed(300); -+ vbios.mid1_sclk = bw_int_to_fixed(350); -+ vbios.mid2_sclk = bw_int_to_fixed(400); -+ vbios.mid3_sclk = bw_int_to_fixed(500); -+ vbios.mid4_sclk = bw_int_to_fixed(600); -+ vbios.mid5_sclk = bw_int_to_fixed(700); -+ vbios.mid6_sclk = bw_int_to_fixed(760); -+ vbios.high_sclk = bw_int_to_fixed(776); -+ vbios.low_voltage_max_dispclk = bw_int_to_fixed(460); -+ vbios.mid_voltage_max_dispclk = bw_int_to_fixed(670); -+ vbios.high_voltage_max_dispclk = bw_int_to_fixed(1133); -+ vbios.low_voltage_max_phyclk = bw_int_to_fixed(540); -+ vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810); -+ vbios.high_voltage_max_phyclk = bw_int_to_fixed(810); -+ vbios.data_return_bus_width = bw_int_to_fixed(32); -+ vbios.trc = bw_int_to_fixed(48); -+ vbios.dmifmc_urgent_latency = bw_int_to_fixed(3); -+ vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(75, 10); -+ vbios.stutter_self_refresh_entry_latency = bw_frc_to_fixed(19, 10); -+ vbios.nbp_state_change_latency = bw_int_to_fixed(39); -+ vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10); -+ vbios.scatter_gather_enable = false; -+ vbios.down_spread_percentage = bw_frc_to_fixed(5, 10); -+ vbios.cursor_width = 32; -+ vbios.average_compression_rate = 4; -+ vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 8; -+ vbios.blackout_duration = bw_int_to_fixed(0); /* us */ -+ vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0); -+ -+ dceip.large_cursor = false; -+ dceip.dmif_request_buffer_size = bw_int_to_fixed(2304); -+ dceip.dmif_pipe_en_fbc_chunk_tracker = true; -+ dceip.cursor_max_outstanding_group_num = 1; -+ dceip.lines_interleaved_into_lb = 2; -+ dceip.chunk_width = 256; -+ dceip.number_of_graphics_pipes = 6; -+ dceip.number_of_underlay_pipes = 0; -+ dceip.low_power_tiling_mode = 0; -+ dceip.display_write_back_supported = true; -+ dceip.argb_compression_support = true; -+ dceip.underlay_vscaler_efficiency6_bit_per_component = -+ bw_frc_to_fixed(35556, 10000); -+ dceip.underlay_vscaler_efficiency8_bit_per_component = -+ bw_frc_to_fixed(34286, 10000); -+ dceip.underlay_vscaler_efficiency10_bit_per_component = -+ bw_frc_to_fixed(32, 10); -+ dceip.underlay_vscaler_efficiency12_bit_per_component = -+ bw_int_to_fixed(3); -+ dceip.graphics_vscaler_efficiency6_bit_per_component = -+ bw_frc_to_fixed(35, 10); -+ dceip.graphics_vscaler_efficiency8_bit_per_component = -+ bw_frc_to_fixed(34286, 10000); -+ dceip.graphics_vscaler_efficiency10_bit_per_component = -+ bw_frc_to_fixed(32, 10); -+ dceip.graphics_vscaler_efficiency12_bit_per_component = -+ bw_int_to_fixed(3); -+ dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3); -+ dceip.max_dmif_buffer_allocated = 4; -+ dceip.graphics_dmif_size = 24576; -+ dceip.underlay_luma_dmif_size = 19456; -+ dceip.underlay_chroma_dmif_size = 23552; -+ dceip.pre_downscaler_enabled = true; -+ dceip.underlay_downscale_prefetch_enabled = false; -+ dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1); -+ dceip.lb_size_per_component444 = bw_int_to_fixed(245952); -+ dceip.graphics_lb_nodownscaling_multi_line_prefetching = true; -+ dceip.stutter_and_dram_clock_state_change_gated_before_cursor = -+ bw_int_to_fixed(1); -+ dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed( -+ 82176); -+ dceip.underlay420_chroma_lb_size_per_component = -+ bw_int_to_fixed(164352); -+ dceip.underlay422_lb_size_per_component = bw_int_to_fixed( -+ 82176); -+ dceip.cursor_chunk_width = bw_int_to_fixed(64); -+ dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4); -+ dceip.underlay_maximum_width_efficient_for_tiling = -+ bw_int_to_fixed(1920); -+ dceip.underlay_maximum_height_efficient_for_tiling = -+ bw_int_to_fixed(1080); -+ dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display = -+ bw_frc_to_fixed(3, 10); -+ dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation = -+ bw_int_to_fixed(25); -+ dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed( -+ 2); -+ dceip.maximum_total_outstanding_pte_requests_allowed_by_saw = -+ bw_int_to_fixed(128); -+ dceip.limit_excessive_outstanding_dmif_requests = true; -+ dceip.linear_mode_line_request_alternation_slice = -+ bw_int_to_fixed(64); -+ dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode = -+ 32; -+ dceip.display_write_back420_luma_mcifwr_buffer_size = 12288; -+ dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192; -+ dceip.request_efficiency = bw_frc_to_fixed(8, 10); -+ dceip.dispclk_per_request = bw_int_to_fixed(2); -+ dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100); -+ dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100); -+ dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2; -+ dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); -+ break; -+#endif - default: - break; - } -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c -index b9ca968..28ed8ea 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c -@@ -1815,3 +1815,32 @@ void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink - } - } - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) -+{ -+ int i; -+ struct core_dc *core_dc = DC_TO_CORE(dc); -+ struct mem_input *mi = NULL; -+ -+ for (i = 0; i < core_dc->res_pool->pipe_count; i++) { -+ if (core_dc->res_pool->mis[i] != NULL) { -+ mi = core_dc->res_pool->mis[i]; -+ break; -+ } -+ } -+ if (mi == NULL) { -+ dm_error("no mem_input!\n"); -+ return false; -+ } -+ -+ if (mi->funcs->mem_input_update_dchub) -+ mi->funcs->mem_input_update_dchub(mi, dh_data); -+ else -+ ASSERT(mi->funcs->mem_input_update_dchub); -+ -+ -+ return true; -+ -+} -+#endif -+ -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c -index 85ddf5f..079558a 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c -@@ -141,6 +141,12 @@ void pre_surface_trace( - surface->format, - surface->rotation, - surface->stereo_format); -+ -+#if defined (CONFIG_DRM_AMD_DC_DCE12_0) -+ SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", -+ surface->tiling_info.gfx9.swizzle); -+#endif -+ - SURFACE_TRACE("\n"); - } - SURFACE_TRACE("\n"); -@@ -221,6 +227,11 @@ void update_surface_trace( - update->plane_info->tiling_info.gfx8.pipe_config, - update->plane_info->tiling_info.gfx8.array_mode, - update->plane_info->visible); -+ -+ #if defined (CONFIG_DRM_AMD_DC_DCE12_0) -+ SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", -+ update->plane_info->tiling_info.gfx9.swizzle); -+ #endif - } - - if (update->scaling_info) { -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c -index 5ca72af..f13da7c 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c -@@ -1217,6 +1217,25 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) - pipe_ctx->dis_clk->funcs->set_min_clocks_state( - pipe_ctx->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL); - } else { -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ uint32_t dp_phyclk_in_khz; -+ const struct clocks_value clocks_value = -+ pipe_ctx->dis_clk->cur_clocks_value; -+ -+ /* 27mhz = 27000000hz= 27000khz */ -+ dp_phyclk_in_khz = link_settings.link_rate * 27000; -+ -+ if (((clocks_value.max_non_dp_phyclk_in_khz != 0) && -+ (dp_phyclk_in_khz > clocks_value.max_non_dp_phyclk_in_khz)) || -+ (dp_phyclk_in_khz > clocks_value.max_dp_phyclk_in_khz)) { -+ pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( -+ pipe_ctx->dis_clk, -+ DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, -+ dp_phyclk_in_khz, -+ false, -+ true); -+ } -+#endif - } - } - -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c -index 6119973..77ef330 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c -@@ -39,6 +39,9 @@ - #include "dce100/dce100_resource.h" - #include "dce110/dce110_resource.h" - #include "dce112/dce112_resource.h" -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#include "dce120/dce120_resource.h" -+#endif - - enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) - { -@@ -65,6 +68,11 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) - dc_version = DCE_VERSION_11_2; - } - break; -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ case FAMILY_AI: -+ dc_version = DCE_VERSION_12_0; -+ break; -+#endif - default: - dc_version = DCE_VERSION_UNKNOWN; - break; -@@ -97,6 +105,12 @@ struct resource_pool *dc_create_resource_pool( - res_pool = dce112_create_resource_pool( - num_virtual_links, dc); - break; -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ case DCE_VERSION_12_0: -+ res_pool = dce120_create_resource_pool( -+ num_virtual_links, dc); -+ break; -+#endif - default: - break; - } -diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h -index c6c0cf5..bc15065 100644 ---- a/drivers/gpu/drm/amd/display/dc/dc.h -+++ b/drivers/gpu/drm/amd/display/dc/dc.h -@@ -55,6 +55,9 @@ struct dc_caps { - struct dc_dcc_surface_param { - enum surface_pixel_format format; - struct dc_size surface_size; -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ enum swizzle_mode_values swizzle_mode; -+#endif - enum dc_scan_direction scan; - }; - -@@ -143,6 +146,9 @@ struct dc_debug { - bool disable_stutter; - bool disable_dcc; - bool disable_dfs_bypass; -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ bool disable_pplib_clock_request; -+#endif - bool disable_clock_gate; - bool disable_dmcu; - bool force_abm_enable; -@@ -157,6 +163,23 @@ struct dc { - struct dc_debug debug; - }; - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+enum frame_buffer_mode { -+ FRAME_BUFFER_MODE_LOCAL_ONLY = 0, -+ FRAME_BUFFER_MODE_ZFB_ONLY, -+ FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, -+} ; -+ -+struct dchub_init_data { -+ bool dchub_initialzied; -+ bool dchub_info_valid; -+ int64_t zfb_phys_addr_base; -+ int64_t zfb_mc_base_addr; -+ uint64_t zfb_size_in_byte; -+ enum frame_buffer_mode fb_mode; -+}; -+#endif -+ - struct dc_init_data { - struct hw_asic_id asic_id; - void *driver; /* ctx */ -@@ -177,6 +200,10 @@ struct dc *dc_create(const struct dc_init_data *init_params); - - void dc_destroy(struct dc **dc); - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data); -+#endif -+ - /******************************************************************************* - * Surface Interfaces - ******************************************************************************/ -diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h -index 75e16ac..6381340 100644 ---- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h -+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h -@@ -259,6 +259,36 @@ enum tile_mode_values { - DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, - }; - -+#if defined (CONFIG_DRM_AMD_DC_DCE12_0) -+enum swizzle_mode_values { -+ DC_SW_LINEAR = 0, -+ DC_SW_256B_S = 1, -+ DC_SW_256_D = 2, -+ DC_SW_256_R = 3, -+ DC_SW_4KB_S = 5, -+ DC_SW_4KB_D = 6, -+ DC_SW_4KB_R = 7, -+ DC_SW_64KB_S = 9, -+ DC_SW_64KB_D = 10, -+ DC_SW_64KB_R = 11, -+ DC_SW_VAR_S = 13, -+ DC_SW_VAR_D = 14, -+ DC_SW_VAR_R = 15, -+ DC_SW_64KB_S_T = 17, -+ DC_SW_64KB_D_T = 18, -+ DC_SW_4KB_S_X = 21, -+ DC_SW_4KB_D_X = 22, -+ DC_SW_4KB_R_X = 23, -+ DC_SW_64KB_S_X = 25, -+ DC_SW_64KB_D_X = 26, -+ DC_SW_64KB_R_X = 27, -+ DC_SW_VAR_S_X = 29, -+ DC_SW_VAR_D_X = 30, -+ DC_SW_VAR_R_X = 31, -+ DC_SW_MAX -+}; -+#endif -+ - union dc_tiling_info { - - struct { -@@ -323,6 +353,22 @@ union dc_tiling_info { - enum array_mode_values array_mode; - } gfx8; - -+#if defined (CONFIG_DRM_AMD_DC_DCE12_0) -+ struct { -+ unsigned int num_pipes; -+ unsigned int num_banks; -+ unsigned int pipe_interleave; -+ unsigned int num_shader_engines; -+ unsigned int num_rb_per_se; -+ unsigned int max_compressed_frags; -+ bool shaderEnable; -+ -+ enum swizzle_mode_values swizzle; -+ bool meta_linear; -+ bool rb_aligned; -+ bool pipe_aligned; -+ } gfx9; -+#endif - }; - - /* Rotation angle */ -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c -index 1d6a9da..f53dc15 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c -@@ -585,6 +585,9 @@ static uint32_t dce110_get_pix_clk_dividers( - pll_settings, pix_clk_params); - break; - case DCE_VERSION_11_2: -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ case DCE_VERSION_12_0: -+#endif - dce112_get_pix_clk_dividers_helper(clk_src, - pll_settings, pix_clk_params); - break; -@@ -868,6 +871,9 @@ static bool dce110_program_pix_clk( - - break; - case DCE_VERSION_11_2: -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ case DCE_VERSION_12_0: -+#endif - if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { - bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = - pll_settings->use_external_clk; -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c -index ac1feba..9c743e5 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c -@@ -80,6 +80,20 @@ static struct state_dependent_clocks dce112_max_clks_by_state[] = { - /*ClocksStatePerformance*/ - { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } }; - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+static struct state_dependent_clocks dce120_max_clks_by_state[] = { -+/*ClocksStateInvalid - should not be used*/ -+{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -+/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ -+{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -+/*ClocksStateLow*/ -+{ .display_clk_khz = 460000, .pixel_clk_khz = 400000 }, -+/*ClocksStateNominal*/ -+{ .display_clk_khz = 670000, .pixel_clk_khz = 600000 }, -+/*ClocksStatePerformance*/ -+{ .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } }; -+#endif -+ - /* Starting point for each divider range.*/ - enum dce_divider_range_start { - DIVIDER_RANGE_01_START = 200, /* 2.00*/ -@@ -483,6 +497,103 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce) - } - } - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+static bool dce_apply_clock_voltage_request( -+ struct display_clock *clk, -+ enum dm_pp_clock_type clocks_type, -+ int clocks_in_khz, -+ bool pre_mode_set, -+ bool update_dp_phyclk) -+{ -+ struct dm_pp_clock_for_voltage_req clock_voltage_req = {0}; -+ -+ switch (clocks_type) { -+ case DM_PP_CLOCK_TYPE_DISPLAY_CLK: -+ case DM_PP_CLOCK_TYPE_PIXELCLK: -+ case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK: -+ break; -+ default: -+ BREAK_TO_DEBUGGER(); -+ return false; -+ } -+ -+ clock_voltage_req.clk_type = clocks_type; -+ clock_voltage_req.clocks_in_khz = clocks_in_khz; -+ -+ /* to pplib */ -+ if (pre_mode_set) { -+ switch (clocks_type) { -+ case DM_PP_CLOCK_TYPE_DISPLAY_CLK: -+ if (clocks_in_khz > clk->cur_clocks_value.dispclk_in_khz) { -+ dm_pp_apply_clock_for_voltage_request( -+ clk->ctx, &clock_voltage_req); -+ clk->cur_clocks_value.dispclk_notify_pplib_done = true; -+ } else -+ clk->cur_clocks_value.dispclk_notify_pplib_done = false; -+ /* no matter incrase or decrase clock, update current clock value */ -+ clk->cur_clocks_value.dispclk_in_khz = clocks_in_khz; -+ break; -+ case DM_PP_CLOCK_TYPE_PIXELCLK: -+ if (clocks_in_khz > clk->cur_clocks_value.max_pixelclk_in_khz) { -+ dm_pp_apply_clock_for_voltage_request( -+ clk->ctx, &clock_voltage_req); -+ clk->cur_clocks_value.pixelclk_notify_pplib_done = true; -+ } else -+ clk->cur_clocks_value.pixelclk_notify_pplib_done = false; -+ /* no matter incrase or decrase clock, update current clock value */ -+ clk->cur_clocks_value.max_pixelclk_in_khz = clocks_in_khz; -+ break; -+ case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK: -+ if (clocks_in_khz > clk->cur_clocks_value.max_non_dp_phyclk_in_khz) { -+ dm_pp_apply_clock_for_voltage_request( -+ clk->ctx, &clock_voltage_req); -+ clk->cur_clocks_value.phyclk_notigy_pplib_done = true; -+ } else -+ clk->cur_clocks_value.phyclk_notigy_pplib_done = false; -+ /* no matter incrase or decrase clock, update current clock value */ -+ clk->cur_clocks_value.max_non_dp_phyclk_in_khz = clocks_in_khz; -+ break; -+ default: -+ ASSERT(0); -+ break; -+ } -+ } else { -+ switch (clocks_type) { -+ case DM_PP_CLOCK_TYPE_DISPLAY_CLK: -+ if (!clk->cur_clocks_value.dispclk_notify_pplib_done) -+ dm_pp_apply_clock_for_voltage_request( -+ clk->ctx, &clock_voltage_req); -+ break; -+ case DM_PP_CLOCK_TYPE_PIXELCLK: -+ if (!clk->cur_clocks_value.pixelclk_notify_pplib_done) -+ dm_pp_apply_clock_for_voltage_request( -+ clk->ctx, &clock_voltage_req); -+ break; -+ case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK: -+ if (!clk->cur_clocks_value.phyclk_notigy_pplib_done) -+ dm_pp_apply_clock_for_voltage_request( -+ clk->ctx, &clock_voltage_req); -+ break; -+ default: -+ ASSERT(0); -+ break; -+ } -+ } -+ -+ if (update_dp_phyclk && (clocks_in_khz > -+ clk->cur_clocks_value.max_dp_phyclk_in_khz)) -+ clk->cur_clocks_value.max_dp_phyclk_in_khz = clocks_in_khz; -+ -+ return true; -+} -+ -+static const struct display_clock_funcs dce120_funcs = { -+ .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq, -+ .apply_clock_voltage_request = dce_apply_clock_voltage_request, -+ .set_clock = dce112_set_clock -+}; -+#endif -+ - static const struct display_clock_funcs dce112_funcs = { - .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq, - .get_required_clocks_state = dce_get_required_clocks_state, -@@ -623,6 +734,44 @@ struct display_clock *dce112_disp_clk_create( - return &clk_dce->base; - } - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+struct display_clock *dce120_disp_clk_create( -+ struct dc_context *ctx, -+ const struct dce_disp_clk_registers *regs, -+ const struct dce_disp_clk_shift *clk_shift, -+ const struct dce_disp_clk_mask *clk_mask) -+{ -+ struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); -+ struct dm_pp_clock_levels_with_voltage clk_level_info = {0}; -+ -+ if (clk_dce == NULL) { -+ BREAK_TO_DEBUGGER(); -+ return NULL; -+ } -+ -+ memcpy(clk_dce->max_clks_by_state, -+ dce120_max_clks_by_state, -+ sizeof(dce120_max_clks_by_state)); -+ -+ dce_disp_clk_construct( -+ clk_dce, ctx, regs, clk_shift, clk_mask); -+ -+ clk_dce->base.funcs = &dce120_funcs; -+ -+ /* new in dce120 */ -+ if (!ctx->dc->debug.disable_pplib_clock_request && -+ dm_pp_get_clock_levels_by_type_with_voltage( -+ ctx, DM_PP_CLOCK_TYPE_DISPLAY_CLK, &clk_level_info) -+ && clk_level_info.num_levels) -+ clk_dce->max_displ_clk_in_khz = -+ clk_level_info.data[clk_level_info.num_levels - 1].clocks_in_khz; -+ else -+ clk_dce->max_displ_clk_in_khz = 1133000; -+ -+ return &clk_dce->base; -+} -+#endif -+ - void dce_disp_clk_destroy(struct display_clock **disp_clk) - { - struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(*disp_clk); -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h -index 020ab9d..18787f6 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h -@@ -45,6 +45,14 @@ - CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ - CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ -+ CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ -+ CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \ -+ CLK_SF(DCCG_DFS_MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ -+ CLK_SF(DCCG_DFS_MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) -+#endif -+ - #define CLK_REG_FIELD_LIST(type) \ - type DPREFCLK_SRC_SEL; \ - type DENTIST_DPREFCLK_WDIVIDER; \ -@@ -118,6 +126,10 @@ struct dce_disp_clk { - int gpu_pll_ss_divider; - - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ /* max disp_clk from PPLIB for max validation display clock*/ -+ int max_displ_clk_in_khz; -+#endif - }; - - -@@ -139,6 +151,14 @@ struct display_clock *dce112_disp_clk_create( - const struct dce_disp_clk_shift *clk_shift, - const struct dce_disp_clk_mask *clk_mask); - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+struct display_clock *dce120_disp_clk_create( -+ struct dc_context *ctx, -+ const struct dce_disp_clk_registers *regs, -+ const struct dce_disp_clk_shift *clk_shift, -+ const struct dce_disp_clk_mask *clk_mask); -+#endif -+ - void dce_disp_clk_destroy(struct display_clock **disp_clk); - - #endif /* _DCE_CLOCKS_H_ */ -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h -index 70e0652..ff7984b 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h -@@ -186,6 +186,14 @@ struct dce_hwseq_registers { - HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ - HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ -+ HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ -+ HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ -+ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ -+ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) -+#endif -+ - #define HWSEQ_REG_FIED_LIST(type) \ - type DCFE_CLOCK_ENABLE; \ - type DCFEV_CLOCK_ENABLE; \ -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h -index f337d60..f6a1006 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h -@@ -31,6 +31,13 @@ - #define TO_DCE110_LINK_ENC(link_encoder)\ - container_of(link_encoder, struct dce110_link_encoder, base) - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+/* Not found regs in dce120 spec -+ * BIOS_SCRATCH_2 -+ * DP_DPHY_INTERNAL_CTRL -+ */ -+#endif -+ - #define AUX_REG_LIST(id)\ - SRI(AUX_CONTROL, DP_AUX, id), \ - SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id) -@@ -79,6 +86,13 @@ - SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ - SR(DCI_MEM_PWR_STATUS) - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ #define LE_DCE120_REG_LIST(id)\ -+ LE_COMMON_REG_LIST_BASE(id), \ -+ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ -+ SR(DCI_MEM_PWR_STATUS) -+#endif -+ - #define LE_DCE80_REG_LIST(id)\ - SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ - LE_COMMON_REG_LIST_BASE(id) -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c -index e14a21c..c494f71 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c -@@ -187,6 +187,20 @@ static void program_nbp_watermark(struct mem_input *mi, - REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, - NB_PSTATE_CHANGE_WATERMARK, nbp_wm); - } -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ if (REG(DPG_PIPE_LOW_POWER_CONTROL)) { -+ REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, -+ PSTATE_CHANGE_WATERMARK_MASK, wm_select); -+ -+ REG_UPDATE_3(DPG_PIPE_LOW_POWER_CONTROL, -+ PSTATE_CHANGE_ENABLE, 1, -+ PSTATE_CHANGE_URGENT_DURING_REQUEST, 1, -+ PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, 1); -+ -+ REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL, -+ PSTATE_CHANGE_WATERMARK, nbp_wm); -+ } -+#endif - } - - static void program_stutter_watermark(struct mem_input *mi, -@@ -196,6 +210,12 @@ static void program_stutter_watermark(struct mem_input *mi, - REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, - STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select); - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ if (REG(DPG_PIPE_STUTTER_CONTROL2)) -+ REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2, -+ STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark); -+ else -+#endif - REG_UPDATE(DPG_PIPE_STUTTER_CONTROL, - STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark); - } -@@ -234,6 +254,21 @@ void dce_mem_input_program_display_marks(struct mem_input *mi, - static void program_tiling(struct mem_input *mi, - const union dc_tiling_info *info) - { -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ if (mi->masks->GRPH_SW_MODE) { /* GFX9 */ -+ REG_UPDATE_6(GRPH_CONTROL, -+ GRPH_SW_MODE, info->gfx9.swizzle, -+ GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), -+ GRPH_NUM_SHADER_ENGINES, log_2(info->gfx9.num_shader_engines), -+ GRPH_NUM_PIPES, log_2(info->gfx9.num_pipes), -+ GRPH_COLOR_EXPANSION_MODE, 1, -+ GRPH_SE_ENABLE, info->gfx9.shaderEnable); -+ /* TODO: DCP0_GRPH_CONTROL__GRPH_SE_ENABLE where to get info -+ GRPH_SE_ENABLE, 1, -+ GRPH_Z, 0); -+ */ -+ } -+#endif - if (mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */ - REG_UPDATE_9(GRPH_CONTROL, - GRPH_NUM_BANKS, info->gfx8.num_banks, -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h -index ec053c2..9e18c2a 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h -@@ -58,6 +58,15 @@ - MI_DCE11_2_REG_LIST(id),\ - MI_DCE_PTE_REG_LIST(id) - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#define MI_DCE12_REG_LIST(id)\ -+ MI_DCE_BASE_REG_LIST(id),\ -+ MI_DCE_PTE_REG_LIST(id),\ -+ SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\ -+ SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\ -+ SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id) -+#endif -+ - struct dce_mem_input_registers { - /* DCP */ - uint32_t GRPH_ENABLE; -@@ -163,6 +172,31 @@ struct dce_mem_input_registers { - MI_DCE11_2_MASK_SH_LIST(mask_sh),\ - MI_DCP_PTE_MASK_SH_LIST(mask_sh, ) - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\ -+ SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\ -+ SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\ -+ SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\ -+ SFB(blk, GRPH_CONTROL, GRPH_NUM_PIPES, mask_sh),\ -+ SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh) -+ -+#define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\ -+ SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\ -+ SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ -+ SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\ -+ SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ -+ SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ -+ SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh) -+ -+#define MI_DCE12_MASK_SH_LIST(mask_sh)\ -+ MI_DCP_MASK_SH_LIST(mask_sh, DCP0_),\ -+ MI_DCP_DCE11_MASK_SH_LIST(mask_sh, DCP0_),\ -+ MI_DCP_PTE_MASK_SH_LIST(mask_sh, DCP0_),\ -+ MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ -+ MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ -+ MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_) -+#endif -+ - #define MI_REG_FIELD_LIST(type) \ - type GRPH_ENABLE; \ - type GRPH_X_START; \ -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h -index a5afc02..4784ced 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h -@@ -107,6 +107,14 @@ enum dce110_opp_reg_type { - SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \ - SRI(CONTROL, FMT_MEMORY, id) - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#define OPP_DCE_120_REG_LIST(id) \ -+ OPP_COMMON_REG_LIST_BASE(id), \ -+ SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ -+ SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ -+ SRI(CONTROL, FMT_MEMORY, id) -+#endif -+ - #define OPP_SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix - -@@ -197,6 +205,70 @@ enum dce110_opp_reg_type { - OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ - OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ -+ OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ -+ OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ -+ OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ -+ OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ -+ OPP_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ -+ OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ -+ OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ -+ OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ -+ OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ -+ OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ -+ OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ -+ OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ -+ OPP_SF(DCFE0_DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ -+ OPP_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ -+ OPP_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ -+ OPP_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ -+ OPP_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ -+ OPP_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ -+ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ -+ OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ -+ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ -+ OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ -+ OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ -+ OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ -+ OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ -+ OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ -+ OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ -+ OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ -+ OPP_SF(FMT0_FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ -+ OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ -+ OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ -+ OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ -+ OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ -+ OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ -+ OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ -+ OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ -+ OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ -+ OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ -+ OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ -+ OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ -+ OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ -+ OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\ -+ OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh) -+#endif -+ - #define OPP_REG_FIELD_LIST(type) \ - type DCP_REGAMMA_MEM_PWR_DIS; \ - type DCP_LUT_MEM_PWR_DIS; \ -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h -index 458a370..c784c1b 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h -@@ -187,6 +187,91 @@ - #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\ - SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\ -+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\ -+ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\ -+ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\ -+ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\ -+ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\ -+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ -+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ -+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\ -+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ -+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ -+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\ -+ SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\ -+ SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\ -+ SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\ -+ SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\ -+ SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\ -+ SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\ -+ SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ -+ SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ -+ SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ -+ SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ -+ SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ -+ SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\ -+ SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ -+ SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\ -+ SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\ -+ SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\ -+ SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\ -+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\ -+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ -+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\ -+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\ -+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\ -+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\ -+ SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\ -+ SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ -+ SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\ -+ SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ -+ SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\ -+ SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\ -+ SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\ -+ SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\ -+ SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\ -+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\ -+ SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\ -+ SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\ -+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\ -+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\ -+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\ -+ SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ -+ SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\ -+ SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\ -+ SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\ -+ SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ -+ SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\ -+ SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\ -+ SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ -+ SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\ -+ SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\ -+ SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\ -+ SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\ -+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\ -+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\ -+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\ -+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\ -+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\ -+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\ -+ SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\ -+ SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\ -+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\ -+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\ -+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\ -+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\ -+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\ -+ SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\ -+ SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ -+ SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ -+ SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh) -+#endif -+ -+#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ -+ SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) -+ - #define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\ - SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\ - SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ -@@ -209,6 +294,21 @@ - SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ - SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#define SE_COMMON_MASK_SH_LIST_DCE120(mask_sh)\ -+ SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ -+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\ -+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\ -+ SE_SF(DP0_DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\ -+ SE_SF(DP0_DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\ -+ SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\ -+ SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\ -+ SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\ -+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\ -+ SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\ -+ SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) -+#endif -+ - struct dce_stream_encoder_shift { - uint8_t AFMT_GENERIC_INDEX; - uint8_t AFMT_GENERIC0_UPDATE; -diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h -index b2cf9bf..aa6bc4f 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h -+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h -@@ -153,6 +153,74 @@ - XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ - XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh) - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ -+ XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \ -+ XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \ -+ XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \ -+ XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \ -+ XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \ -+ XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \ -+ XFM_SF(DCP0_OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \ -+ XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \ -+ XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \ -+ XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \ -+ XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \ -+ XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \ -+ XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \ -+ XFM_SF(DCP0_DENORM_CONTROL, DENORM_MODE, mask_sh), \ -+ XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \ -+ XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \ -+ XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \ -+ XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \ -+ XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \ -+ XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \ -+ XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \ -+ XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \ -+ XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \ -+ XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \ -+ XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \ -+ XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \ -+ XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ -+ XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ -+ XFM_SF(DCP0_GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ -+ XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \ -+ XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ -+ XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ -+ XFM_SF(SCL0_SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \ -+ XFM_SF(SCL0_SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \ -+ XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \ -+ XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \ -+ XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \ -+ XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \ -+ XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \ -+ XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \ -+ XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \ -+ XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \ -+ XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \ -+ XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \ -+ XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \ -+ XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_X_START, mask_sh), \ -+ XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \ -+ XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \ -+ XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \ -+ XFM_SF(SCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \ -+ XFM_SF(SCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \ -+ XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \ -+ XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \ -+ XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \ -+ XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \ -+ XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \ -+ XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \ -+ XFM_SF(SCL0_SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \ -+ XFM_SF(SCL0_SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \ -+ XFM_SF(SCL0_SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \ -+ XFM_SF(LB0_LB_DATA_FORMAT, ALPHA_EN, mask_sh), \ -+ XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ -+ XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ -+ XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh) -+#endif -+ - #define XFM_REG_FIELD_LIST(type) \ - type OUT_CLAMP_MIN_B_CB; \ - type OUT_CLAMP_MAX_B_CB; \ -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c -index 041830e..66d5f34 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c -@@ -1396,9 +1396,12 @@ static uint32_t get_max_pixel_clock_for_all_paths( - return max_pix_clk; - } - --/* -- * Find clock state based on clock requested. if clock value is 0, simply -+/* Find clock state based on clock requested. if clock value is 0, simply - * set clock state as requested without finding clock state by clock value -+ *TODO: when dce120_hw_sequencer.c is created, override apply_min_clock. -+ * -+ * TODOFPGA remove TODO after implement dal_display_clock_get_cur_clocks_value -+ * etc support for dcn1.0 - */ - static void apply_min_clocks( - struct core_dc *dc, -@@ -1425,6 +1428,30 @@ static void apply_min_clocks( - } - - /* TODOFPGA */ -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ /* TODO: This is incorrect. Figure out how to fix. */ -+ pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( -+ pipe_ctx->dis_clk, -+ DM_PP_CLOCK_TYPE_DISPLAY_CLK, -+ pipe_ctx->dis_clk->cur_clocks_value.dispclk_in_khz, -+ pre_mode_set, -+ false); -+ -+ pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( -+ pipe_ctx->dis_clk, -+ DM_PP_CLOCK_TYPE_PIXELCLK, -+ pipe_ctx->dis_clk->cur_clocks_value.max_pixelclk_in_khz, -+ pre_mode_set, -+ false); -+ -+ pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( -+ pipe_ctx->dis_clk, -+ DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, -+ pipe_ctx->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz, -+ pre_mode_set, -+ false); -+ return; -+#endif - } - - /* get the required state based on state dependent clocks: -@@ -1441,6 +1468,28 @@ static void apply_min_clocks( - pipe_ctx->dis_clk->funcs->set_min_clocks_state( - pipe_ctx->dis_clk, *clocks_state); - } else { -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( -+ pipe_ctx->dis_clk, -+ DM_PP_CLOCK_TYPE_DISPLAY_CLK, -+ req_clocks.display_clk_khz, -+ pre_mode_set, -+ false); -+ -+ pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( -+ pipe_ctx->dis_clk, -+ DM_PP_CLOCK_TYPE_PIXELCLK, -+ req_clocks.pixel_clk_khz, -+ pre_mode_set, -+ false); -+ -+ pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( -+ pipe_ctx->dis_clk, -+ DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, -+ req_clocks.pixel_clk_khz, -+ pre_mode_set, -+ false); -+#endif - } - } - -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c -index 1643fb5..3ffb845f 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c -+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c -@@ -409,6 +409,9 @@ static struct mem_input_funcs dce110_mem_input_funcs = { - dce_mem_input_program_surface_config, - .mem_input_is_flip_pending = - dce110_mem_input_is_flip_pending, -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ .mem_input_update_dchub = NULL -+#endif - }; - /*****************************************/ - /* Constructor, Destructor */ -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h -index dcb49fe..55f0a94 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h -+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h -@@ -108,6 +108,9 @@ struct dce110_timing_generator { - uint32_t min_h_front_porch; - uint32_t min_h_back_porch; - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ /* DCE 12 */ -+#endif - uint32_t min_h_sync_width; - uint32_t min_v_sync_width; - uint32_t min_v_blank; -diff --git a/drivers/gpu/drm/amd/display/dc/dce120/Makefile b/drivers/gpu/drm/amd/display/dc/dce120/Makefile -new file mode 100644 -index 0000000..3c6b3fa ---- /dev/null -+++ b/drivers/gpu/drm/amd/display/dc/dce120/Makefile -@@ -0,0 +1,12 @@ -+# -+# Makefile for the 'controller' sub-component of DAL. -+# It provides the control and status of HW CRTC block. -+ -+ -+DCE120 = dce120_resource.o dce120_timing_generator.o \ -+dce120_ipp.o dce120_ipp_cursor.o dce120_ipp_gamma.o \ -+dce120_mem_input.o dce120_hw_sequencer.o -+ -+AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120)) -+ -+AMD_DISPLAY_FILES += $(AMD_DAL_DCE120) -\ No newline at end of file -diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c -index 704a7ce..2f22931 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c -+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c -@@ -54,6 +54,9 @@ static struct mem_input_funcs dce80_mem_input_funcs = { - dce_mem_input_program_surface_config, - .mem_input_is_flip_pending = - dce110_mem_input_is_flip_pending, -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ .mem_input_update_dchub = NULL -+#endif - }; - - /*****************************************/ -diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h -index 73c0f1f..bdc7cb0 100644 ---- a/drivers/gpu/drm/amd/display/dc/dm_services.h -+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h -@@ -192,6 +192,89 @@ unsigned int generic_reg_wait(const struct dc_context *ctx, - unsigned int delay_between_poll_us, unsigned int time_out_num_tries, - const char *func_name); - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ -+/* These macros need to be used with soc15 registers in order to retrieve -+ * the actual offset. -+ */ -+#define REG_OFFSET(reg) (reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX]) -+#define REG_BIF_OFFSET(reg) (reg + NBIF_BASE.instance[0].segment[reg##_BASE_IDX]) -+ -+#define dm_write_reg_soc15(ctx, reg, inst_offset, value) \ -+ dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__) -+ -+#define dm_read_reg_soc15(ctx, reg, inst_offset) \ -+ dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__) -+ -+#define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ -+ generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \ -+ dm_read_reg_func(ctx, mm##reg_name + DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + inst_offset, __func__), \ -+ n, __VA_ARGS__) -+ -+#define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ -+ generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \ -+ n, __VA_ARGS__) -+ -+#define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ -+ get_reg_field_value_ex(\ -+ (reg_value),\ -+ block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ -+ block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) -+ -+#define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ -+ (reg_value) = set_reg_field_value_ex(\ -+ (reg_value),\ -+ (value),\ -+ block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ -+ block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) -+ -+/* TODO get rid of this pos*/ -+static inline bool wait_reg_func( -+ const struct dc_context *ctx, -+ uint32_t addr, -+ uint32_t mask, -+ uint8_t shift, -+ uint32_t condition_value, -+ unsigned int interval_us, -+ unsigned int timeout_us) -+{ -+ uint32_t field_value; -+ uint32_t reg_val; -+ unsigned int count = 0; -+ -+ if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) -+ timeout_us *= 655; /* 6553 give about 30 second before time out */ -+ -+ do { -+ /* try once without sleeping */ -+ if (count > 0) { -+ if (interval_us >= 1000) -+ msleep(interval_us/1000); -+ else -+ udelay(interval_us); -+ } -+ reg_val = dm_read_reg(ctx, addr); -+ field_value = get_reg_field_value_ex(reg_val, mask, shift); -+ count += interval_us; -+ -+ } while (field_value != condition_value && count <= timeout_us); -+ -+ ASSERT(count <= timeout_us); -+ -+ return count <= timeout_us; -+} -+ -+#define wait_reg(ctx, inst_offset, reg_name, reg_field, condition_value)\ -+ wait_reg_func(\ -+ ctx,\ -+ mm##reg_name + inst_offset + DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX],\ -+ reg_name ## __ ## reg_field ## _MASK,\ -+ reg_name ## __ ## reg_field ## __SHIFT,\ -+ condition_value,\ -+ 20000,\ -+ 200000) -+ -+#endif - /************************************** - * Power Play (PP) interfaces - **************************************/ -@@ -254,6 +337,12 @@ bool dm_pp_notify_wm_clock_changes( - const struct dc_context *ctx, - struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges); - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+bool dm_pp_notify_wm_clock_changes_soc15( -+ const struct dc_context *ctx, -+ struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); -+#endif -+ - /* DAL calls this function to notify PP about completion of Mode Set. - * For PP it means that current DCE clocks are those which were returned - * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter. -diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h -index 460971d..8d26615 100644 ---- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h -+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h -@@ -141,6 +141,33 @@ struct dm_pp_wm_sets_with_clock_ranges { - struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS]; - }; - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+struct dm_pp_clock_range_for_dmif_wm_set_soc15 { -+ enum dm_pp_wm_set_id wm_set_id; -+ uint32_t wm_min_dcfclk_clk_in_khz; -+ uint32_t wm_max_dcfclk_clk_in_khz; -+ uint32_t wm_min_memg_clk_in_khz; -+ uint32_t wm_max_mem_clk_in_khz; -+}; -+ -+struct dm_pp_clock_range_for_mcif_wm_set_soc15 { -+ enum dm_pp_wm_set_id wm_set_id; -+ uint32_t wm_min_socclk_clk_in_khz; -+ uint32_t wm_max_socclk_clk_in_khz; -+ uint32_t wm_min_memg_clk_in_khz; -+ uint32_t wm_max_mem_clk_in_khz; -+}; -+ -+struct dm_pp_wm_sets_with_clock_ranges_soc15 { -+ uint32_t num_wm_dmif_sets; -+ uint32_t num_wm_mcif_sets; -+ struct dm_pp_clock_range_for_dmif_wm_set_soc15 -+ wm_dmif_clocks_ranges[MAX_WM_SETS]; -+ struct dm_pp_clock_range_for_mcif_wm_set_soc15 -+ wm_mcif_clocks_ranges[MAX_WM_SETS]; -+}; -+#endif -+ - #define MAX_DISPLAY_CONFIGS 6 - - struct dm_pp_display_configuration { -diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile -index a15c257..8cf12a8 100644 ---- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile -+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile -@@ -29,6 +29,17 @@ AMD_DAL_GPIO_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpio/dce110/,$(GPIO_DCE110)) - AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE110) - - ############################################################################### -+# DCE 12x -+############################################################################### -+ifdef CONFIG_DRM_AMD_DC_DCE12_0 -+GPIO_DCE120 = hw_translate_dce120.o hw_factory_dce120.o -+ -+AMD_DAL_GPIO_DCE120 = $(addprefix $(AMDDALPATH)/dc/gpio/dce120/,$(GPIO_DCE120)) -+ -+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120) -+endif -+ -+############################################################################### - # Diagnostics on FPGA - ############################################################################### - GPIO_DIAG_FPGA = hw_translate_diag.o hw_factory_diag.o -diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c -index f1a6fa7..66ea3b3 100644 ---- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c -+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c -@@ -44,6 +44,10 @@ - - #include "dce110/hw_factory_dce110.h" - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#include "dce120/hw_factory_dce120.h" -+#endif -+ - #include "diagnostics/hw_factory_diag.h" - - /* -@@ -72,6 +76,11 @@ bool dal_hw_factory_init( - case DCE_VERSION_11_2: - dal_hw_factory_dce110_init(factory); - return true; -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ case DCE_VERSION_12_0: -+ dal_hw_factory_dce120_init(factory); -+ return true; -+#endif - default: - ASSERT_CRITICAL(false); - return false; -diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c -index 23e097f..10e8644 100644 ---- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c -+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c -@@ -42,7 +42,9 @@ - - #include "dce80/hw_translate_dce80.h" - #include "dce110/hw_translate_dce110.h" -- -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#include "dce120/hw_translate_dce120.h" -+#endif - #include "diagnostics/hw_translate_diag.h" - - /* -@@ -68,6 +70,11 @@ bool dal_hw_translate_init( - case DCE_VERSION_11_2: - dal_hw_translate_dce110_init(translate); - return true; -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ case DCE_VERSION_12_0: -+ dal_hw_translate_dce120_init(translate); -+ return true; -+#endif - default: - BREAK_TO_DEBUGGER(); - return false; -diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile -index 83dfc43..99aa5d8 100644 ---- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile -+++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile -@@ -48,6 +48,17 @@ AMD_DAL_I2CAUX_DCE112 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce112/,$(I2CAUX_DCE - AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112) - - ############################################################################### -+# DCE 120 family -+############################################################################### -+ifdef CONFIG_DRM_AMD_DC_DCE12_0 -+I2CAUX_DCE120 = i2caux_dce120.o -+ -+AMD_DAL_I2CAUX_DCE120 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce120/,$(I2CAUX_DCE120)) -+ -+AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE120) -+endif -+ -+############################################################################### - # Diagnostics on FPGA - ############################################################################### - I2CAUX_DIAG = i2caux_diag.o -diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c -index 5391655..ea3bd75 100644 ---- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c -+++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c -@@ -57,6 +57,10 @@ - - #include "dce112/i2caux_dce112.h" - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#include "dce120/i2caux_dce120.h" -+#endif -+ - #include "diagnostics/i2caux_diag.h" - - /* -@@ -80,6 +84,10 @@ struct i2caux *dal_i2caux_create( - return dal_i2caux_dce110_create(ctx); - case DCE_VERSION_10_0: - return dal_i2caux_dce100_create(ctx); -+ #if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ case DCE_VERSION_12_0: -+ return dal_i2caux_dce120_create(ctx); -+ #endif - default: - BREAK_TO_DEBUGGER(); - return NULL; -diff --git a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h -index 16f06fa..a7eaecd 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h -@@ -40,6 +40,9 @@ enum bw_calcs_version { - BW_CALCS_VERSION_POLARIS10, - BW_CALCS_VERSION_POLARIS11, - BW_CALCS_VERSION_STONEY, -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ BW_CALCS_VERSION_VEGA10 -+#endif - }; - - /******************************************************************************* -diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h -index e163f58..bf77aa6 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h -@@ -28,6 +28,18 @@ - - #include "dm_services_types.h" - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+struct clocks_value { -+ int dispclk_in_khz; -+ int max_pixelclk_in_khz; -+ int max_non_dp_phyclk_in_khz; -+ int max_dp_phyclk_in_khz; -+ bool dispclk_notify_pplib_done; -+ bool pixelclk_notify_pplib_done; -+ bool phyclk_notigy_pplib_done; -+}; -+#endif -+ - /* Structure containing all state-dependent clocks - * (dependent on "enum clocks_state") */ - struct state_dependent_clocks { -@@ -41,6 +53,9 @@ struct display_clock { - - enum dm_pp_clocks_state max_clks_state; - enum dm_pp_clocks_state cur_min_clks_state; -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ struct clocks_value cur_clocks_value; -+#endif - }; - - struct display_clock_funcs { -@@ -56,6 +71,14 @@ struct display_clock_funcs { - - int (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk); - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ bool (*apply_clock_voltage_request)( -+ struct display_clock *disp_clk, -+ enum dm_pp_clock_type clocks_type, -+ int clocks_in_khz, -+ bool pre_mode_set, -+ bool update_dp_phyclk); -+#endif - }; - - #endif /* __DISPLAY_CLOCK_H__ */ -diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h -index ed980ae..6c06006 100644 ---- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h -+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h -@@ -100,6 +100,10 @@ struct mem_input_funcs { - - bool (*mem_input_is_flip_pending)(struct mem_input *mem_input); - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ void (*mem_input_update_dchub)(struct mem_input *mem_input, -+ struct dchub_init_data *dh_data); -+#endif - }; - - #endif -diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile -index 0271033..140e498 100644 ---- a/drivers/gpu/drm/amd/display/dc/irq/Makefile -+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile -@@ -26,3 +26,15 @@ IRQ_DCE11 = irq_service_dce110.o - AMD_DAL_IRQ_DCE11 = $(addprefix $(AMDDALPATH)/dc/irq/dce110/,$(IRQ_DCE11)) - - AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE11) -+ -+############################################################################### -+# DCE 12x -+############################################################################### -+ifdef CONFIG_DRM_AMD_DC_DCE12_0 -+IRQ_DCE12 = irq_service_dce120.o -+ -+AMD_DAL_IRQ_DCE12 = $(addprefix $(AMDDALPATH)/dc/irq/dce120/,$(IRQ_DCE12)) -+ -+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12) -+endif -+ -diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c -index fbaa2fc..a1b6d83 100644 ---- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c -+++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c -@@ -33,6 +33,9 @@ - - #include "dce80/irq_service_dce80.h" - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#include "dce120/irq_service_dce120.h" -+#endif - - #include "reg_helper.h" - #include "irq_service.h" -diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h -index 46f1e88..15c0b8c 100644 ---- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h -+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h -@@ -123,6 +123,10 @@ - #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */ - #define FAMILY_CZ 135 /* Carrizo */ - -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+#define FAMILY_AI 141 -+#endif -+ - #define FAMILY_UNKNOWN 0xFF - - #endif /* __DAL_ASIC_ID_H__ */ -diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h -index ada5b19..e24c1ef 100644 ---- a/drivers/gpu/drm/amd/display/include/dal_types.h -+++ b/drivers/gpu/drm/amd/display/include/dal_types.h -@@ -38,6 +38,9 @@ enum dce_version { - DCE_VERSION_10_0, - DCE_VERSION_11_0, - DCE_VERSION_11_2, -+#if defined(CONFIG_DRM_AMD_DC_DCE12_0) -+ DCE_VERSION_12_0, -+#endif - DCE_VERSION_MAX, - }; - --- -2.7.4 - |