diff options
Diffstat (limited to 'meta-steppeeagle/recipes-kernel/linux/linux-yocto/0042-yocto-amd-drm-radeon-cik-enable-disable-vce-cg-when-encoding.patch')
| -rw-r--r-- | meta-steppeeagle/recipes-kernel/linux/linux-yocto/0042-yocto-amd-drm-radeon-cik-enable-disable-vce-cg-when-encoding.patch | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0042-yocto-amd-drm-radeon-cik-enable-disable-vce-cg-when-encoding.patch b/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0042-yocto-amd-drm-radeon-cik-enable-disable-vce-cg-when-encoding.patch new file mode 100644 index 00000000..b9b96338 --- /dev/null +++ b/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0042-yocto-amd-drm-radeon-cik-enable-disable-vce-cg-when-encoding.patch @@ -0,0 +1,90 @@ +From c37b6e8a309e0256e0380984ce293594efea71ba Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 6 Sep 2013 12:33:04 -0400 +Subject: [PATCH 42/44] drm/radeon/cik: enable/disable vce cg when encoding + +Some of the vce clocks are automatic, others need to +be manually enabled. For ease, just disable cg when +vce is active. + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/radeon/ci_dpm.c | 7 ++++++- + drivers/gpu/drm/radeon/cik.c | 5 +++++ + drivers/gpu/drm/radeon/kv_dpm.c | 4 ++++ + 3 files changed, 15 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c +index a6a2396..14f7192 100644 +--- a/drivers/gpu/drm/radeon/ci_dpm.c ++++ b/drivers/gpu/drm/radeon/ci_dpm.c +@@ -3598,8 +3598,10 @@ static int ci_update_vce_dpm(struct radeon_device *rdev, + + if (radeon_current_state->evclk != radeon_new_state->evclk) { + if (radeon_new_state->evclk) { +- pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); ++ /* turn the clocks on when encoding */ ++ cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false); + ++ pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); + tmp = RREG32_SMC(DPM_TABLE_475); + tmp &= ~VceBootLevel_MASK; + tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); +@@ -3607,6 +3609,9 @@ static int ci_update_vce_dpm(struct radeon_device *rdev, + + ret = ci_enable_vce_dpm(rdev, true); + } else { ++ /* turn the clocks off when not encoding */ ++ cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true); ++ + ret = ci_enable_vce_dpm(rdev, false); + } + } +diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c +index 9af1f3f..5635f04 100644 +--- a/drivers/gpu/drm/radeon/cik.c ++++ b/drivers/gpu/drm/radeon/cik.c +@@ -72,6 +72,7 @@ extern void cik_sdma_vm_set_page(struct radeon_device *rdev, + uint64_t pe, + uint64_t addr, unsigned count, + uint32_t incr, uint32_t flags); ++extern void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable); + static void cik_rlc_stop(struct radeon_device *rdev); + static void cik_pcie_gen3_enable(struct radeon_device *rdev); + static void cik_program_aspm(struct radeon_device *rdev); +@@ -5409,6 +5410,10 @@ void cik_update_cg(struct radeon_device *rdev, + cik_enable_hdp_mgcg(rdev, enable); + cik_enable_hdp_ls(rdev, enable); + } ++ ++ if (block & RADEON_CG_BLOCK_VCE) { ++ vce_v2_0_enable_mgcg(rdev, enable); ++ } + } + + static void cik_init_cg(struct radeon_device *rdev) +diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c +index c8b9d7b..a100b23 100644 +--- a/drivers/gpu/drm/radeon/kv_dpm.c ++++ b/drivers/gpu/drm/radeon/kv_dpm.c +@@ -1420,6 +1420,8 @@ static int kv_update_vce_dpm(struct radeon_device *rdev, + + if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) { + kv_dpm_powergate_vce(rdev, false); ++ /* turn the clocks on when encoding */ ++ cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false); + if (pi->caps_stable_p_state) + pi->vce_boot_level = table->count - 1; + else +@@ -1442,6 +1444,8 @@ static int kv_update_vce_dpm(struct radeon_device *rdev, + kv_enable_vce_dpm(rdev, true); + } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) { + kv_enable_vce_dpm(rdev, false); ++ /* turn the clocks off when not encoding */ ++ cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true); + kv_dpm_powergate_vce(rdev, true); + } + +-- +1.7.9.5 + |