diff options
Diffstat (limited to 'meta-steppeeagle/recipes-kernel/linux/linux-yocto/0034-yocto-amd-drm-radeon-fill-in-set_vce_clocks-for-CIK-asics.patch')
| -rw-r--r-- | meta-steppeeagle/recipes-kernel/linux/linux-yocto/0034-yocto-amd-drm-radeon-fill-in-set_vce_clocks-for-CIK-asics.patch | 111 |
1 files changed, 111 insertions, 0 deletions
diff --git a/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0034-yocto-amd-drm-radeon-fill-in-set_vce_clocks-for-CIK-asics.patch b/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0034-yocto-amd-drm-radeon-fill-in-set_vce_clocks-for-CIK-asics.patch new file mode 100644 index 00000000..d4669a9f --- /dev/null +++ b/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0034-yocto-amd-drm-radeon-fill-in-set_vce_clocks-for-CIK-asics.patch @@ -0,0 +1,111 @@ +From bfe1cb3c1990b0e7a80ffe5563c86d52292b1565 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 22 Aug 2013 17:09:06 -0400 +Subject: [PATCH 34/44] drm/radeon: fill in set_vce_clocks for CIK asics + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/radeon/cik.c | 35 ++++++++++++++++++++++++++++++++++ + drivers/gpu/drm/radeon/cikd.h | 6 ++++++ + drivers/gpu/drm/radeon/radeon_asic.c | 2 ++ + drivers/gpu/drm/radeon/radeon_asic.h | 1 + + 4 files changed, 44 insertions(+) + +diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c +index 872b146..9af1f3f 100644 +--- a/drivers/gpu/drm/radeon/cik.c ++++ b/drivers/gpu/drm/radeon/cik.c +@@ -8115,6 +8115,41 @@ int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) + return r; + } + ++int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) ++{ ++ int r, i; ++ struct atom_clock_dividers dividers; ++ u32 tmp; ++ ++ r = radeon_atom_get_clock_dividers(rdev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, ++ ecclk, false, ÷rs); ++ if (r) ++ return r; ++ ++ for (i = 0; i < 100; i++) { ++ if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) ++ break; ++ mdelay(10); ++ } ++ if (i == 100) ++ return -ETIMEDOUT; ++ ++ tmp = RREG32_SMC(CG_ECLK_CNTL); ++ tmp &= ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK); ++ tmp |= dividers.post_divider; ++ WREG32_SMC(CG_ECLK_CNTL, tmp); ++ ++ for (i = 0; i < 100; i++) { ++ if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) ++ break; ++ mdelay(10); ++ } ++ if (i == 100) ++ return -ETIMEDOUT; ++ ++ return 0; ++} ++ + static void cik_pcie_gen3_enable(struct radeon_device *rdev) + { + struct pci_dev *root = rdev->pdev->bus->self; +diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h +index b296d50..3224176 100644 +--- a/drivers/gpu/drm/radeon/cikd.h ++++ b/drivers/gpu/drm/radeon/cikd.h +@@ -201,6 +201,12 @@ + #define CTF_TEMP_MASK 0x0003fe00 + #define CTF_TEMP_SHIFT 9 + ++#define CG_ECLK_CNTL 0xC05000AC ++# define ECLK_DIVIDER_MASK 0x7f ++# define ECLK_DIR_CNTL_EN (1 << 8) ++#define CG_ECLK_STATUS 0xC05000B0 ++# define ECLK_STATUS (1 << 0) ++ + #define CG_SPLL_FUNC_CNTL 0xC0500140 + #define SPLL_RESET (1 << 0) + #define SPLL_PWRON (1 << 1) +diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c +index 763280b..19b2eea 100644 +--- a/drivers/gpu/drm/radeon/radeon_asic.c ++++ b/drivers/gpu/drm/radeon/radeon_asic.c +@@ -2067,6 +2067,7 @@ static struct radeon_asic ci_asic = { + .set_pcie_lanes = NULL, + .set_clock_gating = NULL, + .set_uvd_clocks = &cik_set_uvd_clocks, ++ .set_vce_clocks = &cik_set_vce_clocks, + .get_temperature = &ci_get_temp, + }, + .dpm = { +@@ -2170,6 +2171,7 @@ static struct radeon_asic kv_asic = { + .set_pcie_lanes = NULL, + .set_clock_gating = NULL, + .set_uvd_clocks = &cik_set_uvd_clocks, ++ .set_vce_clocks = &cik_set_vce_clocks, + .get_temperature = &kv_get_temp, + }, + .dpm = { +diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h +index a6c3eeb..900ffd7 100644 +--- a/drivers/gpu/drm/radeon/radeon_asic.h ++++ b/drivers/gpu/drm/radeon/radeon_asic.h +@@ -710,6 +710,7 @@ u32 cik_get_xclk(struct radeon_device *rdev); + uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); + void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); + int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); ++int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); + void cik_sdma_fence_ring_emit(struct radeon_device *rdev, + struct radeon_fence *fence); + bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, +-- +1.7.9.5 + |