diff options
Diffstat (limited to 'meta-steppeeagle/recipes-kernel/linux/linux-yocto/0026-yocto-amd-drm-radeon-remove-generic-rptr-wptr-functions-v2.patch')
| -rw-r--r-- | meta-steppeeagle/recipes-kernel/linux/linux-yocto/0026-yocto-amd-drm-radeon-remove-generic-rptr-wptr-functions-v2.patch | 1049 |
1 files changed, 1049 insertions, 0 deletions
diff --git a/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0026-yocto-amd-drm-radeon-remove-generic-rptr-wptr-functions-v2.patch b/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0026-yocto-amd-drm-radeon-remove-generic-rptr-wptr-functions-v2.patch new file mode 100644 index 00000000..628a3230 --- /dev/null +++ b/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0026-yocto-amd-drm-radeon-remove-generic-rptr-wptr-functions-v2.patch @@ -0,0 +1,1049 @@ +From 3f033c032e0fd56dd58707405c037800f0f6fe90 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Tue, 10 Dec 2013 00:44:30 +0000 +Subject: [PATCH 26/44] drm/radeon: remove generic rptr/wptr functions (v2) + +Fill in asic family specific versions rather than +using the generic version. This lets us handle asic +specific differences more easily. In this case, we +disable sw swapping of the rtpr writeback value on +r6xx+ since the hw does it for us. Fixes bogus +rptr readback on BE systems. + +v2: remove missed cpu_to_le32(), add comments + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/radeon/cik.c | 58 +++++++++++++++++++--------- + drivers/gpu/drm/radeon/cik_sdma.c | 69 ++++++++++++++++++++++++++++++++++ + drivers/gpu/drm/radeon/evergreen.c | 3 -- + drivers/gpu/drm/radeon/ni.c | 69 ++++++++++++++++++++++++++++++---- + drivers/gpu/drm/radeon/ni_dma.c | 69 ++++++++++++++++++++++++++++++++++ + drivers/gpu/drm/radeon/r100.c | 31 ++++++++++++++- + drivers/gpu/drm/radeon/r600.c | 32 +++++++++++++++- + drivers/gpu/drm/radeon/r600_dma.c | 13 +++++-- + drivers/gpu/drm/radeon/radeon.h | 4 +- + drivers/gpu/drm/radeon/radeon_asic.c | 66 ++++++++++++++++---------------- + drivers/gpu/drm/radeon/radeon_asic.h | 57 +++++++++++++++++++++------- + drivers/gpu/drm/radeon/radeon_ring.c | 44 +++------------------- + drivers/gpu/drm/radeon/rv770.c | 3 -- + drivers/gpu/drm/radeon/si.c | 8 ---- + 14 files changed, 392 insertions(+), 134 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c +index 5419abe..4a89b5c 100644 +--- a/drivers/gpu/drm/radeon/cik.c ++++ b/drivers/gpu/drm/radeon/cik.c +@@ -3461,15 +3461,43 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev) + return 0; + } + +-u32 cik_compute_ring_get_rptr(struct radeon_device *rdev, +- struct radeon_ring *ring) ++u32 cik_gfx_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) + { + u32 rptr; + ++ if (rdev->wb.enabled) ++ rptr = rdev->wb.wb[ring->rptr_offs/4]; ++ else ++ rptr = RREG32(CP_RB0_RPTR); ++ ++ return rptr; ++} + ++u32 cik_gfx_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 wptr; ++ ++ wptr = RREG32(CP_RB0_WPTR); ++ ++ return wptr; ++} ++ ++void cik_gfx_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ WREG32(CP_RB0_WPTR, ring->wptr); ++ (void)RREG32(CP_RB0_WPTR); ++} ++ ++u32 cik_compute_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 rptr; + + if (rdev->wb.enabled) { +- rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); ++ rptr = rdev->wb.wb[ring->rptr_offs/4]; + } else { + mutex_lock(&rdev->srbm_mutex); + cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); +@@ -3481,13 +3509,14 @@ u32 cik_compute_ring_get_rptr(struct radeon_device *rdev, + return rptr; + } + +-u32 cik_compute_ring_get_wptr(struct radeon_device *rdev, +- struct radeon_ring *ring) ++u32 cik_compute_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) + { + u32 wptr; + + if (rdev->wb.enabled) { +- wptr = le32_to_cpu(rdev->wb.wb[ring->wptr_offs/4]); ++ /* XXX check if swapping is necessary on BE */ ++ wptr = rdev->wb.wb[ring->wptr_offs/4]; + } else { + mutex_lock(&rdev->srbm_mutex); + cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); +@@ -3499,10 +3528,11 @@ u32 cik_compute_ring_get_wptr(struct radeon_device *rdev, + return wptr; + } + +-void cik_compute_ring_set_wptr(struct radeon_device *rdev, +- struct radeon_ring *ring) ++void cik_compute_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) + { +- rdev->wb.wb[ring->wptr_offs/4] = cpu_to_le32(ring->wptr); ++ /* XXX check if swapping is necessary on BE */ ++ rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; + WDOORBELL32(ring->doorbell_offset, ring->wptr); + } + +@@ -7058,8 +7088,7 @@ static int cik_startup(struct radeon_device *rdev) + + ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, +- CP_RB0_RPTR, CP_RB0_WPTR, +- RADEON_CP_PACKET2); ++ PACKET3(PACKET3_NOP, 0x3FFF)); + if (r) + return r; + +@@ -7067,7 +7096,6 @@ static int cik_startup(struct radeon_device *rdev) + /* type-2 packets are deprecated on MEC, use type-3 instead */ + ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, +- CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR, + PACKET3(PACKET3_NOP, 0x3FFF)); + if (r) + return r; +@@ -7079,7 +7107,6 @@ static int cik_startup(struct radeon_device *rdev) + /* type-2 packets are deprecated on MEC, use type-3 instead */ + ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, +- CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR, + PACKET3(PACKET3_NOP, 0x3FFF)); + if (r) + return r; +@@ -7091,16 +7118,12 @@ static int cik_startup(struct radeon_device *rdev) + + ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, +- SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET, +- SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET, + SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); + if (r) + return r; + + ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, +- SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET, +- SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET, + SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); + if (r) + return r; +@@ -7116,7 +7139,6 @@ static int cik_startup(struct radeon_device *rdev) + ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; + if (ring->ring_size) { + r = radeon_ring_init(rdev, ring, ring->ring_size, 0, +- UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, + RADEON_CP_PACKET2); + if (!r) + r = uvd_v1_0_init(rdev); +diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c +index a589d79..f7c0b47 100644 +--- a/drivers/gpu/drm/radeon/cik_sdma.c ++++ b/drivers/gpu/drm/radeon/cik_sdma.c +@@ -60,6 +60,75 @@ static void cik_sdma_hdp_flush(struct radeon_device *rdev, + } + + /** ++ * cik_sdma_get_rptr - get the current read pointer ++ * ++ * @rdev: radeon_device pointer ++ * @ring: radeon ring pointer ++ * ++ * Get the current rptr from the hardware (CIK+). ++ */ ++uint32_t cik_sdma_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 rptr, reg; ++ ++ if (rdev->wb.enabled) { ++ rptr = rdev->wb.wb[ring->rptr_offs/4]; ++ } else { ++ if (ring->idx == R600_RING_TYPE_DMA_INDEX) ++ reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; ++ else ++ reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; ++ ++ rptr = RREG32(reg); ++ } ++ ++ return (rptr & 0x3fffc) >> 2; ++} ++ ++/** ++ * cik_sdma_get_wptr - get the current write pointer ++ * ++ * @rdev: radeon_device pointer ++ * @ring: radeon ring pointer ++ * ++ * Get the current wptr from the hardware (CIK+). ++ */ ++uint32_t cik_sdma_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 reg; ++ ++ if (ring->idx == R600_RING_TYPE_DMA_INDEX) ++ reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; ++ else ++ reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; ++ ++ return (RREG32(reg) & 0x3fffc) >> 2; ++} ++ ++/** ++ * cik_sdma_set_wptr - commit the write pointer ++ * ++ * @rdev: radeon_device pointer ++ * @ring: radeon ring pointer ++ * ++ * Write the wptr back to the hardware (CIK+). ++ */ ++void cik_sdma_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 reg; ++ ++ if (ring->idx == R600_RING_TYPE_DMA_INDEX) ++ reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; ++ else ++ reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; ++ ++ WREG32(reg, (ring->wptr << 2) & 0x3fffc); ++} ++ ++/** + * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine + * + * @rdev: radeon_device pointer +diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c +index b5c67a9..491d048 100644 +--- a/drivers/gpu/drm/radeon/evergreen.c ++++ b/drivers/gpu/drm/radeon/evergreen.c +@@ -5150,14 +5150,12 @@ static int evergreen_startup(struct radeon_device *rdev) + + ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, +- R600_CP_RB_RPTR, R600_CP_RB_WPTR, + RADEON_CP_PACKET2); + if (r) + return r; + + ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, +- DMA_RB_RPTR, DMA_RB_WPTR, + DMA_PACKET(DMA_PACKET_NOP, 0, 0)); + if (r) + return r; +@@ -5175,7 +5173,6 @@ static int evergreen_startup(struct radeon_device *rdev) + ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; + if (ring->ring_size) { + r = radeon_ring_init(rdev, ring, ring->ring_size, 0, +- UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, + RADEON_CP_PACKET2); + if (!r) + r = uvd_v1_0_init(rdev); +diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c +index ce87221..b684fd0 100644 +--- a/drivers/gpu/drm/radeon/ni.c ++++ b/drivers/gpu/drm/radeon/ni.c +@@ -1401,6 +1401,55 @@ static void cayman_cp_enable(struct radeon_device *rdev, bool enable) + } + } + ++u32 cayman_gfx_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 rptr; ++ ++ if (rdev->wb.enabled) ++ rptr = rdev->wb.wb[ring->rptr_offs/4]; ++ else { ++ if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) ++ rptr = RREG32(CP_RB0_RPTR); ++ else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) ++ rptr = RREG32(CP_RB1_RPTR); ++ else ++ rptr = RREG32(CP_RB2_RPTR); ++ } ++ ++ return rptr; ++} ++ ++u32 cayman_gfx_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 wptr; ++ ++ if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) ++ wptr = RREG32(CP_RB0_WPTR); ++ else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) ++ wptr = RREG32(CP_RB1_WPTR); ++ else ++ wptr = RREG32(CP_RB2_WPTR); ++ ++ return wptr; ++} ++ ++void cayman_gfx_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) { ++ WREG32(CP_RB0_WPTR, ring->wptr); ++ (void)RREG32(CP_RB0_WPTR); ++ } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) { ++ WREG32(CP_RB1_WPTR, ring->wptr); ++ (void)RREG32(CP_RB1_WPTR); ++ } else { ++ WREG32(CP_RB2_WPTR, ring->wptr); ++ (void)RREG32(CP_RB2_WPTR); ++ } ++} ++ + static int cayman_cp_load_microcode(struct radeon_device *rdev) + { + const __be32 *fw_data; +@@ -1529,6 +1578,16 @@ static int cayman_cp_resume(struct radeon_device *rdev) + CP_RB1_BASE, + CP_RB2_BASE + }; ++ static const unsigned cp_rb_rptr[] = { ++ CP_RB0_RPTR, ++ CP_RB1_RPTR, ++ CP_RB2_RPTR ++ }; ++ static const unsigned cp_rb_wptr[] = { ++ CP_RB0_WPTR, ++ CP_RB1_WPTR, ++ CP_RB2_WPTR ++ }; + struct radeon_ring *ring; + int i, r; + +@@ -1587,8 +1646,8 @@ static int cayman_cp_resume(struct radeon_device *rdev) + WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); + + ring->rptr = ring->wptr = 0; +- WREG32(ring->rptr_reg, ring->rptr); +- WREG32(ring->wptr_reg, ring->wptr); ++ WREG32(cp_rb_rptr[i], ring->rptr); ++ WREG32(cp_rb_wptr[i], ring->wptr); + + mdelay(1); + WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); +@@ -1984,23 +2043,18 @@ static int cayman_startup(struct radeon_device *rdev) + evergreen_irq_set(rdev); + + r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, +- CP_RB0_RPTR, CP_RB0_WPTR, + RADEON_CP_PACKET2); + if (r) + return r; + + ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, +- DMA_RB_RPTR + DMA0_REGISTER_OFFSET, +- DMA_RB_WPTR + DMA0_REGISTER_OFFSET, + DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); + if (r) + return r; + + ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, +- DMA_RB_RPTR + DMA1_REGISTER_OFFSET, +- DMA_RB_WPTR + DMA1_REGISTER_OFFSET, + DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); + if (r) + return r; +@@ -2019,7 +2073,6 @@ static int cayman_startup(struct radeon_device *rdev) + ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; + if (ring->ring_size) { + r = radeon_ring_init(rdev, ring, ring->ring_size, 0, +- UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, + RADEON_CP_PACKET2); + if (!r) + r = uvd_v1_0_init(rdev); +diff --git a/drivers/gpu/drm/radeon/ni_dma.c b/drivers/gpu/drm/radeon/ni_dma.c +index bdeb65e..51424ab 100644 +--- a/drivers/gpu/drm/radeon/ni_dma.c ++++ b/drivers/gpu/drm/radeon/ni_dma.c +@@ -43,6 +43,75 @@ u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev); + */ + + /** ++ * cayman_dma_get_rptr - get the current read pointer ++ * ++ * @rdev: radeon_device pointer ++ * @ring: radeon ring pointer ++ * ++ * Get the current rptr from the hardware (cayman+). ++ */ ++uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 rptr, reg; ++ ++ if (rdev->wb.enabled) { ++ rptr = rdev->wb.wb[ring->rptr_offs/4]; ++ } else { ++ if (ring->idx == R600_RING_TYPE_DMA_INDEX) ++ reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET; ++ else ++ reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET; ++ ++ rptr = RREG32(reg); ++ } ++ ++ return (rptr & 0x3fffc) >> 2; ++} ++ ++/** ++ * cayman_dma_get_wptr - get the current write pointer ++ * ++ * @rdev: radeon_device pointer ++ * @ring: radeon ring pointer ++ * ++ * Get the current wptr from the hardware (cayman+). ++ */ ++uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 reg; ++ ++ if (ring->idx == R600_RING_TYPE_DMA_INDEX) ++ reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; ++ else ++ reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; ++ ++ return (RREG32(reg) & 0x3fffc) >> 2; ++} ++ ++/** ++ * cayman_dma_set_wptr - commit the write pointer ++ * ++ * @rdev: radeon_device pointer ++ * @ring: radeon ring pointer ++ * ++ * Write the wptr back to the hardware (cayman+). ++ */ ++void cayman_dma_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 reg; ++ ++ if (ring->idx == R600_RING_TYPE_DMA_INDEX) ++ reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; ++ else ++ reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; ++ ++ WREG32(reg, (ring->wptr << 2) & 0x3fffc); ++} ++ ++/** + * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine + * + * @rdev: radeon_device pointer +diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c +index aa015a5..39f6984 100644 +--- a/drivers/gpu/drm/radeon/r100.c ++++ b/drivers/gpu/drm/radeon/r100.c +@@ -1050,6 +1050,36 @@ static int r100_cp_init_microcode(struct radeon_device *rdev) + return err; + } + ++u32 r100_gfx_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 rptr; ++ ++ if (rdev->wb.enabled) ++ rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); ++ else ++ rptr = RREG32(RADEON_CP_RB_RPTR); ++ ++ return rptr; ++} ++ ++u32 r100_gfx_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 wptr; ++ ++ wptr = RREG32(RADEON_CP_RB_WPTR); ++ ++ return wptr; ++} ++ ++void r100_gfx_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ WREG32(RADEON_CP_RB_WPTR, ring->wptr); ++ (void)RREG32(RADEON_CP_RB_WPTR); ++} ++ + static void r100_cp_load_microcode(struct radeon_device *rdev) + { + const __be32 *fw_data; +@@ -1102,7 +1132,6 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) + ring_size = (1 << (rb_bufsz + 1)) * 4; + r100_cp_load_microcode(rdev); + r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, +- RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR, + RADEON_CP_PACKET2); + if (r) { + return r; +diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c +index a5de2cf..5f52b50 100644 +--- a/drivers/gpu/drm/radeon/r600.c ++++ b/drivers/gpu/drm/radeon/r600.c +@@ -2329,6 +2329,36 @@ out: + return err; + } + ++u32 r600_gfx_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 rptr; ++ ++ if (rdev->wb.enabled) ++ rptr = rdev->wb.wb[ring->rptr_offs/4]; ++ else ++ rptr = RREG32(R600_CP_RB_RPTR); ++ ++ return rptr; ++} ++ ++u32 r600_gfx_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ u32 wptr; ++ ++ wptr = RREG32(R600_CP_RB_WPTR); ++ ++ return wptr; ++} ++ ++void r600_gfx_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ WREG32(R600_CP_RB_WPTR, ring->wptr); ++ (void)RREG32(R600_CP_RB_WPTR); ++} ++ + static int r600_cp_load_microcode(struct radeon_device *rdev) + { + const __be32 *fw_data; +@@ -2773,14 +2803,12 @@ static int r600_startup(struct radeon_device *rdev) + + ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, +- R600_CP_RB_RPTR, R600_CP_RB_WPTR, + RADEON_CP_PACKET2); + if (r) + return r; + + ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, +- DMA_RB_RPTR, DMA_RB_WPTR, + DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); + if (r) + return r; +diff --git a/drivers/gpu/drm/radeon/r600_dma.c b/drivers/gpu/drm/radeon/r600_dma.c +index 7844d15..3452c84 100644 +--- a/drivers/gpu/drm/radeon/r600_dma.c ++++ b/drivers/gpu/drm/radeon/r600_dma.c +@@ -51,7 +51,14 @@ u32 r600_gpu_check_soft_reset(struct radeon_device *rdev); + uint32_t r600_dma_get_rptr(struct radeon_device *rdev, + struct radeon_ring *ring) + { +- return (radeon_ring_generic_get_rptr(rdev, ring) & 0x3fffc) >> 2; ++ u32 rptr; ++ ++ if (rdev->wb.enabled) ++ rptr = rdev->wb.wb[ring->rptr_offs/4]; ++ else ++ rptr = RREG32(DMA_RB_RPTR); ++ ++ return (rptr & 0x3fffc) >> 2; + } + + /** +@@ -65,7 +72,7 @@ uint32_t r600_dma_get_rptr(struct radeon_device *rdev, + uint32_t r600_dma_get_wptr(struct radeon_device *rdev, + struct radeon_ring *ring) + { +- return (RREG32(ring->wptr_reg) & 0x3fffc) >> 2; ++ return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2; + } + + /** +@@ -79,7 +86,7 @@ uint32_t r600_dma_get_wptr(struct radeon_device *rdev, + void r600_dma_set_wptr(struct radeon_device *rdev, + struct radeon_ring *ring) + { +- WREG32(ring->wptr_reg, (ring->wptr << 2) & 0x3fffc); ++ WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); + } + + /** +diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h +index 5331fc2..fb7323d 100644 +--- a/drivers/gpu/drm/radeon/radeon.h ++++ b/drivers/gpu/drm/radeon/radeon.h +@@ -782,13 +782,11 @@ struct radeon_ring { + volatile uint32_t *ring; + unsigned rptr; + unsigned rptr_offs; +- unsigned rptr_reg; + unsigned rptr_save_reg; + u64 next_rptr_gpu_addr; + volatile u32 *next_rptr_cpu_addr; + unsigned wptr; + unsigned wptr_old; +- unsigned wptr_reg; + unsigned ring_size; + unsigned ring_free_dw; + int count_dw; +@@ -960,7 +958,7 @@ unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring + int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, + unsigned size, uint32_t *data); + int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, +- unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop); ++ unsigned rptr_offs, u32 nop); + void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); + + +diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c +index 123adfe..a539869 100644 +--- a/drivers/gpu/drm/radeon/radeon_asic.c ++++ b/drivers/gpu/drm/radeon/radeon_asic.c +@@ -182,9 +182,9 @@ static struct radeon_asic_ring r100_gfx_ring = { + .ring_test = &r100_ring_test, + .ib_test = &r100_ib_test, + .is_lockup = &r100_gpu_is_lockup, +- .get_rptr = &radeon_ring_generic_get_rptr, +- .get_wptr = &radeon_ring_generic_get_wptr, +- .set_wptr = &radeon_ring_generic_set_wptr, ++ .get_rptr = &r100_gfx_get_rptr, ++ .get_wptr = &r100_gfx_get_wptr, ++ .set_wptr = &r100_gfx_set_wptr, + }; + + static struct radeon_asic r100_asic = { +@@ -330,9 +330,9 @@ static struct radeon_asic_ring r300_gfx_ring = { + .ring_test = &r100_ring_test, + .ib_test = &r100_ib_test, + .is_lockup = &r100_gpu_is_lockup, +- .get_rptr = &radeon_ring_generic_get_rptr, +- .get_wptr = &radeon_ring_generic_get_wptr, +- .set_wptr = &radeon_ring_generic_set_wptr, ++ .get_rptr = &r100_gfx_get_rptr, ++ .get_wptr = &r100_gfx_get_wptr, ++ .set_wptr = &r100_gfx_set_wptr, + }; + + static struct radeon_asic r300_asic = { +@@ -883,9 +883,9 @@ static struct radeon_asic_ring r600_gfx_ring = { + .ring_test = &r600_ring_test, + .ib_test = &r600_ib_test, + .is_lockup = &r600_gfx_is_lockup, +- .get_rptr = &radeon_ring_generic_get_rptr, +- .get_wptr = &radeon_ring_generic_get_wptr, +- .set_wptr = &radeon_ring_generic_set_wptr, ++ .get_rptr = &r600_gfx_get_rptr, ++ .get_wptr = &r600_gfx_get_wptr, ++ .set_wptr = &r600_gfx_set_wptr, + }; + + static struct radeon_asic_ring r600_dma_ring = { +@@ -1267,9 +1267,9 @@ static struct radeon_asic_ring evergreen_gfx_ring = { + .ring_test = &r600_ring_test, + .ib_test = &r600_ib_test, + .is_lockup = &evergreen_gfx_is_lockup, +- .get_rptr = &radeon_ring_generic_get_rptr, +- .get_wptr = &radeon_ring_generic_get_wptr, +- .set_wptr = &radeon_ring_generic_set_wptr, ++ .get_rptr = &r600_gfx_get_rptr, ++ .get_wptr = &r600_gfx_get_wptr, ++ .set_wptr = &r600_gfx_set_wptr, + }; + + static struct radeon_asic_ring evergreen_dma_ring = { +@@ -1570,9 +1570,9 @@ static struct radeon_asic_ring cayman_gfx_ring = { + .ib_test = &r600_ib_test, + .is_lockup = &cayman_gfx_is_lockup, + .vm_flush = &cayman_vm_flush, +- .get_rptr = &radeon_ring_generic_get_rptr, +- .get_wptr = &radeon_ring_generic_get_wptr, +- .set_wptr = &radeon_ring_generic_set_wptr, ++ .get_rptr = &cayman_gfx_get_rptr, ++ .get_wptr = &cayman_gfx_get_wptr, ++ .set_wptr = &cayman_gfx_set_wptr, + }; + + static struct radeon_asic_ring cayman_dma_ring = { +@@ -1585,9 +1585,9 @@ static struct radeon_asic_ring cayman_dma_ring = { + .ib_test = &r600_dma_ib_test, + .is_lockup = &cayman_dma_is_lockup, + .vm_flush = &cayman_dma_vm_flush, +- .get_rptr = &r600_dma_get_rptr, +- .get_wptr = &r600_dma_get_wptr, +- .set_wptr = &r600_dma_set_wptr ++ .get_rptr = &cayman_dma_get_rptr, ++ .get_wptr = &cayman_dma_get_wptr, ++ .set_wptr = &cayman_dma_set_wptr + }; + + static struct radeon_asic_ring cayman_uvd_ring = { +@@ -1813,9 +1813,9 @@ static struct radeon_asic_ring si_gfx_ring = { + .ib_test = &r600_ib_test, + .is_lockup = &si_gfx_is_lockup, + .vm_flush = &si_vm_flush, +- .get_rptr = &radeon_ring_generic_get_rptr, +- .get_wptr = &radeon_ring_generic_get_wptr, +- .set_wptr = &radeon_ring_generic_set_wptr, ++ .get_rptr = &cayman_gfx_get_rptr, ++ .get_wptr = &cayman_gfx_get_wptr, ++ .set_wptr = &cayman_gfx_set_wptr, + }; + + static struct radeon_asic_ring si_dma_ring = { +@@ -1828,9 +1828,9 @@ static struct radeon_asic_ring si_dma_ring = { + .ib_test = &r600_dma_ib_test, + .is_lockup = &si_dma_is_lockup, + .vm_flush = &si_dma_vm_flush, +- .get_rptr = &r600_dma_get_rptr, +- .get_wptr = &r600_dma_get_wptr, +- .set_wptr = &r600_dma_set_wptr, ++ .get_rptr = &cayman_dma_get_rptr, ++ .get_wptr = &cayman_dma_get_wptr, ++ .set_wptr = &cayman_dma_set_wptr, + }; + + static struct radeon_asic si_asic = { +@@ -1943,9 +1943,9 @@ static struct radeon_asic_ring ci_gfx_ring = { + .ib_test = &cik_ib_test, + .is_lockup = &cik_gfx_is_lockup, + .vm_flush = &cik_vm_flush, +- .get_rptr = &radeon_ring_generic_get_rptr, +- .get_wptr = &radeon_ring_generic_get_wptr, +- .set_wptr = &radeon_ring_generic_set_wptr, ++ .get_rptr = &cik_gfx_get_rptr, ++ .get_wptr = &cik_gfx_get_wptr, ++ .set_wptr = &cik_gfx_set_wptr, + }; + + static struct radeon_asic_ring ci_cp_ring = { +@@ -1958,9 +1958,9 @@ static struct radeon_asic_ring ci_cp_ring = { + .ib_test = &cik_ib_test, + .is_lockup = &cik_gfx_is_lockup, + .vm_flush = &cik_vm_flush, +- .get_rptr = &cik_compute_ring_get_rptr, +- .get_wptr = &cik_compute_ring_get_wptr, +- .set_wptr = &cik_compute_ring_set_wptr, ++ .get_rptr = &cik_compute_get_rptr, ++ .get_wptr = &cik_compute_get_wptr, ++ .set_wptr = &cik_compute_set_wptr, + }; + + static struct radeon_asic_ring ci_dma_ring = { +@@ -1973,9 +1973,9 @@ static struct radeon_asic_ring ci_dma_ring = { + .ib_test = &cik_sdma_ib_test, + .is_lockup = &cik_sdma_is_lockup, + .vm_flush = &cik_dma_vm_flush, +- .get_rptr = &r600_dma_get_rptr, +- .get_wptr = &r600_dma_get_wptr, +- .set_wptr = &r600_dma_set_wptr, ++ .get_rptr = &cik_sdma_get_rptr, ++ .get_wptr = &cik_sdma_get_wptr, ++ .set_wptr = &cik_sdma_set_wptr, + }; + + static struct radeon_asic ci_asic = { +diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h +index 8939cb3..998042e 100644 +--- a/drivers/gpu/drm/radeon/radeon_asic.h ++++ b/drivers/gpu/drm/radeon/radeon_asic.h +@@ -47,13 +47,6 @@ u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); + void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); + u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); + +-u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev, +- struct radeon_ring *ring); +-u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev, +- struct radeon_ring *ring); +-void radeon_ring_generic_set_wptr(struct radeon_device *rdev, +- struct radeon_ring *ring); +- + /* + * r100,rv100,rs100,rv200,rs200 + */ +@@ -148,6 +141,13 @@ extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); + extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); + extern int r100_mc_wait_for_idle(struct radeon_device *rdev); + ++u32 r100_gfx_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++u32 r100_gfx_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++void r100_gfx_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++ + /* + * r200,rv250,rs300,rv280 + */ +@@ -368,6 +368,12 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev); + int r600_pcie_gart_init(struct radeon_device *rdev); + void r600_scratch_init(struct radeon_device *rdev); + int r600_init_microcode(struct radeon_device *rdev); ++u32 r600_gfx_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++u32 r600_gfx_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++void r600_gfx_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); + /* r600 irq */ + int r600_irq_process(struct radeon_device *rdev); + int r600_irq_init(struct radeon_device *rdev); +@@ -591,6 +597,19 @@ void cayman_dma_vm_set_page(struct radeon_device *rdev, + + void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); + ++u32 cayman_gfx_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++u32 cayman_gfx_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++void cayman_gfx_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++void cayman_dma_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++ + int ni_dpm_init(struct radeon_device *rdev); + void ni_dpm_setup_asic(struct radeon_device *rdev); + int ni_dpm_enable(struct radeon_device *rdev); +@@ -735,12 +754,24 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev, + uint32_t incr, uint32_t flags); + void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); + int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); +-u32 cik_compute_ring_get_rptr(struct radeon_device *rdev, +- struct radeon_ring *ring); +-u32 cik_compute_ring_get_wptr(struct radeon_device *rdev, +- struct radeon_ring *ring); +-void cik_compute_ring_set_wptr(struct radeon_device *rdev, +- struct radeon_ring *ring); ++u32 cik_gfx_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++u32 cik_gfx_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++void cik_gfx_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++u32 cik_compute_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++u32 cik_compute_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++void cik_compute_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++u32 cik_sdma_get_rptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++u32 cik_sdma_get_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); ++void cik_sdma_set_wptr(struct radeon_device *rdev, ++ struct radeon_ring *ring); + int ci_get_temp(struct radeon_device *rdev); + int kv_get_temp(struct radeon_device *rdev); + +diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c +index f1cec22..65f1cea 100644 +--- a/drivers/gpu/drm/radeon/radeon_ring.c ++++ b/drivers/gpu/drm/radeon/radeon_ring.c +@@ -332,36 +332,6 @@ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, + } + } + +-u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev, +- struct radeon_ring *ring) +-{ +- u32 rptr; +- +- if (rdev->wb.enabled) +- rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); +- else +- rptr = RREG32(ring->rptr_reg); +- +- return rptr; +-} +- +-u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev, +- struct radeon_ring *ring) +-{ +- u32 wptr; +- +- wptr = RREG32(ring->wptr_reg); +- +- return wptr; +-} +- +-void radeon_ring_generic_set_wptr(struct radeon_device *rdev, +- struct radeon_ring *ring) +-{ +- WREG32(ring->wptr_reg, ring->wptr); +- (void)RREG32(ring->wptr_reg); +-} +- + /** + * radeon_ring_free_size - update the free size + * +@@ -689,22 +659,18 @@ int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, + * @ring: radeon_ring structure holding ring information + * @ring_size: size of the ring + * @rptr_offs: offset of the rptr writeback location in the WB buffer +- * @rptr_reg: MMIO offset of the rptr register +- * @wptr_reg: MMIO offset of the wptr register + * @nop: nop packet for this ring + * + * Initialize the driver information for the selected ring (all asics). + * Returns 0 on success, error on failure. + */ + int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, +- unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop) ++ unsigned rptr_offs, u32 nop) + { + int r; + + ring->ring_size = ring_size; + ring->rptr_offs = rptr_offs; +- ring->rptr_reg = rptr_reg; +- ring->wptr_reg = wptr_reg; + ring->nop = nop; + /* Allocate ring buffer */ + if (ring->ring_obj == NULL) { +@@ -798,12 +764,12 @@ static int radeon_debugfs_ring_info(struct seq_file *m, void *data) + count = (ring->ring_size / 4) - ring->ring_free_dw; + + wptr = radeon_ring_get_wptr(rdev, ring); +- seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", +- ring->wptr_reg, wptr, wptr); ++ seq_printf(m, "wptr: 0x%08x [%5d]\n", ++ wptr, wptr); + + rptr = radeon_ring_get_rptr(rdev, ring); +- seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", +- ring->rptr_reg, rptr, rptr); ++ seq_printf(m, "rptr: 0x%08x [%5d]\n", ++ rptr, rptr); + + if (ring->rptr_save_reg) { + rptr_next = RREG32(ring->rptr_save_reg); +diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c +index 9f58467..6cce0de 100644 +--- a/drivers/gpu/drm/radeon/rv770.c ++++ b/drivers/gpu/drm/radeon/rv770.c +@@ -1728,14 +1728,12 @@ static int rv770_startup(struct radeon_device *rdev) + + ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, +- R600_CP_RB_RPTR, R600_CP_RB_WPTR, + RADEON_CP_PACKET2); + if (r) + return r; + + ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, +- DMA_RB_RPTR, DMA_RB_WPTR, + DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); + if (r) + return r; +@@ -1754,7 +1752,6 @@ static int rv770_startup(struct radeon_device *rdev) + ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; + if (ring->ring_size) { + r = radeon_ring_init(rdev, ring, ring->ring_size, 0, +- UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, + RADEON_CP_PACKET2); + if (!r) + r = uvd_v1_0_init(rdev); +diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c +index a7c53b7..8576a6f 100644 +--- a/drivers/gpu/drm/radeon/si.c ++++ b/drivers/gpu/drm/radeon/si.c +@@ -6424,37 +6424,30 @@ static int si_startup(struct radeon_device *rdev) + + ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, +- CP_RB0_RPTR, CP_RB0_WPTR, + RADEON_CP_PACKET2); + if (r) + return r; + + ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, +- CP_RB1_RPTR, CP_RB1_WPTR, + RADEON_CP_PACKET2); + if (r) + return r; + + ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, +- CP_RB2_RPTR, CP_RB2_WPTR, + RADEON_CP_PACKET2); + if (r) + return r; + + ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, +- DMA_RB_RPTR + DMA0_REGISTER_OFFSET, +- DMA_RB_WPTR + DMA0_REGISTER_OFFSET, + DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); + if (r) + return r; + + ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; + r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, +- DMA_RB_RPTR + DMA1_REGISTER_OFFSET, +- DMA_RB_WPTR + DMA1_REGISTER_OFFSET, + DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); + if (r) + return r; +@@ -6474,7 +6467,6 @@ static int si_startup(struct radeon_device *rdev) + ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; + if (ring->ring_size) { + r = radeon_ring_init(rdev, ring, ring->ring_size, 0, +- UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, + RADEON_CP_PACKET2); + if (!r) + r = uvd_v1_0_init(rdev); +-- +1.7.9.5 + |