diff options
Diffstat (limited to 'meta-steppeeagle/recipes-kernel/linux/linux-yocto/0023-yocto-amd-drm-radeon-set-correct-number-of-banks-for-CIK-chips.patch')
| -rw-r--r-- | meta-steppeeagle/recipes-kernel/linux/linux-yocto/0023-yocto-amd-drm-radeon-set-correct-number-of-banks-for-CIK-chips.patch | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0023-yocto-amd-drm-radeon-set-correct-number-of-banks-for-CIK-chips.patch b/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0023-yocto-amd-drm-radeon-set-correct-number-of-banks-for-CIK-chips.patch new file mode 100644 index 00000000..def7d8fc --- /dev/null +++ b/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0023-yocto-amd-drm-radeon-set-correct-number-of-banks-for-CIK-chips.patch @@ -0,0 +1,102 @@ +From 037690c12dcf3c3c2843f8db082ad2f5d49b7757 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com> +Date: Mon, 23 Dec 2013 17:11:36 +0100 +Subject: [PATCH 23/44] drm/radeon: set correct number of banks for CIK chips + in DCE +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +We don't have the NUM_BANKS parameter, so we have to calculate it +from the other parameters. NUM_BANKS is not constant on CIK. + +This fixes 2D tiling for the display engine on CIK. + +Signed-off-by: Marek Olšák <marek.olsak@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/radeon/atombios_crtc.c | 64 +++++++++++++++++++++----------- + 1 file changed, 43 insertions(+), 21 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c +index 368e1b8..09b35c3 100644 +--- a/drivers/gpu/drm/radeon/atombios_crtc.c ++++ b/drivers/gpu/drm/radeon/atombios_crtc.c +@@ -1143,31 +1143,53 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, + } + + if (tiling_flags & RADEON_TILING_MACRO) { +- if (rdev->family >= CHIP_BONAIRE) +- tmp = rdev->config.cik.tile_config; +- else if (rdev->family >= CHIP_TAHITI) +- tmp = rdev->config.si.tile_config; +- else if (rdev->family >= CHIP_CAYMAN) +- tmp = rdev->config.cayman.tile_config; +- else +- tmp = rdev->config.evergreen.tile_config; ++ evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); + +- switch ((tmp & 0xf0) >> 4) { +- case 0: /* 4 banks */ +- fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); +- break; +- case 1: /* 8 banks */ +- default: +- fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); +- break; +- case 2: /* 16 banks */ +- fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); +- break; ++ /* Set NUM_BANKS. */ ++ if (rdev->family >= CHIP_BONAIRE) { ++ unsigned tileb, index, num_banks, tile_split_bytes; ++ ++ /* Calculate the macrotile mode index. */ ++ tile_split_bytes = 64 << tile_split; ++ tileb = 8 * 8 * target_fb->bits_per_pixel / 8; ++ tileb = min(tile_split_bytes, tileb); ++ ++ for (index = 0; tileb > 64; index++) { ++ tileb >>= 1; ++ } ++ ++ if (index >= 16) { ++ DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", ++ target_fb->bits_per_pixel, tile_split); ++ return -EINVAL; ++ } ++ ++ num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; ++ fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); ++ } else { ++ /* SI and older. */ ++ if (rdev->family >= CHIP_TAHITI) ++ tmp = rdev->config.si.tile_config; ++ else if (rdev->family >= CHIP_CAYMAN) ++ tmp = rdev->config.cayman.tile_config; ++ else ++ tmp = rdev->config.evergreen.tile_config; ++ ++ switch ((tmp & 0xf0) >> 4) { ++ case 0: /* 4 banks */ ++ fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); ++ break; ++ case 1: /* 8 banks */ ++ default: ++ fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); ++ break; ++ case 2: /* 16 banks */ ++ fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); ++ break; ++ } + } + + fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); +- +- evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); + fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); + fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); + fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); +-- +1.7.9.5 + |