diff options
Diffstat (limited to 'meta-steppeeagle/recipes-kernel/linux/linux-yocto/0003-yocto-amd-drm-radeon-cleanup-DMA-HDP-flush-on-CIK-v2.patch')
| -rw-r--r-- | meta-steppeeagle/recipes-kernel/linux/linux-yocto/0003-yocto-amd-drm-radeon-cleanup-DMA-HDP-flush-on-CIK-v2.patch | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0003-yocto-amd-drm-radeon-cleanup-DMA-HDP-flush-on-CIK-v2.patch b/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0003-yocto-amd-drm-radeon-cleanup-DMA-HDP-flush-on-CIK-v2.patch new file mode 100644 index 00000000..8fe9e087 --- /dev/null +++ b/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0003-yocto-amd-drm-radeon-cleanup-DMA-HDP-flush-on-CIK-v2.patch @@ -0,0 +1,100 @@ +From 9c318cd900e41358c7507cb144f0ef8f5c0bbb19 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Tue, 5 Nov 2013 18:12:13 -0500 +Subject: [PATCH 03/44] drm/radeon: cleanup DMA HDP flush on CIK (v2) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +v2: use HDP_MEM_COHERENCY_FLUSH_CNTL again + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Christian König <christian.koenig@amd.com> +--- + drivers/gpu/drm/radeon/cik_sdma.c | 38 ++++++++++--------------------------- + 1 file changed, 10 insertions(+), 28 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c +index ed65b6e..56ede52 100644 +--- a/drivers/gpu/drm/radeon/cik_sdma.c ++++ b/drivers/gpu/drm/radeon/cik_sdma.c +@@ -51,6 +51,14 @@ u32 cik_gpu_check_soft_reset(struct radeon_device *rdev); + * buffers. + */ + ++static void cik_sdma_hdp_flush(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); ++ radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); ++ radeon_ring_write(ring, 0x0); ++} ++ + /** + * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine + * +@@ -102,14 +110,6 @@ void cik_sdma_fence_ring_emit(struct radeon_device *rdev, + { + struct radeon_ring *ring = &rdev->ring[fence->ring]; + u64 addr = rdev->fence_drv[fence->ring].gpu_addr; +- u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | +- SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ +- u32 ref_and_mask; +- +- if (fence->ring == R600_RING_TYPE_DMA_INDEX) +- ref_and_mask = SDMA0; +- else +- ref_and_mask = SDMA1; + + /* write the fence */ + radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); +@@ -119,12 +119,7 @@ void cik_sdma_fence_ring_emit(struct radeon_device *rdev, + /* generate an interrupt */ + radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); + /* flush HDP */ +- radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); +- radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); +- radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); +- radeon_ring_write(ring, ref_and_mask); /* REFERENCE */ +- radeon_ring_write(ring, ref_and_mask); /* MASK */ +- radeon_ring_write(ring, (4 << 16) | 10); /* RETRY_COUNT, POLL_INTERVAL */ ++ cik_sdma_hdp_flush(rdev, ring); + } + + /** +@@ -727,18 +722,10 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev, + void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) + { + struct radeon_ring *ring = &rdev->ring[ridx]; +- u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | +- SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ +- u32 ref_and_mask; + + if (vm == NULL) + return; + +- if (ridx == R600_RING_TYPE_DMA_INDEX) +- ref_and_mask = SDMA0; +- else +- ref_and_mask = SDMA1; +- + radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); + if (vm->id < 8) { + radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); +@@ -773,12 +760,7 @@ void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm + radeon_ring_write(ring, VMID(0)); + + /* flush HDP */ +- radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); +- radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); +- radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); +- radeon_ring_write(ring, ref_and_mask); /* REFERENCE */ +- radeon_ring_write(ring, ref_and_mask); /* MASK */ +- radeon_ring_write(ring, (4 << 16) | 10); /* RETRY_COUNT, POLL_INTERVAL */ ++ cik_sdma_hdp_flush(rdev, ring); + + /* flush TLB */ + radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); +-- +1.7.9.5 + |