diff options
Diffstat (limited to 'meta-steppeeagle/recipes-kernel/linux/linux-yocto/0002-yocto-amd-drm-radeon-cleanup-flushing-on-CIK-v3.patch')
| -rw-r--r-- | meta-steppeeagle/recipes-kernel/linux/linux-yocto/0002-yocto-amd-drm-radeon-cleanup-flushing-on-CIK-v3.patch | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0002-yocto-amd-drm-radeon-cleanup-flushing-on-CIK-v3.patch b/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0002-yocto-amd-drm-radeon-cleanup-flushing-on-CIK-v3.patch new file mode 100644 index 00000000..986489c2 --- /dev/null +++ b/meta-steppeeagle/recipes-kernel/linux/linux-yocto/0002-yocto-amd-drm-radeon-cleanup-flushing-on-CIK-v3.patch @@ -0,0 +1,96 @@ +From eee59eb01ab5dcbf99d6c11d5467f933e76ba99f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com> +Date: Sat, 19 Oct 2013 22:06:43 +0200 +Subject: [PATCH 02/44] drm/radeon: cleanup flushing on CIK (v3) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +v2: fix compute handling. +v3: use HDP_MEM_COHERENCY_FLUSH_CNTL again + +Signed-off-by: Marek Olšák <marek.olsak@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Christian König <christian.koenig@amd.com> +--- + drivers/gpu/drm/radeon/cik.c | 43 +++++++++++++++--------------------------- + 1 file changed, 15 insertions(+), 28 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c +index 31f5f0e..2277a59 100644 +--- a/drivers/gpu/drm/radeon/cik.c ++++ b/drivers/gpu/drm/radeon/cik.c +@@ -3011,6 +3011,18 @@ int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) + return r; + } + ++static void cik_cp_hdp_flush(struct radeon_device *rdev, ++ struct radeon_ring *ring) ++{ ++ /* Request an HDP flush */ ++ radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); ++ radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | ++ WRITE_DATA_DST_SEL(0))); ++ radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); ++ radeon_ring_write(ring, 0); ++ radeon_ring_write(ring, 0); ++} ++ + /** + * cik_fence_gfx_ring_emit - emit a fence on the gfx ring + * +@@ -3037,15 +3049,7 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev, + radeon_ring_write(ring, fence->seq); + radeon_ring_write(ring, 0); + /* HDP flush */ +- /* We should be using the new WAIT_REG_MEM special op packet here +- * but it causes the CP to hang +- */ +- radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); +- radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | +- WRITE_DATA_DST_SEL(0))); +- radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); +- radeon_ring_write(ring, 0); +- radeon_ring_write(ring, 0); ++ cik_cp_hdp_flush(rdev, ring); + } + + /** +@@ -3075,15 +3079,7 @@ void cik_fence_compute_ring_emit(struct radeon_device *rdev, + radeon_ring_write(ring, fence->seq); + radeon_ring_write(ring, 0); + /* HDP flush */ +- /* We should be using the new WAIT_REG_MEM special op packet here +- * but it causes the CP to hang +- */ +- radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); +- radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | +- WRITE_DATA_DST_SEL(0))); +- radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); +- radeon_ring_write(ring, 0); +- radeon_ring_write(ring, 0); ++ cik_cp_hdp_flush(rdev, ring); + } + + void cik_semaphore_ring_emit(struct radeon_device *rdev, +@@ -4809,16 +4805,7 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) + radeon_ring_write(ring, VMID(0)); + + /* HDP flush */ +- /* We should be using the WAIT_REG_MEM packet here like in +- * cik_fence_ring_emit(), but it causes the CP to hang in this +- * context... +- */ +- radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); +- radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | +- WRITE_DATA_DST_SEL(0))); +- radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); +- radeon_ring_write(ring, 0); +- radeon_ring_write(ring, 0); ++ cik_cp_hdp_flush(rdev, ring); + + /* bits 0-15 are the VM contexts0-15 */ + radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); +-- +1.7.9.5 + |