diff options
Diffstat (limited to 'meta-amdfalconx86')
4 files changed, 122 insertions, 1 deletions
diff --git a/meta-amdfalconx86/conf/machine/amdfalconx86.conf b/meta-amdfalconx86/conf/machine/amdfalconx86.conf index 9f49f42b..475c5ff0 100644 --- a/meta-amdfalconx86/conf/machine/amdfalconx86.conf +++ b/meta-amdfalconx86/conf/machine/amdfalconx86.conf @@ -42,6 +42,6 @@ SERIAL_CONSOLES += "115200;ttyS4 115200;ttyS5" APPEND += "console=ttyS0,115200n8" # Enable powerplay -APPEND += "amdgpu.powerplay=1" +APPEND += "amdgpu.powerplay=1 amdgpu.pg_mask=0" MACHINEOVERRIDES =. "amd:amdx86:amdgpu:" diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1124-add-amdgpu.cg_mask-and-amdgpu.pg_mask-parameters.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1124-add-amdgpu.cg_mask-and-amdgpu.pg_mask-parameters.patch new file mode 100644 index 00000000..ff18aa48 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1124-add-amdgpu.cg_mask-and-amdgpu.pg_mask-parameters.patch @@ -0,0 +1,77 @@ +From b6dadf7dceff70f8a09cf57fe7f1aa29427f764f Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Thu, 13 Oct 2016 12:52:22 +0530 +Subject: [PATCH 1/2] add amdgpu.cg_mask and amdgpu.pg_mask parameters +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +They allow disabling clock and power gating from the kernel command line, +which hopefully helps with diagnosing problems in the field. + +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Nicolai Hähnle <Nicolai.Haehnle@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++++ + 3 files changed, 13 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index b15b3b5..d3de21d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -89,6 +89,8 @@ extern int amdgpu_sched_hw_submission; + extern int amdgpu_powerplay; + extern unsigned amdgpu_pcie_gen_cap; + extern unsigned amdgpu_pcie_lane_cap; ++extern unsigned amdgpu_cg_mask; ++extern unsigned amdgpu_pg_mask; + + #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 + #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 6077ec6..ba5a67b 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1208,6 +1208,9 @@ static int amdgpu_early_init(struct amdgpu_device *adev) + } + } + ++ adev->cg_flags &= amdgpu_cg_mask; ++ adev->pg_flags &= amdgpu_pg_mask; ++ + return 0; + } + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +index af014c3..340d5fd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +@@ -83,6 +83,8 @@ int amdgpu_sched_hw_submission = 2; + int amdgpu_powerplay = -1; + unsigned amdgpu_pcie_gen_cap = 0; + unsigned amdgpu_pcie_lane_cap = 0; ++unsigned amdgpu_cg_mask = 0xffffffff; ++unsigned amdgpu_pg_mask = 0xffffffff; + + MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); + module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); +@@ -170,6 +172,12 @@ module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); + MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); + module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); + ++MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); ++module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); ++ ++MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); ++module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); ++ + static const struct pci_device_id pciidlist[] = { + #ifdef CONFIG_DRM_AMDGPU_CIK + /* Kaveri */ +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1125-drm-amdgpu-gfx8-disable-EDC.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1125-drm-amdgpu-gfx8-disable-EDC.patch new file mode 100644 index 00000000..2b51de5e --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1125-drm-amdgpu-gfx8-disable-EDC.patch @@ -0,0 +1,42 @@ +From b8e93c19d2aaa3d0f48a802dd779ca27e66236d2 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Thu, 13 Oct 2016 12:30:35 +0530 +Subject: [PATCH 2/2] drm/amdgpu/gfx8: disable EDC + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 92f3ee6..c5a3d04 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -1700,6 +1700,11 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) + goto fail; + } + ++ /* read back registers to clear the counters */ ++ for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) ++ RREG32(sec_ded_counter_registers[i]); ++ ++#if 0 + tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2); + tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1); + WREG32(mmGB_EDC_MODE, tmp); +@@ -1708,10 +1713,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) + tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1; + WREG32(mmCC_GC_EDC_CONFIG, tmp); + +- +- /* read back registers to clear the counters */ +- for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) +- RREG32(sec_ded_counter_registers[i]); ++#endif + + fail: + fence_put(f); +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc index 309ca158..7129d0e8 100644 --- a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc +++ b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc @@ -1124,4 +1124,6 @@ patch 1120-fix-amdgpu_drm.h-include-problem.patch patch 1121-add-the-interface-of-waiting-multiple-fences-v2.patch patch 1122-Fix-for-vulkan-decode-fail.patch patch 1123-ioctl-number-modified-DRM_AMDGPU_WAIT_FENCES.patch +patch 1124-add-amdgpu.cg_mask-and-amdgpu.pg_mask-parameters.patch +patch 1125-drm-amdgpu-gfx8-disable-EDC.patch patch 0001-amdgpu-fix-various-compilation-issues.patch |