diff options
Diffstat (limited to 'meta-amdfalconx86')
37 files changed, 10810 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0001-amdgpu-fix-various-compilation-issues.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0001-amdgpu-fix-various-compilation-issues.patch new file mode 100644 index 00000000..91aa2bb5 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/0001-amdgpu-fix-various-compilation-issues.patch @@ -0,0 +1,40 @@ +From 480e54e78f3df2bbc21f7977d3f55dc5aef5317e Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Wed, 13 Jul 2016 15:18:23 -0700 +Subject: [PATCH] amdgpu: fix various compilation issues + +Signed-off-by: Awais Belal <awais_belal@mentor.com> +Signed-off-by: Drew Moseley <drew_moseley@mentor.com> +--- + drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 2 +- + drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c | 1 - + 2 files changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c +index f39499a..e995f9b 100644 +--- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c ++++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c +@@ -3181,7 +3181,7 @@ static void calculate_bandwidth( + bw_int_to_fixed( + 2), + vbios->mcifwrmc_urgent_latency), +- results->dmif_burst_time[i][j]), ++ results->dmif_burst_time[results->y_clk_level][results->sclk_level]), + results->mcifwr_burst_time[results->y_clk_level][results->sclk_level])), + results->dispclk), + bw_int_to_fixed( +diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c +index 698a34e..13a1449 100644 +--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c ++++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c +@@ -41,7 +41,6 @@ + #define CV_SMART_DONGLE_ADDRESS 0x20 + /* DVI-HDMI dongle slave address for retrieving dongle signature*/ + #define DVI_HDMI_DONGLE_ADDRESS 0x68 +-static const int8_t dvi_hdmi_dongle_signature_str[] = "6140063500G"; + struct dvi_hdmi_dongle_signature_data { + int8_t vendor[3];/* "AMD" */ + uint8_t version[2]; +-- +2.9.1 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0001-fix-hang-issue-when-enable-CONFIG_DRM_AMD_ACP.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0001-fix-hang-issue-when-enable-CONFIG_DRM_AMD_ACP.patch new file mode 100644 index 00000000..5d66128d --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/0001-fix-hang-issue-when-enable-CONFIG_DRM_AMD_ACP.patch @@ -0,0 +1,55 @@ +From 0425f76fdb78fcede5819426814748912804eaa0 Mon Sep 17 00:00:00 2001 +From: Xiaogang <xiaogang.chen@amd.com> +Date: Wed, 20 Jul 2016 11:48:13 -0500 +Subject: [PATCH] fix hang issue when enable CONFIG_DRM_AMD_ACP + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + mode change 100644 => 100755 drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +old mode 100644 +new mode 100755 +index d6b0bff..34491f8 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +@@ -84,7 +84,6 @@ static int acp_sw_init(void *handle) + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + adev->acp.parent = adev->dev; +- + adev->acp.cgs_device = + amdgpu_cgs_create_device(adev); + if (!adev->acp.cgs_device) +@@ -356,20 +355,27 @@ static int acp_hw_init(void *handle) + adev->acp.acp_cell[0].num_resources = 4; + adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; + ++ adev->acp.acp_cell[0].ignore_resource_conflicts = 1; ++ + adev->acp.acp_cell[1].name = "designware-i2s"; + adev->acp.acp_cell[1].num_resources = 1; + adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; + adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; + adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); + ++ adev->acp.acp_cell[1].ignore_resource_conflicts = 1; ++ + adev->acp.acp_cell[2].name = "designware-i2s"; + adev->acp.acp_cell[2].num_resources = 1; + adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2]; + adev->acp.acp_cell[2].platform_data = &i2s_pdata[1]; + adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data); + ++ adev->acp.acp_cell[2].ignore_resource_conflicts = 1; ++ + r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell, + ACP_DEVS); ++ + if (r) + return r; + +-- +2.1.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1113-enable-UVD-context-buffer-for-older-HW-MIME-Version-.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1113-enable-UVD-context-buffer-for-older-HW-MIME-Version-.patch new file mode 100644 index 00000000..17691311 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1113-enable-UVD-context-buffer-for-older-HW-MIME-Version-.patch @@ -0,0 +1,137 @@ +From d4fc4a943bb3f18c6a1d89c367a04c5ea82c7575 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Sat, 17 Sep 2016 14:39:50 +0530 +Subject: [PATCH 03/12] enable UVD context buffer for older HW MIME-Version: + 1.0 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Supported starting on certain FW versions. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Leo Liu <leo.liu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + + drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 63 +++++++++++++++++++++++++++++++-- + 2 files changed, 61 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index 551f763..28f8481 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1670,6 +1670,7 @@ struct amdgpu_uvd { + struct amdgpu_ring ring; + struct amdgpu_irq_src irq; + bool address_64_bit; ++ bool use_ctx_buf; + struct amd_sched_entity entity; + }; + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +index 74f0019..9050af2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +@@ -42,6 +42,15 @@ + /* 1 second timeout */ + #define UVD_IDLE_TIMEOUT_MS 1000 + ++/* Firmware versions for VI */ ++#define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) ++#define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) ++#define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) ++#define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) ++ ++/* Polaris10/11 firmware version */ ++#define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) ++ + /* Firmware Names */ + #ifdef CONFIG_DRM_AMDGPU_CIK + #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" +@@ -415,7 +424,8 @@ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) + * + * Peek into the decode message and calculate the necessary buffer sizes. + */ +-static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) ++static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, ++ unsigned buf_sizes[]) + { + unsigned stream_type = msg[4]; + unsigned width = msg[6]; +@@ -437,7 +447,6 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) + + switch (stream_type) { + case 0: /* H264 */ +- case 7: /* H264 Perf */ + switch(level) { + case 30: + num_dpb_buffer = 8100 / fs_in_mb; +@@ -515,6 +524,54 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) + min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); + break; + ++ case 7: /* H264 Perf */ ++ switch(level) { ++ case 30: ++ num_dpb_buffer = 8100 / fs_in_mb; ++ break; ++ case 31: ++ num_dpb_buffer = 18000 / fs_in_mb; ++ break; ++ case 32: ++ num_dpb_buffer = 20480 / fs_in_mb; ++ break; ++ case 41: ++ num_dpb_buffer = 32768 / fs_in_mb; ++ break; ++ case 42: ++ num_dpb_buffer = 34816 / fs_in_mb; ++ break; ++ case 50: ++ num_dpb_buffer = 110400 / fs_in_mb; ++ break; ++ case 51: ++ num_dpb_buffer = 184320 / fs_in_mb; ++ break; ++ default: ++ num_dpb_buffer = 184320 / fs_in_mb; ++ break; ++ } ++ num_dpb_buffer++; ++ if (num_dpb_buffer > 17) ++ num_dpb_buffer = 17; ++ ++ /* reference picture buffer */ ++ min_dpb_size = image_size * num_dpb_buffer; ++ ++ if (!adev->uvd.use_ctx_buf){ ++ /* macroblock context buffer */ ++ min_dpb_size += ++ width_in_mb * height_in_mb * num_dpb_buffer * 192; ++ ++ /* IT surface buffer */ ++ min_dpb_size += width_in_mb * height_in_mb * 32; ++ } else { ++ /* macroblock context buffer */ ++ min_ctx_size = ++ width_in_mb * height_in_mb * num_dpb_buffer * 192; ++ } ++ break; ++ + case 16: /* H265 */ + image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; + image_size = ALIGN(image_size, 256); +@@ -610,7 +667,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, + + case 1: + /* it's a decode msg, calc buffer sizes */ +- r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes); ++ r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); + amdgpu_bo_kunmap(bo); + if (r) + return r; +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1114-fix-default-UVD-context-size.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1114-fix-default-UVD-context-size.patch new file mode 100644 index 00000000..9bfac892 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1114-fix-default-UVD-context-size.patch @@ -0,0 +1,34 @@ +From 769574cc4720acfd1eca9bc5467e1a5a4a7956f3 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Sat, 17 Sep 2016 14:41:30 +0530 +Subject: [PATCH 04/12] fix default UVD context size +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Context buffers should be denied by default, not allowed. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Leo Liu <leo.liu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +index 9050af2..ddc487d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +@@ -439,7 +439,7 @@ static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, + unsigned fs_in_mb = width_in_mb * height_in_mb; + + unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; +- unsigned min_ctx_size = 0; ++ unsigned min_ctx_size = ~0; + + image_size = width * height; + image_size += image_size / 2; +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1115-fix-IB-alignment-for-UVD.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1115-fix-IB-alignment-for-UVD.patch new file mode 100644 index 00000000..0f64355f --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1115-fix-IB-alignment-for-UVD.patch @@ -0,0 +1,31 @@ +From 953b9fd99e928cb79128d9339cbb71259ae8f0de Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Sat, 17 Sep 2016 14:53:56 +0530 +Subject: [PATCH 05/12] fix IB alignment for UVD + +According to the hw team, it should be 16, not 8. + +Cc: Peter Fang <peter.fang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Cc: stable@vger.kernel.org +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +index 78bd8b1..459d8b7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +@@ -227,7 +227,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file + type = AMD_IP_BLOCK_TYPE_UVD; + ring_mask = adev->uvd.ring.ready ? 1 : 0; + ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; +- ib_size_alignment = 8; ++ ib_size_alignment = 16; + break; + case AMDGPU_HW_IP_VCE: + type = AMD_IP_BLOCK_TYPE_VCE; +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1116-fix-VCE-ib-alignment-value.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1116-fix-VCE-ib-alignment-value.patch new file mode 100644 index 00000000..39bdd3aa --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1116-fix-VCE-ib-alignment-value.patch @@ -0,0 +1,29 @@ +From 1edb59b7025457bfe3efff045e7120b70b65d1f6 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Sat, 17 Sep 2016 14:56:40 +0530 +Subject: [PATCH 06/12] fix VCE ib alignment value + +The VCE rings only require single dword alignment. + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +index 459d8b7..b6de8d5 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +@@ -234,7 +234,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file + for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++) + ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); + ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; +- ib_size_alignment = 8; ++ ib_size_alignment = 1; + break; + default: + return -EINVAL; +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1117-add-support-for-UVD_NO_OP-register.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1117-add-support-for-UVD_NO_OP-register.patch new file mode 100644 index 00000000..6d1b4da9 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1117-add-support-for-UVD_NO_OP-register.patch @@ -0,0 +1,45 @@ +From 56c8ca5434ce175d98e33cffcfe554cc7e3cb70a Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Sat, 17 Sep 2016 15:10:08 +0530 +Subject: [PATCH 07/12] add support for UVD_NO_OP register +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Writes to this register are the preferred way to do NOPs. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 1 + + drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h | 1 + + 2 files changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +index ddc487d..2ca93a4 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +@@ -823,6 +823,7 @@ static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, + return r; + break; + case mmUVD_ENGINE_CNTL: ++ case mmUVD_NO_OP: + break; + default: + DRM_ERROR("Invalid reg 0x%X!\n", reg); +diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h +index f3e53b1..19802e9 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h +@@ -34,6 +34,7 @@ + #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 + #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 + #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 ++#define mmUVD_NO_OP 0x3bff + #define mmUVD_SEMA_CNTL 0x3d00 + #define mmUVD_LMI_EXT40_ADDR 0x3d26 + #define mmUVD_CTX_INDEX 0x3d28 +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch new file mode 100644 index 00000000..36737218 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch @@ -0,0 +1,106 @@ +From f60f754ee9efe8d43beadccb7bf0b169f77a6247 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Sat, 17 Sep 2016 15:13:33 +0530 +Subject: [PATCH 08/12] switch UVD code to use UVD_NO_OP for padding +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Replace packet2's with packet0 writes to UVD_NO_OP. The +value written to UVD_NO_OP does not matter. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 6 ++++-- + drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 2 +- + drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +- + drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h | 1 + + drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h | 1 + + 6 files changed, 9 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +index 2ca93a4..f14e4aa 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +@@ -964,8 +964,10 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, + ib->ptr[3] = addr >> 32; + ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); + ib->ptr[5] = 0; +- for (i = 6; i < 16; ++i) +- ib->ptr[i] = PACKET2(0); ++ for (i = 6; i < 16; i += 2) { ++ ib->ptr[i] = PACKET0(mmUVD_NO_OP, 0); ++ ib->ptr[i+1] = 0; ++ } + ib->length_dw = 16; + + if (direct) { +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +index a75ffb5b..ab4857d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +@@ -114,7 +114,7 @@ static int uvd_v4_2_sw_init(void *handle) + + ring = &adev->uvd.ring; + sprintf(ring->name, "uvd"); +- r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, ++ r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, + &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + + return r; +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +index ecb8101..2b115bd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +@@ -111,7 +111,7 @@ static int uvd_v5_0_sw_init(void *handle) + + ring = &adev->uvd.ring; + sprintf(ring->name, "uvd"); +- r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, ++ r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, + &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + + return r; +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +index 0887ea9..e33e3f4 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +@@ -115,7 +115,7 @@ static int uvd_v6_0_sw_init(void *handle) + + ring = &adev->uvd.ring; + sprintf(ring->name, "uvd"); +- r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, ++ r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, + &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + + return r; +diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h +index eb4cf53..cc972d2 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h +@@ -34,6 +34,7 @@ + #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 + #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 + #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 ++#define mmUVD_NO_OP 0x3bff + #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69 + #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68 + #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h +index 6f6fb34..d24d086 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h +@@ -35,6 +35,7 @@ + #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 + #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 + #define mmUVD_POWER_STATUS_U 0x3bfd ++#define mmUVD_NO_OP 0x3bff + #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69 + #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68 + #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67 +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1119-move-amdgpu_drm.h-to-driver-include-dir.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1119-move-amdgpu_drm.h-to-driver-include-dir.patch new file mode 100644 index 00000000..34295779 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1119-move-amdgpu_drm.h-to-driver-include-dir.patch @@ -0,0 +1,1366 @@ +From b85cb50d1c4416a804a6c9040675f74df48760ef Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Mon, 19 Sep 2016 12:16:57 +0530 +Subject: [PATCH 09/12] move amdgpu_drm.h to driver include dir + +Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> +Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 683 ++++++++++++++++++++++ + include/uapi/drm/amdgpu_drm.h | 653 --------------------- + 2 files changed, 683 insertions(+), 653 deletions(-) + create mode 100644 drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h + delete mode 100644 include/uapi/drm/amdgpu_drm.h + +diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +new file mode 100644 +index 0000000..c84f977 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +@@ -0,0 +1,683 @@ ++/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- ++ * ++ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. ++ * Copyright 2000 VA Linux Systems, Inc., Fremont, California. ++ * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. ++ * Copyright 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: ++ * Kevin E. Martin <martin@valinux.com> ++ * Gareth Hughes <gareth@valinux.com> ++ * Keith Whitwell <keith@tungstengraphics.com> ++ */ ++ ++#ifndef __AMDGPU_DRM_H__ ++#define __AMDGPU_DRM_H__ ++ ++#include "drm.h" ++ ++#define DRM_AMDGPU_GEM_CREATE 0x00 ++#define DRM_AMDGPU_GEM_MMAP 0x01 ++#define DRM_AMDGPU_CTX 0x02 ++#define DRM_AMDGPU_BO_LIST 0x03 ++#define DRM_AMDGPU_CS 0x04 ++#define DRM_AMDGPU_INFO 0x05 ++#define DRM_AMDGPU_GEM_METADATA 0x06 ++#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 ++#define DRM_AMDGPU_GEM_VA 0x08 ++#define DRM_AMDGPU_WAIT_CS 0x09 ++#define DRM_AMDGPU_GEM_OP 0x10 ++#define DRM_AMDGPU_GEM_USERPTR 0x11 ++#define DRM_AMDGPU_FREESYNC 0x14 ++ ++#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) ++#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) ++#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) ++#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) ++#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) ++#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) ++#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) ++#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) ++#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) ++#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) ++#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) ++#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) ++#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) ++ ++#define AMDGPU_GEM_DOMAIN_CPU 0x1 ++#define AMDGPU_GEM_DOMAIN_GTT 0x2 ++#define AMDGPU_GEM_DOMAIN_VRAM 0x4 ++#define AMDGPU_GEM_DOMAIN_GDS 0x8 ++#define AMDGPU_GEM_DOMAIN_GWS 0x10 ++#define AMDGPU_GEM_DOMAIN_OA 0x20 ++ ++/* Flag that CPU access will be required for the case of VRAM domain */ ++#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) ++/* Flag that CPU access will not work, this VRAM domain is invisible */ ++#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) ++/* Flag that USWC attributes should be used for GTT */ ++#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) ++/* Flag that the memory allocation should be pinned */ ++#define AMDGPU_GEM_CREATE_NO_EVICT (1 << 3) ++ ++struct drm_amdgpu_gem_create_in { ++ /** the requested memory size */ ++ __u64 bo_size; ++ /** physical start_addr alignment in bytes for some HW requirements */ ++ __u64 alignment; ++ /** the requested memory domains */ ++ __u64 domains; ++ /** allocation flags */ ++ __u64 domain_flags; ++}; ++ ++struct drm_amdgpu_gem_create_out { ++ /** returned GEM object handle */ ++ __u32 handle; ++ __u32 _pad; ++}; ++ ++union drm_amdgpu_gem_create { ++ struct drm_amdgpu_gem_create_in in; ++ struct drm_amdgpu_gem_create_out out; ++}; ++ ++/** Opcode to create new residency list. */ ++#define AMDGPU_BO_LIST_OP_CREATE 0 ++/** Opcode to destroy previously created residency list */ ++#define AMDGPU_BO_LIST_OP_DESTROY 1 ++/** Opcode to update resource information in the list */ ++#define AMDGPU_BO_LIST_OP_UPDATE 2 ++ ++struct drm_amdgpu_bo_list_in { ++ /** Type of operation */ ++ __u32 operation; ++ /** Handle of list or 0 if we want to create one */ ++ __u32 list_handle; ++ /** Number of BOs in list */ ++ __u32 bo_number; ++ /** Size of each element describing BO */ ++ __u32 bo_info_size; ++ /** Pointer to array describing BOs */ ++ __u64 bo_info_ptr; ++}; ++ ++struct drm_amdgpu_bo_list_entry { ++ /** Handle of BO */ ++ __u32 bo_handle; ++ /** New (if specified) BO priority to be used during migration */ ++ __u32 bo_priority; ++}; ++ ++struct drm_amdgpu_bo_list_out { ++ /** Handle of resource list */ ++ __u32 list_handle; ++ __u32 _pad; ++}; ++ ++union drm_amdgpu_bo_list { ++ struct drm_amdgpu_bo_list_in in; ++ struct drm_amdgpu_bo_list_out out; ++}; ++ ++/* context related */ ++#define AMDGPU_CTX_OP_ALLOC_CTX 1 ++#define AMDGPU_CTX_OP_FREE_CTX 2 ++#define AMDGPU_CTX_OP_QUERY_STATE 3 ++ ++/* GPU reset status */ ++#define AMDGPU_CTX_NO_RESET 0 ++/* this the context caused it */ ++#define AMDGPU_CTX_GUILTY_RESET 1 ++/* some other context caused it */ ++#define AMDGPU_CTX_INNOCENT_RESET 2 ++/* unknown cause */ ++#define AMDGPU_CTX_UNKNOWN_RESET 3 ++ ++struct drm_amdgpu_ctx_in { ++ /** AMDGPU_CTX_OP_* */ ++ __u32 op; ++ /** For future use, no flags defined so far */ ++ __u32 flags; ++ __u32 ctx_id; ++ __u32 _pad; ++}; ++ ++union drm_amdgpu_ctx_out { ++ struct { ++ __u32 ctx_id; ++ __u32 _pad; ++ } alloc; ++ ++ struct { ++ /** For future use, no flags defined so far */ ++ __u64 flags; ++ /** Number of resets caused by this context so far. */ ++ __u32 hangs; ++ /** Reset status since the last call of the ioctl. */ ++ __u32 reset_status; ++ } state; ++}; ++ ++union drm_amdgpu_ctx { ++ struct drm_amdgpu_ctx_in in; ++ union drm_amdgpu_ctx_out out; ++}; ++ ++/* ++ * This is not a reliable API and you should expect it to fail for any ++ * number of reasons and have fallback path that do not use userptr to ++ * perform any operation. ++ */ ++#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) ++#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) ++#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) ++#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) ++ ++struct drm_amdgpu_gem_userptr { ++ __u64 addr; ++ __u64 size; ++ /* AMDGPU_GEM_USERPTR_* */ ++ __u32 flags; ++ /* Resulting GEM handle */ ++ __u32 handle; ++}; ++ ++/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ ++#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 ++#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf ++#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 ++#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f ++#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 ++#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 ++#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 ++#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 ++#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 ++#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 ++#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 ++#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 ++#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 ++#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 ++#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 ++#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 ++ ++#define AMDGPU_TILING_SET(field, value) \ ++ (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) ++#define AMDGPU_TILING_GET(value, field) \ ++ (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) ++ ++#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 ++#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 ++ ++/** The same structure is shared for input/output */ ++struct drm_amdgpu_gem_metadata { ++ /** GEM Object handle */ ++ __u32 handle; ++ /** Do we want get or set metadata */ ++ __u32 op; ++ struct { ++ /** For future use, no flags defined so far */ ++ __u64 flags; ++ /** family specific tiling info */ ++ __u64 tiling_info; ++ __u32 data_size_bytes; ++ __u32 data[64]; ++ } data; ++}; ++ ++struct drm_amdgpu_gem_mmap_in { ++ /** the GEM object handle */ ++ __u32 handle; ++ __u32 _pad; ++}; ++ ++struct drm_amdgpu_gem_mmap_out { ++ /** mmap offset from the vma offset manager */ ++ __u64 addr_ptr; ++}; ++ ++union drm_amdgpu_gem_mmap { ++ struct drm_amdgpu_gem_mmap_in in; ++ struct drm_amdgpu_gem_mmap_out out; ++}; ++ ++struct drm_amdgpu_gem_wait_idle_in { ++ /** GEM object handle */ ++ __u32 handle; ++ /** For future use, no flags defined so far */ ++ __u32 flags; ++ /** Absolute timeout to wait */ ++ __u64 timeout; ++}; ++ ++struct drm_amdgpu_gem_wait_idle_out { ++ /** BO status: 0 - BO is idle, 1 - BO is busy */ ++ __u32 status; ++ /** Returned current memory domain */ ++ __u32 domain; ++}; ++ ++union drm_amdgpu_gem_wait_idle { ++ struct drm_amdgpu_gem_wait_idle_in in; ++ struct drm_amdgpu_gem_wait_idle_out out; ++}; ++ ++struct drm_amdgpu_wait_cs_in { ++ /** Command submission handle */ ++ __u64 handle; ++ /** Absolute timeout to wait */ ++ __u64 timeout; ++ __u32 ip_type; ++ __u32 ip_instance; ++ __u32 ring; ++ __u32 ctx_id; ++}; ++ ++struct drm_amdgpu_wait_cs_out { ++ /** CS status: 0 - CS completed, 1 - CS still busy */ ++ __u64 status; ++}; ++ ++union drm_amdgpu_wait_cs { ++ struct drm_amdgpu_wait_cs_in in; ++ struct drm_amdgpu_wait_cs_out out; ++}; ++ ++#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 ++#define AMDGPU_GEM_OP_SET_PLACEMENT 1 ++ ++/* Sets or returns a value associated with a buffer. */ ++struct drm_amdgpu_gem_op { ++ /** GEM object handle */ ++ __u32 handle; ++ /** AMDGPU_GEM_OP_* */ ++ __u32 op; ++ /** Input or return value */ ++ __u64 value; ++}; ++ ++#define AMDGPU_VA_OP_MAP 1 ++#define AMDGPU_VA_OP_UNMAP 2 ++ ++/* Delay the page table update till the next CS */ ++#define AMDGPU_VM_DELAY_UPDATE (1 << 0) ++ ++/* Mapping flags */ ++/* readable mapping */ ++#define AMDGPU_VM_PAGE_READABLE (1 << 1) ++/* writable mapping */ ++#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) ++/* executable mapping, new for VI */ ++#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) ++ ++struct drm_amdgpu_gem_va { ++ /** GEM object handle */ ++ __u32 handle; ++ __u32 _pad; ++ /** AMDGPU_VA_OP_* */ ++ __u32 operation; ++ /** AMDGPU_VM_PAGE_* */ ++ __u32 flags; ++ /** va address to assign . Must be correctly aligned.*/ ++ __u64 va_address; ++ /** Specify offset inside of BO to assign. Must be correctly aligned.*/ ++ __u64 offset_in_bo; ++ /** Specify mapping size. Must be correctly aligned. */ ++ __u64 map_size; ++}; ++ ++#define AMDGPU_HW_IP_GFX 0 ++#define AMDGPU_HW_IP_COMPUTE 1 ++#define AMDGPU_HW_IP_DMA 2 ++#define AMDGPU_HW_IP_UVD 3 ++#define AMDGPU_HW_IP_VCE 4 ++#define AMDGPU_HW_IP_NUM 5 ++ ++#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 ++ ++#define AMDGPU_CHUNK_ID_IB 0x01 ++#define AMDGPU_CHUNK_ID_FENCE 0x02 ++#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 ++ ++struct drm_amdgpu_cs_chunk { ++ __u32 chunk_id; ++ __u32 length_dw; ++ __u64 chunk_data; ++}; ++ ++struct drm_amdgpu_cs_in { ++ /** Rendering context id */ ++ __u32 ctx_id; ++ /** Handle of resource list associated with CS */ ++ __u32 bo_list_handle; ++ __u32 num_chunks; ++ __u32 _pad; ++ /** this points to __u64 * which point to cs chunks */ ++ __u64 chunks; ++}; ++ ++struct drm_amdgpu_cs_out { ++ __u64 handle; ++}; ++ ++union drm_amdgpu_cs { ++ struct drm_amdgpu_cs_in in; ++ struct drm_amdgpu_cs_out out; ++}; ++ ++/* Specify flags to be used for IB */ ++ ++/* This IB should be submitted to CE */ ++#define AMDGPU_IB_FLAG_CE (1<<0) ++ ++/* CE Preamble */ ++#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) ++ ++struct drm_amdgpu_cs_chunk_ib { ++ __u32 _pad; ++ /** AMDGPU_IB_FLAG_* */ ++ __u32 flags; ++ /** Virtual address to begin IB execution */ ++ __u64 va_start; ++ /** Size of submission */ ++ __u32 ib_bytes; ++ /** HW IP to submit to */ ++ __u32 ip_type; ++ /** HW IP index of the same type to submit to */ ++ __u32 ip_instance; ++ /** Ring index to submit to */ ++ __u32 ring; ++}; ++ ++struct drm_amdgpu_cs_chunk_dep { ++ __u32 ip_type; ++ __u32 ip_instance; ++ __u32 ring; ++ __u32 ctx_id; ++ __u64 handle; ++}; ++ ++struct drm_amdgpu_cs_chunk_fence { ++ __u32 handle; ++ __u32 offset; ++}; ++ ++struct drm_amdgpu_cs_chunk_data { ++ union { ++ struct drm_amdgpu_cs_chunk_ib ib_data; ++ struct drm_amdgpu_cs_chunk_fence fence_data; ++ }; ++}; ++ ++/** ++ * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU ++ * ++ */ ++#define AMDGPU_IDS_FLAGS_FUSION 0x1 ++ ++/* indicate if acceleration can be working */ ++#define AMDGPU_INFO_ACCEL_WORKING 0x00 ++/* get the crtc_id from the mode object id? */ ++#define AMDGPU_INFO_CRTC_FROM_ID 0x01 ++/* query hw IP info */ ++#define AMDGPU_INFO_HW_IP_INFO 0x02 ++/* query hw IP instance count for the specified type */ ++#define AMDGPU_INFO_HW_IP_COUNT 0x03 ++/* timestamp for GL_ARB_timer_query */ ++#define AMDGPU_INFO_TIMESTAMP 0x05 ++/* Query the firmware version */ ++#define AMDGPU_INFO_FW_VERSION 0x0e ++ /* Subquery id: Query VCE firmware version */ ++ #define AMDGPU_INFO_FW_VCE 0x1 ++ /* Subquery id: Query UVD firmware version */ ++ #define AMDGPU_INFO_FW_UVD 0x2 ++ /* Subquery id: Query GMC firmware version */ ++ #define AMDGPU_INFO_FW_GMC 0x03 ++ /* Subquery id: Query GFX ME firmware version */ ++ #define AMDGPU_INFO_FW_GFX_ME 0x04 ++ /* Subquery id: Query GFX PFP firmware version */ ++ #define AMDGPU_INFO_FW_GFX_PFP 0x05 ++ /* Subquery id: Query GFX CE firmware version */ ++ #define AMDGPU_INFO_FW_GFX_CE 0x06 ++ /* Subquery id: Query GFX RLC firmware version */ ++ #define AMDGPU_INFO_FW_GFX_RLC 0x07 ++ /* Subquery id: Query GFX MEC firmware version */ ++ #define AMDGPU_INFO_FW_GFX_MEC 0x08 ++ /* Subquery id: Query SMC firmware version */ ++ #define AMDGPU_INFO_FW_SMC 0x0a ++ /* Subquery id: Query SDMA firmware version */ ++ #define AMDGPU_INFO_FW_SDMA 0x0b ++/* number of bytes moved for TTM migration */ ++#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f ++/* the used VRAM size */ ++#define AMDGPU_INFO_VRAM_USAGE 0x10 ++/* the used GTT size */ ++#define AMDGPU_INFO_GTT_USAGE 0x11 ++/* Information about GDS, etc. resource configuration */ ++#define AMDGPU_INFO_GDS_CONFIG 0x13 ++/* Query information about VRAM and GTT domains */ ++#define AMDGPU_INFO_VRAM_GTT 0x14 ++/* Query information about register in MMR address space*/ ++#define AMDGPU_INFO_READ_MMR_REG 0x15 ++/* Query information about device: rev id, family, etc. */ ++#define AMDGPU_INFO_DEV_INFO 0x16 ++/* visible vram usage */ ++#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 ++/* virtual range */ ++#define AMDGPU_INFO_VIRTUAL_RANGE 0x18 ++/* gpu capability */ ++#define AMDGPU_INFO_CAPABILITY 0x50 ++/* query pin memory capability */ ++#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) ++ ++#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 ++#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff ++#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 ++#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff ++ ++/* Input structure for the INFO ioctl */ ++struct drm_amdgpu_info { ++ /* Where the return value will be stored */ ++ __u64 return_pointer; ++ /* The size of the return value. Just like "size" in "snprintf", ++ * it limits how many bytes the kernel can write. */ ++ __u32 return_size; ++ /* The query request id. */ ++ __u32 query; ++ ++ union { ++ struct { ++ __u32 id; ++ __u32 _pad; ++ } mode_crtc; ++ ++ struct { ++ /** AMDGPU_HW_IP_* */ ++ __u32 type; ++ /** ++ * Index of the IP if there are more IPs of the same ++ * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. ++ */ ++ __u32 ip_instance; ++ } query_hw_ip; ++ ++ struct { ++ __u32 dword_offset; ++ /** number of registers to read */ ++ __u32 count; ++ __u32 instance; ++ /** For future use, no flags defined so far */ ++ __u32 flags; ++ } read_mmr_reg; ++ ++ struct { ++ /** AMDGPU_INFO_FW_* */ ++ __u32 fw_type; ++ /** ++ * Index of the IP if there are more IPs of ++ * the same type. ++ */ ++ __u32 ip_instance; ++ /** ++ * Index of the engine. Whether this is used depends ++ * on the firmware type. (e.g. MEC, SDMA) ++ */ ++ __u32 index; ++ __u32 _pad; ++ } query_fw; ++ ++ struct { ++ uint32_t aperture; ++ uint32_t _pad; ++ } virtual_range; ++ }; ++}; ++ ++struct drm_amdgpu_info_gds { ++ /** GDS GFX partition size */ ++ __u32 gds_gfx_partition_size; ++ /** GDS compute partition size */ ++ __u32 compute_partition_size; ++ /** total GDS memory size */ ++ __u32 gds_total_size; ++ /** GWS size per GFX partition */ ++ __u32 gws_per_gfx_partition; ++ /** GSW size per compute partition */ ++ __u32 gws_per_compute_partition; ++ /** OA size per GFX partition */ ++ __u32 oa_per_gfx_partition; ++ /** OA size per compute partition */ ++ __u32 oa_per_compute_partition; ++ __u32 _pad; ++}; ++ ++struct drm_amdgpu_info_vram_gtt { ++ __u64 vram_size; ++ __u64 vram_cpu_accessible_size; ++ __u64 gtt_size; ++}; ++ ++struct drm_amdgpu_info_firmware { ++ __u32 ver; ++ __u32 feature; ++}; ++ ++#define AMDGPU_VRAM_TYPE_UNKNOWN 0 ++#define AMDGPU_VRAM_TYPE_GDDR1 1 ++#define AMDGPU_VRAM_TYPE_DDR2 2 ++#define AMDGPU_VRAM_TYPE_GDDR3 3 ++#define AMDGPU_VRAM_TYPE_GDDR4 4 ++#define AMDGPU_VRAM_TYPE_GDDR5 5 ++#define AMDGPU_VRAM_TYPE_HBM 6 ++#define AMDGPU_VRAM_TYPE_DDR3 7 ++ ++struct drm_amdgpu_info_device { ++ /** PCI Device ID */ ++ __u32 device_id; ++ /** Internal chip revision: A0, A1, etc.) */ ++ __u32 chip_rev; ++ __u32 external_rev; ++ /** Revision id in PCI Config space */ ++ __u32 pci_rev; ++ __u32 family; ++ __u32 num_shader_engines; ++ __u32 num_shader_arrays_per_engine; ++ /* in KHz */ ++ __u32 gpu_counter_freq; ++ __u64 max_engine_clock; ++ __u64 max_memory_clock; ++ /* cu information */ ++ __u32 cu_active_number; ++ __u32 cu_ao_mask; ++ __u32 cu_bitmap[4][4]; ++ /** Render backend pipe mask. One render backend is CB+DB. */ ++ __u32 enabled_rb_pipes_mask; ++ __u32 num_rb_pipes; ++ __u32 num_hw_gfx_contexts; ++ __u32 _pad; ++ __u64 ids_flags; ++ /** Starting virtual address for UMDs. */ ++ __u64 virtual_address_offset; ++ /** The maximum virtual address */ ++ __u64 virtual_address_max; ++ /** Required alignment of virtual addresses. */ ++ __u32 virtual_address_alignment; ++ /** Page table entry - fragment size */ ++ __u32 pte_fragment_size; ++ __u32 gart_page_size; ++ /** constant engine ram size*/ ++ __u32 ce_ram_size; ++ /** video memory type info*/ ++ __u32 vram_type; ++ /** video memory bit width*/ ++ __u32 vram_bit_width; ++ /* vce harvesting instance */ ++ __u32 vce_harvest_config; ++}; ++ ++struct drm_amdgpu_info_hw_ip { ++ /** Version of h/w IP */ ++ __u32 hw_ip_version_major; ++ __u32 hw_ip_version_minor; ++ /** Capabilities */ ++ __u64 capabilities_flags; ++ /** command buffer address start alignment*/ ++ __u32 ib_start_alignment; ++ /** command buffer size alignment*/ ++ __u32 ib_size_alignment; ++ /** Bitmask of available rings. Bit 0 means ring 0, etc. */ ++ __u32 available_rings; ++ __u32 _pad; ++}; ++ ++/* ++ * Supported GPU families ++ */ ++#define AMDGPU_FAMILY_UNKNOWN 0 ++#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ ++#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ ++#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ ++#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ ++ ++/** ++ * Definition of System Unified Address (SUA) apertures ++ */ ++#define AMDGPU_SUA_APERTURE_PRIVATE 1 ++#define AMDGPU_SUA_APERTURE_SHARED 2 ++struct drm_amdgpu_virtual_range { ++ uint64_t start; ++ uint64_t end; ++}; ++ ++/* ++ * Definition of free sync enter and exit signals ++ * We may have more options in the future ++ */ ++#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1 ++#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2 ++ ++struct drm_amdgpu_freesync { ++ __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ ++ /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ ++ __u32 spare[7]; ++}; ++ ++#endif +diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h +deleted file mode 100644 +index 7039d22..0000000 +--- a/include/uapi/drm/amdgpu_drm.h ++++ /dev/null +@@ -1,653 +0,0 @@ +-/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- +- * +- * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. +- * Copyright 2000 VA Linux Systems, Inc., Fremont, California. +- * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. +- * Copyright 2014 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: +- * Kevin E. Martin <martin@valinux.com> +- * Gareth Hughes <gareth@valinux.com> +- * Keith Whitwell <keith@tungstengraphics.com> +- */ +- +-#ifndef __AMDGPU_DRM_H__ +-#define __AMDGPU_DRM_H__ +- +-#include "drm.h" +- +-#define DRM_AMDGPU_GEM_CREATE 0x00 +-#define DRM_AMDGPU_GEM_MMAP 0x01 +-#define DRM_AMDGPU_CTX 0x02 +-#define DRM_AMDGPU_BO_LIST 0x03 +-#define DRM_AMDGPU_CS 0x04 +-#define DRM_AMDGPU_INFO 0x05 +-#define DRM_AMDGPU_GEM_METADATA 0x06 +-#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 +-#define DRM_AMDGPU_GEM_VA 0x08 +-#define DRM_AMDGPU_WAIT_CS 0x09 +-#define DRM_AMDGPU_GEM_OP 0x10 +-#define DRM_AMDGPU_GEM_USERPTR 0x11 +-#define DRM_AMDGPU_FREESYNC 0x14 +- +-#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) +-#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) +-#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) +-#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) +-#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) +-#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) +-#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) +-#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) +-#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) +-#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) +-#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) +-#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) +-#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) +- +-#define AMDGPU_GEM_DOMAIN_CPU 0x1 +-#define AMDGPU_GEM_DOMAIN_GTT 0x2 +-#define AMDGPU_GEM_DOMAIN_VRAM 0x4 +-#define AMDGPU_GEM_DOMAIN_GDS 0x8 +-#define AMDGPU_GEM_DOMAIN_GWS 0x10 +-#define AMDGPU_GEM_DOMAIN_OA 0x20 +- +-/* Flag that CPU access will be required for the case of VRAM domain */ +-#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) +-/* Flag that CPU access will not work, this VRAM domain is invisible */ +-#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) +-/* Flag that USWC attributes should be used for GTT */ +-#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) +- +-struct drm_amdgpu_gem_create_in { +- /** the requested memory size */ +- uint64_t bo_size; +- /** physical start_addr alignment in bytes for some HW requirements */ +- uint64_t alignment; +- /** the requested memory domains */ +- uint64_t domains; +- /** allocation flags */ +- uint64_t domain_flags; +-}; +- +-struct drm_amdgpu_gem_create_out { +- /** returned GEM object handle */ +- uint32_t handle; +- uint32_t _pad; +-}; +- +-union drm_amdgpu_gem_create { +- struct drm_amdgpu_gem_create_in in; +- struct drm_amdgpu_gem_create_out out; +-}; +- +-/** Opcode to create new residency list. */ +-#define AMDGPU_BO_LIST_OP_CREATE 0 +-/** Opcode to destroy previously created residency list */ +-#define AMDGPU_BO_LIST_OP_DESTROY 1 +-/** Opcode to update resource information in the list */ +-#define AMDGPU_BO_LIST_OP_UPDATE 2 +- +-struct drm_amdgpu_bo_list_in { +- /** Type of operation */ +- uint32_t operation; +- /** Handle of list or 0 if we want to create one */ +- uint32_t list_handle; +- /** Number of BOs in list */ +- uint32_t bo_number; +- /** Size of each element describing BO */ +- uint32_t bo_info_size; +- /** Pointer to array describing BOs */ +- uint64_t bo_info_ptr; +-}; +- +-struct drm_amdgpu_bo_list_entry { +- /** Handle of BO */ +- uint32_t bo_handle; +- /** New (if specified) BO priority to be used during migration */ +- uint32_t bo_priority; +-}; +- +-struct drm_amdgpu_bo_list_out { +- /** Handle of resource list */ +- uint32_t list_handle; +- uint32_t _pad; +-}; +- +-union drm_amdgpu_bo_list { +- struct drm_amdgpu_bo_list_in in; +- struct drm_amdgpu_bo_list_out out; +-}; +- +-/* context related */ +-#define AMDGPU_CTX_OP_ALLOC_CTX 1 +-#define AMDGPU_CTX_OP_FREE_CTX 2 +-#define AMDGPU_CTX_OP_QUERY_STATE 3 +- +-/* GPU reset status */ +-#define AMDGPU_CTX_NO_RESET 0 +-/* this the context caused it */ +-#define AMDGPU_CTX_GUILTY_RESET 1 +-/* some other context caused it */ +-#define AMDGPU_CTX_INNOCENT_RESET 2 +-/* unknown cause */ +-#define AMDGPU_CTX_UNKNOWN_RESET 3 +- +-struct drm_amdgpu_ctx_in { +- /** AMDGPU_CTX_OP_* */ +- uint32_t op; +- /** For future use, no flags defined so far */ +- uint32_t flags; +- uint32_t ctx_id; +- uint32_t _pad; +-}; +- +-union drm_amdgpu_ctx_out { +- struct { +- uint32_t ctx_id; +- uint32_t _pad; +- } alloc; +- +- struct { +- /** For future use, no flags defined so far */ +- uint64_t flags; +- /** Number of resets caused by this context so far. */ +- uint32_t hangs; +- /** Reset status since the last call of the ioctl. */ +- uint32_t reset_status; +- } state; +-}; +- +-union drm_amdgpu_ctx { +- struct drm_amdgpu_ctx_in in; +- union drm_amdgpu_ctx_out out; +-}; +- +-/* +- * This is not a reliable API and you should expect it to fail for any +- * number of reasons and have fallback path that do not use userptr to +- * perform any operation. +- */ +-#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) +-#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) +-#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) +-#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) +- +-struct drm_amdgpu_gem_userptr { +- uint64_t addr; +- uint64_t size; +- /* AMDGPU_GEM_USERPTR_* */ +- uint32_t flags; +- /* Resulting GEM handle */ +- uint32_t handle; +-}; +- +-/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ +-#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 +-#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf +-#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 +-#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f +-#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 +-#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 +-#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 +-#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 +-#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 +-#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 +-#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 +-#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 +-#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 +-#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 +-#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 +-#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 +- +-#define AMDGPU_TILING_SET(field, value) \ +- (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) +-#define AMDGPU_TILING_GET(value, field) \ +- (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) +- +-#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 +-#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 +- +-/** The same structure is shared for input/output */ +-struct drm_amdgpu_gem_metadata { +- /** GEM Object handle */ +- uint32_t handle; +- /** Do we want get or set metadata */ +- uint32_t op; +- struct { +- /** For future use, no flags defined so far */ +- uint64_t flags; +- /** family specific tiling info */ +- uint64_t tiling_info; +- uint32_t data_size_bytes; +- uint32_t data[64]; +- } data; +-}; +- +-struct drm_amdgpu_gem_mmap_in { +- /** the GEM object handle */ +- uint32_t handle; +- uint32_t _pad; +-}; +- +-struct drm_amdgpu_gem_mmap_out { +- /** mmap offset from the vma offset manager */ +- uint64_t addr_ptr; +-}; +- +-union drm_amdgpu_gem_mmap { +- struct drm_amdgpu_gem_mmap_in in; +- struct drm_amdgpu_gem_mmap_out out; +-}; +- +-struct drm_amdgpu_gem_wait_idle_in { +- /** GEM object handle */ +- uint32_t handle; +- /** For future use, no flags defined so far */ +- uint32_t flags; +- /** Absolute timeout to wait */ +- uint64_t timeout; +-}; +- +-struct drm_amdgpu_gem_wait_idle_out { +- /** BO status: 0 - BO is idle, 1 - BO is busy */ +- uint32_t status; +- /** Returned current memory domain */ +- uint32_t domain; +-}; +- +-union drm_amdgpu_gem_wait_idle { +- struct drm_amdgpu_gem_wait_idle_in in; +- struct drm_amdgpu_gem_wait_idle_out out; +-}; +- +-struct drm_amdgpu_wait_cs_in { +- /** Command submission handle */ +- uint64_t handle; +- /** Absolute timeout to wait */ +- uint64_t timeout; +- uint32_t ip_type; +- uint32_t ip_instance; +- uint32_t ring; +- uint32_t ctx_id; +-}; +- +-struct drm_amdgpu_wait_cs_out { +- /** CS status: 0 - CS completed, 1 - CS still busy */ +- uint64_t status; +-}; +- +-union drm_amdgpu_wait_cs { +- struct drm_amdgpu_wait_cs_in in; +- struct drm_amdgpu_wait_cs_out out; +-}; +- +-#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 +-#define AMDGPU_GEM_OP_SET_PLACEMENT 1 +- +-/* Sets or returns a value associated with a buffer. */ +-struct drm_amdgpu_gem_op { +- /** GEM object handle */ +- uint32_t handle; +- /** AMDGPU_GEM_OP_* */ +- uint32_t op; +- /** Input or return value */ +- uint64_t value; +-}; +- +-#define AMDGPU_VA_OP_MAP 1 +-#define AMDGPU_VA_OP_UNMAP 2 +- +-/* Delay the page table update till the next CS */ +-#define AMDGPU_VM_DELAY_UPDATE (1 << 0) +- +-/* Mapping flags */ +-/* readable mapping */ +-#define AMDGPU_VM_PAGE_READABLE (1 << 1) +-/* writable mapping */ +-#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) +-/* executable mapping, new for VI */ +-#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) +- +-struct drm_amdgpu_gem_va { +- /** GEM object handle */ +- uint32_t handle; +- uint32_t _pad; +- /** AMDGPU_VA_OP_* */ +- uint32_t operation; +- /** AMDGPU_VM_PAGE_* */ +- uint32_t flags; +- /** va address to assign . Must be correctly aligned.*/ +- uint64_t va_address; +- /** Specify offset inside of BO to assign. Must be correctly aligned.*/ +- uint64_t offset_in_bo; +- /** Specify mapping size. Must be correctly aligned. */ +- uint64_t map_size; +-}; +- +-#define AMDGPU_HW_IP_GFX 0 +-#define AMDGPU_HW_IP_COMPUTE 1 +-#define AMDGPU_HW_IP_DMA 2 +-#define AMDGPU_HW_IP_UVD 3 +-#define AMDGPU_HW_IP_VCE 4 +-#define AMDGPU_HW_IP_NUM 5 +- +-#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 +- +-#define AMDGPU_CHUNK_ID_IB 0x01 +-#define AMDGPU_CHUNK_ID_FENCE 0x02 +-#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 +- +-struct drm_amdgpu_cs_chunk { +- uint32_t chunk_id; +- uint32_t length_dw; +- uint64_t chunk_data; +-}; +- +-struct drm_amdgpu_cs_in { +- /** Rendering context id */ +- uint32_t ctx_id; +- /** Handle of resource list associated with CS */ +- uint32_t bo_list_handle; +- uint32_t num_chunks; +- uint32_t _pad; +- /** this points to uint64_t * which point to cs chunks */ +- uint64_t chunks; +-}; +- +-struct drm_amdgpu_cs_out { +- uint64_t handle; +-}; +- +-union drm_amdgpu_cs { +- struct drm_amdgpu_cs_in in; +- struct drm_amdgpu_cs_out out; +-}; +- +-/* Specify flags to be used for IB */ +- +-/* This IB should be submitted to CE */ +-#define AMDGPU_IB_FLAG_CE (1<<0) +- +-/* CE Preamble */ +-#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) +- +-struct drm_amdgpu_cs_chunk_ib { +- uint32_t _pad; +- /** AMDGPU_IB_FLAG_* */ +- uint32_t flags; +- /** Virtual address to begin IB execution */ +- uint64_t va_start; +- /** Size of submission */ +- uint32_t ib_bytes; +- /** HW IP to submit to */ +- uint32_t ip_type; +- /** HW IP index of the same type to submit to */ +- uint32_t ip_instance; +- /** Ring index to submit to */ +- uint32_t ring; +-}; +- +-struct drm_amdgpu_cs_chunk_dep { +- uint32_t ip_type; +- uint32_t ip_instance; +- uint32_t ring; +- uint32_t ctx_id; +- uint64_t handle; +-}; +- +-struct drm_amdgpu_cs_chunk_fence { +- uint32_t handle; +- uint32_t offset; +-}; +- +-struct drm_amdgpu_cs_chunk_data { +- union { +- struct drm_amdgpu_cs_chunk_ib ib_data; +- struct drm_amdgpu_cs_chunk_fence fence_data; +- }; +-}; +- +-/** +- * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU +- * +- */ +-#define AMDGPU_IDS_FLAGS_FUSION 0x1 +- +-/* indicate if acceleration can be working */ +-#define AMDGPU_INFO_ACCEL_WORKING 0x00 +-/* get the crtc_id from the mode object id? */ +-#define AMDGPU_INFO_CRTC_FROM_ID 0x01 +-/* query hw IP info */ +-#define AMDGPU_INFO_HW_IP_INFO 0x02 +-/* query hw IP instance count for the specified type */ +-#define AMDGPU_INFO_HW_IP_COUNT 0x03 +-/* timestamp for GL_ARB_timer_query */ +-#define AMDGPU_INFO_TIMESTAMP 0x05 +-/* Query the firmware version */ +-#define AMDGPU_INFO_FW_VERSION 0x0e +- /* Subquery id: Query VCE firmware version */ +- #define AMDGPU_INFO_FW_VCE 0x1 +- /* Subquery id: Query UVD firmware version */ +- #define AMDGPU_INFO_FW_UVD 0x2 +- /* Subquery id: Query GMC firmware version */ +- #define AMDGPU_INFO_FW_GMC 0x03 +- /* Subquery id: Query GFX ME firmware version */ +- #define AMDGPU_INFO_FW_GFX_ME 0x04 +- /* Subquery id: Query GFX PFP firmware version */ +- #define AMDGPU_INFO_FW_GFX_PFP 0x05 +- /* Subquery id: Query GFX CE firmware version */ +- #define AMDGPU_INFO_FW_GFX_CE 0x06 +- /* Subquery id: Query GFX RLC firmware version */ +- #define AMDGPU_INFO_FW_GFX_RLC 0x07 +- /* Subquery id: Query GFX MEC firmware version */ +- #define AMDGPU_INFO_FW_GFX_MEC 0x08 +- /* Subquery id: Query SMC firmware version */ +- #define AMDGPU_INFO_FW_SMC 0x0a +- /* Subquery id: Query SDMA firmware version */ +- #define AMDGPU_INFO_FW_SDMA 0x0b +-/* number of bytes moved for TTM migration */ +-#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f +-/* the used VRAM size */ +-#define AMDGPU_INFO_VRAM_USAGE 0x10 +-/* the used GTT size */ +-#define AMDGPU_INFO_GTT_USAGE 0x11 +-/* Information about GDS, etc. resource configuration */ +-#define AMDGPU_INFO_GDS_CONFIG 0x13 +-/* Query information about VRAM and GTT domains */ +-#define AMDGPU_INFO_VRAM_GTT 0x14 +-/* Query information about register in MMR address space*/ +-#define AMDGPU_INFO_READ_MMR_REG 0x15 +-/* Query information about device: rev id, family, etc. */ +-#define AMDGPU_INFO_DEV_INFO 0x16 +-/* visible vram usage */ +-#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 +- +-#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 +-#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff +-#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 +-#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff +- +-/* Input structure for the INFO ioctl */ +-struct drm_amdgpu_info { +- /* Where the return value will be stored */ +- uint64_t return_pointer; +- /* The size of the return value. Just like "size" in "snprintf", +- * it limits how many bytes the kernel can write. */ +- uint32_t return_size; +- /* The query request id. */ +- uint32_t query; +- +- union { +- struct { +- uint32_t id; +- uint32_t _pad; +- } mode_crtc; +- +- struct { +- /** AMDGPU_HW_IP_* */ +- uint32_t type; +- /** +- * Index of the IP if there are more IPs of the same +- * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. +- */ +- uint32_t ip_instance; +- } query_hw_ip; +- +- struct { +- uint32_t dword_offset; +- /** number of registers to read */ +- uint32_t count; +- uint32_t instance; +- /** For future use, no flags defined so far */ +- uint32_t flags; +- } read_mmr_reg; +- +- struct { +- /** AMDGPU_INFO_FW_* */ +- uint32_t fw_type; +- /** +- * Index of the IP if there are more IPs of +- * the same type. +- */ +- uint32_t ip_instance; +- /** +- * Index of the engine. Whether this is used depends +- * on the firmware type. (e.g. MEC, SDMA) +- */ +- uint32_t index; +- uint32_t _pad; +- } query_fw; +- }; +-}; +- +-struct drm_amdgpu_info_gds { +- /** GDS GFX partition size */ +- uint32_t gds_gfx_partition_size; +- /** GDS compute partition size */ +- uint32_t compute_partition_size; +- /** total GDS memory size */ +- uint32_t gds_total_size; +- /** GWS size per GFX partition */ +- uint32_t gws_per_gfx_partition; +- /** GSW size per compute partition */ +- uint32_t gws_per_compute_partition; +- /** OA size per GFX partition */ +- uint32_t oa_per_gfx_partition; +- /** OA size per compute partition */ +- uint32_t oa_per_compute_partition; +- uint32_t _pad; +-}; +- +-struct drm_amdgpu_info_vram_gtt { +- uint64_t vram_size; +- uint64_t vram_cpu_accessible_size; +- uint64_t gtt_size; +-}; +- +-struct drm_amdgpu_info_firmware { +- uint32_t ver; +- uint32_t feature; +-}; +- +-#define AMDGPU_VRAM_TYPE_UNKNOWN 0 +-#define AMDGPU_VRAM_TYPE_GDDR1 1 +-#define AMDGPU_VRAM_TYPE_DDR2 2 +-#define AMDGPU_VRAM_TYPE_GDDR3 3 +-#define AMDGPU_VRAM_TYPE_GDDR4 4 +-#define AMDGPU_VRAM_TYPE_GDDR5 5 +-#define AMDGPU_VRAM_TYPE_HBM 6 +-#define AMDGPU_VRAM_TYPE_DDR3 7 +- +-struct drm_amdgpu_info_device { +- /** PCI Device ID */ +- uint32_t device_id; +- /** Internal chip revision: A0, A1, etc.) */ +- uint32_t chip_rev; +- uint32_t external_rev; +- /** Revision id in PCI Config space */ +- uint32_t pci_rev; +- uint32_t family; +- uint32_t num_shader_engines; +- uint32_t num_shader_arrays_per_engine; +- /* in KHz */ +- uint32_t gpu_counter_freq; +- uint64_t max_engine_clock; +- uint64_t max_memory_clock; +- /* cu information */ +- uint32_t cu_active_number; +- uint32_t cu_ao_mask; +- uint32_t cu_bitmap[4][4]; +- /** Render backend pipe mask. One render backend is CB+DB. */ +- uint32_t enabled_rb_pipes_mask; +- uint32_t num_rb_pipes; +- uint32_t num_hw_gfx_contexts; +- uint32_t _pad; +- uint64_t ids_flags; +- /** Starting virtual address for UMDs. */ +- uint64_t virtual_address_offset; +- /** The maximum virtual address */ +- uint64_t virtual_address_max; +- /** Required alignment of virtual addresses. */ +- uint32_t virtual_address_alignment; +- /** Page table entry - fragment size */ +- uint32_t pte_fragment_size; +- uint32_t gart_page_size; +- /** constant engine ram size*/ +- uint32_t ce_ram_size; +- /** video memory type info*/ +- uint32_t vram_type; +- /** video memory bit width*/ +- uint32_t vram_bit_width; +- /* vce harvesting instance */ +- uint32_t vce_harvest_config; +-}; +- +-struct drm_amdgpu_info_hw_ip { +- /** Version of h/w IP */ +- uint32_t hw_ip_version_major; +- uint32_t hw_ip_version_minor; +- /** Capabilities */ +- uint64_t capabilities_flags; +- /** command buffer address start alignment*/ +- uint32_t ib_start_alignment; +- /** command buffer size alignment*/ +- uint32_t ib_size_alignment; +- /** Bitmask of available rings. Bit 0 means ring 0, etc. */ +- uint32_t available_rings; +- uint32_t _pad; +-}; +- +-/* +- * Supported GPU families +- */ +-#define AMDGPU_FAMILY_UNKNOWN 0 +-#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ +-#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ +-#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ +-#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ +- +-struct drm_amdgpu_freesync { +- __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ +- /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ +- __u32 spare[7]; +-}; +- +-#endif +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1120-fix-amdgpu_drm.h-include-problem.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1120-fix-amdgpu_drm.h-include-problem.patch new file mode 100644 index 00000000..820c021e --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1120-fix-amdgpu_drm.h-include-problem.patch @@ -0,0 +1,51 @@ +From e194f8487e72796b41916e5df38658ee891d0007 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Wed, 28 Sep 2016 14:57:00 +0530 +Subject: [PATCH] fix amdgpu_drm.h include problem. + +Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> +Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/Makefile | 2 ++ + drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 2 +- + include/uapi/drm/amdgpu_drm.h | 1 + + 3 files changed, 4 insertions(+), 1 deletion(-) + create mode 100644 include/uapi/drm/amdgpu_drm.h + +diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile +index 215f8fc..28e8e4c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/Makefile ++++ b/drivers/gpu/drm/amd/amdgpu/Makefile +@@ -17,6 +17,8 @@ ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \ + -I$(FULL_AMD_DAL_PATH)/dc \ + -I$(FULL_AMD_DAL_PATH)/amdgpu_dm + ++LINUXINCLUDE := -I$(FULL_AMD_PATH)/include/uapi $(LINUXINCLUDE) ++ + amdgpu-y := amdgpu_drv.o + + # add KMS driver +diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +index c84f977..17c7d3f 100644 +--- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h ++++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +@@ -32,7 +32,7 @@ + #ifndef __AMDGPU_DRM_H__ + #define __AMDGPU_DRM_H__ + +-#include "drm.h" ++#include <drm/drm.h> + + #define DRM_AMDGPU_GEM_CREATE 0x00 + #define DRM_AMDGPU_GEM_MMAP 0x01 +diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h +new file mode 100644 +index 0000000..22890bb +--- /dev/null ++++ b/include/uapi/drm/amdgpu_drm.h +@@ -0,0 +1 @@ ++#include "../../../drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h" +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1121-add-the-interface-of-waiting-multiple-fences-v2.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1121-add-the-interface-of-waiting-multiple-fences-v2.patch new file mode 100644 index 00000000..1502ec44 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1121-add-the-interface-of-waiting-multiple-fences-v2.patch @@ -0,0 +1,281 @@ +From 5f2af20ad85a19ddbdd1ea7b63b0f21ac499ed88 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Mon, 19 Sep 2016 12:31:46 +0530 +Subject: [PATCH 11/12] add the interface of waiting multiple fences (v2) + +v2: agd: rebase and squash in all the previous optimizations and +changes so everything compiles. + +Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> +Reviewed-by: Monk Liu <monk.liu@amd.com> +Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 171 ++++++++++++++++++++++ + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 + + drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 27 ++++ + 4 files changed, 201 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index 28f8481..b15b3b5 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1861,6 +1861,8 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); + int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); ++int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *filp); + + int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +index f983846..0d1346c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +@@ -1021,6 +1021,177 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, + } + + /** ++ * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence ++ * ++ * @adev: amdgpu device ++ * @filp: file private ++ * @user: drm_amdgpu_fence copied from user space ++ */ ++static struct fence *amdgpu_cs_get_fence(struct amdgpu_device *adev, ++ struct drm_file *filp, ++ struct drm_amdgpu_fence *user) ++{ ++ struct amdgpu_ring *ring; ++ struct amdgpu_ctx *ctx; ++ struct fence *fence; ++ int r; ++ ++ r = amdgpu_cs_get_ring(adev, user->ip_type, user->ip_instance, ++ user->ring, &ring); ++ if (r) ++ return ERR_PTR(r); ++ ++ ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id); ++ if (ctx == NULL) ++ return ERR_PTR(-EINVAL); ++ ++ fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no); ++ amdgpu_ctx_put(ctx); ++ ++ return fence; ++} ++ ++/** ++ * amdgpu_cs_wait_all_fence - wait on all fences to signal ++ * ++ * @adev: amdgpu device ++ * @filp: file private ++ * @wait: wait parameters ++ * @fences: array of drm_amdgpu_fence ++ */ ++static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev, ++ struct drm_file *filp, ++ union drm_amdgpu_wait_fences *wait, ++ struct drm_amdgpu_fence *fences) ++{ ++ uint32_t fence_count = wait->in.fence_count; ++ unsigned i; ++ long r = 1; ++ ++ for (i = 0; i < fence_count; i++) { ++ struct fence *fence; ++ unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns); ++ ++ fence = amdgpu_cs_get_fence(adev, filp, &fences[i]); ++ if (IS_ERR(fence)) ++ return PTR_ERR(fence); ++ else if (!fence) ++ continue; ++ ++ r = fence_wait_timeout(fence, true, timeout); ++ if (r < 0) ++ return r; ++ ++ if (r == 0) ++ break; ++ } ++ ++ memset(wait, 0, sizeof(*wait)); ++ wait->out.status = (r > 0); ++ ++ return 0; ++} ++ ++/** ++ * amdgpu_cs_wait_any_fence - wait on any fence to signal ++ * ++ * @adev: amdgpu device ++ * @filp: file private ++ * @wait: wait parameters ++ * @fences: array of drm_amdgpu_fence ++ */ ++static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev, ++ struct drm_file *filp, ++ union drm_amdgpu_wait_fences *wait, ++ struct drm_amdgpu_fence *fences) ++{ ++ unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns); ++ uint32_t fence_count = wait->in.fence_count; ++ struct fence **array; ++ unsigned i; ++ long r; ++ ++ /* Prepare the fence array */ ++ array = (struct fence **)kcalloc(fence_count, sizeof(struct fence *), ++ GFP_KERNEL); ++ if (array == NULL) ++ return -ENOMEM; ++ ++ for (i = 0; i < fence_count; i++) { ++ struct fence *fence; ++ ++ fence = amdgpu_cs_get_fence(adev, filp, &fences[i]); ++ if (IS_ERR(fence)) { ++ r = PTR_ERR(fence); ++ goto err_free_fence_array; ++ } else if (fence) { ++ array[i] = fence; ++ } else { /* NULL, the fence has been already signaled */ ++ r = 1; ++ goto out; ++ } ++ } ++ ++ r = fence_wait_any_timeout(array, fence_count, true, timeout); ++ if (r < 0) ++ goto err_free_fence_array; ++ ++out: ++ memset(wait, 0, sizeof(*wait)); ++ wait->out.status = (r > 0); ++ /* set return value 0 to indicate success */ ++ r = 0; ++ ++err_free_fence_array: ++ for (i = 0; i < fence_count; i++) ++ fence_put(array[i]); ++ kfree(array); ++ ++ return r; ++} ++ ++/** ++ * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish ++ * ++ * @dev: drm device ++ * @data: data from userspace ++ * @filp: file private ++ */ ++int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *filp) ++{ ++ struct amdgpu_device *adev = dev->dev_private; ++ union drm_amdgpu_wait_fences *wait = data; ++ uint32_t fence_count = wait->in.fence_count; ++ struct drm_amdgpu_fence *fences_user; ++ struct drm_amdgpu_fence *fences; ++ int r; ++ ++ /* Get the fences from userspace */ ++ fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence), ++ GFP_KERNEL); ++ if (fences == NULL) ++ return -ENOMEM; ++ ++ fences_user = (void __user *)wait->in.fences; ++ if (copy_from_user(fences, fences_user, ++ sizeof(struct drm_amdgpu_fence) * fence_count)) { ++ r = -EFAULT; ++ goto err_free_fences; ++ } ++ ++ if (wait->in.wait_all) ++ r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences); ++ else ++ r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences); ++ ++err_free_fences: ++ kfree(fences); ++ ++ return r; ++} ++ ++/** + * amdgpu_cs_find_bo_va - find bo_va for VM address + * + * @parser: command submission parser context +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +index b6de8d5..3ce4ee3 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +@@ -749,6 +749,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { + DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), ++ DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), +diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +index 17c7d3f..8ff615b 100644 +--- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h ++++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +@@ -46,6 +46,7 @@ + #define DRM_AMDGPU_WAIT_CS 0x09 + #define DRM_AMDGPU_GEM_OP 0x10 + #define DRM_AMDGPU_GEM_USERPTR 0x11 ++#define DRM_AMDGPU_WAIT_FENCES 0x12 + #define DRM_AMDGPU_FREESYNC 0x14 + + #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) +@@ -60,6 +61,7 @@ + #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) + #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) + #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) ++#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) + #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) + + #define AMDGPU_GEM_DOMAIN_CPU 0x1 +@@ -301,6 +303,31 @@ union drm_amdgpu_wait_cs { + struct drm_amdgpu_wait_cs_out out; + }; + ++struct drm_amdgpu_fence { ++ uint32_t ctx_id; ++ uint32_t ip_type; ++ uint32_t ip_instance; ++ uint32_t ring; ++ uint64_t seq_no; ++}; ++ ++struct drm_amdgpu_wait_fences_in { ++ /** This points to uint64_t * which points to fences */ ++ uint64_t fences; ++ uint32_t fence_count; ++ uint32_t wait_all; ++ uint64_t timeout_ns; ++}; ++ ++struct drm_amdgpu_wait_fences_out { ++ uint64_t status; ++}; ++ ++union drm_amdgpu_wait_fences { ++ struct drm_amdgpu_wait_fences_in in; ++ struct drm_amdgpu_wait_fences_out out; ++}; ++ + #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 + #define AMDGPU_GEM_OP_SET_PLACEMENT 1 + +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1122-Fix-for-vulkan-decode-fail.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1122-Fix-for-vulkan-decode-fail.patch new file mode 100644 index 00000000..3ced8ac3 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1122-Fix-for-vulkan-decode-fail.patch @@ -0,0 +1,44 @@ +From b9951504af58c2ffefb7bcf9f420653414328fa4 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@.com> +Date: Wed, 21 Sep 2016 15:51:08 +0530 +Subject: [PATCH 12/12] Fix for vulkan decode fail + +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +index f14e4aa..849c795 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +@@ -247,6 +247,26 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) + if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) + adev->uvd.address_64_bit = true; + ++ ++ switch (adev->asic_type) { ++ case CHIP_TONGA: ++ adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; ++ break; ++ case CHIP_CARRIZO: ++ adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; ++ break; ++ case CHIP_FIJI: ++ adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; ++ break; ++ case CHIP_STONEY: ++ adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; ++ break; ++ default: ++ adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; ++ ++ } ++ ++ + return 0; + } + +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1123-ioctl-number-modified-DRM_AMDGPU_WAIT_FENCES.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1123-ioctl-number-modified-DRM_AMDGPU_WAIT_FENCES.patch new file mode 100644 index 00000000..99b4d727 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1123-ioctl-number-modified-DRM_AMDGPU_WAIT_FENCES.patch @@ -0,0 +1,28 @@ +From 26488f88527f81632b56e978af744f7d697a6e06 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <Sanju.Mehta@amd.com> +Date: Tue, 27 Sep 2016 17:28:00 +0530 +Subject: [PATCH] ioctl number modified DRM_AMDGPU_WAIT_FENCES + +--- + drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +index 8ff615b..ada6576 100644 +--- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h ++++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +@@ -46,9 +46,10 @@ + #define DRM_AMDGPU_WAIT_CS 0x09 + #define DRM_AMDGPU_GEM_OP 0x10 + #define DRM_AMDGPU_GEM_USERPTR 0x11 +-#define DRM_AMDGPU_WAIT_FENCES 0x12 + #define DRM_AMDGPU_FREESYNC 0x14 + ++#define DRM_AMDGPU_WAIT_FENCES 0x5e ++ + #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) + #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) + #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1124-add-amdgpu.cg_mask-and-amdgpu.pg_mask-parameters.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1124-add-amdgpu.cg_mask-and-amdgpu.pg_mask-parameters.patch new file mode 100644 index 00000000..ff18aa48 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1124-add-amdgpu.cg_mask-and-amdgpu.pg_mask-parameters.patch @@ -0,0 +1,77 @@ +From b6dadf7dceff70f8a09cf57fe7f1aa29427f764f Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Thu, 13 Oct 2016 12:52:22 +0530 +Subject: [PATCH 1/2] add amdgpu.cg_mask and amdgpu.pg_mask parameters +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +They allow disabling clock and power gating from the kernel command line, +which hopefully helps with diagnosing problems in the field. + +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Nicolai Hähnle <Nicolai.Haehnle@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++++ + 3 files changed, 13 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index b15b3b5..d3de21d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -89,6 +89,8 @@ extern int amdgpu_sched_hw_submission; + extern int amdgpu_powerplay; + extern unsigned amdgpu_pcie_gen_cap; + extern unsigned amdgpu_pcie_lane_cap; ++extern unsigned amdgpu_cg_mask; ++extern unsigned amdgpu_pg_mask; + + #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 + #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 6077ec6..ba5a67b 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1208,6 +1208,9 @@ static int amdgpu_early_init(struct amdgpu_device *adev) + } + } + ++ adev->cg_flags &= amdgpu_cg_mask; ++ adev->pg_flags &= amdgpu_pg_mask; ++ + return 0; + } + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +index af014c3..340d5fd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +@@ -83,6 +83,8 @@ int amdgpu_sched_hw_submission = 2; + int amdgpu_powerplay = -1; + unsigned amdgpu_pcie_gen_cap = 0; + unsigned amdgpu_pcie_lane_cap = 0; ++unsigned amdgpu_cg_mask = 0xffffffff; ++unsigned amdgpu_pg_mask = 0xffffffff; + + MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); + module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); +@@ -170,6 +172,12 @@ module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); + MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); + module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); + ++MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); ++module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); ++ ++MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); ++module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); ++ + static const struct pci_device_id pciidlist[] = { + #ifdef CONFIG_DRM_AMDGPU_CIK + /* Kaveri */ +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1125-drm-amdgpu-gfx8-disable-EDC.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1125-drm-amdgpu-gfx8-disable-EDC.patch new file mode 100644 index 00000000..2b51de5e --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1125-drm-amdgpu-gfx8-disable-EDC.patch @@ -0,0 +1,42 @@ +From b8e93c19d2aaa3d0f48a802dd779ca27e66236d2 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Thu, 13 Oct 2016 12:30:35 +0530 +Subject: [PATCH 2/2] drm/amdgpu/gfx8: disable EDC + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 92f3ee6..c5a3d04 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -1700,6 +1700,11 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) + goto fail; + } + ++ /* read back registers to clear the counters */ ++ for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) ++ RREG32(sec_ded_counter_registers[i]); ++ ++#if 0 + tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2); + tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1); + WREG32(mmGB_EDC_MODE, tmp); +@@ -1708,10 +1713,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) + tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1; + WREG32(mmCC_GC_EDC_CONFIG, tmp); + +- +- /* read back registers to clear the counters */ +- for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) +- RREG32(sec_ded_counter_registers[i]); ++#endif + + fail: + fence_put(f); +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1126-ASoC-AMD-add-ACP-2.2-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1126-ASoC-AMD-add-ACP-2.2-register-headers.patch new file mode 100644 index 00000000..d625d781 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1126-ASoC-AMD-add-ACP-2.2-register-headers.patch @@ -0,0 +1,4049 @@ +From dd2944623f22469b05842032d161e522c1fca725 Mon Sep 17 00:00:00 2001 +From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> +Date: Fri, 18 Sep 2015 13:11:22 +0530 +Subject: [PATCH 01/17] ASoC : AMD : add ACP 2.2 register headers + +These are register headers for the ACP (Audio CoProcessor) v2.2 + +Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + drivers/base/power/domain.c | 2 + + include/sound/designware_i2s.h | 6 + + sound/soc/amd/include/acp_2_2_d.h | 609 ++++++++ + sound/soc/amd/include/acp_2_2_enum.h | 1068 ++++++++++++++ + sound/soc/amd/include/acp_2_2_sh_mask.h | 2292 +++++++++++++++++++++++++++++++ + 5 files changed, 3977 insertions(+) + create mode 100644 sound/soc/amd/include/acp_2_2_d.h + create mode 100644 sound/soc/amd/include/acp_2_2_enum.h + create mode 100644 sound/soc/amd/include/acp_2_2_sh_mask.h + +diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c +index a48824d..ac913f8 100644 +--- a/drivers/base/power/domain.c ++++ b/drivers/base/power/domain.c +@@ -1263,6 +1263,7 @@ int __pm_genpd_add_device(struct generic_pm_domain *genpd, struct device *dev, + + return ret; + } ++EXPORT_SYMBOL_GPL(__pm_genpd_add_device); + + /** + * pm_genpd_remove_device - Remove a device from an I/O PM domain. +@@ -1313,6 +1314,7 @@ int pm_genpd_remove_device(struct generic_pm_domain *genpd, + + return ret; + } ++EXPORT_SYMBOL_GPL(pm_genpd_remove_device); + + /** + * pm_genpd_add_subdomain - Add a subdomain to an I/O PM domain. +diff --git a/include/sound/designware_i2s.h b/include/sound/designware_i2s.h +index 8966ba7..f919a9b 100644 +--- a/include/sound/designware_i2s.h ++++ b/include/sound/designware_i2s.h +@@ -45,6 +45,12 @@ struct i2s_platform_data { + u32 snd_fmts; + u32 snd_rates; + ++ #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0) ++ #define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1) ++ unsigned int quirks; ++ unsigned int i2s_reg_comp1; ++ unsigned int i2s_reg_comp2; ++ + void *play_dma_data; + void *capture_dma_data; + bool (*filter)(struct dma_chan *chan, void *slave); +diff --git a/sound/soc/amd/include/acp_2_2_d.h b/sound/soc/amd/include/acp_2_2_d.h +new file mode 100644 +index 0000000..0118fe9 +--- /dev/null ++++ b/sound/soc/amd/include/acp_2_2_d.h +@@ -0,0 +1,609 @@ ++/* ++ * ACP_2_2 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef ACP_2_2_D_H ++#define ACP_2_2_D_H ++ ++#define mmACP_DMA_CNTL_0 0x5000 ++#define mmACP_DMA_CNTL_1 0x5001 ++#define mmACP_DMA_CNTL_2 0x5002 ++#define mmACP_DMA_CNTL_3 0x5003 ++#define mmACP_DMA_CNTL_4 0x5004 ++#define mmACP_DMA_CNTL_5 0x5005 ++#define mmACP_DMA_CNTL_6 0x5006 ++#define mmACP_DMA_CNTL_7 0x5007 ++#define mmACP_DMA_CNTL_8 0x5008 ++#define mmACP_DMA_CNTL_9 0x5009 ++#define mmACP_DMA_CNTL_10 0x500a ++#define mmACP_DMA_CNTL_11 0x500b ++#define mmACP_DMA_CNTL_12 0x500c ++#define mmACP_DMA_CNTL_13 0x500d ++#define mmACP_DMA_CNTL_14 0x500e ++#define mmACP_DMA_CNTL_15 0x500f ++#define mmACP_DMA_DSCR_STRT_IDX_0 0x5010 ++#define mmACP_DMA_DSCR_STRT_IDX_1 0x5011 ++#define mmACP_DMA_DSCR_STRT_IDX_2 0x5012 ++#define mmACP_DMA_DSCR_STRT_IDX_3 0x5013 ++#define mmACP_DMA_DSCR_STRT_IDX_4 0x5014 ++#define mmACP_DMA_DSCR_STRT_IDX_5 0x5015 ++#define mmACP_DMA_DSCR_STRT_IDX_6 0x5016 ++#define mmACP_DMA_DSCR_STRT_IDX_7 0x5017 ++#define mmACP_DMA_DSCR_STRT_IDX_8 0x5018 ++#define mmACP_DMA_DSCR_STRT_IDX_9 0x5019 ++#define mmACP_DMA_DSCR_STRT_IDX_10 0x501a ++#define mmACP_DMA_DSCR_STRT_IDX_11 0x501b ++#define mmACP_DMA_DSCR_STRT_IDX_12 0x501c ++#define mmACP_DMA_DSCR_STRT_IDX_13 0x501d ++#define mmACP_DMA_DSCR_STRT_IDX_14 0x501e ++#define mmACP_DMA_DSCR_STRT_IDX_15 0x501f ++#define mmACP_DMA_DSCR_CNT_0 0x5020 ++#define mmACP_DMA_DSCR_CNT_1 0x5021 ++#define mmACP_DMA_DSCR_CNT_2 0x5022 ++#define mmACP_DMA_DSCR_CNT_3 0x5023 ++#define mmACP_DMA_DSCR_CNT_4 0x5024 ++#define mmACP_DMA_DSCR_CNT_5 0x5025 ++#define mmACP_DMA_DSCR_CNT_6 0x5026 ++#define mmACP_DMA_DSCR_CNT_7 0x5027 ++#define mmACP_DMA_DSCR_CNT_8 0x5028 ++#define mmACP_DMA_DSCR_CNT_9 0x5029 ++#define mmACP_DMA_DSCR_CNT_10 0x502a ++#define mmACP_DMA_DSCR_CNT_11 0x502b ++#define mmACP_DMA_DSCR_CNT_12 0x502c ++#define mmACP_DMA_DSCR_CNT_13 0x502d ++#define mmACP_DMA_DSCR_CNT_14 0x502e ++#define mmACP_DMA_DSCR_CNT_15 0x502f ++#define mmACP_DMA_PRIO_0 0x5030 ++#define mmACP_DMA_PRIO_1 0x5031 ++#define mmACP_DMA_PRIO_2 0x5032 ++#define mmACP_DMA_PRIO_3 0x5033 ++#define mmACP_DMA_PRIO_4 0x5034 ++#define mmACP_DMA_PRIO_5 0x5035 ++#define mmACP_DMA_PRIO_6 0x5036 ++#define mmACP_DMA_PRIO_7 0x5037 ++#define mmACP_DMA_PRIO_8 0x5038 ++#define mmACP_DMA_PRIO_9 0x5039 ++#define mmACP_DMA_PRIO_10 0x503a ++#define mmACP_DMA_PRIO_11 0x503b ++#define mmACP_DMA_PRIO_12 0x503c ++#define mmACP_DMA_PRIO_13 0x503d ++#define mmACP_DMA_PRIO_14 0x503e ++#define mmACP_DMA_PRIO_15 0x503f ++#define mmACP_DMA_CUR_DSCR_0 0x5040 ++#define mmACP_DMA_CUR_DSCR_1 0x5041 ++#define mmACP_DMA_CUR_DSCR_2 0x5042 ++#define mmACP_DMA_CUR_DSCR_3 0x5043 ++#define mmACP_DMA_CUR_DSCR_4 0x5044 ++#define mmACP_DMA_CUR_DSCR_5 0x5045 ++#define mmACP_DMA_CUR_DSCR_6 0x5046 ++#define mmACP_DMA_CUR_DSCR_7 0x5047 ++#define mmACP_DMA_CUR_DSCR_8 0x5048 ++#define mmACP_DMA_CUR_DSCR_9 0x5049 ++#define mmACP_DMA_CUR_DSCR_10 0x504a ++#define mmACP_DMA_CUR_DSCR_11 0x504b ++#define mmACP_DMA_CUR_DSCR_12 0x504c ++#define mmACP_DMA_CUR_DSCR_13 0x504d ++#define mmACP_DMA_CUR_DSCR_14 0x504e ++#define mmACP_DMA_CUR_DSCR_15 0x504f ++#define mmACP_DMA_CUR_TRANS_CNT_0 0x5050 ++#define mmACP_DMA_CUR_TRANS_CNT_1 0x5051 ++#define mmACP_DMA_CUR_TRANS_CNT_2 0x5052 ++#define mmACP_DMA_CUR_TRANS_CNT_3 0x5053 ++#define mmACP_DMA_CUR_TRANS_CNT_4 0x5054 ++#define mmACP_DMA_CUR_TRANS_CNT_5 0x5055 ++#define mmACP_DMA_CUR_TRANS_CNT_6 0x5056 ++#define mmACP_DMA_CUR_TRANS_CNT_7 0x5057 ++#define mmACP_DMA_CUR_TRANS_CNT_8 0x5058 ++#define mmACP_DMA_CUR_TRANS_CNT_9 0x5059 ++#define mmACP_DMA_CUR_TRANS_CNT_10 0x505a ++#define mmACP_DMA_CUR_TRANS_CNT_11 0x505b ++#define mmACP_DMA_CUR_TRANS_CNT_12 0x505c ++#define mmACP_DMA_CUR_TRANS_CNT_13 0x505d ++#define mmACP_DMA_CUR_TRANS_CNT_14 0x505e ++#define mmACP_DMA_CUR_TRANS_CNT_15 0x505f ++#define mmACP_DMA_ERR_STS_0 0x5060 ++#define mmACP_DMA_ERR_STS_1 0x5061 ++#define mmACP_DMA_ERR_STS_2 0x5062 ++#define mmACP_DMA_ERR_STS_3 0x5063 ++#define mmACP_DMA_ERR_STS_4 0x5064 ++#define mmACP_DMA_ERR_STS_5 0x5065 ++#define mmACP_DMA_ERR_STS_6 0x5066 ++#define mmACP_DMA_ERR_STS_7 0x5067 ++#define mmACP_DMA_ERR_STS_8 0x5068 ++#define mmACP_DMA_ERR_STS_9 0x5069 ++#define mmACP_DMA_ERR_STS_10 0x506a ++#define mmACP_DMA_ERR_STS_11 0x506b ++#define mmACP_DMA_ERR_STS_12 0x506c ++#define mmACP_DMA_ERR_STS_13 0x506d ++#define mmACP_DMA_ERR_STS_14 0x506e ++#define mmACP_DMA_ERR_STS_15 0x506f ++#define mmACP_DMA_DESC_BASE_ADDR 0x5070 ++#define mmACP_DMA_DESC_MAX_NUM_DSCR 0x5071 ++#define mmACP_DMA_CH_STS 0x5072 ++#define mmACP_DMA_CH_GROUP 0x5073 ++#define mmACP_DSP0_CACHE_OFFSET0 0x5078 ++#define mmACP_DSP0_CACHE_SIZE0 0x5079 ++#define mmACP_DSP0_CACHE_OFFSET1 0x507a ++#define mmACP_DSP0_CACHE_SIZE1 0x507b ++#define mmACP_DSP0_CACHE_OFFSET2 0x507c ++#define mmACP_DSP0_CACHE_SIZE2 0x507d ++#define mmACP_DSP0_CACHE_OFFSET3 0x507e ++#define mmACP_DSP0_CACHE_SIZE3 0x507f ++#define mmACP_DSP0_CACHE_OFFSET4 0x5080 ++#define mmACP_DSP0_CACHE_SIZE4 0x5081 ++#define mmACP_DSP0_CACHE_OFFSET5 0x5082 ++#define mmACP_DSP0_CACHE_SIZE5 0x5083 ++#define mmACP_DSP0_CACHE_OFFSET6 0x5084 ++#define mmACP_DSP0_CACHE_SIZE6 0x5085 ++#define mmACP_DSP0_CACHE_OFFSET7 0x5086 ++#define mmACP_DSP0_CACHE_SIZE7 0x5087 ++#define mmACP_DSP0_CACHE_OFFSET8 0x5088 ++#define mmACP_DSP0_CACHE_SIZE8 0x5089 ++#define mmACP_DSP0_NONCACHE_OFFSET0 0x508a ++#define mmACP_DSP0_NONCACHE_SIZE0 0x508b ++#define mmACP_DSP0_NONCACHE_OFFSET1 0x508c ++#define mmACP_DSP0_NONCACHE_SIZE1 0x508d ++#define mmACP_DSP0_DEBUG_PC 0x508e ++#define mmACP_DSP0_NMI_SEL 0x508f ++#define mmACP_DSP0_CLKRST_CNTL 0x5090 ++#define mmACP_DSP0_RUNSTALL 0x5091 ++#define mmACP_DSP0_OCD_HALT_ON_RST 0x5092 ++#define mmACP_DSP0_WAIT_MODE 0x5093 ++#define mmACP_DSP0_VECT_SEL 0x5094 ++#define mmACP_DSP0_DEBUG_REG1 0x5095 ++#define mmACP_DSP0_DEBUG_REG2 0x5096 ++#define mmACP_DSP0_DEBUG_REG3 0x5097 ++#define mmACP_DSP1_CACHE_OFFSET0 0x509d ++#define mmACP_DSP1_CACHE_SIZE0 0x509e ++#define mmACP_DSP1_CACHE_OFFSET1 0x509f ++#define mmACP_DSP1_CACHE_SIZE1 0x50a0 ++#define mmACP_DSP1_CACHE_OFFSET2 0x50a1 ++#define mmACP_DSP1_CACHE_SIZE2 0x50a2 ++#define mmACP_DSP1_CACHE_OFFSET3 0x50a3 ++#define mmACP_DSP1_CACHE_SIZE3 0x50a4 ++#define mmACP_DSP1_CACHE_OFFSET4 0x50a5 ++#define mmACP_DSP1_CACHE_SIZE4 0x50a6 ++#define mmACP_DSP1_CACHE_OFFSET5 0x50a7 ++#define mmACP_DSP1_CACHE_SIZE5 0x50a8 ++#define mmACP_DSP1_CACHE_OFFSET6 0x50a9 ++#define mmACP_DSP1_CACHE_SIZE6 0x50aa ++#define mmACP_DSP1_CACHE_OFFSET7 0x50ab ++#define mmACP_DSP1_CACHE_SIZE7 0x50ac ++#define mmACP_DSP1_CACHE_OFFSET8 0x50ad ++#define mmACP_DSP1_CACHE_SIZE8 0x50ae ++#define mmACP_DSP1_NONCACHE_OFFSET0 0x50af ++#define mmACP_DSP1_NONCACHE_SIZE0 0x50b0 ++#define mmACP_DSP1_NONCACHE_OFFSET1 0x50b1 ++#define mmACP_DSP1_NONCACHE_SIZE1 0x50b2 ++#define mmACP_DSP1_DEBUG_PC 0x50b3 ++#define mmACP_DSP1_NMI_SEL 0x50b4 ++#define mmACP_DSP1_CLKRST_CNTL 0x50b5 ++#define mmACP_DSP1_RUNSTALL 0x50b6 ++#define mmACP_DSP1_OCD_HALT_ON_RST 0x50b7 ++#define mmACP_DSP1_WAIT_MODE 0x50b8 ++#define mmACP_DSP1_VECT_SEL 0x50b9 ++#define mmACP_DSP1_DEBUG_REG1 0x50ba ++#define mmACP_DSP1_DEBUG_REG2 0x50bb ++#define mmACP_DSP1_DEBUG_REG3 0x50bc ++#define mmACP_DSP2_CACHE_OFFSET0 0x50c2 ++#define mmACP_DSP2_CACHE_SIZE0 0x50c3 ++#define mmACP_DSP2_CACHE_OFFSET1 0x50c4 ++#define mmACP_DSP2_CACHE_SIZE1 0x50c5 ++#define mmACP_DSP2_CACHE_OFFSET2 0x50c6 ++#define mmACP_DSP2_CACHE_SIZE2 0x50c7 ++#define mmACP_DSP2_CACHE_OFFSET3 0x50c8 ++#define mmACP_DSP2_CACHE_SIZE3 0x50c9 ++#define mmACP_DSP2_CACHE_OFFSET4 0x50ca ++#define mmACP_DSP2_CACHE_SIZE4 0x50cb ++#define mmACP_DSP2_CACHE_OFFSET5 0x50cc ++#define mmACP_DSP2_CACHE_SIZE5 0x50cd ++#define mmACP_DSP2_CACHE_OFFSET6 0x50ce ++#define mmACP_DSP2_CACHE_SIZE6 0x50cf ++#define mmACP_DSP2_CACHE_OFFSET7 0x50d0 ++#define mmACP_DSP2_CACHE_SIZE7 0x50d1 ++#define mmACP_DSP2_CACHE_OFFSET8 0x50d2 ++#define mmACP_DSP2_CACHE_SIZE8 0x50d3 ++#define mmACP_DSP2_NONCACHE_OFFSET0 0x50d4 ++#define mmACP_DSP2_NONCACHE_SIZE0 0x50d5 ++#define mmACP_DSP2_NONCACHE_OFFSET1 0x50d6 ++#define mmACP_DSP2_NONCACHE_SIZE1 0x50d7 ++#define mmACP_DSP2_DEBUG_PC 0x50d8 ++#define mmACP_DSP2_NMI_SEL 0x50d9 ++#define mmACP_DSP2_CLKRST_CNTL 0x50da ++#define mmACP_DSP2_RUNSTALL 0x50db ++#define mmACP_DSP2_OCD_HALT_ON_RST 0x50dc ++#define mmACP_DSP2_WAIT_MODE 0x50dd ++#define mmACP_DSP2_VECT_SEL 0x50de ++#define mmACP_DSP2_DEBUG_REG1 0x50df ++#define mmACP_DSP2_DEBUG_REG2 0x50e0 ++#define mmACP_DSP2_DEBUG_REG3 0x50e1 ++#define mmACP_AXI2DAGB_ONION_CNTL 0x50e7 ++#define mmACP_AXI2DAGB_ONION_ERR_STATUS_WR 0x50e8 ++#define mmACP_AXI2DAGB_ONION_ERR_STATUS_RD 0x50e9 ++#define mmACP_DAGB_Onion_TransPerf_Counter_Control 0x50ea ++#define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Current 0x50eb ++#define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Peak 0x50ec ++#define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Current 0x50ed ++#define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Peak 0x50ee ++#define mmACP_AXI2DAGB_GARLIC_CNTL 0x50f3 ++#define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_WR 0x50f4 ++#define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_RD 0x50f5 ++#define mmACP_DAGB_Garlic_TransPerf_Counter_Control 0x50f6 ++#define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Current 0x50f7 ++#define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak 0x50f8 ++#define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Current 0x50f9 ++#define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak 0x50fa ++#define mmACP_DAGB_PAGE_SIZE_GRP_1 0x50ff ++#define mmACP_DAGB_BASE_ADDR_GRP_1 0x5100 ++#define mmACP_DAGB_PAGE_SIZE_GRP_2 0x5101 ++#define mmACP_DAGB_BASE_ADDR_GRP_2 0x5102 ++#define mmACP_DAGB_PAGE_SIZE_GRP_3 0x5103 ++#define mmACP_DAGB_BASE_ADDR_GRP_3 0x5104 ++#define mmACP_DAGB_PAGE_SIZE_GRP_4 0x5105 ++#define mmACP_DAGB_BASE_ADDR_GRP_4 0x5106 ++#define mmACP_DAGB_PAGE_SIZE_GRP_5 0x5107 ++#define mmACP_DAGB_BASE_ADDR_GRP_5 0x5108 ++#define mmACP_DAGB_PAGE_SIZE_GRP_6 0x5109 ++#define mmACP_DAGB_BASE_ADDR_GRP_6 0x510a ++#define mmACP_DAGB_PAGE_SIZE_GRP_7 0x510b ++#define mmACP_DAGB_BASE_ADDR_GRP_7 0x510c ++#define mmACP_DAGB_PAGE_SIZE_GRP_8 0x510d ++#define mmACP_DAGB_BASE_ADDR_GRP_8 0x510e ++#define mmACP_DAGB_ATU_CTRL 0x510f ++#define mmACP_CONTROL 0x5131 ++#define mmACP_STATUS 0x5133 ++#define mmACP_SOFT_RESET 0x5134 ++#define mmACP_PwrMgmt_CNTL 0x5135 ++#define mmACP_CAC_INDICATOR_CONTROL 0x5136 ++#define mmACP_SMU_MAILBOX 0x5137 ++#define mmACP_FUTURE_REG_SCLK_0 0x5138 ++#define mmACP_FUTURE_REG_SCLK_1 0x5139 ++#define mmACP_FUTURE_REG_SCLK_2 0x513a ++#define mmACP_FUTURE_REG_SCLK_3 0x513b ++#define mmACP_FUTURE_REG_SCLK_4 0x513c ++#define mmACP_DAGB_DEBUG_CNT_ENABLE 0x513d ++#define mmACP_DAGBG_WR_ASK_CNT 0x513e ++#define mmACP_DAGBG_WR_GO_CNT 0x513f ++#define mmACP_DAGBG_WR_EXP_RESP_CNT 0x5140 ++#define mmACP_DAGBG_WR_ACTUAL_RESP_CNT 0x5141 ++#define mmACP_DAGBG_RD_ASK_CNT 0x5142 ++#define mmACP_DAGBG_RD_GO_CNT 0x5143 ++#define mmACP_DAGBG_RD_EXP_RESP_CNT 0x5144 ++#define mmACP_DAGBG_RD_ACTUAL_RESP_CNT 0x5145 ++#define mmACP_DAGBO_WR_ASK_CNT 0x5146 ++#define mmACP_DAGBO_WR_GO_CNT 0x5147 ++#define mmACP_DAGBO_WR_EXP_RESP_CNT 0x5148 ++#define mmACP_DAGBO_WR_ACTUAL_RESP_CNT 0x5149 ++#define mmACP_DAGBO_RD_ASK_CNT 0x514a ++#define mmACP_DAGBO_RD_GO_CNT 0x514b ++#define mmACP_DAGBO_RD_EXP_RESP_CNT 0x514c ++#define mmACP_DAGBO_RD_ACTUAL_RESP_CNT 0x514d ++#define mmACP_BRB_CONTROL 0x5156 ++#define mmACP_EXTERNAL_INTR_ENB 0x5157 ++#define mmACP_EXTERNAL_INTR_CNTL 0x5158 ++#define mmACP_ERROR_SOURCE_STS 0x5159 ++#define mmACP_DSP_SW_INTR_TRIG 0x515a ++#define mmACP_DSP_SW_INTR_CNTL 0x515b ++#define mmACP_DAGBG_TIMEOUT_CNTL 0x515c ++#define mmACP_DAGBO_TIMEOUT_CNTL 0x515d ++#define mmACP_EXTERNAL_INTR_STAT 0x515e ++#define mmACP_DSP_SW_INTR_STAT 0x515f ++#define mmACP_DSP0_INTR_CNTL 0x5160 ++#define mmACP_DSP0_INTR_STAT 0x5161 ++#define mmACP_DSP0_TIMEOUT_CNTL 0x5162 ++#define mmACP_DSP1_INTR_CNTL 0x5163 ++#define mmACP_DSP1_INTR_STAT 0x5164 ++#define mmACP_DSP1_TIMEOUT_CNTL 0x5165 ++#define mmACP_DSP2_INTR_CNTL 0x5166 ++#define mmACP_DSP2_INTR_STAT 0x5167 ++#define mmACP_DSP2_TIMEOUT_CNTL 0x5168 ++#define mmACP_DSP0_EXT_TIMER_CNTL 0x5169 ++#define mmACP_DSP1_EXT_TIMER_CNTL 0x516a ++#define mmACP_DSP2_EXT_TIMER_CNTL 0x516b ++#define mmACP_AXI2DAGB_SEM_0 0x516c ++#define mmACP_AXI2DAGB_SEM_1 0x516d ++#define mmACP_AXI2DAGB_SEM_2 0x516e ++#define mmACP_AXI2DAGB_SEM_3 0x516f ++#define mmACP_AXI2DAGB_SEM_4 0x5170 ++#define mmACP_AXI2DAGB_SEM_5 0x5171 ++#define mmACP_AXI2DAGB_SEM_6 0x5172 ++#define mmACP_AXI2DAGB_SEM_7 0x5173 ++#define mmACP_AXI2DAGB_SEM_8 0x5174 ++#define mmACP_AXI2DAGB_SEM_9 0x5175 ++#define mmACP_AXI2DAGB_SEM_10 0x5176 ++#define mmACP_AXI2DAGB_SEM_11 0x5177 ++#define mmACP_AXI2DAGB_SEM_12 0x5178 ++#define mmACP_AXI2DAGB_SEM_13 0x5179 ++#define mmACP_AXI2DAGB_SEM_14 0x517a ++#define mmACP_AXI2DAGB_SEM_15 0x517b ++#define mmACP_AXI2DAGB_SEM_16 0x517c ++#define mmACP_AXI2DAGB_SEM_17 0x517d ++#define mmACP_AXI2DAGB_SEM_18 0x517e ++#define mmACP_AXI2DAGB_SEM_19 0x517f ++#define mmACP_AXI2DAGB_SEM_20 0x5180 ++#define mmACP_AXI2DAGB_SEM_21 0x5181 ++#define mmACP_AXI2DAGB_SEM_22 0x5182 ++#define mmACP_AXI2DAGB_SEM_23 0x5183 ++#define mmACP_AXI2DAGB_SEM_24 0x5184 ++#define mmACP_AXI2DAGB_SEM_25 0x5185 ++#define mmACP_AXI2DAGB_SEM_26 0x5186 ++#define mmACP_AXI2DAGB_SEM_27 0x5187 ++#define mmACP_AXI2DAGB_SEM_28 0x5188 ++#define mmACP_AXI2DAGB_SEM_29 0x5189 ++#define mmACP_AXI2DAGB_SEM_30 0x518a ++#define mmACP_AXI2DAGB_SEM_31 0x518b ++#define mmACP_AXI2DAGB_SEM_32 0x518c ++#define mmACP_AXI2DAGB_SEM_33 0x518d ++#define mmACP_AXI2DAGB_SEM_34 0x518e ++#define mmACP_AXI2DAGB_SEM_35 0x518f ++#define mmACP_AXI2DAGB_SEM_36 0x5190 ++#define mmACP_AXI2DAGB_SEM_37 0x5191 ++#define mmACP_AXI2DAGB_SEM_38 0x5192 ++#define mmACP_AXI2DAGB_SEM_39 0x5193 ++#define mmACP_AXI2DAGB_SEM_40 0x5194 ++#define mmACP_AXI2DAGB_SEM_41 0x5195 ++#define mmACP_AXI2DAGB_SEM_42 0x5196 ++#define mmACP_AXI2DAGB_SEM_43 0x5197 ++#define mmACP_AXI2DAGB_SEM_44 0x5198 ++#define mmACP_AXI2DAGB_SEM_45 0x5199 ++#define mmACP_AXI2DAGB_SEM_46 0x519a ++#define mmACP_AXI2DAGB_SEM_47 0x519b ++#define mmACP_SRBM_Client_Base_Addr 0x519c ++#define mmACP_SRBM_Client_RDDATA 0x519d ++#define mmACP_SRBM_Cycle_Sts 0x519e ++#define mmACP_SRBM_Targ_Idx_Addr 0x519f ++#define mmACP_SRBM_Targ_Idx_Data 0x51a0 ++#define mmACP_SEMA_ADDR_LOW 0x51a1 ++#define mmACP_SEMA_ADDR_HIGH 0x51a2 ++#define mmACP_SEMA_CMD 0x51a3 ++#define mmACP_SEMA_STS 0x51a4 ++#define mmACP_SEMA_REQ 0x51a5 ++#define mmACP_FW_STATUS 0x51a6 ++#define mmACP_FUTURE_REG_ACLK_0 0x51a7 ++#define mmACP_FUTURE_REG_ACLK_1 0x51a8 ++#define mmACP_FUTURE_REG_ACLK_2 0x51a9 ++#define mmACP_FUTURE_REG_ACLK_3 0x51aa ++#define mmACP_FUTURE_REG_ACLK_4 0x51ab ++#define mmACP_TIMER 0x51ac ++#define mmACP_TIMER_CNTL 0x51ad ++#define mmACP_DSP0_TIMER 0x51ae ++#define mmACP_DSP1_TIMER 0x51af ++#define mmACP_DSP2_TIMER 0x51b0 ++#define mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH 0x51b1 ++#define mmACP_I2S_TRANSMIT_BYTE_CNT_LOW 0x51b2 ++#define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH 0x51b3 ++#define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW 0x51b4 ++#define mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH 0x51b5 ++#define mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW 0x51b6 ++#define mmACP_DSP0_CS_STATE 0x51b7 ++#define mmACP_DSP1_CS_STATE 0x51b8 ++#define mmACP_DSP2_CS_STATE 0x51b9 ++#define mmACP_SCRATCH_REG_BASE_ADDR 0x51ba ++#define mmCC_ACP_EFUSE 0x51c8 ++#define mmACP_PGFSM_RETAIN_REG 0x51c9 ++#define mmACP_PGFSM_CONFIG_REG 0x51ca ++#define mmACP_PGFSM_WRITE_REG 0x51cb ++#define mmACP_PGFSM_READ_REG_0 0x51cc ++#define mmACP_PGFSM_READ_REG_1 0x51cd ++#define mmACP_PGFSM_READ_REG_2 0x51ce ++#define mmACP_PGFSM_READ_REG_3 0x51cf ++#define mmACP_PGFSM_READ_REG_4 0x51d0 ++#define mmACP_PGFSM_READ_REG_5 0x51d1 ++#define mmACP_IP_PGFSM_ENABLE 0x51d2 ++#define mmACP_I2S_PIN_CONFIG 0x51d3 ++#define mmACP_AZALIA_I2S_SELECT 0x51d4 ++#define mmACP_CHIP_PKG_FOR_PAD_ISOLATION 0x51d5 ++#define mmACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL 0x51d6 ++#define mmACP_BT_UART_PAD_SEL 0x51d7 ++#define mmACP_SCRATCH_REG_0 0x52c0 ++#define mmACP_SCRATCH_REG_1 0x52c1 ++#define mmACP_SCRATCH_REG_2 0x52c2 ++#define mmACP_SCRATCH_REG_3 0x52c3 ++#define mmACP_SCRATCH_REG_4 0x52c4 ++#define mmACP_SCRATCH_REG_5 0x52c5 ++#define mmACP_SCRATCH_REG_6 0x52c6 ++#define mmACP_SCRATCH_REG_7 0x52c7 ++#define mmACP_SCRATCH_REG_8 0x52c8 ++#define mmACP_SCRATCH_REG_9 0x52c9 ++#define mmACP_SCRATCH_REG_10 0x52ca ++#define mmACP_SCRATCH_REG_11 0x52cb ++#define mmACP_SCRATCH_REG_12 0x52cc ++#define mmACP_SCRATCH_REG_13 0x52cd ++#define mmACP_SCRATCH_REG_14 0x52ce ++#define mmACP_SCRATCH_REG_15 0x52cf ++#define mmACP_SCRATCH_REG_16 0x52d0 ++#define mmACP_SCRATCH_REG_17 0x52d1 ++#define mmACP_SCRATCH_REG_18 0x52d2 ++#define mmACP_SCRATCH_REG_19 0x52d3 ++#define mmACP_SCRATCH_REG_20 0x52d4 ++#define mmACP_SCRATCH_REG_21 0x52d5 ++#define mmACP_SCRATCH_REG_22 0x52d6 ++#define mmACP_SCRATCH_REG_23 0x52d7 ++#define mmACP_SCRATCH_REG_24 0x52d8 ++#define mmACP_SCRATCH_REG_25 0x52d9 ++#define mmACP_SCRATCH_REG_26 0x52da ++#define mmACP_SCRATCH_REG_27 0x52db ++#define mmACP_SCRATCH_REG_28 0x52dc ++#define mmACP_SCRATCH_REG_29 0x52dd ++#define mmACP_SCRATCH_REG_30 0x52de ++#define mmACP_SCRATCH_REG_31 0x52df ++#define mmACP_SCRATCH_REG_32 0x52e0 ++#define mmACP_SCRATCH_REG_33 0x52e1 ++#define mmACP_SCRATCH_REG_34 0x52e2 ++#define mmACP_SCRATCH_REG_35 0x52e3 ++#define mmACP_SCRATCH_REG_36 0x52e4 ++#define mmACP_SCRATCH_REG_37 0x52e5 ++#define mmACP_SCRATCH_REG_38 0x52e6 ++#define mmACP_SCRATCH_REG_39 0x52e7 ++#define mmACP_SCRATCH_REG_40 0x52e8 ++#define mmACP_SCRATCH_REG_41 0x52e9 ++#define mmACP_SCRATCH_REG_42 0x52ea ++#define mmACP_SCRATCH_REG_43 0x52eb ++#define mmACP_SCRATCH_REG_44 0x52ec ++#define mmACP_SCRATCH_REG_45 0x52ed ++#define mmACP_SCRATCH_REG_46 0x52ee ++#define mmACP_SCRATCH_REG_47 0x52ef ++#define mmACP_VOICE_WAKEUP_ENABLE 0x51e8 ++#define mmACP_VOICE_WAKEUP_STATUS 0x51e9 ++#define mmI2S_VOICE_WAKEUP_LOWER_THRESHOLD 0x51ea ++#define mmI2S_VOICE_WAKEUP_HIGHER_THRESHOLD 0x51eb ++#define mmI2S_VOICE_WAKEUP_NO_OF_SAMPLES 0x51ec ++#define mmI2S_VOICE_WAKEUP_NO_OF_PEAKS 0x51ed ++#define mmI2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS 0x51ee ++#define mmI2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION 0x51ef ++#define mmI2S_VOICE_WAKEUP_DATA_PATH_SWITCH 0x51f0 ++#define mmI2S_VOICE_WAKEUP_DATA_POINTER 0x51f1 ++#define mmI2S_VOICE_WAKEUP_AUTH_MATCH 0x51f2 ++#define mmI2S_VOICE_WAKEUP_8KB_WRAP 0x51f3 ++#define mmACP_I2S_RECEIVED_BYTE_CNT_HIGH 0x51f4 ++#define mmACP_I2S_RECEIVED_BYTE_CNT_LOW 0x51f5 ++#define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH 0x51f6 ++#define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW 0x51f7 ++#define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8 ++#define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9 ++#define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa ++#define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb ++#define mmACP_MEM_DEEP_SLEEP_REQ_LO 0x51fc ++#define mmACP_MEM_DEEP_SLEEP_REQ_HI 0x51fd ++#define mmACP_MEM_DEEP_SLEEP_STS_LO 0x51fe ++#define mmACP_MEM_DEEP_SLEEP_STS_HI 0x51ff ++#define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO 0x5200 ++#define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI 0x5201 ++#define mmACP_MEM_WAKEUP_FROM_SLEEP_LO 0x5202 ++#define mmACP_MEM_WAKEUP_FROM_SLEEP_HI 0x5203 ++#define mmACP_I2SSP_IER 0x5210 ++#define mmACP_I2SSP_IRER 0x5211 ++#define mmACP_I2SSP_ITER 0x5212 ++#define mmACP_I2SSP_CER 0x5213 ++#define mmACP_I2SSP_CCR 0x5214 ++#define mmACP_I2SSP_RXFFR 0x5215 ++#define mmACP_I2SSP_TXFFR 0x5216 ++#define mmACP_I2SSP_LRBR0 0x5218 ++#define mmACP_I2SSP_RRBR0 0x5219 ++#define mmACP_I2SSP_RER0 0x521a ++#define mmACP_I2SSP_TER0 0x521b ++#define mmACP_I2SSP_RCR0 0x521c ++#define mmACP_I2SSP_TCR0 0x521d ++#define mmACP_I2SSP_ISR0 0x521e ++#define mmACP_I2SSP_IMR0 0x521f ++#define mmACP_I2SSP_ROR0 0x5220 ++#define mmACP_I2SSP_TOR0 0x5221 ++#define mmACP_I2SSP_RFCR0 0x5222 ++#define mmACP_I2SSP_TFCR0 0x5223 ++#define mmACP_I2SSP_RFF0 0x5224 ++#define mmACP_I2SSP_TFF0 0x5225 ++#define mmACP_I2SSP_RXDMA 0x5226 ++#define mmACP_I2SSP_RRXDMA 0x5227 ++#define mmACP_I2SSP_TXDMA 0x5228 ++#define mmACP_I2SSP_RTXDMA 0x5229 ++#define mmACP_I2SSP_COMP_PARAM_2 0x522a ++#define mmACP_I2SSP_COMP_PARAM_1 0x522b ++#define mmACP_I2SSP_COMP_VERSION 0x522c ++#define mmACP_I2SSP_COMP_TYPE 0x522d ++#define mmACP_I2SMICSP_IER 0x522e ++#define mmACP_I2SMICSP_IRER 0x522f ++#define mmACP_I2SMICSP_ITER 0x5230 ++#define mmACP_I2SMICSP_CER 0x5231 ++#define mmACP_I2SMICSP_CCR 0x5232 ++#define mmACP_I2SMICSP_RXFFR 0x5233 ++#define mmACP_I2SMICSP_TXFFR 0x5234 ++#define mmACP_I2SMICSP_LRBR0 0x5236 ++#define mmACP_I2SMICSP_RRBR0 0x5237 ++#define mmACP_I2SMICSP_RER0 0x5238 ++#define mmACP_I2SMICSP_TER0 0x5239 ++#define mmACP_I2SMICSP_RCR0 0x523a ++#define mmACP_I2SMICSP_TCR0 0x523b ++#define mmACP_I2SMICSP_ISR0 0x523c ++#define mmACP_I2SMICSP_IMR0 0x523d ++#define mmACP_I2SMICSP_ROR0 0x523e ++#define mmACP_I2SMICSP_TOR0 0x523f ++#define mmACP_I2SMICSP_RFCR0 0x5240 ++#define mmACP_I2SMICSP_TFCR0 0x5241 ++#define mmACP_I2SMICSP_RFF0 0x5242 ++#define mmACP_I2SMICSP_TFF0 0x5243 ++#define mmACP_I2SMICSP_LRBR1 0x5246 ++#define mmACP_I2SMICSP_RRBR1 0x5247 ++#define mmACP_I2SMICSP_RER1 0x5248 ++#define mmACP_I2SMICSP_TER1 0x5249 ++#define mmACP_I2SMICSP_RCR1 0x524a ++#define mmACP_I2SMICSP_TCR1 0x524b ++#define mmACP_I2SMICSP_ISR1 0x524c ++#define mmACP_I2SMICSP_IMR1 0x524d ++#define mmACP_I2SMICSP_ROR1 0x524e ++#define mmACP_I2SMICSP_TOR1 0x524f ++#define mmACP_I2SMICSP_RFCR1 0x5250 ++#define mmACP_I2SMICSP_TFCR1 0x5251 ++#define mmACP_I2SMICSP_RFF1 0x5252 ++#define mmACP_I2SMICSP_TFF1 0x5253 ++#define mmACP_I2SMICSP_RXDMA 0x5254 ++#define mmACP_I2SMICSP_RRXDMA 0x5255 ++#define mmACP_I2SMICSP_TXDMA 0x5256 ++#define mmACP_I2SMICSP_RTXDMA 0x5257 ++#define mmACP_I2SMICSP_COMP_PARAM_2 0x5258 ++#define mmACP_I2SMICSP_COMP_PARAM_1 0x5259 ++#define mmACP_I2SMICSP_COMP_VERSION 0x525a ++#define mmACP_I2SMICSP_COMP_TYPE 0x525b ++#define mmACP_I2SBT_IER 0x525c ++#define mmACP_I2SBT_IRER 0x525d ++#define mmACP_I2SBT_ITER 0x525e ++#define mmACP_I2SBT_CER 0x525f ++#define mmACP_I2SBT_CCR 0x5260 ++#define mmACP_I2SBT_RXFFR 0x5261 ++#define mmACP_I2SBT_TXFFR 0x5262 ++#define mmACP_I2SBT_LRBR0 0x5264 ++#define mmACP_I2SBT_RRBR0 0x5265 ++#define mmACP_I2SBT_RER0 0x5266 ++#define mmACP_I2SBT_TER0 0x5267 ++#define mmACP_I2SBT_RCR0 0x5268 ++#define mmACP_I2SBT_TCR0 0x5269 ++#define mmACP_I2SBT_ISR0 0x526a ++#define mmACP_I2SBT_IMR0 0x526b ++#define mmACP_I2SBT_ROR0 0x526c ++#define mmACP_I2SBT_TOR0 0x526d ++#define mmACP_I2SBT_RFCR0 0x526e ++#define mmACP_I2SBT_TFCR0 0x526f ++#define mmACP_I2SBT_RFF0 0x5270 ++#define mmACP_I2SBT_TFF0 0x5271 ++#define mmACP_I2SBT_LRBR1 0x5274 ++#define mmACP_I2SBT_RRBR1 0x5275 ++#define mmACP_I2SBT_RER1 0x5276 ++#define mmACP_I2SBT_TER1 0x5277 ++#define mmACP_I2SBT_RCR1 0x5278 ++#define mmACP_I2SBT_TCR1 0x5279 ++#define mmACP_I2SBT_ISR1 0x527a ++#define mmACP_I2SBT_IMR1 0x527b ++#define mmACP_I2SBT_ROR1 0x527c ++#define mmACP_I2SBT_TOR1 0x527d ++#define mmACP_I2SBT_RFCR1 0x527e ++#define mmACP_I2SBT_TFCR1 0x527f ++#define mmACP_I2SBT_RFF1 0x5280 ++#define mmACP_I2SBT_TFF1 0x5281 ++#define mmACP_I2SBT_RXDMA 0x5282 ++#define mmACP_I2SBT_RRXDMA 0x5283 ++#define mmACP_I2SBT_TXDMA 0x5284 ++#define mmACP_I2SBT_RTXDMA 0x5285 ++#define mmACP_I2SBT_COMP_PARAM_2 0x5286 ++#define mmACP_I2SBT_COMP_PARAM_1 0x5287 ++#define mmACP_I2SBT_COMP_VERSION 0x5288 ++#define mmACP_I2SBT_COMP_TYPE 0x5289 ++ ++#endif /* ACP_2_2_D_H */ +diff --git a/sound/soc/amd/include/acp_2_2_enum.h b/sound/soc/amd/include/acp_2_2_enum.h +new file mode 100644 +index 0000000..f3577c8 +--- /dev/null ++++ b/sound/soc/amd/include/acp_2_2_enum.h +@@ -0,0 +1,1068 @@ ++/* ++ * ACP_2_2 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef ACP_2_2_ENUM_H ++#define ACP_2_2_ENUM_H ++ ++typedef enum DebugBlockId { ++ DBG_BLOCK_ID_RESERVED = 0x0, ++ DBG_BLOCK_ID_DBG = 0x1, ++ DBG_BLOCK_ID_VMC = 0x2, ++ DBG_BLOCK_ID_PDMA = 0x3, ++ DBG_BLOCK_ID_CG = 0x4, ++ DBG_BLOCK_ID_SRBM = 0x5, ++ DBG_BLOCK_ID_GRBM = 0x6, ++ DBG_BLOCK_ID_RLC = 0x7, ++ DBG_BLOCK_ID_CSC = 0x8, ++ DBG_BLOCK_ID_SEM = 0x9, ++ DBG_BLOCK_ID_IH = 0xa, ++ DBG_BLOCK_ID_SC = 0xb, ++ DBG_BLOCK_ID_SQ = 0xc, ++ DBG_BLOCK_ID_UVDU = 0xd, ++ DBG_BLOCK_ID_SQA = 0xe, ++ DBG_BLOCK_ID_SDMA0 = 0xf, ++ DBG_BLOCK_ID_SDMA1 = 0x10, ++ DBG_BLOCK_ID_SPIM = 0x11, ++ DBG_BLOCK_ID_GDS = 0x12, ++ DBG_BLOCK_ID_VC0 = 0x13, ++ DBG_BLOCK_ID_VC1 = 0x14, ++ DBG_BLOCK_ID_PA0 = 0x15, ++ DBG_BLOCK_ID_PA1 = 0x16, ++ DBG_BLOCK_ID_CP0 = 0x17, ++ DBG_BLOCK_ID_CP1 = 0x18, ++ DBG_BLOCK_ID_CP2 = 0x19, ++ DBG_BLOCK_ID_XBR = 0x1a, ++ DBG_BLOCK_ID_UVDM = 0x1b, ++ DBG_BLOCK_ID_VGT0 = 0x1c, ++ DBG_BLOCK_ID_VGT1 = 0x1d, ++ DBG_BLOCK_ID_IA = 0x1e, ++ DBG_BLOCK_ID_SXM0 = 0x1f, ++ DBG_BLOCK_ID_SXM1 = 0x20, ++ DBG_BLOCK_ID_SCT0 = 0x21, ++ DBG_BLOCK_ID_SCT1 = 0x22, ++ DBG_BLOCK_ID_SPM0 = 0x23, ++ DBG_BLOCK_ID_SPM1 = 0x24, ++ DBG_BLOCK_ID_UNUSED0 = 0x25, ++ DBG_BLOCK_ID_UNUSED1 = 0x26, ++ DBG_BLOCK_ID_TCAA = 0x27, ++ DBG_BLOCK_ID_TCAB = 0x28, ++ DBG_BLOCK_ID_TCCA = 0x29, ++ DBG_BLOCK_ID_TCCB = 0x2a, ++ DBG_BLOCK_ID_MCC0 = 0x2b, ++ DBG_BLOCK_ID_MCC1 = 0x2c, ++ DBG_BLOCK_ID_MCC2 = 0x2d, ++ DBG_BLOCK_ID_MCC3 = 0x2e, ++ DBG_BLOCK_ID_SXS0 = 0x2f, ++ DBG_BLOCK_ID_SXS1 = 0x30, ++ DBG_BLOCK_ID_SXS2 = 0x31, ++ DBG_BLOCK_ID_SXS3 = 0x32, ++ DBG_BLOCK_ID_SXS4 = 0x33, ++ DBG_BLOCK_ID_SXS5 = 0x34, ++ DBG_BLOCK_ID_SXS6 = 0x35, ++ DBG_BLOCK_ID_SXS7 = 0x36, ++ DBG_BLOCK_ID_SXS8 = 0x37, ++ DBG_BLOCK_ID_SXS9 = 0x38, ++ DBG_BLOCK_ID_BCI0 = 0x39, ++ DBG_BLOCK_ID_BCI1 = 0x3a, ++ DBG_BLOCK_ID_BCI2 = 0x3b, ++ DBG_BLOCK_ID_BCI3 = 0x3c, ++ DBG_BLOCK_ID_MCB = 0x3d, ++ DBG_BLOCK_ID_UNUSED6 = 0x3e, ++ DBG_BLOCK_ID_SQA00 = 0x3f, ++ DBG_BLOCK_ID_SQA01 = 0x40, ++ DBG_BLOCK_ID_SQA02 = 0x41, ++ DBG_BLOCK_ID_SQA10 = 0x42, ++ DBG_BLOCK_ID_SQA11 = 0x43, ++ DBG_BLOCK_ID_SQA12 = 0x44, ++ DBG_BLOCK_ID_UNUSED7 = 0x45, ++ DBG_BLOCK_ID_UNUSED8 = 0x46, ++ DBG_BLOCK_ID_SQB00 = 0x47, ++ DBG_BLOCK_ID_SQB01 = 0x48, ++ DBG_BLOCK_ID_SQB10 = 0x49, ++ DBG_BLOCK_ID_SQB11 = 0x4a, ++ DBG_BLOCK_ID_SQ00 = 0x4b, ++ DBG_BLOCK_ID_SQ01 = 0x4c, ++ DBG_BLOCK_ID_SQ10 = 0x4d, ++ DBG_BLOCK_ID_SQ11 = 0x4e, ++ DBG_BLOCK_ID_CB00 = 0x4f, ++ DBG_BLOCK_ID_CB01 = 0x50, ++ DBG_BLOCK_ID_CB02 = 0x51, ++ DBG_BLOCK_ID_CB03 = 0x52, ++ DBG_BLOCK_ID_CB04 = 0x53, ++ DBG_BLOCK_ID_UNUSED9 = 0x54, ++ DBG_BLOCK_ID_UNUSED10 = 0x55, ++ DBG_BLOCK_ID_UNUSED11 = 0x56, ++ DBG_BLOCK_ID_CB10 = 0x57, ++ DBG_BLOCK_ID_CB11 = 0x58, ++ DBG_BLOCK_ID_CB12 = 0x59, ++ DBG_BLOCK_ID_CB13 = 0x5a, ++ DBG_BLOCK_ID_CB14 = 0x5b, ++ DBG_BLOCK_ID_UNUSED12 = 0x5c, ++ DBG_BLOCK_ID_UNUSED13 = 0x5d, ++ DBG_BLOCK_ID_UNUSED14 = 0x5e, ++ DBG_BLOCK_ID_TCP0 = 0x5f, ++ DBG_BLOCK_ID_TCP1 = 0x60, ++ DBG_BLOCK_ID_TCP2 = 0x61, ++ DBG_BLOCK_ID_TCP3 = 0x62, ++ DBG_BLOCK_ID_TCP4 = 0x63, ++ DBG_BLOCK_ID_TCP5 = 0x64, ++ DBG_BLOCK_ID_TCP6 = 0x65, ++ DBG_BLOCK_ID_TCP7 = 0x66, ++ DBG_BLOCK_ID_TCP8 = 0x67, ++ DBG_BLOCK_ID_TCP9 = 0x68, ++ DBG_BLOCK_ID_TCP10 = 0x69, ++ DBG_BLOCK_ID_TCP11 = 0x6a, ++ DBG_BLOCK_ID_TCP12 = 0x6b, ++ DBG_BLOCK_ID_TCP13 = 0x6c, ++ DBG_BLOCK_ID_TCP14 = 0x6d, ++ DBG_BLOCK_ID_TCP15 = 0x6e, ++ DBG_BLOCK_ID_TCP16 = 0x6f, ++ DBG_BLOCK_ID_TCP17 = 0x70, ++ DBG_BLOCK_ID_TCP18 = 0x71, ++ DBG_BLOCK_ID_TCP19 = 0x72, ++ DBG_BLOCK_ID_TCP20 = 0x73, ++ DBG_BLOCK_ID_TCP21 = 0x74, ++ DBG_BLOCK_ID_TCP22 = 0x75, ++ DBG_BLOCK_ID_TCP23 = 0x76, ++ DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, ++ DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, ++ DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, ++ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, ++ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, ++ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, ++ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, ++ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, ++ DBG_BLOCK_ID_DB00 = 0x7f, ++ DBG_BLOCK_ID_DB01 = 0x80, ++ DBG_BLOCK_ID_DB02 = 0x81, ++ DBG_BLOCK_ID_DB03 = 0x82, ++ DBG_BLOCK_ID_DB04 = 0x83, ++ DBG_BLOCK_ID_UNUSED15 = 0x84, ++ DBG_BLOCK_ID_UNUSED16 = 0x85, ++ DBG_BLOCK_ID_UNUSED17 = 0x86, ++ DBG_BLOCK_ID_DB10 = 0x87, ++ DBG_BLOCK_ID_DB11 = 0x88, ++ DBG_BLOCK_ID_DB12 = 0x89, ++ DBG_BLOCK_ID_DB13 = 0x8a, ++ DBG_BLOCK_ID_DB14 = 0x8b, ++ DBG_BLOCK_ID_UNUSED18 = 0x8c, ++ DBG_BLOCK_ID_UNUSED19 = 0x8d, ++ DBG_BLOCK_ID_UNUSED20 = 0x8e, ++ DBG_BLOCK_ID_TCC0 = 0x8f, ++ DBG_BLOCK_ID_TCC1 = 0x90, ++ DBG_BLOCK_ID_TCC2 = 0x91, ++ DBG_BLOCK_ID_TCC3 = 0x92, ++ DBG_BLOCK_ID_TCC4 = 0x93, ++ DBG_BLOCK_ID_TCC5 = 0x94, ++ DBG_BLOCK_ID_TCC6 = 0x95, ++ DBG_BLOCK_ID_TCC7 = 0x96, ++ DBG_BLOCK_ID_SPS00 = 0x97, ++ DBG_BLOCK_ID_SPS01 = 0x98, ++ DBG_BLOCK_ID_SPS02 = 0x99, ++ DBG_BLOCK_ID_SPS10 = 0x9a, ++ DBG_BLOCK_ID_SPS11 = 0x9b, ++ DBG_BLOCK_ID_SPS12 = 0x9c, ++ DBG_BLOCK_ID_UNUSED21 = 0x9d, ++ DBG_BLOCK_ID_UNUSED22 = 0x9e, ++ DBG_BLOCK_ID_TA00 = 0x9f, ++ DBG_BLOCK_ID_TA01 = 0xa0, ++ DBG_BLOCK_ID_TA02 = 0xa1, ++ DBG_BLOCK_ID_TA03 = 0xa2, ++ DBG_BLOCK_ID_TA04 = 0xa3, ++ DBG_BLOCK_ID_TA05 = 0xa4, ++ DBG_BLOCK_ID_TA06 = 0xa5, ++ DBG_BLOCK_ID_TA07 = 0xa6, ++ DBG_BLOCK_ID_TA08 = 0xa7, ++ DBG_BLOCK_ID_TA09 = 0xa8, ++ DBG_BLOCK_ID_TA0A = 0xa9, ++ DBG_BLOCK_ID_TA0B = 0xaa, ++ DBG_BLOCK_ID_UNUSED23 = 0xab, ++ DBG_BLOCK_ID_UNUSED24 = 0xac, ++ DBG_BLOCK_ID_UNUSED25 = 0xad, ++ DBG_BLOCK_ID_UNUSED26 = 0xae, ++ DBG_BLOCK_ID_TA10 = 0xaf, ++ DBG_BLOCK_ID_TA11 = 0xb0, ++ DBG_BLOCK_ID_TA12 = 0xb1, ++ DBG_BLOCK_ID_TA13 = 0xb2, ++ DBG_BLOCK_ID_TA14 = 0xb3, ++ DBG_BLOCK_ID_TA15 = 0xb4, ++ DBG_BLOCK_ID_TA16 = 0xb5, ++ DBG_BLOCK_ID_TA17 = 0xb6, ++ DBG_BLOCK_ID_TA18 = 0xb7, ++ DBG_BLOCK_ID_TA19 = 0xb8, ++ DBG_BLOCK_ID_TA1A = 0xb9, ++ DBG_BLOCK_ID_TA1B = 0xba, ++ DBG_BLOCK_ID_UNUSED27 = 0xbb, ++ DBG_BLOCK_ID_UNUSED28 = 0xbc, ++ DBG_BLOCK_ID_UNUSED29 = 0xbd, ++ DBG_BLOCK_ID_UNUSED30 = 0xbe, ++ DBG_BLOCK_ID_TD00 = 0xbf, ++ DBG_BLOCK_ID_TD01 = 0xc0, ++ DBG_BLOCK_ID_TD02 = 0xc1, ++ DBG_BLOCK_ID_TD03 = 0xc2, ++ DBG_BLOCK_ID_TD04 = 0xc3, ++ DBG_BLOCK_ID_TD05 = 0xc4, ++ DBG_BLOCK_ID_TD06 = 0xc5, ++ DBG_BLOCK_ID_TD07 = 0xc6, ++ DBG_BLOCK_ID_TD08 = 0xc7, ++ DBG_BLOCK_ID_TD09 = 0xc8, ++ DBG_BLOCK_ID_TD0A = 0xc9, ++ DBG_BLOCK_ID_TD0B = 0xca, ++ DBG_BLOCK_ID_UNUSED31 = 0xcb, ++ DBG_BLOCK_ID_UNUSED32 = 0xcc, ++ DBG_BLOCK_ID_UNUSED33 = 0xcd, ++ DBG_BLOCK_ID_UNUSED34 = 0xce, ++ DBG_BLOCK_ID_TD10 = 0xcf, ++ DBG_BLOCK_ID_TD11 = 0xd0, ++ DBG_BLOCK_ID_TD12 = 0xd1, ++ DBG_BLOCK_ID_TD13 = 0xd2, ++ DBG_BLOCK_ID_TD14 = 0xd3, ++ DBG_BLOCK_ID_TD15 = 0xd4, ++ DBG_BLOCK_ID_TD16 = 0xd5, ++ DBG_BLOCK_ID_TD17 = 0xd6, ++ DBG_BLOCK_ID_TD18 = 0xd7, ++ DBG_BLOCK_ID_TD19 = 0xd8, ++ DBG_BLOCK_ID_TD1A = 0xd9, ++ DBG_BLOCK_ID_TD1B = 0xda, ++ DBG_BLOCK_ID_UNUSED35 = 0xdb, ++ DBG_BLOCK_ID_UNUSED36 = 0xdc, ++ DBG_BLOCK_ID_UNUSED37 = 0xdd, ++ DBG_BLOCK_ID_UNUSED38 = 0xde, ++ DBG_BLOCK_ID_LDS00 = 0xdf, ++ DBG_BLOCK_ID_LDS01 = 0xe0, ++ DBG_BLOCK_ID_LDS02 = 0xe1, ++ DBG_BLOCK_ID_LDS03 = 0xe2, ++ DBG_BLOCK_ID_LDS04 = 0xe3, ++ DBG_BLOCK_ID_LDS05 = 0xe4, ++ DBG_BLOCK_ID_LDS06 = 0xe5, ++ DBG_BLOCK_ID_LDS07 = 0xe6, ++ DBG_BLOCK_ID_LDS08 = 0xe7, ++ DBG_BLOCK_ID_LDS09 = 0xe8, ++ DBG_BLOCK_ID_LDS0A = 0xe9, ++ DBG_BLOCK_ID_LDS0B = 0xea, ++ DBG_BLOCK_ID_UNUSED39 = 0xeb, ++ DBG_BLOCK_ID_UNUSED40 = 0xec, ++ DBG_BLOCK_ID_UNUSED41 = 0xed, ++ DBG_BLOCK_ID_UNUSED42 = 0xee, ++ DBG_BLOCK_ID_LDS10 = 0xef, ++ DBG_BLOCK_ID_LDS11 = 0xf0, ++ DBG_BLOCK_ID_LDS12 = 0xf1, ++ DBG_BLOCK_ID_LDS13 = 0xf2, ++ DBG_BLOCK_ID_LDS14 = 0xf3, ++ DBG_BLOCK_ID_LDS15 = 0xf4, ++ DBG_BLOCK_ID_LDS16 = 0xf5, ++ DBG_BLOCK_ID_LDS17 = 0xf6, ++ DBG_BLOCK_ID_LDS18 = 0xf7, ++ DBG_BLOCK_ID_LDS19 = 0xf8, ++ DBG_BLOCK_ID_LDS1A = 0xf9, ++ DBG_BLOCK_ID_LDS1B = 0xfa, ++ DBG_BLOCK_ID_UNUSED43 = 0xfb, ++ DBG_BLOCK_ID_UNUSED44 = 0xfc, ++ DBG_BLOCK_ID_UNUSED45 = 0xfd, ++ DBG_BLOCK_ID_UNUSED46 = 0xfe, ++} DebugBlockId; ++typedef enum DebugBlockId_BY2 { ++ DBG_BLOCK_ID_RESERVED_BY2 = 0x0, ++ DBG_BLOCK_ID_VMC_BY2 = 0x1, ++ DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, ++ DBG_BLOCK_ID_GRBM_BY2 = 0x3, ++ DBG_BLOCK_ID_CSC_BY2 = 0x4, ++ DBG_BLOCK_ID_IH_BY2 = 0x5, ++ DBG_BLOCK_ID_SQ_BY2 = 0x6, ++ DBG_BLOCK_ID_UVD_BY2 = 0x7, ++ DBG_BLOCK_ID_SDMA0_BY2 = 0x8, ++ DBG_BLOCK_ID_SPIM_BY2 = 0x9, ++ DBG_BLOCK_ID_VC0_BY2 = 0xa, ++ DBG_BLOCK_ID_PA_BY2 = 0xb, ++ DBG_BLOCK_ID_CP0_BY2 = 0xc, ++ DBG_BLOCK_ID_CP2_BY2 = 0xd, ++ DBG_BLOCK_ID_PC0_BY2 = 0xe, ++ DBG_BLOCK_ID_BCI0_BY2 = 0xf, ++ DBG_BLOCK_ID_SXM0_BY2 = 0x10, ++ DBG_BLOCK_ID_SCT0_BY2 = 0x11, ++ DBG_BLOCK_ID_SPM0_BY2 = 0x12, ++ DBG_BLOCK_ID_BCI2_BY2 = 0x13, ++ DBG_BLOCK_ID_TCA_BY2 = 0x14, ++ DBG_BLOCK_ID_TCCA_BY2 = 0x15, ++ DBG_BLOCK_ID_MCC_BY2 = 0x16, ++ DBG_BLOCK_ID_MCC2_BY2 = 0x17, ++ DBG_BLOCK_ID_MCD_BY2 = 0x18, ++ DBG_BLOCK_ID_MCD2_BY2 = 0x19, ++ DBG_BLOCK_ID_MCD4_BY2 = 0x1a, ++ DBG_BLOCK_ID_MCB_BY2 = 0x1b, ++ DBG_BLOCK_ID_SQA_BY2 = 0x1c, ++ DBG_BLOCK_ID_SQA02_BY2 = 0x1d, ++ DBG_BLOCK_ID_SQA11_BY2 = 0x1e, ++ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, ++ DBG_BLOCK_ID_SQB_BY2 = 0x20, ++ DBG_BLOCK_ID_SQB10_BY2 = 0x21, ++ DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, ++ DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, ++ DBG_BLOCK_ID_CB_BY2 = 0x24, ++ DBG_BLOCK_ID_CB02_BY2 = 0x25, ++ DBG_BLOCK_ID_CB10_BY2 = 0x26, ++ DBG_BLOCK_ID_CB12_BY2 = 0x27, ++ DBG_BLOCK_ID_SXS_BY2 = 0x28, ++ DBG_BLOCK_ID_SXS2_BY2 = 0x29, ++ DBG_BLOCK_ID_SXS4_BY2 = 0x2a, ++ DBG_BLOCK_ID_SXS6_BY2 = 0x2b, ++ DBG_BLOCK_ID_DB_BY2 = 0x2c, ++ DBG_BLOCK_ID_DB02_BY2 = 0x2d, ++ DBG_BLOCK_ID_DB10_BY2 = 0x2e, ++ DBG_BLOCK_ID_DB12_BY2 = 0x2f, ++ DBG_BLOCK_ID_TCP_BY2 = 0x30, ++ DBG_BLOCK_ID_TCP2_BY2 = 0x31, ++ DBG_BLOCK_ID_TCP4_BY2 = 0x32, ++ DBG_BLOCK_ID_TCP6_BY2 = 0x33, ++ DBG_BLOCK_ID_TCP8_BY2 = 0x34, ++ DBG_BLOCK_ID_TCP10_BY2 = 0x35, ++ DBG_BLOCK_ID_TCP12_BY2 = 0x36, ++ DBG_BLOCK_ID_TCP14_BY2 = 0x37, ++ DBG_BLOCK_ID_TCP16_BY2 = 0x38, ++ DBG_BLOCK_ID_TCP18_BY2 = 0x39, ++ DBG_BLOCK_ID_TCP20_BY2 = 0x3a, ++ DBG_BLOCK_ID_TCP22_BY2 = 0x3b, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, ++ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, ++ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, ++ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, ++ DBG_BLOCK_ID_TCC_BY2 = 0x40, ++ DBG_BLOCK_ID_TCC2_BY2 = 0x41, ++ DBG_BLOCK_ID_TCC4_BY2 = 0x42, ++ DBG_BLOCK_ID_TCC6_BY2 = 0x43, ++ DBG_BLOCK_ID_SPS_BY2 = 0x44, ++ DBG_BLOCK_ID_SPS02_BY2 = 0x45, ++ DBG_BLOCK_ID_SPS11_BY2 = 0x46, ++ DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, ++ DBG_BLOCK_ID_TA_BY2 = 0x48, ++ DBG_BLOCK_ID_TA02_BY2 = 0x49, ++ DBG_BLOCK_ID_TA04_BY2 = 0x4a, ++ DBG_BLOCK_ID_TA06_BY2 = 0x4b, ++ DBG_BLOCK_ID_TA08_BY2 = 0x4c, ++ DBG_BLOCK_ID_TA0A_BY2 = 0x4d, ++ DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, ++ DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, ++ DBG_BLOCK_ID_TA10_BY2 = 0x50, ++ DBG_BLOCK_ID_TA12_BY2 = 0x51, ++ DBG_BLOCK_ID_TA14_BY2 = 0x52, ++ DBG_BLOCK_ID_TA16_BY2 = 0x53, ++ DBG_BLOCK_ID_TA18_BY2 = 0x54, ++ DBG_BLOCK_ID_TA1A_BY2 = 0x55, ++ DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, ++ DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, ++ DBG_BLOCK_ID_TD_BY2 = 0x58, ++ DBG_BLOCK_ID_TD02_BY2 = 0x59, ++ DBG_BLOCK_ID_TD04_BY2 = 0x5a, ++ DBG_BLOCK_ID_TD06_BY2 = 0x5b, ++ DBG_BLOCK_ID_TD08_BY2 = 0x5c, ++ DBG_BLOCK_ID_TD0A_BY2 = 0x5d, ++ DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, ++ DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, ++ DBG_BLOCK_ID_TD10_BY2 = 0x60, ++ DBG_BLOCK_ID_TD12_BY2 = 0x61, ++ DBG_BLOCK_ID_TD14_BY2 = 0x62, ++ DBG_BLOCK_ID_TD16_BY2 = 0x63, ++ DBG_BLOCK_ID_TD18_BY2 = 0x64, ++ DBG_BLOCK_ID_TD1A_BY2 = 0x65, ++ DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, ++ DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, ++ DBG_BLOCK_ID_LDS_BY2 = 0x68, ++ DBG_BLOCK_ID_LDS02_BY2 = 0x69, ++ DBG_BLOCK_ID_LDS04_BY2 = 0x6a, ++ DBG_BLOCK_ID_LDS06_BY2 = 0x6b, ++ DBG_BLOCK_ID_LDS08_BY2 = 0x6c, ++ DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, ++ DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, ++ DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, ++ DBG_BLOCK_ID_LDS10_BY2 = 0x70, ++ DBG_BLOCK_ID_LDS12_BY2 = 0x71, ++ DBG_BLOCK_ID_LDS14_BY2 = 0x72, ++ DBG_BLOCK_ID_LDS16_BY2 = 0x73, ++ DBG_BLOCK_ID_LDS18_BY2 = 0x74, ++ DBG_BLOCK_ID_LDS1A_BY2 = 0x75, ++ DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, ++ DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, ++} DebugBlockId_BY2; ++typedef enum DebugBlockId_BY4 { ++ DBG_BLOCK_ID_RESERVED_BY4 = 0x0, ++ DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, ++ DBG_BLOCK_ID_CSC_BY4 = 0x2, ++ DBG_BLOCK_ID_SQ_BY4 = 0x3, ++ DBG_BLOCK_ID_SDMA0_BY4 = 0x4, ++ DBG_BLOCK_ID_VC0_BY4 = 0x5, ++ DBG_BLOCK_ID_CP0_BY4 = 0x6, ++ DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, ++ DBG_BLOCK_ID_SXM0_BY4 = 0x8, ++ DBG_BLOCK_ID_SPM0_BY4 = 0x9, ++ DBG_BLOCK_ID_TCAA_BY4 = 0xa, ++ DBG_BLOCK_ID_MCC_BY4 = 0xb, ++ DBG_BLOCK_ID_MCD_BY4 = 0xc, ++ DBG_BLOCK_ID_MCD4_BY4 = 0xd, ++ DBG_BLOCK_ID_SQA_BY4 = 0xe, ++ DBG_BLOCK_ID_SQA11_BY4 = 0xf, ++ DBG_BLOCK_ID_SQB_BY4 = 0x10, ++ DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, ++ DBG_BLOCK_ID_CB_BY4 = 0x12, ++ DBG_BLOCK_ID_CB10_BY4 = 0x13, ++ DBG_BLOCK_ID_SXS_BY4 = 0x14, ++ DBG_BLOCK_ID_SXS4_BY4 = 0x15, ++ DBG_BLOCK_ID_DB_BY4 = 0x16, ++ DBG_BLOCK_ID_DB10_BY4 = 0x17, ++ DBG_BLOCK_ID_TCP_BY4 = 0x18, ++ DBG_BLOCK_ID_TCP4_BY4 = 0x19, ++ DBG_BLOCK_ID_TCP8_BY4 = 0x1a, ++ DBG_BLOCK_ID_TCP12_BY4 = 0x1b, ++ DBG_BLOCK_ID_TCP16_BY4 = 0x1c, ++ DBG_BLOCK_ID_TCP20_BY4 = 0x1d, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, ++ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, ++ DBG_BLOCK_ID_TCC_BY4 = 0x20, ++ DBG_BLOCK_ID_TCC4_BY4 = 0x21, ++ DBG_BLOCK_ID_SPS_BY4 = 0x22, ++ DBG_BLOCK_ID_SPS11_BY4 = 0x23, ++ DBG_BLOCK_ID_TA_BY4 = 0x24, ++ DBG_BLOCK_ID_TA04_BY4 = 0x25, ++ DBG_BLOCK_ID_TA08_BY4 = 0x26, ++ DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, ++ DBG_BLOCK_ID_TA10_BY4 = 0x28, ++ DBG_BLOCK_ID_TA14_BY4 = 0x29, ++ DBG_BLOCK_ID_TA18_BY4 = 0x2a, ++ DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, ++ DBG_BLOCK_ID_TD_BY4 = 0x2c, ++ DBG_BLOCK_ID_TD04_BY4 = 0x2d, ++ DBG_BLOCK_ID_TD08_BY4 = 0x2e, ++ DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, ++ DBG_BLOCK_ID_TD10_BY4 = 0x30, ++ DBG_BLOCK_ID_TD14_BY4 = 0x31, ++ DBG_BLOCK_ID_TD18_BY4 = 0x32, ++ DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, ++ DBG_BLOCK_ID_LDS_BY4 = 0x34, ++ DBG_BLOCK_ID_LDS04_BY4 = 0x35, ++ DBG_BLOCK_ID_LDS08_BY4 = 0x36, ++ DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, ++ DBG_BLOCK_ID_LDS10_BY4 = 0x38, ++ DBG_BLOCK_ID_LDS14_BY4 = 0x39, ++ DBG_BLOCK_ID_LDS18_BY4 = 0x3a, ++ DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, ++} DebugBlockId_BY4; ++typedef enum DebugBlockId_BY8 { ++ DBG_BLOCK_ID_RESERVED_BY8 = 0x0, ++ DBG_BLOCK_ID_CSC_BY8 = 0x1, ++ DBG_BLOCK_ID_SDMA0_BY8 = 0x2, ++ DBG_BLOCK_ID_CP0_BY8 = 0x3, ++ DBG_BLOCK_ID_SXM0_BY8 = 0x4, ++ DBG_BLOCK_ID_TCA_BY8 = 0x5, ++ DBG_BLOCK_ID_MCD_BY8 = 0x6, ++ DBG_BLOCK_ID_SQA_BY8 = 0x7, ++ DBG_BLOCK_ID_SQB_BY8 = 0x8, ++ DBG_BLOCK_ID_CB_BY8 = 0x9, ++ DBG_BLOCK_ID_SXS_BY8 = 0xa, ++ DBG_BLOCK_ID_DB_BY8 = 0xb, ++ DBG_BLOCK_ID_TCP_BY8 = 0xc, ++ DBG_BLOCK_ID_TCP8_BY8 = 0xd, ++ DBG_BLOCK_ID_TCP16_BY8 = 0xe, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, ++ DBG_BLOCK_ID_TCC_BY8 = 0x10, ++ DBG_BLOCK_ID_SPS_BY8 = 0x11, ++ DBG_BLOCK_ID_TA_BY8 = 0x12, ++ DBG_BLOCK_ID_TA08_BY8 = 0x13, ++ DBG_BLOCK_ID_TA10_BY8 = 0x14, ++ DBG_BLOCK_ID_TA18_BY8 = 0x15, ++ DBG_BLOCK_ID_TD_BY8 = 0x16, ++ DBG_BLOCK_ID_TD08_BY8 = 0x17, ++ DBG_BLOCK_ID_TD10_BY8 = 0x18, ++ DBG_BLOCK_ID_TD18_BY8 = 0x19, ++ DBG_BLOCK_ID_LDS_BY8 = 0x1a, ++ DBG_BLOCK_ID_LDS08_BY8 = 0x1b, ++ DBG_BLOCK_ID_LDS10_BY8 = 0x1c, ++ DBG_BLOCK_ID_LDS18_BY8 = 0x1d, ++} DebugBlockId_BY8; ++typedef enum DebugBlockId_BY16 { ++ DBG_BLOCK_ID_RESERVED_BY16 = 0x0, ++ DBG_BLOCK_ID_SDMA0_BY16 = 0x1, ++ DBG_BLOCK_ID_SXM_BY16 = 0x2, ++ DBG_BLOCK_ID_MCD_BY16 = 0x3, ++ DBG_BLOCK_ID_SQB_BY16 = 0x4, ++ DBG_BLOCK_ID_SXS_BY16 = 0x5, ++ DBG_BLOCK_ID_TCP_BY16 = 0x6, ++ DBG_BLOCK_ID_TCP16_BY16 = 0x7, ++ DBG_BLOCK_ID_TCC_BY16 = 0x8, ++ DBG_BLOCK_ID_TA_BY16 = 0x9, ++ DBG_BLOCK_ID_TA10_BY16 = 0xa, ++ DBG_BLOCK_ID_TD_BY16 = 0xb, ++ DBG_BLOCK_ID_TD10_BY16 = 0xc, ++ DBG_BLOCK_ID_LDS_BY16 = 0xd, ++ DBG_BLOCK_ID_LDS10_BY16 = 0xe, ++} DebugBlockId_BY16; ++typedef enum SurfaceEndian { ++ ENDIAN_NONE = 0x0, ++ ENDIAN_8IN16 = 0x1, ++ ENDIAN_8IN32 = 0x2, ++ ENDIAN_8IN64 = 0x3, ++} SurfaceEndian; ++typedef enum ArrayMode { ++ ARRAY_LINEAR_GENERAL = 0x0, ++ ARRAY_LINEAR_ALIGNED = 0x1, ++ ARRAY_1D_TILED_THIN1 = 0x2, ++ ARRAY_1D_TILED_THICK = 0x3, ++ ARRAY_2D_TILED_THIN1 = 0x4, ++ ARRAY_PRT_TILED_THIN1 = 0x5, ++ ARRAY_PRT_2D_TILED_THIN1 = 0x6, ++ ARRAY_2D_TILED_THICK = 0x7, ++ ARRAY_2D_TILED_XTHICK = 0x8, ++ ARRAY_PRT_TILED_THICK = 0x9, ++ ARRAY_PRT_2D_TILED_THICK = 0xa, ++ ARRAY_PRT_3D_TILED_THIN1 = 0xb, ++ ARRAY_3D_TILED_THIN1 = 0xc, ++ ARRAY_3D_TILED_THICK = 0xd, ++ ARRAY_3D_TILED_XTHICK = 0xe, ++ ARRAY_PRT_3D_TILED_THICK = 0xf, ++} ArrayMode; ++typedef enum PipeTiling { ++ CONFIG_1_PIPE = 0x0, ++ CONFIG_2_PIPE = 0x1, ++ CONFIG_4_PIPE = 0x2, ++ CONFIG_8_PIPE = 0x3, ++} PipeTiling; ++typedef enum BankTiling { ++ CONFIG_4_BANK = 0x0, ++ CONFIG_8_BANK = 0x1, ++} BankTiling; ++typedef enum GroupInterleave { ++ CONFIG_256B_GROUP = 0x0, ++ CONFIG_512B_GROUP = 0x1, ++} GroupInterleave; ++typedef enum RowTiling { ++ CONFIG_1KB_ROW = 0x0, ++ CONFIG_2KB_ROW = 0x1, ++ CONFIG_4KB_ROW = 0x2, ++ CONFIG_8KB_ROW = 0x3, ++ CONFIG_1KB_ROW_OPT = 0x4, ++ CONFIG_2KB_ROW_OPT = 0x5, ++ CONFIG_4KB_ROW_OPT = 0x6, ++ CONFIG_8KB_ROW_OPT = 0x7, ++} RowTiling; ++typedef enum BankSwapBytes { ++ CONFIG_128B_SWAPS = 0x0, ++ CONFIG_256B_SWAPS = 0x1, ++ CONFIG_512B_SWAPS = 0x2, ++ CONFIG_1KB_SWAPS = 0x3, ++} BankSwapBytes; ++typedef enum SampleSplitBytes { ++ CONFIG_1KB_SPLIT = 0x0, ++ CONFIG_2KB_SPLIT = 0x1, ++ CONFIG_4KB_SPLIT = 0x2, ++ CONFIG_8KB_SPLIT = 0x3, ++} SampleSplitBytes; ++typedef enum NumPipes { ++ ADDR_CONFIG_1_PIPE = 0x0, ++ ADDR_CONFIG_2_PIPE = 0x1, ++ ADDR_CONFIG_4_PIPE = 0x2, ++ ADDR_CONFIG_8_PIPE = 0x3, ++} NumPipes; ++typedef enum PipeInterleaveSize { ++ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, ++ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, ++} PipeInterleaveSize; ++typedef enum BankInterleaveSize { ++ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, ++ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, ++ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, ++ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, ++} BankInterleaveSize; ++typedef enum NumShaderEngines { ++ ADDR_CONFIG_1_SHADER_ENGINE = 0x0, ++ ADDR_CONFIG_2_SHADER_ENGINE = 0x1, ++} NumShaderEngines; ++typedef enum ShaderEngineTileSize { ++ ADDR_CONFIG_SE_TILE_16 = 0x0, ++ ADDR_CONFIG_SE_TILE_32 = 0x1, ++} ShaderEngineTileSize; ++typedef enum NumGPUs { ++ ADDR_CONFIG_1_GPU = 0x0, ++ ADDR_CONFIG_2_GPU = 0x1, ++ ADDR_CONFIG_4_GPU = 0x2, ++} NumGPUs; ++typedef enum MultiGPUTileSize { ++ ADDR_CONFIG_GPU_TILE_16 = 0x0, ++ ADDR_CONFIG_GPU_TILE_32 = 0x1, ++ ADDR_CONFIG_GPU_TILE_64 = 0x2, ++ ADDR_CONFIG_GPU_TILE_128 = 0x3, ++} MultiGPUTileSize; ++typedef enum RowSize { ++ ADDR_CONFIG_1KB_ROW = 0x0, ++ ADDR_CONFIG_2KB_ROW = 0x1, ++ ADDR_CONFIG_4KB_ROW = 0x2, ++} RowSize; ++typedef enum NumLowerPipes { ++ ADDR_CONFIG_1_LOWER_PIPES = 0x0, ++ ADDR_CONFIG_2_LOWER_PIPES = 0x1, ++} NumLowerPipes; ++typedef enum ColorTransform { ++ DCC_CT_AUTO = 0x0, ++ DCC_CT_NONE = 0x1, ++ ABGR_TO_A_BG_G_RB = 0x2, ++ BGRA_TO_BG_G_RB_A = 0x3, ++} ColorTransform; ++typedef enum CompareRef { ++ REF_NEVER = 0x0, ++ REF_LESS = 0x1, ++ REF_EQUAL = 0x2, ++ REF_LEQUAL = 0x3, ++ REF_GREATER = 0x4, ++ REF_NOTEQUAL = 0x5, ++ REF_GEQUAL = 0x6, ++ REF_ALWAYS = 0x7, ++} CompareRef; ++typedef enum ReadSize { ++ READ_256_BITS = 0x0, ++ READ_512_BITS = 0x1, ++} ReadSize; ++typedef enum DepthFormat { ++ DEPTH_INVALID = 0x0, ++ DEPTH_16 = 0x1, ++ DEPTH_X8_24 = 0x2, ++ DEPTH_8_24 = 0x3, ++ DEPTH_X8_24_FLOAT = 0x4, ++ DEPTH_8_24_FLOAT = 0x5, ++ DEPTH_32_FLOAT = 0x6, ++ DEPTH_X24_8_32_FLOAT = 0x7, ++} DepthFormat; ++typedef enum ZFormat { ++ Z_INVALID = 0x0, ++ Z_16 = 0x1, ++ Z_24 = 0x2, ++ Z_32_FLOAT = 0x3, ++} ZFormat; ++typedef enum StencilFormat { ++ STENCIL_INVALID = 0x0, ++ STENCIL_8 = 0x1, ++} StencilFormat; ++typedef enum CmaskMode { ++ CMASK_CLEAR_NONE = 0x0, ++ CMASK_CLEAR_ONE = 0x1, ++ CMASK_CLEAR_ALL = 0x2, ++ CMASK_ANY_EXPANDED = 0x3, ++ CMASK_ALPHA0_FRAG1 = 0x4, ++ CMASK_ALPHA0_FRAG2 = 0x5, ++ CMASK_ALPHA0_FRAG4 = 0x6, ++ CMASK_ALPHA0_FRAGS = 0x7, ++ CMASK_ALPHA1_FRAG1 = 0x8, ++ CMASK_ALPHA1_FRAG2 = 0x9, ++ CMASK_ALPHA1_FRAG4 = 0xa, ++ CMASK_ALPHA1_FRAGS = 0xb, ++ CMASK_ALPHAX_FRAG1 = 0xc, ++ CMASK_ALPHAX_FRAG2 = 0xd, ++ CMASK_ALPHAX_FRAG4 = 0xe, ++ CMASK_ALPHAX_FRAGS = 0xf, ++} CmaskMode; ++typedef enum QuadExportFormat { ++ EXPORT_UNUSED = 0x0, ++ EXPORT_32_R = 0x1, ++ EXPORT_32_GR = 0x2, ++ EXPORT_32_AR = 0x3, ++ EXPORT_FP16_ABGR = 0x4, ++ EXPORT_UNSIGNED16_ABGR = 0x5, ++ EXPORT_SIGNED16_ABGR = 0x6, ++ EXPORT_32_ABGR = 0x7, ++} QuadExportFormat; ++typedef enum QuadExportFormatOld { ++ EXPORT_4P_32BPC_ABGR = 0x0, ++ EXPORT_4P_16BPC_ABGR = 0x1, ++ EXPORT_4P_32BPC_GR = 0x2, ++ EXPORT_4P_32BPC_AR = 0x3, ++ EXPORT_2P_32BPC_ABGR = 0x4, ++ EXPORT_8P_32BPC_R = 0x5, ++} QuadExportFormatOld; ++typedef enum ColorFormat { ++ COLOR_INVALID = 0x0, ++ COLOR_8 = 0x1, ++ COLOR_16 = 0x2, ++ COLOR_8_8 = 0x3, ++ COLOR_32 = 0x4, ++ COLOR_16_16 = 0x5, ++ COLOR_10_11_11 = 0x6, ++ COLOR_11_11_10 = 0x7, ++ COLOR_10_10_10_2 = 0x8, ++ COLOR_2_10_10_10 = 0x9, ++ COLOR_8_8_8_8 = 0xa, ++ COLOR_32_32 = 0xb, ++ COLOR_16_16_16_16 = 0xc, ++ COLOR_RESERVED_13 = 0xd, ++ COLOR_32_32_32_32 = 0xe, ++ COLOR_RESERVED_15 = 0xf, ++ COLOR_5_6_5 = 0x10, ++ COLOR_1_5_5_5 = 0x11, ++ COLOR_5_5_5_1 = 0x12, ++ COLOR_4_4_4_4 = 0x13, ++ COLOR_8_24 = 0x14, ++ COLOR_24_8 = 0x15, ++ COLOR_X24_8_32_FLOAT = 0x16, ++ COLOR_RESERVED_23 = 0x17, ++} ColorFormat; ++typedef enum SurfaceFormat { ++ FMT_INVALID = 0x0, ++ FMT_8 = 0x1, ++ FMT_16 = 0x2, ++ FMT_8_8 = 0x3, ++ FMT_32 = 0x4, ++ FMT_16_16 = 0x5, ++ FMT_10_11_11 = 0x6, ++ FMT_11_11_10 = 0x7, ++ FMT_10_10_10_2 = 0x8, ++ FMT_2_10_10_10 = 0x9, ++ FMT_8_8_8_8 = 0xa, ++ FMT_32_32 = 0xb, ++ FMT_16_16_16_16 = 0xc, ++ FMT_32_32_32 = 0xd, ++ FMT_32_32_32_32 = 0xe, ++ FMT_RESERVED_4 = 0xf, ++ FMT_5_6_5 = 0x10, ++ FMT_1_5_5_5 = 0x11, ++ FMT_5_5_5_1 = 0x12, ++ FMT_4_4_4_4 = 0x13, ++ FMT_8_24 = 0x14, ++ FMT_24_8 = 0x15, ++ FMT_X24_8_32_FLOAT = 0x16, ++ FMT_RESERVED_33 = 0x17, ++ FMT_11_11_10_FLOAT = 0x18, ++ FMT_16_FLOAT = 0x19, ++ FMT_32_FLOAT = 0x1a, ++ FMT_16_16_FLOAT = 0x1b, ++ FMT_8_24_FLOAT = 0x1c, ++ FMT_24_8_FLOAT = 0x1d, ++ FMT_32_32_FLOAT = 0x1e, ++ FMT_10_11_11_FLOAT = 0x1f, ++ FMT_16_16_16_16_FLOAT = 0x20, ++ FMT_3_3_2 = 0x21, ++ FMT_6_5_5 = 0x22, ++ FMT_32_32_32_32_FLOAT = 0x23, ++ FMT_RESERVED_36 = 0x24, ++ FMT_1 = 0x25, ++ FMT_1_REVERSED = 0x26, ++ FMT_GB_GR = 0x27, ++ FMT_BG_RG = 0x28, ++ FMT_32_AS_8 = 0x29, ++ FMT_32_AS_8_8 = 0x2a, ++ FMT_5_9_9_9_SHAREDEXP = 0x2b, ++ FMT_8_8_8 = 0x2c, ++ FMT_16_16_16 = 0x2d, ++ FMT_16_16_16_FLOAT = 0x2e, ++ FMT_4_4 = 0x2f, ++ FMT_32_32_32_FLOAT = 0x30, ++ FMT_BC1 = 0x31, ++ FMT_BC2 = 0x32, ++ FMT_BC3 = 0x33, ++ FMT_BC4 = 0x34, ++ FMT_BC5 = 0x35, ++ FMT_BC6 = 0x36, ++ FMT_BC7 = 0x37, ++ FMT_32_AS_32_32_32_32 = 0x38, ++ FMT_APC3 = 0x39, ++ FMT_APC4 = 0x3a, ++ FMT_APC5 = 0x3b, ++ FMT_APC6 = 0x3c, ++ FMT_APC7 = 0x3d, ++ FMT_CTX1 = 0x3e, ++ FMT_RESERVED_63 = 0x3f, ++} SurfaceFormat; ++typedef enum BUF_DATA_FORMAT { ++ BUF_DATA_FORMAT_INVALID = 0x0, ++ BUF_DATA_FORMAT_8 = 0x1, ++ BUF_DATA_FORMAT_16 = 0x2, ++ BUF_DATA_FORMAT_8_8 = 0x3, ++ BUF_DATA_FORMAT_32 = 0x4, ++ BUF_DATA_FORMAT_16_16 = 0x5, ++ BUF_DATA_FORMAT_10_11_11 = 0x6, ++ BUF_DATA_FORMAT_11_11_10 = 0x7, ++ BUF_DATA_FORMAT_10_10_10_2 = 0x8, ++ BUF_DATA_FORMAT_2_10_10_10 = 0x9, ++ BUF_DATA_FORMAT_8_8_8_8 = 0xa, ++ BUF_DATA_FORMAT_32_32 = 0xb, ++ BUF_DATA_FORMAT_16_16_16_16 = 0xc, ++ BUF_DATA_FORMAT_32_32_32 = 0xd, ++ BUF_DATA_FORMAT_32_32_32_32 = 0xe, ++ BUF_DATA_FORMAT_RESERVED_15 = 0xf, ++} BUF_DATA_FORMAT; ++typedef enum IMG_DATA_FORMAT { ++ IMG_DATA_FORMAT_INVALID = 0x0, ++ IMG_DATA_FORMAT_8 = 0x1, ++ IMG_DATA_FORMAT_16 = 0x2, ++ IMG_DATA_FORMAT_8_8 = 0x3, ++ IMG_DATA_FORMAT_32 = 0x4, ++ IMG_DATA_FORMAT_16_16 = 0x5, ++ IMG_DATA_FORMAT_10_11_11 = 0x6, ++ IMG_DATA_FORMAT_11_11_10 = 0x7, ++ IMG_DATA_FORMAT_10_10_10_2 = 0x8, ++ IMG_DATA_FORMAT_2_10_10_10 = 0x9, ++ IMG_DATA_FORMAT_8_8_8_8 = 0xa, ++ IMG_DATA_FORMAT_32_32 = 0xb, ++ IMG_DATA_FORMAT_16_16_16_16 = 0xc, ++ IMG_DATA_FORMAT_32_32_32 = 0xd, ++ IMG_DATA_FORMAT_32_32_32_32 = 0xe, ++ IMG_DATA_FORMAT_RESERVED_15 = 0xf, ++ IMG_DATA_FORMAT_5_6_5 = 0x10, ++ IMG_DATA_FORMAT_1_5_5_5 = 0x11, ++ IMG_DATA_FORMAT_5_5_5_1 = 0x12, ++ IMG_DATA_FORMAT_4_4_4_4 = 0x13, ++ IMG_DATA_FORMAT_8_24 = 0x14, ++ IMG_DATA_FORMAT_24_8 = 0x15, ++ IMG_DATA_FORMAT_X24_8_32 = 0x16, ++ IMG_DATA_FORMAT_RESERVED_23 = 0x17, ++ IMG_DATA_FORMAT_RESERVED_24 = 0x18, ++ IMG_DATA_FORMAT_RESERVED_25 = 0x19, ++ IMG_DATA_FORMAT_RESERVED_26 = 0x1a, ++ IMG_DATA_FORMAT_RESERVED_27 = 0x1b, ++ IMG_DATA_FORMAT_RESERVED_28 = 0x1c, ++ IMG_DATA_FORMAT_RESERVED_29 = 0x1d, ++ IMG_DATA_FORMAT_RESERVED_30 = 0x1e, ++ IMG_DATA_FORMAT_RESERVED_31 = 0x1f, ++ IMG_DATA_FORMAT_GB_GR = 0x20, ++ IMG_DATA_FORMAT_BG_RG = 0x21, ++ IMG_DATA_FORMAT_5_9_9_9 = 0x22, ++ IMG_DATA_FORMAT_BC1 = 0x23, ++ IMG_DATA_FORMAT_BC2 = 0x24, ++ IMG_DATA_FORMAT_BC3 = 0x25, ++ IMG_DATA_FORMAT_BC4 = 0x26, ++ IMG_DATA_FORMAT_BC5 = 0x27, ++ IMG_DATA_FORMAT_BC6 = 0x28, ++ IMG_DATA_FORMAT_BC7 = 0x29, ++ IMG_DATA_FORMAT_RESERVED_42 = 0x2a, ++ IMG_DATA_FORMAT_RESERVED_43 = 0x2b, ++ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, ++ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, ++ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, ++ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, ++ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, ++ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, ++ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, ++ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, ++ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, ++ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, ++ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, ++ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, ++ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, ++ IMG_DATA_FORMAT_4_4 = 0x39, ++ IMG_DATA_FORMAT_6_5_5 = 0x3a, ++ IMG_DATA_FORMAT_1 = 0x3b, ++ IMG_DATA_FORMAT_1_REVERSED = 0x3c, ++ IMG_DATA_FORMAT_32_AS_8 = 0x3d, ++ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, ++ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, ++} IMG_DATA_FORMAT; ++typedef enum BUF_NUM_FORMAT { ++ BUF_NUM_FORMAT_UNORM = 0x0, ++ BUF_NUM_FORMAT_SNORM = 0x1, ++ BUF_NUM_FORMAT_USCALED = 0x2, ++ BUF_NUM_FORMAT_SSCALED = 0x3, ++ BUF_NUM_FORMAT_UINT = 0x4, ++ BUF_NUM_FORMAT_SINT = 0x5, ++ BUF_NUM_FORMAT_RESERVED_6 = 0x6, ++ BUF_NUM_FORMAT_FLOAT = 0x7, ++} BUF_NUM_FORMAT; ++typedef enum IMG_NUM_FORMAT { ++ IMG_NUM_FORMAT_UNORM = 0x0, ++ IMG_NUM_FORMAT_SNORM = 0x1, ++ IMG_NUM_FORMAT_USCALED = 0x2, ++ IMG_NUM_FORMAT_SSCALED = 0x3, ++ IMG_NUM_FORMAT_UINT = 0x4, ++ IMG_NUM_FORMAT_SINT = 0x5, ++ IMG_NUM_FORMAT_RESERVED_6 = 0x6, ++ IMG_NUM_FORMAT_FLOAT = 0x7, ++ IMG_NUM_FORMAT_RESERVED_8 = 0x8, ++ IMG_NUM_FORMAT_SRGB = 0x9, ++ IMG_NUM_FORMAT_RESERVED_10 = 0xa, ++ IMG_NUM_FORMAT_RESERVED_11 = 0xb, ++ IMG_NUM_FORMAT_RESERVED_12 = 0xc, ++ IMG_NUM_FORMAT_RESERVED_13 = 0xd, ++ IMG_NUM_FORMAT_RESERVED_14 = 0xe, ++ IMG_NUM_FORMAT_RESERVED_15 = 0xf, ++} IMG_NUM_FORMAT; ++typedef enum TileType { ++ ARRAY_COLOR_TILE = 0x0, ++ ARRAY_DEPTH_TILE = 0x1, ++} TileType; ++typedef enum NonDispTilingOrder { ++ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, ++ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, ++} NonDispTilingOrder; ++typedef enum MicroTileMode { ++ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, ++ ADDR_SURF_THIN_MICRO_TILING = 0x1, ++ ADDR_SURF_DEPTH_MICRO_TILING = 0x2, ++ ADDR_SURF_ROTATED_MICRO_TILING = 0x3, ++ ADDR_SURF_THICK_MICRO_TILING = 0x4, ++} MicroTileMode; ++typedef enum TileSplit { ++ ADDR_SURF_TILE_SPLIT_64B = 0x0, ++ ADDR_SURF_TILE_SPLIT_128B = 0x1, ++ ADDR_SURF_TILE_SPLIT_256B = 0x2, ++ ADDR_SURF_TILE_SPLIT_512B = 0x3, ++ ADDR_SURF_TILE_SPLIT_1KB = 0x4, ++ ADDR_SURF_TILE_SPLIT_2KB = 0x5, ++ ADDR_SURF_TILE_SPLIT_4KB = 0x6, ++} TileSplit; ++typedef enum SampleSplit { ++ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, ++ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, ++ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, ++ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, ++} SampleSplit; ++typedef enum PipeConfig { ++ ADDR_SURF_P2 = 0x0, ++ ADDR_SURF_P2_RESERVED0 = 0x1, ++ ADDR_SURF_P2_RESERVED1 = 0x2, ++ ADDR_SURF_P2_RESERVED2 = 0x3, ++ ADDR_SURF_P4_8x16 = 0x4, ++ ADDR_SURF_P4_16x16 = 0x5, ++ ADDR_SURF_P4_16x32 = 0x6, ++ ADDR_SURF_P4_32x32 = 0x7, ++ ADDR_SURF_P8_16x16_8x16 = 0x8, ++ ADDR_SURF_P8_16x32_8x16 = 0x9, ++ ADDR_SURF_P8_32x32_8x16 = 0xa, ++ ADDR_SURF_P8_16x32_16x16 = 0xb, ++ ADDR_SURF_P8_32x32_16x16 = 0xc, ++ ADDR_SURF_P8_32x32_16x32 = 0xd, ++ ADDR_SURF_P8_32x64_32x32 = 0xe, ++ ADDR_SURF_P8_RESERVED0 = 0xf, ++ ADDR_SURF_P16_32x32_8x16 = 0x10, ++ ADDR_SURF_P16_32x32_16x16 = 0x11, ++} PipeConfig; ++typedef enum NumBanks { ++ ADDR_SURF_2_BANK = 0x0, ++ ADDR_SURF_4_BANK = 0x1, ++ ADDR_SURF_8_BANK = 0x2, ++ ADDR_SURF_16_BANK = 0x3, ++} NumBanks; ++typedef enum BankWidth { ++ ADDR_SURF_BANK_WIDTH_1 = 0x0, ++ ADDR_SURF_BANK_WIDTH_2 = 0x1, ++ ADDR_SURF_BANK_WIDTH_4 = 0x2, ++ ADDR_SURF_BANK_WIDTH_8 = 0x3, ++} BankWidth; ++typedef enum BankHeight { ++ ADDR_SURF_BANK_HEIGHT_1 = 0x0, ++ ADDR_SURF_BANK_HEIGHT_2 = 0x1, ++ ADDR_SURF_BANK_HEIGHT_4 = 0x2, ++ ADDR_SURF_BANK_HEIGHT_8 = 0x3, ++} BankHeight; ++typedef enum BankWidthHeight { ++ ADDR_SURF_BANK_WH_1 = 0x0, ++ ADDR_SURF_BANK_WH_2 = 0x1, ++ ADDR_SURF_BANK_WH_4 = 0x2, ++ ADDR_SURF_BANK_WH_8 = 0x3, ++} BankWidthHeight; ++typedef enum MacroTileAspect { ++ ADDR_SURF_MACRO_ASPECT_1 = 0x0, ++ ADDR_SURF_MACRO_ASPECT_2 = 0x1, ++ ADDR_SURF_MACRO_ASPECT_4 = 0x2, ++ ADDR_SURF_MACRO_ASPECT_8 = 0x3, ++} MacroTileAspect; ++typedef enum GATCL1RequestType { ++ GATCL1_TYPE_NORMAL = 0x0, ++ GATCL1_TYPE_SHOOTDOWN = 0x1, ++ GATCL1_TYPE_BYPASS = 0x2, ++} GATCL1RequestType; ++typedef enum TCC_CACHE_POLICIES { ++ TCC_CACHE_POLICY_LRU = 0x0, ++ TCC_CACHE_POLICY_STREAM = 0x1, ++} TCC_CACHE_POLICIES; ++typedef enum MTYPE { ++ MTYPE_NC_NV = 0x0, ++ MTYPE_NC = 0x1, ++ MTYPE_CC = 0x2, ++ MTYPE_UC = 0x3, ++} MTYPE; ++typedef enum PERFMON_COUNTER_MODE { ++ PERFMON_COUNTER_MODE_ACCUM = 0x0, ++ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, ++ PERFMON_COUNTER_MODE_MAX = 0x2, ++ PERFMON_COUNTER_MODE_DIRTY = 0x3, ++ PERFMON_COUNTER_MODE_SAMPLE = 0x4, ++ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, ++ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, ++ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, ++ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, ++ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, ++ PERFMON_COUNTER_MODE_RESERVED = 0xf, ++} PERFMON_COUNTER_MODE; ++typedef enum PERFMON_SPM_MODE { ++ PERFMON_SPM_MODE_OFF = 0x0, ++ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, ++ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, ++ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, ++ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, ++ PERFMON_SPM_MODE_RESERVED_5 = 0x5, ++ PERFMON_SPM_MODE_RESERVED_6 = 0x6, ++ PERFMON_SPM_MODE_RESERVED_7 = 0x7, ++ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, ++ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, ++ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, ++} PERFMON_SPM_MODE; ++typedef enum SurfaceTiling { ++ ARRAY_LINEAR = 0x0, ++ ARRAY_TILED = 0x1, ++} SurfaceTiling; ++typedef enum SurfaceArray { ++ ARRAY_1D = 0x0, ++ ARRAY_2D = 0x1, ++ ARRAY_3D = 0x2, ++ ARRAY_3D_SLICE = 0x3, ++} SurfaceArray; ++typedef enum ColorArray { ++ ARRAY_2D_ALT_COLOR = 0x0, ++ ARRAY_2D_COLOR = 0x1, ++ ARRAY_3D_SLICE_COLOR = 0x3, ++} ColorArray; ++typedef enum DepthArray { ++ ARRAY_2D_ALT_DEPTH = 0x0, ++ ARRAY_2D_DEPTH = 0x1, ++} DepthArray; ++typedef enum ENUM_NUM_SIMD_PER_CU { ++ NUM_SIMD_PER_CU = 0x4, ++} ENUM_NUM_SIMD_PER_CU; ++typedef enum MEM_PWR_FORCE_CTRL { ++ NO_FORCE_REQUEST = 0x0, ++ FORCE_LIGHT_SLEEP_REQUEST = 0x1, ++ FORCE_DEEP_SLEEP_REQUEST = 0x2, ++ FORCE_SHUT_DOWN_REQUEST = 0x3, ++} MEM_PWR_FORCE_CTRL; ++typedef enum MEM_PWR_FORCE_CTRL2 { ++ NO_FORCE_REQ = 0x0, ++ FORCE_LIGHT_SLEEP_REQ = 0x1, ++} MEM_PWR_FORCE_CTRL2; ++typedef enum MEM_PWR_DIS_CTRL { ++ ENABLE_MEM_PWR_CTRL = 0x0, ++ DISABLE_MEM_PWR_CTRL = 0x1, ++} MEM_PWR_DIS_CTRL; ++typedef enum MEM_PWR_SEL_CTRL { ++ DYNAMIC_SHUT_DOWN_ENABLE = 0x0, ++ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, ++ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, ++} MEM_PWR_SEL_CTRL; ++typedef enum MEM_PWR_SEL_CTRL2 { ++ DYNAMIC_DEEP_SLEEP_EN = 0x0, ++ DYNAMIC_LIGHT_SLEEP_EN = 0x1, ++} MEM_PWR_SEL_CTRL2; ++ ++#endif /* ACP_2_2_ENUM_H */ +diff --git a/sound/soc/amd/include/acp_2_2_sh_mask.h b/sound/soc/amd/include/acp_2_2_sh_mask.h +new file mode 100644 +index 0000000..32d2d41 +--- /dev/null ++++ b/sound/soc/amd/include/acp_2_2_sh_mask.h +@@ -0,0 +1,2292 @@ ++/* ++ * ACP_2_2 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef ACP_2_2_SH_MASK_H ++#define ACP_2_2_SH_MASK_H ++ ++#define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_1__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_1__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_1__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_1__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_1__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_1__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_1__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_1__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_1__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_1__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_2__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_2__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_2__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_2__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_2__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_2__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_2__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_2__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_2__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_2__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_3__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_3__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_3__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_3__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_3__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_3__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_3__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_3__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_3__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_3__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_4__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_4__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_4__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_4__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_4__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_4__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_4__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_4__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_4__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_4__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_5__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_5__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_5__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_5__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_5__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_5__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_5__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_5__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_5__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_5__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_6__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_6__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_6__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_6__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_6__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_6__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_6__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_6__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_6__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_6__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_7__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_7__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_7__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_7__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_7__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_7__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_7__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_7__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_7__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_7__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_8__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_8__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_8__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_8__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_8__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_8__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_8__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_8__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_8__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_8__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_9__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_9__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_9__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_9__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_9__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_9__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_9__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_9__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_9__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_9__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_10__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_10__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_10__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_10__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_10__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_10__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_10__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_10__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_10__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_10__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_11__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_11__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_11__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_11__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_11__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_11__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_11__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_11__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_11__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_11__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_12__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_12__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_12__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_12__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_12__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_12__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_12__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_12__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_12__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_12__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_13__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_13__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_13__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_13__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_13__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_13__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_13__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_13__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_13__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_13__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_14__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_14__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_14__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_14__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_14__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_14__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_14__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_14__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_14__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_14__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_15__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_15__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_15__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_15__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_15__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_15__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_15__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_15__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_15__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_15__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_PRIO_0__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_0__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_1__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_1__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_2__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_2__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_3__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_3__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_4__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_4__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_5__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_5__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_6__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_6__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_7__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_7__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_8__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_8__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_9__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_9__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_10__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_10__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_11__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_11__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_12__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_12__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_13__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_13__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_14__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_14__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_15__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_15__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_0__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_0__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_0__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_0__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_1__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_1__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_1__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_1__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_2__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_2__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_2__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_2__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_3__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_3__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_3__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_3__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_4__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_4__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_4__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_4__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_5__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_5__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_5__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_5__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_6__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_6__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_6__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_6__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_7__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_7__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_7__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_7__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_8__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_8__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_8__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_8__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_9__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_9__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_9__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_9__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_10__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_10__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_10__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_10__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_11__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_11__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_11__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_11__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_12__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_12__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_12__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_12__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_13__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_13__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_13__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_13__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_14__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_14__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_14__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_14__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_15__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_15__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_15__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_15__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr_MASK 0xffffffff ++#define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr__SHIFT 0x0 ++#define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr_MASK 0xf ++#define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr__SHIFT 0x0 ++#define ACP_DMA_CH_STS__DMAChSts_MASK 0xffff ++#define ACP_DMA_CH_STS__DMAChSts__SHIFT 0x0 ++#define ACP_DMA_CH_GROUP__DMAChanelGrouping_MASK 0x1 ++#define ACP_DMA_CH_GROUP__DMAChanelGrouping__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET0__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET0__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE0__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE0__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE0__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE0__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET1__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET1__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE1__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE1__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE1__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE1__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET2__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET2__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE2__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE2__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE2__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE2__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET3__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET3__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE3__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE3__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE3__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE3__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET4__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET4__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE4__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE4__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE4__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE4__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET5__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET5__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE5__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE5__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE5__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE5__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET6__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET6__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE6__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE6__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE6__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE6__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET7__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET7__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE7__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE7__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE7__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE7__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET8__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET8__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE8__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE8__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE8__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE8__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_NONCACHE_OFFSET0__Offset_MASK 0xfffffff ++#define ACP_DSP0_NONCACHE_OFFSET0__Offset__SHIFT 0x0 ++#define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_NONCACHE_SIZE0__Size_MASK 0xffffff ++#define ACP_DSP0_NONCACHE_SIZE0__Size__SHIFT 0x0 ++#define ACP_DSP0_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_NONCACHE_OFFSET1__Offset_MASK 0xfffffff ++#define ACP_DSP0_NONCACHE_OFFSET1__Offset__SHIFT 0x0 ++#define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_NONCACHE_SIZE1__Size_MASK 0xffffff ++#define ACP_DSP0_NONCACHE_SIZE1__Size__SHIFT 0x0 ++#define ACP_DSP0_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_DEBUG_PC__DebugPC_MASK 0xffffffff ++#define ACP_DSP0_DEBUG_PC__DebugPC__SHIFT 0x0 ++#define ACP_DSP0_NMI_SEL__NMISel_MASK 0x1 ++#define ACP_DSP0_NMI_SEL__NMISel__SHIFT 0x0 ++#define ACP_DSP0_CLKRST_CNTL__ClkEn_MASK 0x1 ++#define ACP_DSP0_CLKRST_CNTL__ClkEn__SHIFT 0x0 ++#define ACP_DSP0_CLKRST_CNTL__SoftResetDSP_MASK 0x2 ++#define ACP_DSP0_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 ++#define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 ++#define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 ++#define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 ++#define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 ++#define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 ++#define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 ++#define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 ++#define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 ++#define ACP_DSP0_RUNSTALL__RunStallCntl_MASK 0x1 ++#define ACP_DSP0_RUNSTALL__RunStallCntl__SHIFT 0x0 ++#define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 ++#define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 ++#define ACP_DSP0_WAIT_MODE__WaitMode_MASK 0x1 ++#define ACP_DSP0_WAIT_MODE__WaitMode__SHIFT 0x0 ++#define ACP_DSP0_VECT_SEL__StaticVectorSel_MASK 0x1 ++#define ACP_DSP0_VECT_SEL__StaticVectorSel__SHIFT 0x0 ++#define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff ++#define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 ++#define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff ++#define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 ++#define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff ++#define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET0__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET0__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE0__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE0__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE0__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE0__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET1__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET1__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE1__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE1__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE1__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE1__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET2__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET2__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE2__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE2__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE2__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE2__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET3__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET3__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE3__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE3__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE3__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE3__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET4__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET4__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE4__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE4__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE4__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE4__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET5__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET5__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE5__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE5__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE5__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE5__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET6__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET6__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE6__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE6__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE6__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE6__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET7__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET7__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE7__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE7__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE7__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE7__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET8__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET8__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE8__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE8__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE8__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE8__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_NONCACHE_OFFSET0__Offset_MASK 0xfffffff ++#define ACP_DSP1_NONCACHE_OFFSET0__Offset__SHIFT 0x0 ++#define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_NONCACHE_SIZE0__Size_MASK 0xffffff ++#define ACP_DSP1_NONCACHE_SIZE0__Size__SHIFT 0x0 ++#define ACP_DSP1_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_NONCACHE_OFFSET1__Offset_MASK 0xfffffff ++#define ACP_DSP1_NONCACHE_OFFSET1__Offset__SHIFT 0x0 ++#define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_NONCACHE_SIZE1__Size_MASK 0xffffff ++#define ACP_DSP1_NONCACHE_SIZE1__Size__SHIFT 0x0 ++#define ACP_DSP1_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_DEBUG_PC__DebugPC_MASK 0xffffffff ++#define ACP_DSP1_DEBUG_PC__DebugPC__SHIFT 0x0 ++#define ACP_DSP1_NMI_SEL__NMISel_MASK 0x1 ++#define ACP_DSP1_NMI_SEL__NMISel__SHIFT 0x0 ++#define ACP_DSP1_CLKRST_CNTL__ClkEn_MASK 0x1 ++#define ACP_DSP1_CLKRST_CNTL__ClkEn__SHIFT 0x0 ++#define ACP_DSP1_CLKRST_CNTL__SoftResetDSP_MASK 0x2 ++#define ACP_DSP1_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 ++#define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 ++#define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 ++#define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 ++#define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 ++#define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 ++#define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 ++#define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 ++#define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 ++#define ACP_DSP1_RUNSTALL__RunStallCntl_MASK 0x1 ++#define ACP_DSP1_RUNSTALL__RunStallCntl__SHIFT 0x0 ++#define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 ++#define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 ++#define ACP_DSP1_WAIT_MODE__WaitMode_MASK 0x1 ++#define ACP_DSP1_WAIT_MODE__WaitMode__SHIFT 0x0 ++#define ACP_DSP1_VECT_SEL__StaticVectorSel_MASK 0x1 ++#define ACP_DSP1_VECT_SEL__StaticVectorSel__SHIFT 0x0 ++#define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff ++#define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 ++#define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff ++#define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 ++#define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff ++#define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET0__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET0__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE0__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE0__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE0__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE0__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET1__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET1__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE1__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE1__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE1__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE1__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET2__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET2__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE2__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE2__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE2__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE2__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET3__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET3__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE3__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE3__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE3__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE3__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET4__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET4__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE4__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE4__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE4__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE4__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET5__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET5__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE5__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE5__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE5__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE5__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET6__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET6__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE6__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE6__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE6__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE6__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET7__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET7__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE7__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE7__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE7__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE7__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET8__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET8__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE8__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE8__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE8__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE8__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_NONCACHE_OFFSET0__Offset_MASK 0xfffffff ++#define ACP_DSP2_NONCACHE_OFFSET0__Offset__SHIFT 0x0 ++#define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_NONCACHE_SIZE0__Size_MASK 0xffffff ++#define ACP_DSP2_NONCACHE_SIZE0__Size__SHIFT 0x0 ++#define ACP_DSP2_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_NONCACHE_OFFSET1__Offset_MASK 0xfffffff ++#define ACP_DSP2_NONCACHE_OFFSET1__Offset__SHIFT 0x0 ++#define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_NONCACHE_SIZE1__Size_MASK 0xffffff ++#define ACP_DSP2_NONCACHE_SIZE1__Size__SHIFT 0x0 ++#define ACP_DSP2_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_DEBUG_PC__DebugPC_MASK 0xffffffff ++#define ACP_DSP2_DEBUG_PC__DebugPC__SHIFT 0x0 ++#define ACP_DSP2_NMI_SEL__NMISel_MASK 0x1 ++#define ACP_DSP2_NMI_SEL__NMISel__SHIFT 0x0 ++#define ACP_DSP2_CLKRST_CNTL__ClkEn_MASK 0x1 ++#define ACP_DSP2_CLKRST_CNTL__ClkEn__SHIFT 0x0 ++#define ACP_DSP2_CLKRST_CNTL__SoftResetDSP_MASK 0x2 ++#define ACP_DSP2_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 ++#define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 ++#define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 ++#define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 ++#define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 ++#define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 ++#define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 ++#define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 ++#define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 ++#define ACP_DSP2_RUNSTALL__RunStallCntl_MASK 0x1 ++#define ACP_DSP2_RUNSTALL__RunStallCntl__SHIFT 0x0 ++#define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 ++#define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 ++#define ACP_DSP2_WAIT_MODE__WaitMode_MASK 0x1 ++#define ACP_DSP2_WAIT_MODE__WaitMode__SHIFT 0x0 ++#define ACP_DSP2_VECT_SEL__StaticVectorSel_MASK 0x1 ++#define ACP_DSP2_VECT_SEL__StaticVectorSel__SHIFT 0x0 ++#define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff ++#define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 ++#define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff ++#define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 ++#define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff ++#define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap_MASK 0x3 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap__SHIFT 0x0 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb_MASK 0x80 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb__SHIFT 0x7 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb_MASK 0x100 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb_MASK 0x400 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode_MASK 0x2000 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode__SHIFT 0xd ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f ++#define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1 ++#define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0 ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap_MASK 0x3 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap__SHIFT 0x0 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb_MASK 0x80 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb__SHIFT 0x7 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb_MASK 0x100 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb_MASK 0x400 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode_MASK 0x2000 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode__SHIFT 0xd ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f ++#define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1 ++#define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0 ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate_MASK 0x1 ++#define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate__SHIFT 0x0 ++#define ACP_CONTROL__ClkEn_MASK 0x1 ++#define ACP_CONTROL__ClkEn__SHIFT 0x0 ++#define ACP_CONTROL__JtagEn_MASK 0x400 ++#define ACP_CONTROL__JtagEn__SHIFT 0xa ++#define ACP_STATUS__ClkOn_MASK 0x1 ++#define ACP_STATUS__ClkOn__SHIFT 0x0 ++#define ACP_STATUS__ACPRefClkSpd_MASK 0x2 ++#define ACP_STATUS__ACPRefClkSpd__SHIFT 0x1 ++#define ACP_STATUS__SMUStutterLastEdge_MASK 0x4 ++#define ACP_STATUS__SMUStutterLastEdge__SHIFT 0x2 ++#define ACP_STATUS__MCStutterLastEdge_MASK 0x8 ++#define ACP_STATUS__MCStutterLastEdge__SHIFT 0x3 ++#define ACP_SOFT_RESET__SoftResetAud_MASK 0x100 ++#define ACP_SOFT_RESET__SoftResetAud__SHIFT 0x8 ++#define ACP_SOFT_RESET__SoftResetDMA_MASK 0x200 ++#define ACP_SOFT_RESET__SoftResetDMA__SHIFT 0x9 ++#define ACP_SOFT_RESET__InternalSoftResetMode_MASK 0x4000 ++#define ACP_SOFT_RESET__InternalSoftResetMode__SHIFT 0xe ++#define ACP_SOFT_RESET__ExternalSoftResetMode_MASK 0x8000 ++#define ACP_SOFT_RESET__ExternalSoftResetMode__SHIFT 0xf ++#define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000 ++#define ACP_SOFT_RESET__SoftResetAudDone__SHIFT 0x18 ++#define ACP_SOFT_RESET__SoftResetDMADone_MASK 0x2000000 ++#define ACP_SOFT_RESET__SoftResetDMADone__SHIFT 0x19 ++#define ACP_PwrMgmt_CNTL__SCLKSleepCntl_MASK 0x3 ++#define ACP_PwrMgmt_CNTL__SCLKSleepCntl__SHIFT 0x0 ++#define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter_MASK 0xffff ++#define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter__SHIFT 0x0 ++#define ACP_SMU_MAILBOX__ACP_SMU_Mailbox_MASK 0xffffffff ++#define ACP_SMU_MAILBOX__ACP_SMU_Mailbox__SHIFT 0x0 ++#define ACP_FUTURE_REG_SCLK_0__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_SCLK_0__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_SCLK_1__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_SCLK_1__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_SCLK_2__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_SCLK_2__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_SCLK_3__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_SCLK_3__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_SCLK_4__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_SCLK_4__ACPFutureReg__SHIFT 0x0 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable_MASK 0x1 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable__SHIFT 0x0 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable_MASK 0x2 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable__SHIFT 0x1 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable_MASK 0x4 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable__SHIFT 0x2 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable_MASK 0x8 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable__SHIFT 0x3 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable_MASK 0x10 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable__SHIFT 0x4 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable_MASK 0x20 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable__SHIFT 0x5 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable_MASK 0x40 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable__SHIFT 0x6 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable_MASK 0x80 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable__SHIFT 0x7 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable_MASK 0x100 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable__SHIFT 0x8 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable_MASK 0x200 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable__SHIFT 0x9 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable_MASK 0x400 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable__SHIFT 0xa ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable_MASK 0x800 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable__SHIFT 0xb ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable_MASK 0x1000 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable__SHIFT 0xc ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable_MASK 0x2000 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable__SHIFT 0xd ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable_MASK 0x4000 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable__SHIFT 0xe ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable_MASK 0x8000 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable__SHIFT 0xf ++#define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt_MASK 0xffff ++#define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt__SHIFT 0x0 ++#define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt_MASK 0xffff ++#define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt__SHIFT 0x0 ++#define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt_MASK 0xffff ++#define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt_MASK 0xffff ++#define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt_MASK 0xffff ++#define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt__SHIFT 0x0 ++#define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt_MASK 0xffff ++#define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt__SHIFT 0x0 ++#define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt_MASK 0xffff ++#define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt_MASK 0xffff ++#define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt_MASK 0xffff ++#define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt__SHIFT 0x0 ++#define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt_MASK 0xffff ++#define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt__SHIFT 0x0 ++#define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt_MASK 0xffff ++#define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt_MASK 0xffff ++#define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt_MASK 0xffff ++#define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt__SHIFT 0x0 ++#define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt_MASK 0xffff ++#define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt__SHIFT 0x0 ++#define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt_MASK 0xffff ++#define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt_MASK 0xffff ++#define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt__SHIFT 0x0 ++#define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl_MASK 0xf ++#define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl__SHIFT 0x0 ++#define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb_MASK 0x1 ++#define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb__SHIFT 0x0 ++#define ACP_EXTERNAL_INTR_CNTL__ACPErrMask_MASK 0x1 ++#define ACP_EXTERNAL_INTR_CNTL__ACPErrMask__SHIFT 0x0 ++#define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 ++#define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 ++#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 ++#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 ++#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 ++#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 ++#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 ++#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 ++#define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask_MASK 0x40 ++#define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 ++#define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask_MASK 0x100 ++#define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask__SHIFT 0x8 ++#define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask_MASK 0x200 ++#define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask__SHIFT 0x9 ++#define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask_MASK 0x400 ++#define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask__SHIFT 0xa ++#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x800 ++#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xb ++#define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 ++#define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask__SHIFT 0x10 ++#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr_MASK 0x1 ++#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr__SHIFT 0x0 ++#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource_MASK 0xe ++#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource__SHIFT 0x1 ++#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver_MASK 0x10 ++#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver__SHIFT 0x4 ++#define ACP_ERROR_SOURCE_STS__BRBAddrErr_MASK 0x20 ++#define ACP_ERROR_SOURCE_STS__BRBAddrErr__SHIFT 0x5 ++#define ACP_ERROR_SOURCE_STS__BRBAddrErrSource_MASK 0x3c0 ++#define ACP_ERROR_SOURCE_STS__BRBAddrErrSource__SHIFT 0x6 ++#define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver_MASK 0x400 ++#define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver__SHIFT 0xa ++#define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr_MASK 0x800 ++#define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr__SHIFT 0xb ++#define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr_MASK 0x1000 ++#define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr__SHIFT 0xc ++#define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr_MASK 0x2000 ++#define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr__SHIFT 0xd ++#define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr_MASK 0x4000 ++#define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr__SHIFT 0xe ++#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr_MASK 0x8000 ++#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr__SHIFT 0xf ++#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource_MASK 0x70000 ++#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource__SHIFT 0x10 ++#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver_MASK 0x80000 ++#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver__SHIFT 0x13 ++#define ACP_ERROR_SOURCE_STS__DAGBErr_MASK 0x100000 ++#define ACP_ERROR_SOURCE_STS__DAGBErr__SHIFT 0x14 ++#define ACP_ERROR_SOURCE_STS__DAGBErrSource_MASK 0x1e00000 ++#define ACP_ERROR_SOURCE_STS__DAGBErrSource__SHIFT 0x15 ++#define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver_MASK 0x2000000 ++#define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver__SHIFT 0x19 ++#define ACP_ERROR_SOURCE_STS__DMATermOnErr_MASK 0x4000000 ++#define ACP_ERROR_SOURCE_STS__DMATermOnErr__SHIFT 0x1a ++#define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr_MASK 0x10000000 ++#define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr__SHIFT 0x1c ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0_MASK 0x1 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0__SHIFT 0x0 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1_MASK 0x2 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1__SHIFT 0x1 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2_MASK 0x4 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2__SHIFT 0x2 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0_MASK 0x100 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0__SHIFT 0x8 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1_MASK 0x200 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1__SHIFT 0x9 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2_MASK 0x400 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2__SHIFT 0xa ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host_MASK 0x10000 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host__SHIFT 0x10 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host_MASK 0x20000 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host__SHIFT 0x11 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host_MASK 0x40000 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host__SHIFT 0x12 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0_MASK 0x1 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0__SHIFT 0x0 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1_MASK 0x2 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1__SHIFT 0x1 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2_MASK 0x4 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2__SHIFT 0x2 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0_MASK 0x100 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0__SHIFT 0x8 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1_MASK 0x200 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1__SHIFT 0x9 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2_MASK 0x400 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2__SHIFT 0xa ++#define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask_MASK 0x10000 ++#define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask__SHIFT 0x10 ++#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask_MASK 0x20000 ++#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask__SHIFT 0x11 ++#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask_MASK 0x40000 ++#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask__SHIFT 0x12 ++#define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue_MASK 0x3ffff ++#define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue__SHIFT 0x0 ++#define ACP_DAGBG_TIMEOUT_CNTL__CntEn_MASK 0x80000000 ++#define ACP_DAGBG_TIMEOUT_CNTL__CntEn__SHIFT 0x1f ++#define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue_MASK 0x3ffff ++#define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue__SHIFT 0x0 ++#define ACP_DAGBO_TIMEOUT_CNTL__CntEn_MASK 0x80000000 ++#define ACP_DAGBO_TIMEOUT_CNTL__CntEn__SHIFT 0x1f ++#define ACP_EXTERNAL_INTR_STAT__ACPErrStat_MASK 0x1 ++#define ACP_EXTERNAL_INTR_STAT__ACPErrStat__SHIFT 0x0 ++#define ACP_EXTERNAL_INTR_STAT__ACPErrAck_MASK 0x1 ++#define ACP_EXTERNAL_INTR_STAT__ACPErrAck__SHIFT 0x0 ++#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat_MASK 0x2 ++#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 ++#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck_MASK 0x2 ++#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat_MASK 0x10 ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck_MASK 0x10 ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 ++#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat_MASK 0x40 ++#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 ++#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck_MASK 0x40 ++#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 ++#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat_MASK 0x100 ++#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat__SHIFT 0x8 ++#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck_MASK 0x100 ++#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck__SHIFT 0x8 ++#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat_MASK 0x200 ++#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat__SHIFT 0x9 ++#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck_MASK 0x200 ++#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck__SHIFT 0x9 ++#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat_MASK 0x400 ++#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat__SHIFT 0xa ++#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck_MASK 0x400 ++#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck__SHIFT 0xa ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat_MASK 0x800 ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xb ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck_MASK 0x800 ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xb ++#define ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK 0xffff0000 ++#define ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT 0x10 ++#define ACP_EXTERNAL_INTR_STAT__DMAIOCAck_MASK 0xffff0000 ++#define ACP_EXTERNAL_INTR_STAT__DMAIOCAck__SHIFT 0x10 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat_MASK 0x1 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat__SHIFT 0x0 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack_MASK 0x1 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack__SHIFT 0x0 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat_MASK 0x2 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat__SHIFT 0x1 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack_MASK 0x2 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack__SHIFT 0x1 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat_MASK 0x4 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat__SHIFT 0x2 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack_MASK 0x4 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack__SHIFT 0x2 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat_MASK 0x100 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat__SHIFT 0x8 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack_MASK 0x100 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack__SHIFT 0x8 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat_MASK 0x200 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat__SHIFT 0x9 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack_MASK 0x200 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack__SHIFT 0x9 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat_MASK 0x400 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat__SHIFT 0xa ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack_MASK 0x400 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack__SHIFT 0xa ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat_MASK 0x10000 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat__SHIFT 0x10 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack_MASK 0x10000 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack__SHIFT 0x10 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat_MASK 0x20000 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat__SHIFT 0x11 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack_MASK 0x20000 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack__SHIFT 0x11 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat_MASK 0x40000 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat__SHIFT 0x12 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack_MASK 0x40000 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack__SHIFT 0x12 ++#define ACP_DSP0_INTR_CNTL__ACPErrMask_MASK 0x1 ++#define ACP_DSP0_INTR_CNTL__ACPErrMask__SHIFT 0x0 ++#define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 ++#define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 ++#define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 ++#define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 ++#define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 ++#define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 ++#define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 ++#define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 ++#define ACP_DSP0_INTR_CNTL__AzaliaIntrMask_MASK 0x40 ++#define ACP_DSP0_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 ++#define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 ++#define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 ++#define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 ++#define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 ++#define ACP_DSP0_INTR_CNTL__MCStutterStatusMask_MASK 0x400 ++#define ACP_DSP0_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa ++#define ACP_DSP0_INTR_CNTL__DSPExtTimerMask_MASK 0x800 ++#define ACP_DSP0_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb ++#define ACP_DSP0_INTR_CNTL__DSPSemRespMask_MASK 0x1000 ++#define ACP_DSP0_INTR_CNTL__DSPSemRespMask__SHIFT 0xc ++#define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 ++#define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd ++#define ACP_DSP0_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 ++#define ACP_DSP0_INTR_CNTL__DMAIOCMask__SHIFT 0x10 ++#define ACP_DSP0_INTR_STAT__ACPErrStat_MASK 0x1 ++#define ACP_DSP0_INTR_STAT__ACPErrStat__SHIFT 0x0 ++#define ACP_DSP0_INTR_STAT__ACPErrAck_MASK 0x1 ++#define ACP_DSP0_INTR_STAT__ACPErrAck__SHIFT 0x0 ++#define ACP_DSP0_INTR_STAT__I2SMicDataAvStat_MASK 0x2 ++#define ACP_DSP0_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 ++#define ACP_DSP0_INTR_STAT__I2SMicDataAvAck_MASK 0x2 ++#define ACP_DSP0_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 ++#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 ++#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 ++#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 ++#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 ++#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 ++#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 ++#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 ++#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 ++#define ACP_DSP0_INTR_STAT__I2SBTDataAvStat_MASK 0x10 ++#define ACP_DSP0_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 ++#define ACP_DSP0_INTR_STAT__I2SBTDataAvAck_MASK 0x10 ++#define ACP_DSP0_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 ++#define ACP_DSP0_INTR_STAT__AzaliaIntrStat_MASK 0x40 ++#define ACP_DSP0_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 ++#define ACP_DSP0_INTR_STAT__AzaliaIntrAck_MASK 0x40 ++#define ACP_DSP0_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 ++#define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 ++#define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 ++#define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 ++#define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 ++#define ACP_DSP0_INTR_STAT__SMUStutterStatusStat_MASK 0x200 ++#define ACP_DSP0_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 ++#define ACP_DSP0_INTR_STAT__SMUStutterStatusAck_MASK 0x200 ++#define ACP_DSP0_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 ++#define ACP_DSP0_INTR_STAT__MCStutterStatusStat_MASK 0x400 ++#define ACP_DSP0_INTR_STAT__MCStutterStatusStat__SHIFT 0xa ++#define ACP_DSP0_INTR_STAT__MCStutterStatusAck_MASK 0x400 ++#define ACP_DSP0_INTR_STAT__MCStutterStatusAck__SHIFT 0xa ++#define ACP_DSP0_INTR_STAT__DSPExtTimerStat_MASK 0x800 ++#define ACP_DSP0_INTR_STAT__DSPExtTimerStat__SHIFT 0xb ++#define ACP_DSP0_INTR_STAT__DSPExtTimerAck_MASK 0x800 ++#define ACP_DSP0_INTR_STAT__DSPExtTimerAck__SHIFT 0xb ++#define ACP_DSP0_INTR_STAT__DSPSemRespStat_MASK 0x1000 ++#define ACP_DSP0_INTR_STAT__DSPSemRespStat__SHIFT 0xc ++#define ACP_DSP0_INTR_STAT__DSPSemRespAck_MASK 0x1000 ++#define ACP_DSP0_INTR_STAT__DSPSemRespAck__SHIFT 0xc ++#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 ++#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd ++#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 ++#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd ++#define ACP_DSP0_INTR_STAT__DMAIOCStat_MASK 0xffff0000 ++#define ACP_DSP0_INTR_STAT__DMAIOCStat__SHIFT 0x10 ++#define ACP_DSP0_INTR_STAT__DMAIOCAck_MASK 0xffff0000 ++#define ACP_DSP0_INTR_STAT__DMAIOCAck__SHIFT 0x10 ++#define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue_MASK 0x3ffff ++#define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue__SHIFT 0x0 ++#define ACP_DSP0_TIMEOUT_CNTL__CntEn_MASK 0x80000000 ++#define ACP_DSP0_TIMEOUT_CNTL__CntEn__SHIFT 0x1f ++#define ACP_DSP1_INTR_CNTL__ACPErrMask_MASK 0x1 ++#define ACP_DSP1_INTR_CNTL__ACPErrMask__SHIFT 0x0 ++#define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 ++#define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 ++#define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 ++#define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 ++#define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 ++#define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 ++#define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 ++#define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 ++#define ACP_DSP1_INTR_CNTL__AzaliaIntrMask_MASK 0x40 ++#define ACP_DSP1_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 ++#define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 ++#define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 ++#define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 ++#define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 ++#define ACP_DSP1_INTR_CNTL__MCStutterStatusMask_MASK 0x400 ++#define ACP_DSP1_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa ++#define ACP_DSP1_INTR_CNTL__DSPExtTimerMask_MASK 0x800 ++#define ACP_DSP1_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb ++#define ACP_DSP1_INTR_CNTL__DSPSemRespMask_MASK 0x1000 ++#define ACP_DSP1_INTR_CNTL__DSPSemRespMask__SHIFT 0xc ++#define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 ++#define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd ++#define ACP_DSP1_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 ++#define ACP_DSP1_INTR_CNTL__DMAIOCMask__SHIFT 0x10 ++#define ACP_DSP1_INTR_STAT__ACPErrStat_MASK 0x1 ++#define ACP_DSP1_INTR_STAT__ACPErrStat__SHIFT 0x0 ++#define ACP_DSP1_INTR_STAT__ACPErrAck_MASK 0x1 ++#define ACP_DSP1_INTR_STAT__ACPErrAck__SHIFT 0x0 ++#define ACP_DSP1_INTR_STAT__I2SMicDataAvStat_MASK 0x2 ++#define ACP_DSP1_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 ++#define ACP_DSP1_INTR_STAT__I2SMicDataAvAck_MASK 0x2 ++#define ACP_DSP1_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 ++#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 ++#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 ++#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 ++#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 ++#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 ++#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 ++#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 ++#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 ++#define ACP_DSP1_INTR_STAT__I2SBTDataAvStat_MASK 0x10 ++#define ACP_DSP1_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 ++#define ACP_DSP1_INTR_STAT__I2SBTDataAvAck_MASK 0x10 ++#define ACP_DSP1_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 ++#define ACP_DSP1_INTR_STAT__AzaliaIntrStat_MASK 0x40 ++#define ACP_DSP1_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 ++#define ACP_DSP1_INTR_STAT__AzaliaIntrAck_MASK 0x40 ++#define ACP_DSP1_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 ++#define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 ++#define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 ++#define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 ++#define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 ++#define ACP_DSP1_INTR_STAT__SMUStutterStatusStat_MASK 0x200 ++#define ACP_DSP1_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 ++#define ACP_DSP1_INTR_STAT__SMUStutterStatusAck_MASK 0x200 ++#define ACP_DSP1_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 ++#define ACP_DSP1_INTR_STAT__MCStutterStatusStat_MASK 0x400 ++#define ACP_DSP1_INTR_STAT__MCStutterStatusStat__SHIFT 0xa ++#define ACP_DSP1_INTR_STAT__MCStutterStatusAck_MASK 0x400 ++#define ACP_DSP1_INTR_STAT__MCStutterStatusAck__SHIFT 0xa ++#define ACP_DSP1_INTR_STAT__DSPExtTimerStat_MASK 0x800 ++#define ACP_DSP1_INTR_STAT__DSPExtTimerStat__SHIFT 0xb ++#define ACP_DSP1_INTR_STAT__DSPExtTimerAck_MASK 0x800 ++#define ACP_DSP1_INTR_STAT__DSPExtTimerAck__SHIFT 0xb ++#define ACP_DSP1_INTR_STAT__DSPSemRespStat_MASK 0x1000 ++#define ACP_DSP1_INTR_STAT__DSPSemRespStat__SHIFT 0xc ++#define ACP_DSP1_INTR_STAT__DSPSemRespAck_MASK 0x1000 ++#define ACP_DSP1_INTR_STAT__DSPSemRespAck__SHIFT 0xc ++#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 ++#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd ++#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 ++#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd ++#define ACP_DSP1_INTR_STAT__DMAIOCStat_MASK 0xffff0000 ++#define ACP_DSP1_INTR_STAT__DMAIOCStat__SHIFT 0x10 ++#define ACP_DSP1_INTR_STAT__DMAIOCAck_MASK 0xffff0000 ++#define ACP_DSP1_INTR_STAT__DMAIOCAck__SHIFT 0x10 ++#define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue_MASK 0x3ffff ++#define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue__SHIFT 0x0 ++#define ACP_DSP1_TIMEOUT_CNTL__CntEn_MASK 0x80000000 ++#define ACP_DSP1_TIMEOUT_CNTL__CntEn__SHIFT 0x1f ++#define ACP_DSP2_INTR_CNTL__ACPErrMask_MASK 0x1 ++#define ACP_DSP2_INTR_CNTL__ACPErrMask__SHIFT 0x0 ++#define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 ++#define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 ++#define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 ++#define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 ++#define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 ++#define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 ++#define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 ++#define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 ++#define ACP_DSP2_INTR_CNTL__AzaliaIntrMask_MASK 0x40 ++#define ACP_DSP2_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 ++#define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 ++#define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 ++#define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 ++#define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 ++#define ACP_DSP2_INTR_CNTL__MCStutterStatusMask_MASK 0x400 ++#define ACP_DSP2_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa ++#define ACP_DSP2_INTR_CNTL__DSPExtTimerMask_MASK 0x800 ++#define ACP_DSP2_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb ++#define ACP_DSP2_INTR_CNTL__DSPSemRespMask_MASK 0x1000 ++#define ACP_DSP2_INTR_CNTL__DSPSemRespMask__SHIFT 0xc ++#define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 ++#define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd ++#define ACP_DSP2_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 ++#define ACP_DSP2_INTR_CNTL__DMAIOCMask__SHIFT 0x10 ++#define ACP_DSP2_INTR_STAT__ACPErrStat_MASK 0x1 ++#define ACP_DSP2_INTR_STAT__ACPErrStat__SHIFT 0x0 ++#define ACP_DSP2_INTR_STAT__ACPErrAck_MASK 0x1 ++#define ACP_DSP2_INTR_STAT__ACPErrAck__SHIFT 0x0 ++#define ACP_DSP2_INTR_STAT__I2SMicDataAvStat_MASK 0x2 ++#define ACP_DSP2_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 ++#define ACP_DSP2_INTR_STAT__I2SMicDataAvAck_MASK 0x2 ++#define ACP_DSP2_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 ++#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 ++#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 ++#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 ++#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 ++#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 ++#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 ++#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 ++#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 ++#define ACP_DSP2_INTR_STAT__I2SBTDataAvStat_MASK 0x10 ++#define ACP_DSP2_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 ++#define ACP_DSP2_INTR_STAT__I2SBTDataAvAck_MASK 0x10 ++#define ACP_DSP2_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 ++#define ACP_DSP2_INTR_STAT__AzaliaIntrStat_MASK 0x40 ++#define ACP_DSP2_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 ++#define ACP_DSP2_INTR_STAT__AzaliaIntrAck_MASK 0x40 ++#define ACP_DSP2_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 ++#define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 ++#define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 ++#define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 ++#define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 ++#define ACP_DSP2_INTR_STAT__SMUStutterStatusStat_MASK 0x200 ++#define ACP_DSP2_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 ++#define ACP_DSP2_INTR_STAT__SMUStutterStatusAck_MASK 0x200 ++#define ACP_DSP2_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 ++#define ACP_DSP2_INTR_STAT__MCStutterStatusStat_MASK 0x400 ++#define ACP_DSP2_INTR_STAT__MCStutterStatusStat__SHIFT 0xa ++#define ACP_DSP2_INTR_STAT__MCStutterStatusAck_MASK 0x400 ++#define ACP_DSP2_INTR_STAT__MCStutterStatusAck__SHIFT 0xa ++#define ACP_DSP2_INTR_STAT__DSPExtTimerStat_MASK 0x800 ++#define ACP_DSP2_INTR_STAT__DSPExtTimerStat__SHIFT 0xb ++#define ACP_DSP2_INTR_STAT__DSPExtTimerAck_MASK 0x800 ++#define ACP_DSP2_INTR_STAT__DSPExtTimerAck__SHIFT 0xb ++#define ACP_DSP2_INTR_STAT__DSPSemRespStat_MASK 0x1000 ++#define ACP_DSP2_INTR_STAT__DSPSemRespStat__SHIFT 0xc ++#define ACP_DSP2_INTR_STAT__DSPSemRespAck_MASK 0x1000 ++#define ACP_DSP2_INTR_STAT__DSPSemRespAck__SHIFT 0xc ++#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 ++#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd ++#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 ++#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd ++#define ACP_DSP2_INTR_STAT__DMAIOCStat_MASK 0xffff0000 ++#define ACP_DSP2_INTR_STAT__DMAIOCStat__SHIFT 0x10 ++#define ACP_DSP2_INTR_STAT__DMAIOCAck_MASK 0xffff0000 ++#define ACP_DSP2_INTR_STAT__DMAIOCAck__SHIFT 0x10 ++#define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue_MASK 0x3ffff ++#define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue__SHIFT 0x0 ++#define ACP_DSP2_TIMEOUT_CNTL__CntEn_MASK 0x80000000 ++#define ACP_DSP2_TIMEOUT_CNTL__CntEn__SHIFT 0x1f ++#define ACP_DSP0_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff ++#define ACP_DSP0_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 ++#define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 ++#define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e ++#define ACP_DSP1_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff ++#define ACP_DSP1_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 ++#define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 ++#define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e ++#define ACP_DSP2_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff ++#define ACP_DSP2_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 ++#define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 ++#define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e ++#define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr_MASK 0xff ++#define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr__SHIFT 0x0 ++#define ACP_SRBM_Client_RDDATA__ReadData_MASK 0xffffffff ++#define ACP_SRBM_Client_RDDATA__ReadData__SHIFT 0x0 ++#define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts_MASK 0x1 ++#define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts__SHIFT 0x0 ++#define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr_MASK 0x7ffffff ++#define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr__SHIFT 0x0 ++#define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data_MASK 0xffffffff ++#define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data__SHIFT 0x0 ++#define ACP_SEMA_ADDR_LOW__ADDR_9_3_MASK 0x7f ++#define ACP_SEMA_ADDR_LOW__ADDR_9_3__SHIFT 0x0 ++#define ACP_SEMA_ADDR_HIGH__ADDR_39_10_MASK 0x3fffffff ++#define ACP_SEMA_ADDR_HIGH__ADDR_39_10__SHIFT 0x0 ++#define ACP_SEMA_CMD__REQ_CMD_MASK 0xf ++#define ACP_SEMA_CMD__REQ_CMD__SHIFT 0x0 ++#define ACP_SEMA_CMD__WR_PHASE_MASK 0x30 ++#define ACP_SEMA_CMD__WR_PHASE__SHIFT 0x4 ++#define ACP_SEMA_CMD__VMID_EN_MASK 0x80 ++#define ACP_SEMA_CMD__VMID_EN__SHIFT 0x7 ++#define ACP_SEMA_CMD__VMID_MASK 0xf00 ++#define ACP_SEMA_CMD__VMID__SHIFT 0x8 ++#define ACP_SEMA_CMD__ATC_MASK 0x1000 ++#define ACP_SEMA_CMD__ATC__SHIFT 0xc ++#define ACP_SEMA_STS__REQ_STS_MASK 0x3 ++#define ACP_SEMA_STS__REQ_STS__SHIFT 0x0 ++#define ACP_SEMA_STS__REQ_RESP_AVAIL_MASK 0x100 ++#define ACP_SEMA_STS__REQ_RESP_AVAIL__SHIFT 0x8 ++#define ACP_SEMA_REQ__ISSUE_POLL_REQ_MASK 0x1 ++#define ACP_SEMA_REQ__ISSUE_POLL_REQ__SHIFT 0x0 ++#define ACP_FW_STATUS__RUN_MASK 0x1 ++#define ACP_FW_STATUS__RUN__SHIFT 0x0 ++#define ACP_FUTURE_REG_ACLK_0__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_ACLK_0__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_ACLK_1__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_ACLK_1__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_ACLK_2__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_ACLK_2__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_ACLK_3__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_ACLK_3__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_ACLK_4__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_ACLK_4__ACPFutureReg__SHIFT 0x0 ++#define ACP_TIMER__ACP_Timer_count_MASK 0xffffffff ++#define ACP_TIMER__ACP_Timer_count__SHIFT 0x0 ++#define ACP_TIMER_CNTL__ACP_Timer_control_MASK 0x1 ++#define ACP_TIMER_CNTL__ACP_Timer_control__SHIFT 0x0 ++#define ACP_DSP0_TIMER__ACP_DSP0_timer_MASK 0xffffff ++#define ACP_DSP0_TIMER__ACP_DSP0_timer__SHIFT 0x0 ++#define ACP_DSP1_TIMER__ACP_DSP1_timer_MASK 0xffffff ++#define ACP_DSP1_TIMER__ACP_DSP1_timer__SHIFT 0x0 ++#define ACP_DSP2_TIMER__ACP_DSP2_timer_MASK 0xffffff ++#define ACP_DSP2_TIMER__ACP_DSP2_timer__SHIFT 0x0 ++#define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high_MASK 0xffffffff ++#define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high__SHIFT 0x0 ++#define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low_MASK 0xffffffff ++#define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low__SHIFT 0x0 ++#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high_MASK 0xffffffff ++#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high__SHIFT 0x0 ++#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low_MASK 0xffffffff ++#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low__SHIFT 0x0 ++#define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high_MASK 0xffffffff ++#define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high__SHIFT 0x0 ++#define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low_MASK 0xffffffff ++#define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low__SHIFT 0x0 ++#define ACP_DSP0_CS_STATE__DSP0_CS_state_MASK 0x1 ++#define ACP_DSP0_CS_STATE__DSP0_CS_state__SHIFT 0x0 ++#define ACP_DSP1_CS_STATE__DSP1_CS_state_MASK 0x1 ++#define ACP_DSP1_CS_STATE__DSP1_CS_state__SHIFT 0x0 ++#define ACP_DSP2_CS_STATE__DSP2_CS_state_MASK 0x1 ++#define ACP_DSP2_CS_STATE__DSP2_CS_state__SHIFT 0x0 ++#define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR_MASK 0x7ffff ++#define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR__SHIFT 0x0 ++#define CC_ACP_EFUSE__DSP0_DISABLE_MASK 0x2 ++#define CC_ACP_EFUSE__DSP0_DISABLE__SHIFT 0x1 ++#define CC_ACP_EFUSE__DSP1_DISABLE_MASK 0x4 ++#define CC_ACP_EFUSE__DSP1_DISABLE__SHIFT 0x2 ++#define CC_ACP_EFUSE__DSP2_DISABLE_MASK 0x8 ++#define CC_ACP_EFUSE__DSP2_DISABLE__SHIFT 0x3 ++#define CC_ACP_EFUSE__ACP_DISABLE_MASK 0x10 ++#define CC_ACP_EFUSE__ACP_DISABLE__SHIFT 0x4 ++#define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF_MASK 0x1 ++#define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF__SHIFT 0x0 ++#define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF_MASK 0x2 ++#define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF__SHIFT 0x1 ++#define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF_MASK 0x4 ++#define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF__SHIFT 0x2 ++#define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF_MASK 0x8 ++#define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF__SHIFT 0x3 ++#define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF_MASK 0x10 ++#define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF__SHIFT 0x4 ++#define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF_MASK 0x20 ++#define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF__SHIFT 0x5 ++#define ACP_PGFSM_CONFIG_REG__FSM_ADDR_MASK 0xff ++#define ACP_PGFSM_CONFIG_REG__FSM_ADDR__SHIFT 0x0 ++#define ACP_PGFSM_CONFIG_REG__Power_Down_MASK 0x100 ++#define ACP_PGFSM_CONFIG_REG__Power_Down__SHIFT 0x8 ++#define ACP_PGFSM_CONFIG_REG__Power_Up_MASK 0x200 ++#define ACP_PGFSM_CONFIG_REG__Power_Up__SHIFT 0x9 ++#define ACP_PGFSM_CONFIG_REG__P1_Select_MASK 0x400 ++#define ACP_PGFSM_CONFIG_REG__P1_Select__SHIFT 0xa ++#define ACP_PGFSM_CONFIG_REG__P2_Select_MASK 0x800 ++#define ACP_PGFSM_CONFIG_REG__P2_Select__SHIFT 0xb ++#define ACP_PGFSM_CONFIG_REG__Wr_MASK 0x1000 ++#define ACP_PGFSM_CONFIG_REG__Wr__SHIFT 0xc ++#define ACP_PGFSM_CONFIG_REG__Rd_MASK 0x2000 ++#define ACP_PGFSM_CONFIG_REG__Rd__SHIFT 0xd ++#define ACP_PGFSM_CONFIG_REG__RdData_Reset_MASK 0x4000 ++#define ACP_PGFSM_CONFIG_REG__RdData_Reset__SHIFT 0xe ++#define ACP_PGFSM_CONFIG_REG__Short_Format_MASK 0x8000 ++#define ACP_PGFSM_CONFIG_REG__Short_Format__SHIFT 0xf ++#define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG_MASK 0x3ff0000 ++#define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG__SHIFT 0x10 ++#define ACP_PGFSM_CONFIG_REG__SRBM_override_MASK 0x4000000 ++#define ACP_PGFSM_CONFIG_REG__SRBM_override__SHIFT 0x1a ++#define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr_MASK 0x8000000 ++#define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr__SHIFT 0x1b ++#define ACP_PGFSM_CONFIG_REG__REG_ADDR_MASK 0xf0000000 ++#define ACP_PGFSM_CONFIG_REG__REG_ADDR__SHIFT 0x1c ++#define ACP_PGFSM_WRITE_REG__Write_value_MASK 0xffffffff ++#define ACP_PGFSM_WRITE_REG__Write_value__SHIFT 0x0 ++#define ACP_PGFSM_READ_REG_0__Read_value_MASK 0xffffff ++#define ACP_PGFSM_READ_REG_0__Read_value__SHIFT 0x0 ++#define ACP_PGFSM_READ_REG_1__Read_value_MASK 0xffffff ++#define ACP_PGFSM_READ_REG_1__Read_value__SHIFT 0x0 ++#define ACP_PGFSM_READ_REG_2__Read_value_MASK 0xffffff ++#define ACP_PGFSM_READ_REG_2__Read_value__SHIFT 0x0 ++#define ACP_PGFSM_READ_REG_3__Read_value_MASK 0xffffff ++#define ACP_PGFSM_READ_REG_3__Read_value__SHIFT 0x0 ++#define ACP_PGFSM_READ_REG_4__Read_value_MASK 0xffffff ++#define ACP_PGFSM_READ_REG_4__Read_value__SHIFT 0x0 ++#define ACP_PGFSM_READ_REG_5__Read_value_MASK 0xffffff ++#define ACP_PGFSM_READ_REG_5__Read_value__SHIFT 0x0 ++#define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS_MASK 0x1 ++#define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS__SHIFT 0x0 ++#define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG_MASK 0x3 ++#define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG__SHIFT 0x0 ++#define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT_MASK 0x1 ++#define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT__SHIFT 0x0 ++#define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package_MASK 0x1 ++#define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package__SHIFT 0x0 ++#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable_MASK 0x7ff ++#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable__SHIFT 0x0 ++#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable_MASK 0x7ff0000 ++#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable__SHIFT 0x10 ++#define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL_MASK 0x1 ++#define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL__SHIFT 0x0 ++#define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable_MASK 0x1 ++#define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable__SHIFT 0x0 ++#define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status_MASK 0x1 ++#define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold_MASK 0xffffffff ++#define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold_MASK 0xffffffff ++#define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples_MASK 0xffff ++#define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks_MASK 0xffff ++#define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks_MASK 0xffffffff ++#define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en_MASK 0x1 ++#define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req_MASK 0x1 ++#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack_MASK 0x2 ++#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack__SHIFT 0x1 ++#define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer_MASK 0xffffffff ++#define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid_MASK 0x1 ++#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match_MASK 0x2 ++#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match__SHIFT 0x1 ++#define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap_MASK 0x1 ++#define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap__SHIFT 0x0 ++#define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high_MASK 0xffffffff ++#define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high__SHIFT 0x0 ++#define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low_MASK 0xffffffff ++#define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low__SHIFT 0x0 ++#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high_MASK 0xffffffff ++#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high__SHIFT 0x0 ++#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low_MASK 0xffffffff ++#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low__SHIFT 0x0 ++#define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML_MASK 0xffffffff ++#define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML__SHIFT 0x0 ++#define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH_MASK 0xffff ++#define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH__SHIFT 0x0 ++#define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML_MASK 0xffffffff ++#define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML__SHIFT 0x0 ++#define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH_MASK 0xffff ++#define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH__SHIFT 0x0 ++#define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML_MASK 0xffffffff ++#define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML__SHIFT 0x0 ++#define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH_MASK 0xffff ++#define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH__SHIFT 0x0 ++#define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML_MASK 0xffffffff ++#define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML__SHIFT 0x0 ++#define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH_MASK 0xffff ++#define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH__SHIFT 0x0 ++#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo_MASK 0xffffffff ++#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo__SHIFT 0x0 ++#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi_MASK 0xffff ++#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi__SHIFT 0x0 ++#define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo_MASK 0xffffffff ++#define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo__SHIFT 0x0 ++#define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi_MASK 0xffff ++#define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi__SHIFT 0x0 ++#define ACP_I2SSP_IER__I2SSP_IEN_MASK 0x1 ++#define ACP_I2SSP_IER__I2SSP_IEN__SHIFT 0x0 ++#define ACP_I2SSP_IRER__I2SSP_RXEN_MASK 0x1 ++#define ACP_I2SSP_IRER__I2SSP_RXEN__SHIFT 0x0 ++#define ACP_I2SSP_ITER__I2SSP_TXEN_MASK 0x1 ++#define ACP_I2SSP_ITER__I2SSP_TXEN__SHIFT 0x0 ++#define ACP_I2SSP_CER__I2SSP_CLKEN_MASK 0x1 ++#define ACP_I2SSP_CER__I2SSP_CLKEN__SHIFT 0x0 ++#define ACP_I2SSP_CCR__I2SSP_SCLKG_MASK 0x7 ++#define ACP_I2SSP_CCR__I2SSP_SCLKG__SHIFT 0x0 ++#define ACP_I2SSP_CCR__I2SSP_WSS_MASK 0x18 ++#define ACP_I2SSP_CCR__I2SSP_WSS__SHIFT 0x3 ++#define ACP_I2SSP_RXFFR__I2SSP_RXFFR_MASK 0x1 ++#define ACP_I2SSP_RXFFR__I2SSP_RXFFR__SHIFT 0x0 ++#define ACP_I2SSP_TXFFR__I2SSP_TXFFR_MASK 0x1 ++#define ACP_I2SSP_TXFFR__I2SSP_TXFFR__SHIFT 0x0 ++#define ACP_I2SSP_LRBR0__I2SSP_LRBR0_MASK 0xffffffff ++#define ACP_I2SSP_LRBR0__I2SSP_LRBR0__SHIFT 0x0 ++#define ACP_I2SSP_RRBR0__I2SSP_RRBR0_MASK 0xffffffff ++#define ACP_I2SSP_RRBR0__I2SSP_RRBR0__SHIFT 0x0 ++#define ACP_I2SSP_RER0__I2SSP_RXCHEN0_MASK 0x1 ++#define ACP_I2SSP_RER0__I2SSP_RXCHEN0__SHIFT 0x0 ++#define ACP_I2SSP_TER0__I2SSP_TXCHEN0_MASK 0x1 ++#define ACP_I2SSP_TER0__I2SSP_TXCHEN0__SHIFT 0x0 ++#define ACP_I2SSP_RCR0__I2SSP_WLEN_MASK 0x7 ++#define ACP_I2SSP_RCR0__I2SSP_WLEN__SHIFT 0x0 ++#define ACP_I2SSP_TCR0__I2SSP_WLEN_MASK 0x7 ++#define ACP_I2SSP_TCR0__I2SSP_WLEN__SHIFT 0x0 ++#define ACP_I2SSP_ISR0__I2SSP_RXDA_MASK 0x1 ++#define ACP_I2SSP_ISR0__I2SSP_RXDA__SHIFT 0x0 ++#define ACP_I2SSP_ISR0__I2SSP_RXFO_MASK 0x2 ++#define ACP_I2SSP_ISR0__I2SSP_RXFO__SHIFT 0x1 ++#define ACP_I2SSP_ISR0__I2SSP_TXFE_MASK 0x10 ++#define ACP_I2SSP_ISR0__I2SSP_TXFE__SHIFT 0x4 ++#define ACP_I2SSP_ISR0__I2SSP_TXFO_MASK 0x20 ++#define ACP_I2SSP_ISR0__I2SSP_TXFO__SHIFT 0x5 ++#define ACP_I2SSP_IMR0__I2SSP_RXDAM_MASK 0x1 ++#define ACP_I2SSP_IMR0__I2SSP_RXDAM__SHIFT 0x0 ++#define ACP_I2SSP_IMR0__I2SSP_RXFOM_MASK 0x2 ++#define ACP_I2SSP_IMR0__I2SSP_RXFOM__SHIFT 0x1 ++#define ACP_I2SSP_IMR0__I2SSP_TXFEM_MASK 0x10 ++#define ACP_I2SSP_IMR0__I2SSP_TXFEM__SHIFT 0x4 ++#define ACP_I2SSP_IMR0__I2SSP_TXFOM_MASK 0x20 ++#define ACP_I2SSP_IMR0__I2SSP_TXFOM__SHIFT 0x5 ++#define ACP_I2SSP_ROR0__I2SSP_RXCHO_MASK 0x1 ++#define ACP_I2SSP_ROR0__I2SSP_RXCHO__SHIFT 0x0 ++#define ACP_I2SSP_TOR0__I2SSP_TXCHO_MASK 0x1 ++#define ACP_I2SSP_TOR0__I2SSP_TXCHO__SHIFT 0x0 ++#define ACP_I2SSP_RFCR0__I2SSP_RXCHDT_MASK 0xf ++#define ACP_I2SSP_RFCR0__I2SSP_RXCHDT__SHIFT 0x0 ++#define ACP_I2SSP_TFCR0__I2SSP_TXCHET_MASK 0xf ++#define ACP_I2SSP_TFCR0__I2SSP_TXCHET__SHIFT 0x0 ++#define ACP_I2SSP_RFF0__I2SSP_RXCHFR_MASK 0x1 ++#define ACP_I2SSP_RFF0__I2SSP_RXCHFR__SHIFT 0x0 ++#define ACP_I2SSP_TFF0__I2SSP_TXCHFR_MASK 0x1 ++#define ACP_I2SSP_TFF0__I2SSP_TXCHFR__SHIFT 0x0 ++#define ACP_I2SSP_RXDMA__I2SSP_RXDMA_MASK 0xffffffff ++#define ACP_I2SSP_RXDMA__I2SSP_RXDMA__SHIFT 0x0 ++#define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA_MASK 0x1 ++#define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA__SHIFT 0x0 ++#define ACP_I2SSP_TXDMA__I2SSP_TXDMA_MASK 0xffffffff ++#define ACP_I2SSP_TXDMA__I2SSP_TXDMA__SHIFT 0x0 ++#define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA_MASK 0x1 ++#define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA__SHIFT 0x0 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0_MASK 0x7 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0__SHIFT 0x0 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1_MASK 0x38 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1__SHIFT 0x3 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2_MASK 0x380 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2__SHIFT 0x7 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3_MASK 0x1c00 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3__SHIFT 0xa ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH_MASK 0x3 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH__SHIFT 0x0 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL_MASK 0xc ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL__SHIFT 0x2 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN_MASK 0x10 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN__SHIFT 0x4 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK_MASK 0x20 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK__SHIFT 0x5 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK_MASK 0x40 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK__SHIFT 0x6 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES_MASK 0x180 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES__SHIFT 0x7 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES_MASK 0x600 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES__SHIFT 0x9 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0_MASK 0x70000 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0__SHIFT 0x10 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1_MASK 0x380000 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1__SHIFT 0x13 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2_MASK 0x1c00000 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2__SHIFT 0x16 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3_MASK 0xe000000 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3__SHIFT 0x19 ++#define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH_MASK 0xffffffff ++#define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH__SHIFT 0x0 ++#define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE_MASK 0xffffffff ++#define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE__SHIFT 0x0 ++#define ACP_I2SMICSP_IER__I2SMICSP_IEN_MASK 0x1 ++#define ACP_I2SMICSP_IER__I2SMICSP_IEN__SHIFT 0x0 ++#define ACP_I2SMICSP_IRER__I2SMICSP_RXEN_MASK 0x1 ++#define ACP_I2SMICSP_IRER__I2SMICSP_RXEN__SHIFT 0x0 ++#define ACP_I2SMICSP_ITER__I2SMICSP_TXEN_MASK 0x1 ++#define ACP_I2SMICSP_ITER__I2SMICSP_TXEN__SHIFT 0x0 ++#define ACP_I2SMICSP_CER__I2SMICSP_CLKEN_MASK 0x1 ++#define ACP_I2SMICSP_CER__I2SMICSP_CLKEN__SHIFT 0x0 ++#define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG_MASK 0x7 ++#define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG__SHIFT 0x0 ++#define ACP_I2SMICSP_CCR__I2SMICSP_WSS_MASK 0x18 ++#define ACP_I2SMICSP_CCR__I2SMICSP_WSS__SHIFT 0x3 ++#define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR_MASK 0x1 ++#define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR__SHIFT 0x0 ++#define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR_MASK 0x1 ++#define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR__SHIFT 0x0 ++#define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0_MASK 0xffffffff ++#define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0__SHIFT 0x0 ++#define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0_MASK 0xffffffff ++#define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0__SHIFT 0x0 ++#define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0_MASK 0x1 ++#define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0__SHIFT 0x0 ++#define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0_MASK 0x1 ++#define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0__SHIFT 0x0 ++#define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN_MASK 0x7 ++#define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN__SHIFT 0x0 ++#define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN_MASK 0x7 ++#define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN__SHIFT 0x0 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA_MASK 0x1 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA__SHIFT 0x0 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO_MASK 0x2 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO__SHIFT 0x1 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE_MASK 0x10 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE__SHIFT 0x4 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO_MASK 0x20 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO__SHIFT 0x5 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM_MASK 0x1 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM__SHIFT 0x0 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM_MASK 0x2 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM__SHIFT 0x1 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM_MASK 0x10 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM__SHIFT 0x4 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM_MASK 0x20 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM__SHIFT 0x5 ++#define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO_MASK 0x1 ++#define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO__SHIFT 0x0 ++#define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO_MASK 0x1 ++#define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO__SHIFT 0x0 ++#define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT_MASK 0xf ++#define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT__SHIFT 0x0 ++#define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET_MASK 0xf ++#define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET__SHIFT 0x0 ++#define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR_MASK 0x1 ++#define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR__SHIFT 0x0 ++#define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR_MASK 0x1 ++#define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR__SHIFT 0x0 ++#define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1_MASK 0xffffffff ++#define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1__SHIFT 0x0 ++#define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1_MASK 0xffffffff ++#define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1__SHIFT 0x0 ++#define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1_MASK 0x1 ++#define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1__SHIFT 0x0 ++#define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1_MASK 0x1 ++#define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1__SHIFT 0x0 ++#define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN_MASK 0x7 ++#define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN__SHIFT 0x0 ++#define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN_MASK 0x7 ++#define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN__SHIFT 0x0 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA_MASK 0x1 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA__SHIFT 0x0 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO_MASK 0x2 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO__SHIFT 0x1 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE_MASK 0x10 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE__SHIFT 0x4 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO_MASK 0x20 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO__SHIFT 0x5 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK 0x1 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM__SHIFT 0x0 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK 0x2 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM__SHIFT 0x1 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM_MASK 0x10 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM__SHIFT 0x4 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM_MASK 0x20 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM__SHIFT 0x5 ++#define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO_MASK 0x1 ++#define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO__SHIFT 0x0 ++#define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO_MASK 0x1 ++#define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO__SHIFT 0x0 ++#define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT_MASK 0xf ++#define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT__SHIFT 0x0 ++#define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET_MASK 0xf ++#define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET__SHIFT 0x0 ++#define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR_MASK 0x1 ++#define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR__SHIFT 0x0 ++#define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR_MASK 0x1 ++#define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR__SHIFT 0x0 ++#define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA_MASK 0xffffffff ++#define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA__SHIFT 0x0 ++#define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA_MASK 0x1 ++#define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA__SHIFT 0x0 ++#define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA_MASK 0xffffffff ++#define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA__SHIFT 0x0 ++#define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA_MASK 0x1 ++#define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA__SHIFT 0x0 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0_MASK 0x7 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0__SHIFT 0x0 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1_MASK 0x38 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1__SHIFT 0x3 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2_MASK 0x380 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2__SHIFT 0x7 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3_MASK 0x1c00 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3__SHIFT 0xa ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH_MASK 0x3 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x0 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL_MASK 0xc ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL__SHIFT 0x2 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN_MASK 0x10 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN__SHIFT 0x4 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK_MASK 0x20 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK__SHIFT 0x5 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK_MASK 0x40 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK__SHIFT 0x6 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES_MASK 0x180 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES__SHIFT 0x7 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES_MASK 0x600 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES__SHIFT 0x9 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0_MASK 0x70000 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0__SHIFT 0x10 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1_MASK 0x380000 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1__SHIFT 0x13 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2_MASK 0x1c00000 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2__SHIFT 0x16 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3_MASK 0xe000000 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3__SHIFT 0x19 ++#define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH_MASK 0xffffffff ++#define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x0 ++#define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE_MASK 0xffffffff ++#define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE__SHIFT 0x0 ++#define ACP_I2SBT_IER__I2SBT_IEN_MASK 0x1 ++#define ACP_I2SBT_IER__I2SBT_IEN__SHIFT 0x0 ++#define ACP_I2SBT_IRER__I2SBT_RXEN_MASK 0x1 ++#define ACP_I2SBT_IRER__I2SBT_RXEN__SHIFT 0x0 ++#define ACP_I2SBT_ITER__I2SBT_TXEN_MASK 0x1 ++#define ACP_I2SBT_ITER__I2SBT_TXEN__SHIFT 0x0 ++#define ACP_I2SBT_CER__I2SBT_CLKEN_MASK 0x1 ++#define ACP_I2SBT_CER__I2SBT_CLKEN__SHIFT 0x0 ++#define ACP_I2SBT_CCR__I2SBT_SCLKG_MASK 0x7 ++#define ACP_I2SBT_CCR__I2SBT_SCLKG__SHIFT 0x0 ++#define ACP_I2SBT_CCR__I2SBT_WSS_MASK 0x18 ++#define ACP_I2SBT_CCR__I2SBT_WSS__SHIFT 0x3 ++#define ACP_I2SBT_RXFFR__I2SBT_RXFFR_MASK 0x1 ++#define ACP_I2SBT_RXFFR__I2SBT_RXFFR__SHIFT 0x0 ++#define ACP_I2SBT_TXFFR__I2SBT_TXFFR_MASK 0x1 ++#define ACP_I2SBT_TXFFR__I2SBT_TXFFR__SHIFT 0x0 ++#define ACP_I2SBT_LRBR0__I2SBT_LRBR0_MASK 0xffffffff ++#define ACP_I2SBT_LRBR0__I2SBT_LRBR0__SHIFT 0x0 ++#define ACP_I2SBT_RRBR0__I2SBT_RRBR0_MASK 0xffffffff ++#define ACP_I2SBT_RRBR0__I2SBT_RRBR0__SHIFT 0x0 ++#define ACP_I2SBT_RER0__I2SBT_RXCHEN0_MASK 0x1 ++#define ACP_I2SBT_RER0__I2SBT_RXCHEN0__SHIFT 0x0 ++#define ACP_I2SBT_TER0__I2SBT_TXCHEN0_MASK 0x1 ++#define ACP_I2SBT_TER0__I2SBT_TXCHEN0__SHIFT 0x0 ++#define ACP_I2SBT_RCR0__I2SBT_WLEN_MASK 0x7 ++#define ACP_I2SBT_RCR0__I2SBT_WLEN__SHIFT 0x0 ++#define ACP_I2SBT_TCR0__I2SBT_WLEN_MASK 0x7 ++#define ACP_I2SBT_TCR0__I2SBT_WLEN__SHIFT 0x0 ++#define ACP_I2SBT_ISR0__I2SBT_RXDA_MASK 0x1 ++#define ACP_I2SBT_ISR0__I2SBT_RXDA__SHIFT 0x0 ++#define ACP_I2SBT_ISR0__I2SBT_RXFO_MASK 0x2 ++#define ACP_I2SBT_ISR0__I2SBT_RXFO__SHIFT 0x1 ++#define ACP_I2SBT_ISR0__I2SBT_TXFE_MASK 0x10 ++#define ACP_I2SBT_ISR0__I2SBT_TXFE__SHIFT 0x4 ++#define ACP_I2SBT_ISR0__I2SBT_TXFO_MASK 0x20 ++#define ACP_I2SBT_ISR0__I2SBT_TXFO__SHIFT 0x5 ++#define ACP_I2SBT_IMR0__I2SBT_RXDAM_MASK 0x1 ++#define ACP_I2SBT_IMR0__I2SBT_RXDAM__SHIFT 0x0 ++#define ACP_I2SBT_IMR0__I2SBT_RXFOM_MASK 0x2 ++#define ACP_I2SBT_IMR0__I2SBT_RXFOM__SHIFT 0x1 ++#define ACP_I2SBT_IMR0__I2SBT_TXFEM_MASK 0x10 ++#define ACP_I2SBT_IMR0__I2SBT_TXFEM__SHIFT 0x4 ++#define ACP_I2SBT_IMR0__I2SBT_TXFOM_MASK 0x20 ++#define ACP_I2SBT_IMR0__I2SBT_TXFOM__SHIFT 0x5 ++#define ACP_I2SBT_ROR0__I2SBT_RXCHO_MASK 0x1 ++#define ACP_I2SBT_ROR0__I2SBT_RXCHO__SHIFT 0x0 ++#define ACP_I2SBT_TOR0__I2SBT_TXCHO_MASK 0x1 ++#define ACP_I2SBT_TOR0__I2SBT_TXCHO__SHIFT 0x0 ++#define ACP_I2SBT_RFCR0__I2SBT_RXCHDT_MASK 0xf ++#define ACP_I2SBT_RFCR0__I2SBT_RXCHDT__SHIFT 0x0 ++#define ACP_I2SBT_TFCR0__I2SBT_TXCHET_MASK 0xf ++#define ACP_I2SBT_TFCR0__I2SBT_TXCHET__SHIFT 0x0 ++#define ACP_I2SBT_RFF0__I2SBT_RXCHFR_MASK 0x1 ++#define ACP_I2SBT_RFF0__I2SBT_RXCHFR__SHIFT 0x0 ++#define ACP_I2SBT_TFF0__I2SBT_TXCHFR_MASK 0x1 ++#define ACP_I2SBT_TFF0__I2SBT_TXCHFR__SHIFT 0x0 ++#define ACP_I2SBT_LRBR1__I2SBT_LRBR1_MASK 0xffffffff ++#define ACP_I2SBT_LRBR1__I2SBT_LRBR1__SHIFT 0x0 ++#define ACP_I2SBT_RRBR1__I2SBT_RRBR1_MASK 0xffffffff ++#define ACP_I2SBT_RRBR1__I2SBT_RRBR1__SHIFT 0x0 ++#define ACP_I2SBT_RER1__I2SBT_RXCHEN1_MASK 0x1 ++#define ACP_I2SBT_RER1__I2SBT_RXCHEN1__SHIFT 0x0 ++#define ACP_I2SBT_TER1__I2SBT_TXCHEN1_MASK 0x1 ++#define ACP_I2SBT_TER1__I2SBT_TXCHEN1__SHIFT 0x0 ++#define ACP_I2SBT_RCR1__I2SBT_WLEN_MASK 0x7 ++#define ACP_I2SBT_RCR1__I2SBT_WLEN__SHIFT 0x0 ++#define ACP_I2SBT_TCR1__I2SBT_WLEN_MASK 0x7 ++#define ACP_I2SBT_TCR1__I2SBT_WLEN__SHIFT 0x0 ++#define ACP_I2SBT_ISR1__I2SBT_RXDA_MASK 0x1 ++#define ACP_I2SBT_ISR1__I2SBT_RXDA__SHIFT 0x0 ++#define ACP_I2SBT_ISR1__I2SBT_RXFO_MASK 0x2 ++#define ACP_I2SBT_ISR1__I2SBT_RXFO__SHIFT 0x1 ++#define ACP_I2SBT_ISR1__I2SBT_TXFE_MASK 0x10 ++#define ACP_I2SBT_ISR1__I2SBT_TXFE__SHIFT 0x4 ++#define ACP_I2SBT_ISR1__I2SBT_TXFO_MASK 0x20 ++#define ACP_I2SBT_ISR1__I2SBT_TXFO__SHIFT 0x5 ++#define ACP_I2SBT_IMR1__I2SBT_RXDAM_MASK 0x1 ++#define ACP_I2SBT_IMR1__I2SBT_RXDAM__SHIFT 0x0 ++#define ACP_I2SBT_IMR1__I2SBT_RXFOM_MASK 0x2 ++#define ACP_I2SBT_IMR1__I2SBT_RXFOM__SHIFT 0x1 ++#define ACP_I2SBT_IMR1__I2SBT_TXFEM_MASK 0x10 ++#define ACP_I2SBT_IMR1__I2SBT_TXFEM__SHIFT 0x4 ++#define ACP_I2SBT_IMR1__I2SBT_TXFOM_MASK 0x20 ++#define ACP_I2SBT_IMR1__I2SBT_TXFOM__SHIFT 0x5 ++#define ACP_I2SBT_ROR1__I2SBT_RXCHO_MASK 0x1 ++#define ACP_I2SBT_ROR1__I2SBT_RXCHO__SHIFT 0x0 ++#define ACP_I2SBT_TOR1__I2SBT_TXCHO_MASK 0x1 ++#define ACP_I2SBT_TOR1__I2SBT_TXCHO__SHIFT 0x0 ++#define ACP_I2SBT_RFCR1__I2SBT_RXCHDT_MASK 0xf ++#define ACP_I2SBT_RFCR1__I2SBT_RXCHDT__SHIFT 0x0 ++#define ACP_I2SBT_TFCR1__I2SBT_TXCHET_MASK 0xf ++#define ACP_I2SBT_TFCR1__I2SBT_TXCHET__SHIFT 0x0 ++#define ACP_I2SBT_RFF1__I2SBT_RXCHFR_MASK 0x1 ++#define ACP_I2SBT_RFF1__I2SBT_RXCHFR__SHIFT 0x0 ++#define ACP_I2SBT_TFF1__I2SBT_TXCHFR_MASK 0x1 ++#define ACP_I2SBT_TFF1__I2SBT_TXCHFR__SHIFT 0x0 ++#define ACP_I2SBT_RXDMA__I2SBT_RXDMA_MASK 0xffffffff ++#define ACP_I2SBT_RXDMA__I2SBT_RXDMA__SHIFT 0x0 ++#define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA_MASK 0x1 ++#define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA__SHIFT 0x0 ++#define ACP_I2SBT_TXDMA__I2SBT_TXDMA_MASK 0xffffffff ++#define ACP_I2SBT_TXDMA__I2SBT_TXDMA__SHIFT 0x0 ++#define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA_MASK 0x1 ++#define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA__SHIFT 0x0 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0_MASK 0x7 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0__SHIFT 0x0 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1_MASK 0x38 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1__SHIFT 0x3 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2_MASK 0x380 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2__SHIFT 0x7 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3_MASK 0x1c00 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3__SHIFT 0xa ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH_MASK 0x3 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH__SHIFT 0x0 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL_MASK 0xc ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL__SHIFT 0x2 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN_MASK 0x10 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN__SHIFT 0x4 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK_MASK 0x20 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK__SHIFT 0x5 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK_MASK 0x40 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK__SHIFT 0x6 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES_MASK 0x180 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES__SHIFT 0x7 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES_MASK 0x600 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES__SHIFT 0x9 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0_MASK 0x70000 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0__SHIFT 0x10 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1_MASK 0x380000 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1__SHIFT 0x13 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2_MASK 0x1c00000 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2__SHIFT 0x16 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3_MASK 0xe000000 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3__SHIFT 0x19 ++#define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH_MASK 0xffffffff ++#define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH__SHIFT 0x0 ++#define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE_MASK 0xffffffff ++#define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE__SHIFT 0x0 ++ ++#endif /* ACP_2_2_SH_MASK_H */ +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1127-ASoC-AMD-add-AMD-ASoC-ACP-2.x-DMA-driver.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1127-ASoC-AMD-add-AMD-ASoC-ACP-2.x-DMA-driver.patch new file mode 100644 index 00000000..6ad546e3 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1127-ASoC-AMD-add-AMD-ASoC-ACP-2.x-DMA-driver.patch @@ -0,0 +1,1092 @@ +From e3a10e5c1dd68d0a0133023084f15aa05662090c Mon Sep 17 00:00:00 2001 +From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> +Date: Tue, 24 Nov 2015 11:54:50 +0530 +Subject: [PATCH 02/17] ASoC: AMD: add AMD ASoC ACP 2.x DMA driver + +ACP IP has internal DMA controller with multiple channels which +can be programmed in cyclic/non cyclic manner. ACP can generate +interrupt upon completion of DMA transfer, if required. +The PCM driver provides the platform DMA component to ALSA core. + +Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Murali Krishna Vemuri <murali-krishna.vemuri@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + sound/soc/amd/Kconfig | 4 + + sound/soc/amd/Makefile | 3 + + sound/soc/amd/acp-pcm-dma.c | 914 ++++++++++++++++++++++++++++++++++++++++++++ + sound/soc/amd/acp.h | 118 ++++++ + 4 files changed, 1039 insertions(+) + create mode 100644 sound/soc/amd/Kconfig + create mode 100644 sound/soc/amd/Makefile + create mode 100644 sound/soc/amd/acp-pcm-dma.c + create mode 100644 sound/soc/amd/acp.h + +diff --git a/sound/soc/amd/Kconfig b/sound/soc/amd/Kconfig +new file mode 100644 +index 0000000..78187eb +--- /dev/null ++++ b/sound/soc/amd/Kconfig +@@ -0,0 +1,4 @@ ++config SND_SOC_AMD_ACP ++ tristate "AMD Audio Coprocessor support" ++ help ++ This option enables ACP DMA support on AMD platform. +diff --git a/sound/soc/amd/Makefile b/sound/soc/amd/Makefile +new file mode 100644 +index 0000000..1a66ec0 +--- /dev/null ++++ b/sound/soc/amd/Makefile +@@ -0,0 +1,3 @@ ++snd-soc-acp-pcm-objs := acp-pcm-dma.o ++ ++obj-$(CONFIG_SND_SOC_AMD_ACP) += snd-soc-acp-pcm.o +diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c +new file mode 100644 +index 0000000..0724d78 +--- /dev/null ++++ b/sound/soc/amd/acp-pcm-dma.c +@@ -0,0 +1,914 @@ ++/* ++ * AMD ALSA SoC PCM Driver for ACP 2.x ++ * ++ * Copyright 2014-2015 Advanced Micro Devices, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ */ ++ ++#include <linux/module.h> ++#include <linux/delay.h> ++#include <linux/sizes.h> ++ ++#include <sound/soc.h> ++ ++#include "acp.h" ++ ++#define PLAYBACK_MIN_NUM_PERIODS 2 ++#define PLAYBACK_MAX_NUM_PERIODS 2 ++#define PLAYBACK_MAX_PERIOD_SIZE 16384 ++#define PLAYBACK_MIN_PERIOD_SIZE 1024 ++#define CAPTURE_MIN_NUM_PERIODS 2 ++#define CAPTURE_MAX_NUM_PERIODS 2 ++#define CAPTURE_MAX_PERIOD_SIZE 16384 ++#define CAPTURE_MIN_PERIOD_SIZE 1024 ++ ++#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) ++#define MIN_BUFFER MAX_BUFFER ++ ++static const struct snd_pcm_hardware acp_pcm_hardware_playback = { ++ .info = SNDRV_PCM_INFO_INTERLEAVED | ++ SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | ++ SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, ++ .channels_min = 1, ++ .channels_max = 8, ++ .rates = SNDRV_PCM_RATE_8000_96000, ++ .rate_min = 8000, ++ .rate_max = 96000, ++ .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, ++ .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, ++ .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, ++ .periods_min = PLAYBACK_MIN_NUM_PERIODS, ++ .periods_max = PLAYBACK_MAX_NUM_PERIODS, ++}; ++ ++static const struct snd_pcm_hardware acp_pcm_hardware_capture = { ++ .info = SNDRV_PCM_INFO_INTERLEAVED | ++ SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | ++ SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_48000, ++ .rate_min = 8000, ++ .rate_max = 48000, ++ .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, ++ .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, ++ .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, ++ .periods_min = CAPTURE_MIN_NUM_PERIODS, ++ .periods_max = CAPTURE_MAX_NUM_PERIODS, ++}; ++ ++struct audio_drv_data { ++ struct snd_pcm_substream *play_stream; ++ struct snd_pcm_substream *capture_stream; ++ void __iomem *acp_mmio; ++}; ++ ++static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) ++{ ++ return readl(acp_mmio + (reg * 4)); ++} ++ ++static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) ++{ ++ writel(val, acp_mmio + (reg * 4)); ++} ++ ++/* Configure a given dma channel parameters - enable/disble, ++ * number of descriptors, priority ++ */ ++static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, ++ u16 dscr_strt_idx, u16 num_dscrs, ++ enum acp_dma_priority_level priority_level) ++{ ++ u32 dma_ctrl; ++ ++ /* disable the channel run field */ ++ dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); ++ dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; ++ acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); ++ ++ /* program a DMA channel with first descriptor to be processed. */ ++ acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK ++ & dscr_strt_idx), ++ acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); ++ ++ /* program a DMA channel with the number of descriptors to be ++ * processed in the transfer ++ */ ++ acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, ++ acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); ++ ++ /* set DMA channel priority */ ++ acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); ++} ++ ++/* Initialize a dma descriptor in SRAM based on descritor information passed */ ++static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, ++ u16 descr_idx, ++ acp_dma_dscr_transfer_t *descr_info) ++{ ++ u32 sram_offset; ++ ++ sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); ++ ++ /* program the source base address. */ ++ acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); ++ acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); ++ /* program the destination base address. */ ++ acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); ++ acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); ++ ++ /* program the number of bytes to be transferred for this descriptor. */ ++ acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); ++ acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); ++} ++ ++/* Initialize the DMA descriptor information for transfer between ++ * system memory <-> ACP SRAM ++ */ ++static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, ++ u32 size, int direction, ++ u32 pte_offset) ++{ ++ u16 i; ++ u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; ++ acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; ++ ++ for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { ++ dmadscr[i].xfer_val = 0; ++ if (direction == SNDRV_PCM_STREAM_PLAYBACK) { ++ dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12 + i; ++ dmadscr[i].dest = ACP_SHARED_RAM_BANK_1_ADDRESS + ++ (size / 2) - (i * (size/2)); ++ dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS ++ + (pte_offset * SZ_4K) + (i * (size/2)); ++ dmadscr[i].xfer_val |= ++ (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM << 16) | ++ (size / 2); ++ } else { ++ dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14 + i; ++ dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS + ++ (i * (size/2)); ++ dmadscr[i].dest = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS ++ + (pte_offset * SZ_4K) + ++ (i * (size/2)); ++ dmadscr[i].xfer_val |= ++ BIT(22) | ++ (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) | ++ (size / 2); ++ } ++ config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, ++ &dmadscr[i]); ++ } ++ if (direction == SNDRV_PCM_STREAM_PLAYBACK) ++ config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, ++ PLAYBACK_START_DMA_DESCR_CH12, ++ NUM_DSCRS_PER_CHANNEL, ++ ACP_DMA_PRIORITY_LEVEL_NORMAL); ++ else ++ config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, ++ CAPTURE_START_DMA_DESCR_CH14, ++ NUM_DSCRS_PER_CHANNEL, ++ ACP_DMA_PRIORITY_LEVEL_NORMAL); ++} ++ ++/* Initialize the DMA descriptor information for transfer between ++ * ACP SRAM <-> I2S ++ */ ++static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, ++ u32 size, int direction) ++{ ++ ++ u16 i; ++ u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13; ++ acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; ++ ++ for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { ++ dmadscr[i].xfer_val = 0; ++ if (direction == SNDRV_PCM_STREAM_PLAYBACK) { ++ dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13 + i; ++ dmadscr[i].src = ACP_SHARED_RAM_BANK_1_ADDRESS + ++ (i * (size/2)); ++ /* dmadscr[i].dest is unused by hardware. */ ++ dmadscr[i].dest = 0; ++ dmadscr[i].xfer_val |= BIT(22) | (TO_ACP_I2S_1 << 16) | ++ (size / 2); ++ } else { ++ dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15 + i; ++ /* dmadscr[i].src is unused by hardware. */ ++ dmadscr[i].src = 0; ++ dmadscr[i].dest = ACP_SHARED_RAM_BANK_5_ADDRESS + ++ (i * (size / 2)); ++ dmadscr[i].xfer_val |= BIT(22) | ++ (FROM_ACP_I2S_1 << 16) | (size / 2); ++ } ++ config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, ++ &dmadscr[i]); ++ } ++ /* Configure the DMA channel with the above descriptore */ ++ if (direction == SNDRV_PCM_STREAM_PLAYBACK) ++ config_acp_dma_channel(acp_mmio, ACP_TO_I2S_DMA_CH_NUM, ++ PLAYBACK_START_DMA_DESCR_CH13, ++ NUM_DSCRS_PER_CHANNEL, ++ ACP_DMA_PRIORITY_LEVEL_NORMAL); ++ else ++ config_acp_dma_channel(acp_mmio, I2S_TO_ACP_DMA_CH_NUM, ++ CAPTURE_START_DMA_DESCR_CH15, ++ NUM_DSCRS_PER_CHANNEL, ++ ACP_DMA_PRIORITY_LEVEL_NORMAL); ++} ++ ++/* Create page table entries in ACP SRAM for the allocated memory */ ++static void acp_pte_config(void __iomem *acp_mmio, struct page *pg, ++ u16 num_of_pages, u32 pte_offset) ++{ ++ u16 page_idx; ++ u64 addr; ++ u32 low; ++ u32 high; ++ u32 offset; ++ ++ offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); ++ for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { ++ /* Load the low address of page int ACP SRAM through SRBM */ ++ acp_reg_write((offset + (page_idx * 8)), ++ acp_mmio, mmACP_SRBM_Targ_Idx_Addr); ++ addr = page_to_phys(pg); ++ ++ low = lower_32_bits(addr); ++ high = upper_32_bits(addr); ++ ++ acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); ++ ++ /* Load the High address of page int ACP SRAM through SRBM */ ++ acp_reg_write((offset + (page_idx * 8) + 4), ++ acp_mmio, mmACP_SRBM_Targ_Idx_Addr); ++ ++ /* page enable in ACP */ ++ high |= BIT(31); ++ acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); ++ ++ /* Move to next physically contiguos page */ ++ pg++; ++ } ++} ++ ++static void config_acp_dma(void __iomem *acp_mmio, ++ struct audio_substream_data *audio_config) ++{ ++ u32 pte_offset; ++ ++ if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) ++ pte_offset = ACP_PLAYBACK_PTE_OFFSET; ++ else ++ pte_offset = ACP_CAPTURE_PTE_OFFSET; ++ ++ acp_pte_config(acp_mmio, audio_config->pg, audio_config->num_of_pages, ++ pte_offset); ++ ++ /* Configure System memory <-> ACP SRAM DMA descriptors */ ++ set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size, ++ audio_config->direction, pte_offset); ++ ++ /* Configure ACP SRAM <-> I2S DMA descriptors */ ++ set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size, ++ audio_config->direction); ++} ++ ++/* Start a given DMA channel transfer */ ++static void acp_dma_start(void __iomem *acp_mmio, ++ u16 ch_num, bool is_circular) ++{ ++ u32 dma_ctrl; ++ ++ /* read the dma control register and disable the channel run field */ ++ dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); ++ ++ /* Invalidating the DAGB cache */ ++ acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); ++ ++ /* configure the DMA channel and start the DMA transfer ++ * set dmachrun bit to start the transfer and enable the ++ * interrupt on completion of the dma transfer ++ */ ++ dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; ++ ++ switch (ch_num) { ++ case ACP_TO_I2S_DMA_CH_NUM: ++ case ACP_TO_SYSRAM_CH_NUM: ++ case I2S_TO_ACP_DMA_CH_NUM: ++ dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; ++ break; ++ default: ++ dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; ++ break; ++ } ++ ++ /* enable for ACP SRAM to/from I2S DMA channel */ ++ if (is_circular == true) ++ dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; ++ else ++ dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK; ++ ++ acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); ++} ++ ++/* Stop a given DMA channel transfer */ ++static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) ++{ ++ u32 dma_ctrl; ++ u32 dma_ch_sts; ++ u32 count = ACP_DMA_RESET_TIME; ++ ++ dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); ++ ++ /* clear the dma control register fields before writing zero ++ * in reset bit ++ */ ++ dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; ++ dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; ++ ++ acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); ++ dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); ++ ++ if (dma_ch_sts & BIT(ch_num)) { ++ /* set the reset bit for this channel to stop the dma ++ * transfer ++ */ ++ dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; ++ acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); ++ } ++ ++ /* check the channel status bit for some time and return the status */ ++ while (true) { ++ dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); ++ if (!(dma_ch_sts & BIT(ch_num))) { ++ /* clear the reset flag after successfully stopping ++ * the dma transfer and break from the loop ++ */ ++ dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; ++ ++ acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 ++ + ch_num); ++ break; ++ } ++ if (--count == 0) { ++ pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); ++ return -ETIMEDOUT; ++ } ++ udelay(100); ++ } ++ return 0; ++} ++ ++/* Initialize and bring ACP hardware to default state. */ ++static int acp_init(void __iomem *acp_mmio) ++{ ++ u32 val, count, sram_pte_offset; ++ ++ /* Assert Soft reset of ACP */ ++ val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); ++ ++ val |= ACP_SOFT_RESET__SoftResetAud_MASK; ++ acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); ++ ++ count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; ++ while (true) { ++ val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); ++ if (ACP_SOFT_RESET__SoftResetAudDone_MASK == ++ (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) ++ break; ++ if (--count == 0) { ++ pr_err("Failed to reset ACP\n"); ++ return -ETIMEDOUT; ++ } ++ udelay(100); ++ } ++ ++ /* Enable clock to ACP and wait until the clock is enabled */ ++ val = acp_reg_read(acp_mmio, mmACP_CONTROL); ++ val = val | ACP_CONTROL__ClkEn_MASK; ++ acp_reg_write(val, acp_mmio, mmACP_CONTROL); ++ ++ count = ACP_CLOCK_EN_TIME_OUT_VALUE; ++ ++ while (true) { ++ val = acp_reg_read(acp_mmio, mmACP_STATUS); ++ if (val & (u32) 0x1) ++ break; ++ if (--count == 0) { ++ pr_err("Failed to reset ACP\n"); ++ return -ETIMEDOUT; ++ } ++ udelay(100); ++ } ++ ++ /* Deassert the SOFT RESET flags */ ++ val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); ++ val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; ++ acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); ++ ++ /* initiailize Onion control DAGB register */ ++ acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, ++ mmACP_AXI2DAGB_ONION_CNTL); ++ ++ /* initiailize Garlic control DAGB registers */ ++ acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, ++ mmACP_AXI2DAGB_GARLIC_CNTL); ++ ++ sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | ++ ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | ++ ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | ++ ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; ++ acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); ++ acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, ++ mmACP_DAGB_PAGE_SIZE_GRP_1); ++ ++ acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, ++ mmACP_DMA_DESC_BASE_ADDR); ++ ++ /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */ ++ acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); ++ acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, ++ acp_mmio, mmACP_EXTERNAL_INTR_CNTL); ++ ++ return 0; ++} ++ ++/* Deintialize ACP */ ++static int acp_deinit(void __iomem *acp_mmio) ++{ ++ u32 val; ++ u32 count; ++ ++ /* Assert Soft reset of ACP */ ++ val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); ++ ++ val |= ACP_SOFT_RESET__SoftResetAud_MASK; ++ acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); ++ ++ count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; ++ while (true) { ++ val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); ++ if (ACP_SOFT_RESET__SoftResetAudDone_MASK == ++ (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) ++ break; ++ if (--count == 0) { ++ pr_err("Failed to reset ACP\n"); ++ return -ETIMEDOUT; ++ } ++ udelay(100); ++ } ++ /** Disable ACP clock */ ++ val = acp_reg_read(acp_mmio, mmACP_CONTROL); ++ val &= ~ACP_CONTROL__ClkEn_MASK; ++ acp_reg_write(val, acp_mmio, mmACP_CONTROL); ++ ++ count = ACP_CLOCK_EN_TIME_OUT_VALUE; ++ ++ while (true) { ++ val = acp_reg_read(acp_mmio, mmACP_STATUS); ++ if (!(val & (u32) 0x1)) ++ break; ++ if (--count == 0) { ++ pr_err("Failed to reset ACP\n"); ++ return -ETIMEDOUT; ++ } ++ udelay(100); ++ } ++ return 0; ++} ++ ++/* ACP DMA irq handler routine for playback, capture usecases */ ++static irqreturn_t dma_irq_handler(int irq, void *arg) ++{ ++ u16 dscr_idx; ++ u32 intr_flag, ext_intr_status; ++ struct audio_drv_data *irq_data; ++ void __iomem *acp_mmio; ++ struct device *dev = arg; ++ bool valid_irq = false; ++ ++ irq_data = dev_get_drvdata(dev); ++ acp_mmio = irq_data->acp_mmio; ++ ++ ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); ++ intr_flag = (((ext_intr_status & ++ ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> ++ ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); ++ ++ if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { ++ valid_irq = true; ++ if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_13) == ++ PLAYBACK_START_DMA_DESCR_CH13) ++ dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; ++ else ++ dscr_idx = PLAYBACK_END_DMA_DESCR_CH12; ++ config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, dscr_idx, ++ 1, 0); ++ acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false); ++ ++ snd_pcm_period_elapsed(irq_data->play_stream); ++ ++ acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, ++ acp_mmio, mmACP_EXTERNAL_INTR_STAT); ++ } ++ ++ if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { ++ valid_irq = true; ++ if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_15) == ++ CAPTURE_START_DMA_DESCR_CH15) ++ dscr_idx = CAPTURE_END_DMA_DESCR_CH14; ++ else ++ dscr_idx = CAPTURE_START_DMA_DESCR_CH14; ++ config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx, ++ 1, 0); ++ acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false); ++ ++ acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, ++ acp_mmio, mmACP_EXTERNAL_INTR_STAT); ++ } ++ ++ if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) { ++ valid_irq = true; ++ snd_pcm_period_elapsed(irq_data->capture_stream); ++ acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16, ++ acp_mmio, mmACP_EXTERNAL_INTR_STAT); ++ } ++ ++ if (valid_irq) ++ return IRQ_HANDLED; ++ else ++ return IRQ_NONE; ++} ++ ++static int acp_dma_open(struct snd_pcm_substream *substream) ++{ ++ int ret = 0; ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct snd_soc_pcm_runtime *prtd = substream->private_data; ++ struct audio_drv_data *intr_data = dev_get_drvdata(prtd->platform->dev); ++ ++ struct audio_substream_data *adata = ++ kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); ++ if (adata == NULL) ++ return -ENOMEM; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ runtime->hw = acp_pcm_hardware_playback; ++ else ++ runtime->hw = acp_pcm_hardware_capture; ++ ++ ret = snd_pcm_hw_constraint_integer(runtime, ++ SNDRV_PCM_HW_PARAM_PERIODS); ++ if (ret < 0) { ++ dev_err(prtd->platform->dev, "set integer constraint failed\n"); ++ return ret; ++ } ++ ++ adata->acp_mmio = intr_data->acp_mmio; ++ runtime->private_data = adata; ++ ++ /* Enable ACP irq, when neither playback or capture streams are ++ * active by the time when a new stream is being opened. ++ * This enablement is not required for another stream, if current ++ * stream is not closed ++ */ ++ if (!intr_data->play_stream && !intr_data->capture_stream) ++ acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ intr_data->play_stream = substream; ++ else ++ intr_data->capture_stream = substream; ++ ++ return 0; ++} ++ ++static int acp_dma_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ int status; ++ uint64_t size; ++ struct snd_dma_buffer *dma_buffer; ++ struct page *pg; ++ struct snd_pcm_runtime *runtime; ++ struct audio_substream_data *rtd; ++ ++ dma_buffer = &substream->dma_buffer; ++ ++ runtime = substream->runtime; ++ rtd = runtime->private_data; ++ ++ if (WARN_ON(!rtd)) ++ return -EINVAL; ++ ++ size = params_buffer_bytes(params); ++ status = snd_pcm_lib_malloc_pages(substream, size); ++ if (status < 0) ++ return status; ++ ++ memset(substream->runtime->dma_area, 0, params_buffer_bytes(params)); ++ pg = virt_to_page(substream->dma_buffer.area); ++ ++ if (pg != NULL) { ++ /* Save for runtime private data */ ++ rtd->pg = pg; ++ rtd->order = get_order(size); ++ ++ /* Fill the page table entries in ACP SRAM */ ++ rtd->pg = pg; ++ rtd->size = size; ++ rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; ++ rtd->direction = substream->stream; ++ ++ config_acp_dma(rtd->acp_mmio, rtd); ++ status = 0; ++ } else { ++ status = -ENOMEM; ++ } ++ return status; ++} ++ ++static int acp_dma_hw_free(struct snd_pcm_substream *substream) ++{ ++ return snd_pcm_lib_free_pages(substream); ++} ++ ++static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream) ++{ ++ u16 dscr; ++ u32 mul, dma_config, period_bytes; ++ u32 pos = 0; ++ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct audio_substream_data *rtd = runtime->private_data; ++ ++ period_bytes = frames_to_bytes(runtime, runtime->period_size); ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ dscr = acp_reg_read(rtd->acp_mmio, mmACP_DMA_CUR_DSCR_13); ++ ++ if (dscr == PLAYBACK_START_DMA_DESCR_CH13) ++ mul = 0; ++ else ++ mul = 1; ++ pos = (mul * period_bytes); ++ } else { ++ dma_config = acp_reg_read(rtd->acp_mmio, mmACP_DMA_CNTL_14); ++ if (dma_config != 0) { ++ dscr = acp_reg_read(rtd->acp_mmio, ++ mmACP_DMA_CUR_DSCR_14); ++ if (dscr == CAPTURE_START_DMA_DESCR_CH14) ++ mul = 1; ++ else ++ mul = 2; ++ pos = (mul * period_bytes); ++ } ++ ++ if (pos >= (2 * period_bytes)) ++ pos = 0; ++ ++ } ++ return bytes_to_frames(runtime, pos); ++} ++ ++static int acp_dma_mmap(struct snd_pcm_substream *substream, ++ struct vm_area_struct *vma) ++{ ++ return snd_pcm_lib_default_mmap(substream, vma); ++} ++ ++static int acp_dma_prepare(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct audio_substream_data *rtd = runtime->private_data; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, ++ PLAYBACK_START_DMA_DESCR_CH12, ++ NUM_DSCRS_PER_CHANNEL, 0); ++ config_acp_dma_channel(rtd->acp_mmio, ACP_TO_I2S_DMA_CH_NUM, ++ PLAYBACK_START_DMA_DESCR_CH13, ++ NUM_DSCRS_PER_CHANNEL, 0); ++ /* Fill ACP SRAM (2 periods) with zeros from System RAM ++ * which is zero-ed in hw_params ++ */ ++ acp_dma_start(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, false); ++ ++ /* ACP SRAM (2 periods of buffer size) is intially filled with ++ * zeros. Before rendering starts, 2nd half of SRAM will be ++ * filled with valid audio data DMA'ed from first half of system ++ * RAM and 1st half of SRAM will be filled with Zeros. This is ++ * the initial scenario when redering starts from SRAM. Later ++ * on, 2nd half of system memory will be DMA'ed to 1st half of ++ * SRAM, 1st half of system memory will be DMA'ed to 2nd half of ++ * SRAM in ping-pong way till rendering stops. ++ */ ++ config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, ++ PLAYBACK_START_DMA_DESCR_CH12, ++ 1, 0); ++ } else { ++ config_acp_dma_channel(rtd->acp_mmio, ACP_TO_SYSRAM_CH_NUM, ++ CAPTURE_START_DMA_DESCR_CH14, ++ NUM_DSCRS_PER_CHANNEL, 0); ++ config_acp_dma_channel(rtd->acp_mmio, I2S_TO_ACP_DMA_CH_NUM, ++ CAPTURE_START_DMA_DESCR_CH15, ++ NUM_DSCRS_PER_CHANNEL, 0); ++ } ++ return 0; ++} ++ ++static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ int ret; ++ u32 loops = 1000; ++ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct snd_soc_pcm_runtime *prtd = substream->private_data; ++ struct audio_substream_data *rtd = runtime->private_data; ++ ++ if (!rtd) ++ return -EINVAL; ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ acp_dma_start(rtd->acp_mmio, ++ SYSRAM_TO_ACP_CH_NUM, false); ++ while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) & ++ BIT(SYSRAM_TO_ACP_CH_NUM)) { ++ if (!loops--) { ++ dev_err(prtd->platform->dev, ++ "acp dma start timeout\n"); ++ return -ETIMEDOUT; ++ } ++ cpu_relax(); ++ } ++ ++ acp_dma_start(rtd->acp_mmio, ++ ACP_TO_I2S_DMA_CH_NUM, true); ++ ++ } else { ++ acp_dma_start(rtd->acp_mmio, ++ I2S_TO_ACP_DMA_CH_NUM, true); ++ } ++ ret = 0; ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ /* Need to stop only circular DMA channels : ++ * ACP_TO_I2S_DMA_CH_NUM / I2S_TO_ACP_DMA_CH_NUM. Non-circular ++ * channels will stopped automatically after its transfer ++ * completes : SYSRAM_TO_ACP_CH_NUM / ACP_TO_SYSRAM_CH_NUM ++ */ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ ret = acp_dma_stop(rtd->acp_mmio, ++ ACP_TO_I2S_DMA_CH_NUM); ++ else ++ ret = acp_dma_stop(rtd->acp_mmio, ++ I2S_TO_ACP_DMA_CH_NUM); ++ break; ++ default: ++ ret = -EINVAL; ++ ++ } ++ return ret; ++} ++ ++static int acp_dma_new(struct snd_soc_pcm_runtime *rtd) ++{ ++ return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, ++ SNDRV_DMA_TYPE_DEV, ++ NULL, MIN_BUFFER, ++ MAX_BUFFER); ++} ++ ++static int acp_dma_close(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct audio_substream_data *rtd = runtime->private_data; ++ struct snd_soc_pcm_runtime *prtd = substream->private_data; ++ struct audio_drv_data *adata = dev_get_drvdata(prtd->platform->dev); ++ ++ kfree(rtd); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ adata->play_stream = NULL; ++ else ++ adata->capture_stream = NULL; ++ ++ /* Disable ACP irq, when the current stream is being closed and ++ * another stream is also not active. ++ */ ++ if (!adata->play_stream && !adata->capture_stream) ++ acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); ++ ++ return 0; ++} ++ ++static struct snd_pcm_ops acp_dma_ops = { ++ .open = acp_dma_open, ++ .close = acp_dma_close, ++ .ioctl = snd_pcm_lib_ioctl, ++ .hw_params = acp_dma_hw_params, ++ .hw_free = acp_dma_hw_free, ++ .trigger = acp_dma_trigger, ++ .pointer = acp_dma_pointer, ++ .mmap = acp_dma_mmap, ++ .prepare = acp_dma_prepare, ++}; ++ ++static struct snd_soc_platform_driver acp_asoc_platform = { ++ .ops = &acp_dma_ops, ++ .pcm_new = acp_dma_new, ++}; ++ ++static int acp_audio_probe(struct platform_device *pdev) ++{ ++ int status; ++ struct audio_drv_data *audio_drv_data; ++ struct resource *res; ++ ++ audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), ++ GFP_KERNEL); ++ if (audio_drv_data == NULL) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res); ++ ++ /* The following members gets populated in device 'open' ++ * function. Till then interrupts are disabled in 'acp_init' ++ * and device doesn't generate any interrupts. ++ */ ++ ++ audio_drv_data->play_stream = NULL; ++ audio_drv_data->capture_stream = NULL; ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); ++ return -ENODEV; ++ } ++ ++ status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler, ++ 0, "ACP_IRQ", &pdev->dev); ++ if (status) { ++ dev_err(&pdev->dev, "ACP IRQ request failed\n"); ++ return status; ++ } ++ ++ dev_set_drvdata(&pdev->dev, audio_drv_data); ++ ++ /* Initialize the ACP */ ++ acp_init(audio_drv_data->acp_mmio); ++ ++ status = snd_soc_register_platform(&pdev->dev, &acp_asoc_platform); ++ if (status != 0) { ++ dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); ++ return status; ++ } ++ ++ return status; ++} ++ ++static int acp_audio_remove(struct platform_device *pdev) ++{ ++ struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); ++ ++ acp_deinit(adata->acp_mmio); ++ snd_soc_unregister_platform(&pdev->dev); ++ ++ return 0; ++} ++ ++static struct platform_driver acp_dma_driver = { ++ .probe = acp_audio_probe, ++ .remove = acp_audio_remove, ++ .driver = { ++ .name = "acp_audio_dma", ++ }, ++}; ++ ++module_platform_driver(acp_dma_driver); ++ ++MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); ++MODULE_DESCRIPTION("AMD ACP PCM Driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:acp-dma-audio"); +diff --git a/sound/soc/amd/acp.h b/sound/soc/amd/acp.h +new file mode 100644 +index 0000000..330832e +--- /dev/null ++++ b/sound/soc/amd/acp.h +@@ -0,0 +1,118 @@ ++#ifndef __ACP_HW_H ++#define __ACP_HW_H ++ ++#include "include/acp_2_2_d.h" ++#include "include/acp_2_2_sh_mask.h" ++ ++#define ACP_PAGE_SIZE_4K_ENABLE 0x02 ++ ++#define ACP_PLAYBACK_PTE_OFFSET 10 ++#define ACP_CAPTURE_PTE_OFFSET 0 ++ ++#define ACP_GARLIC_CNTL_DEFAULT 0x00000FB4 ++#define ACP_ONION_CNTL_DEFAULT 0x00000FB4 ++ ++#define ACP_PHYSICAL_BASE 0x14000 ++ ++/* Playback SRAM address (as a destination in dma descriptor) */ ++#define ACP_SHARED_RAM_BANK_1_ADDRESS 0x4002000 ++ ++/* Capture SRAM address (as a source in dma descriptor) */ ++#define ACP_SHARED_RAM_BANK_5_ADDRESS 0x400A000 ++ ++#define ACP_DMA_RESET_TIME 10000 ++#define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF ++#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF ++#define ACP_DMA_COMPLETE_TIME_OUT_VALUE 0x000000FF ++ ++#define ACP_SRAM_BASE_ADDRESS 0x4000000 ++#define ACP_DAGB_GRP_SRAM_BASE_ADDRESS 0x4001000 ++#define ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET 0x1000 ++#define ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 0x00000000 ++#define ACP_INTERNAL_APERTURE_WINDOW_4_ADDRESS 0x01800000 ++ ++#define TO_ACP_I2S_1 0x2 ++#define TO_ACP_I2S_2 0x4 ++#define FROM_ACP_I2S_1 0xa ++#define FROM_ACP_I2S_2 0xb ++ ++#define ACP_TILE_ON_MASK 0x03 ++#define ACP_TILE_OFF_MASK 0x02 ++#define ACP_TILE_ON_RETAIN_REG_MASK 0x1f ++#define ACP_TILE_OFF_RETAIN_REG_MASK 0x20 ++ ++#define ACP_TILE_P1_MASK 0x3e ++#define ACP_TILE_P2_MASK 0x3d ++#define ACP_TILE_DSP0_MASK 0x3b ++#define ACP_TILE_DSP1_MASK 0x37 ++ ++#define ACP_TILE_DSP2_MASK 0x2f ++/* Playback DMA channels */ ++#define SYSRAM_TO_ACP_CH_NUM 12 ++#define ACP_TO_I2S_DMA_CH_NUM 13 ++ ++/* Capture DMA channels */ ++#define ACP_TO_SYSRAM_CH_NUM 14 ++#define I2S_TO_ACP_DMA_CH_NUM 15 ++ ++#define NUM_DSCRS_PER_CHANNEL 2 ++ ++#define PLAYBACK_START_DMA_DESCR_CH12 0 ++#define PLAYBACK_END_DMA_DESCR_CH12 1 ++#define PLAYBACK_START_DMA_DESCR_CH13 2 ++#define PLAYBACK_END_DMA_DESCR_CH13 3 ++ ++#define CAPTURE_START_DMA_DESCR_CH14 4 ++#define CAPTURE_END_DMA_DESCR_CH14 5 ++#define CAPTURE_START_DMA_DESCR_CH15 6 ++#define CAPTURE_END_DMA_DESCR_CH15 7 ++ ++enum acp_dma_priority_level { ++ /* 0x0 Specifies the DMA channel is given normal priority */ ++ ACP_DMA_PRIORITY_LEVEL_NORMAL = 0x0, ++ /* 0x1 Specifies the DMA channel is given high priority */ ++ ACP_DMA_PRIORITY_LEVEL_HIGH = 0x1, ++ ACP_DMA_PRIORITY_LEVEL_FORCESIZE = 0xFF ++}; ++ ++struct audio_substream_data { ++ struct page *pg; ++ unsigned int order; ++ u16 num_of_pages; ++ u16 direction; ++ uint64_t size; ++ void __iomem *acp_mmio; ++}; ++ ++enum { ++ ACP_TILE_P1 = 0, ++ ACP_TILE_P2, ++ ACP_TILE_DSP0, ++ ACP_TILE_DSP1, ++ ACP_TILE_DSP2, ++}; ++ ++enum { ++ ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION = 0x0, ++ ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC = 0x1, ++ ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM = 0x8, ++ ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM = 0x9, ++ ACP_DMA_ATTRIBUTES_FORCE_SIZE = 0xF ++}; ++ ++typedef struct acp_dma_dscr_transfer { ++ /* Specifies the source memory location for the DMA data transfer. */ ++ u32 src; ++ /* Specifies the destination memory location to where the data will ++ * be transferred. ++ */ ++ u32 dest; ++ /* Specifies the number of bytes need to be transferred ++ * from source to destination memory.Transfer direction & IOC enable ++ */ ++ u32 xfer_val; ++ /* Reserved for future use */ ++ u32 reserved; ++} acp_dma_dscr_transfer_t; ++ ++#endif /*__ACP_HW_H */ +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1128-ASoC-AMD-add-pm-ops.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1128-ASoC-AMD-add-pm-ops.patch new file mode 100644 index 00000000..cf6d3eda --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1128-ASoC-AMD-add-pm-ops.patch @@ -0,0 +1,106 @@ +From 2cb46c7ba1f892f2bf66f0e050434dd18bd0c2ed Mon Sep 17 00:00:00 2001 +From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> +Date: Mon, 21 Dec 2015 15:37:47 +0530 +Subject: [PATCH 03/17] ASoC: AMD: add pm ops + +genpd will power off/on ACP to manage runtime ACP PM. ACP runtime PM +hooks are added to get it deinitialized and initialized respectively, +after it is powered off/on. + +When system goes to suspend when audio usecase is active, ACP will +be powered off through genpd. When it resumes, ACP needs to be +initialized and reconfigured. + +Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + sound/soc/amd/acp-pcm-dma.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 48 insertions(+) + +diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c +index 0724d78..c0819b5 100644 +--- a/sound/soc/amd/acp-pcm-dma.c ++++ b/sound/soc/amd/acp-pcm-dma.c +@@ -16,6 +16,7 @@ + #include <linux/module.h> + #include <linux/delay.h> + #include <linux/sizes.h> ++#include <linux/pm_runtime.h> + + #include <sound/soc.h> + +@@ -885,6 +886,10 @@ static int acp_audio_probe(struct platform_device *pdev) + return status; + } + ++ pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); ++ pm_runtime_use_autosuspend(&pdev->dev); ++ pm_runtime_enable(&pdev->dev); ++ + return status; + } + +@@ -894,15 +899,58 @@ static int acp_audio_remove(struct platform_device *pdev) + + acp_deinit(adata->acp_mmio); + snd_soc_unregister_platform(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); + + return 0; + } + ++static int acp_pcm_resume(struct device *dev) ++{ ++ struct audio_drv_data *adata = dev_get_drvdata(dev); ++ ++ acp_init(adata->acp_mmio); ++ ++ if (adata->play_stream && adata->play_stream->runtime) ++ config_acp_dma(adata->acp_mmio, ++ adata->play_stream->runtime->private_data); ++ if (adata->capture_stream && adata->capture_stream->runtime) ++ config_acp_dma(adata->acp_mmio, ++ adata->capture_stream->runtime->private_data); ++ ++ acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); ++ return 0; ++} ++ ++static int acp_pcm_runtime_suspend(struct device *dev) ++{ ++ struct audio_drv_data *adata = dev_get_drvdata(dev); ++ ++ acp_deinit(adata->acp_mmio); ++ acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); ++ return 0; ++} ++ ++static int acp_pcm_runtime_resume(struct device *dev) ++{ ++ struct audio_drv_data *adata = dev_get_drvdata(dev); ++ ++ acp_init(adata->acp_mmio); ++ acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); ++ return 0; ++} ++ ++static const struct dev_pm_ops acp_pm_ops = { ++ .resume = acp_pcm_resume, ++ .runtime_suspend = acp_pcm_runtime_suspend, ++ .runtime_resume = acp_pcm_runtime_resume, ++}; ++ + static struct platform_driver acp_dma_driver = { + .probe = acp_audio_probe, + .remove = acp_audio_remove, + .driver = { + .name = "acp_audio_dma", ++ .pm = &acp_pm_ops, + }, + }; + +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1129-ASoC-AMD-Manage-ACP-2.x-SRAM-banks-power.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1129-ASoC-AMD-Manage-ACP-2.x-SRAM-banks-power.patch new file mode 100644 index 00000000..76135b6e --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1129-ASoC-AMD-Manage-ACP-2.x-SRAM-banks-power.patch @@ -0,0 +1,190 @@ +From 21a602911b8e34e680a969e28db3f9966567612d Mon Sep 17 00:00:00 2001 +From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> +Date: Mon, 21 Dec 2015 16:13:29 +0530 +Subject: [PATCH 04/17] ASoC: AMD: Manage ACP 2.x SRAM banks power + +ACP SRAM banks gets turned on when ACP is powered on. +Not all banks are used for playback/capture. So, power on +required banks during audio device open and power off during +audio device close. + +Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + sound/soc/amd/acp-pcm-dma.c | 94 +++++++++++++++++++++++++++++++++++++++++---- + 1 file changed, 87 insertions(+), 7 deletions(-) + +diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c +index c0819b5..cc8b841 100644 +--- a/sound/soc/amd/acp-pcm-dma.c ++++ b/sound/soc/amd/acp-pcm-dma.c +@@ -376,9 +376,57 @@ static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) + return 0; + } + ++static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, ++ bool power_on) ++{ ++ u32 val, req_reg, sts_reg, sts_reg_mask; ++ u32 loops = 1000; ++ ++ if (bank < 32) { ++ req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; ++ sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; ++ sts_reg_mask = 0xFFFFFFFF; ++ ++ } else { ++ bank -= 32; ++ req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; ++ sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; ++ sts_reg_mask = 0x0000FFFF; ++ } ++ ++ val = acp_reg_read(acp_mmio, req_reg); ++ if (val & (1 << bank)) { ++ /* bank is in off state */ ++ if (power_on == true) ++ /* request to on */ ++ val &= ~(1 << bank); ++ else ++ /* request to off */ ++ return; ++ } else { ++ /* bank is in on state */ ++ if (power_on == false) ++ /* request to off */ ++ val |= 1 << bank; ++ else ++ /* request to on */ ++ return; ++ } ++ acp_reg_write(val, acp_mmio, req_reg); ++ ++ while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { ++ if (!loops--) { ++ pr_err("ACP SRAM bank %d state change failed\n", bank); ++ break; ++ } ++ cpu_relax(); ++ } ++} ++ + /* Initialize and bring ACP hardware to default state. */ + static int acp_init(void __iomem *acp_mmio) + { ++ u16 bank; + u32 val, count, sram_pte_offset; + + /* Assert Soft reset of ACP */ +@@ -447,6 +495,13 @@ static int acp_init(void __iomem *acp_mmio) + acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, + acp_mmio, mmACP_EXTERNAL_INTR_CNTL); + ++ /* When ACP_TILE_P1 is turned on, all SRAM banks get turned on. ++ * Now, turn off all of them. This can't be done in 'poweron' of ++ * ACP pm domain, as this requires ACP to be initialized. ++ */ ++ for (bank = 1; bank < 48; bank++) ++ acp_set_sram_bank_state(acp_mmio, bank, false); ++ + return 0; + } + +@@ -559,6 +614,7 @@ static irqreturn_t dma_irq_handler(int irq, void *arg) + + static int acp_dma_open(struct snd_pcm_substream *substream) + { ++ u16 bank; + int ret = 0; + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *prtd = substream->private_data; +@@ -592,10 +648,17 @@ static int acp_dma_open(struct snd_pcm_substream *substream) + if (!intr_data->play_stream && !intr_data->capture_stream) + acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); + +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + intr_data->play_stream = substream; +- else ++ for (bank = 1; bank <= 4; bank++) ++ acp_set_sram_bank_state(intr_data->acp_mmio, bank, ++ true); ++ } else { + intr_data->capture_stream = substream; ++ for (bank = 5; bank <= 8; bank++) ++ acp_set_sram_bank_state(intr_data->acp_mmio, bank, ++ true); ++ } + + return 0; + } +@@ -627,6 +690,7 @@ static int acp_dma_hw_params(struct snd_pcm_substream *substream, + pg = virt_to_page(substream->dma_buffer.area); + + if (pg != NULL) { ++ acp_set_sram_bank_state(rtd->acp_mmio, 0, true); + /* Save for runtime private data */ + rtd->pg = pg; + rtd->order = get_order(size); +@@ -802,6 +866,7 @@ static int acp_dma_new(struct snd_soc_pcm_runtime *rtd) + + static int acp_dma_close(struct snd_pcm_substream *substream) + { ++ u16 bank; + struct snd_pcm_runtime *runtime = substream->runtime; + struct audio_substream_data *rtd = runtime->private_data; + struct snd_soc_pcm_runtime *prtd = substream->private_data; +@@ -809,10 +874,17 @@ static int acp_dma_close(struct snd_pcm_substream *substream) + + kfree(rtd); + +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + adata->play_stream = NULL; +- else ++ for (bank = 1; bank <= 4; bank++) ++ acp_set_sram_bank_state(adata->acp_mmio, bank, ++ false); ++ } else { + adata->capture_stream = NULL; ++ for (bank = 5; bank <= 8; bank++) ++ acp_set_sram_bank_state(adata->acp_mmio, bank, ++ false); ++ } + + /* Disable ACP irq, when the current stream is being closed and + * another stream is also not active. +@@ -906,17 +978,25 @@ static int acp_audio_remove(struct platform_device *pdev) + + static int acp_pcm_resume(struct device *dev) + { ++ u16 bank; + struct audio_drv_data *adata = dev_get_drvdata(dev); + + acp_init(adata->acp_mmio); + +- if (adata->play_stream && adata->play_stream->runtime) ++ if (adata->play_stream && adata->play_stream->runtime) { ++ for (bank = 1; bank <= 4; bank++) ++ acp_set_sram_bank_state(adata->acp_mmio, bank, ++ true); + config_acp_dma(adata->acp_mmio, + adata->play_stream->runtime->private_data); +- if (adata->capture_stream && adata->capture_stream->runtime) ++ } ++ if (adata->capture_stream && adata->capture_stream->runtime) { ++ for (bank = 5; bank <= 8; bank++) ++ acp_set_sram_bank_state(adata->acp_mmio, bank, ++ true); + config_acp_dma(adata->acp_mmio, + adata->capture_stream->runtime->private_data); +- ++ } + acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); + return 0; + } +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1130-ASoc-AMD-Machine-driver-for-AMD-ACP-Audio-engine-usi.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1130-ASoc-AMD-Machine-driver-for-AMD-ACP-Audio-engine-usi.patch new file mode 100644 index 00000000..03e85464 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1130-ASoc-AMD-Machine-driver-for-AMD-ACP-Audio-engine-usi.patch @@ -0,0 +1,251 @@ +From 13a790e8d490f59170004fd20d74c0267d08c69e Mon Sep 17 00:00:00 2001 +From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> +Date: Fri, 1 Jul 2016 12:47:49 +0530 +Subject: [PATCH 05/17] ASoc: AMD: Machine driver for AMD ACP Audio engine + using Realtek RT286 codec + +Added machine driver support in the Kconfig file and the Makefile + +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + sound/soc/Kconfig | 1 + + sound/soc/Makefile | 1 + + sound/soc/amd/Kconfig | 7 ++ + sound/soc/amd/Makefile | 2 + + sound/soc/amd/acp-rt286.c | 175 ++++++++++++++++++++++++++++++++++++++++++++++ + 5 files changed, 186 insertions(+) + create mode 100644 sound/soc/amd/acp-rt286.c + +diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig +index 7ff7d88..a34e9e9 100644 +--- a/sound/soc/Kconfig ++++ b/sound/soc/Kconfig +@@ -38,6 +38,7 @@ config SND_SOC_TOPOLOGY + + # All the supported SoCs + source "sound/soc/adi/Kconfig" ++source "sound/soc/amd/Kconfig" + source "sound/soc/atmel/Kconfig" + source "sound/soc/au1x/Kconfig" + source "sound/soc/bcm/Kconfig" +diff --git a/sound/soc/Makefile b/sound/soc/Makefile +index 8eb06db..3ab378b 100644 +--- a/sound/soc/Makefile ++++ b/sound/soc/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_SND_SOC) += snd-soc-core.o + obj-$(CONFIG_SND_SOC) += codecs/ + obj-$(CONFIG_SND_SOC) += generic/ + obj-$(CONFIG_SND_SOC) += adi/ ++obj-$(CONFIG_SND_SOC) += amd/ + obj-$(CONFIG_SND_SOC) += atmel/ + obj-$(CONFIG_SND_SOC) += au1x/ + obj-$(CONFIG_SND_SOC) += bcm/ +diff --git a/sound/soc/amd/Kconfig b/sound/soc/amd/Kconfig +index 78187eb..3724f54 100644 +--- a/sound/soc/amd/Kconfig ++++ b/sound/soc/amd/Kconfig +@@ -1,3 +1,10 @@ ++config SND_SOC_AMD_CZ_RT286_MACH ++ tristate "AMD ASoC Audio driver for Carrizo with rt286 codec" ++ select SND_SOC_RT286 ++ select SND_SOC_AMD_ACP ++ depends on I2C_DESIGNWARE_PLATFORM ++ help ++ This option enables AMD I2S Audio support on Carrizo with ALC288 codec. + config SND_SOC_AMD_ACP + tristate "AMD Audio Coprocessor support" + help +diff --git a/sound/soc/amd/Makefile b/sound/soc/amd/Makefile +index 1a66ec0..a75574d 100644 +--- a/sound/soc/amd/Makefile ++++ b/sound/soc/amd/Makefile +@@ -1,3 +1,5 @@ + snd-soc-acp-pcm-objs := acp-pcm-dma.o ++snd-soc-acp-rt286-mach-objs := acp-rt286.o + + obj-$(CONFIG_SND_SOC_AMD_ACP) += snd-soc-acp-pcm.o ++obj-$(CONFIG_SND_SOC_AMD_CZ_RT286_MACH) += snd-soc-acp-rt286-mach.o +diff --git a/sound/soc/amd/acp-rt286.c b/sound/soc/amd/acp-rt286.c +new file mode 100644 +index 0000000..3fa714e +--- /dev/null ++++ b/sound/soc/amd/acp-rt286.c +@@ -0,0 +1,175 @@ ++/* ++ * Machine driver for AMD ACP Audio engine using Realtek RT286 codec ++ * ++ * Copyright 2014-2015 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * ++ */ ++ ++#include <sound/core.h> ++#include <sound/soc.h> ++#include <sound/pcm.h> ++#include <sound/pcm_params.h> ++#include <sound/soc-dapm.h> ++#include <sound/jack.h> ++#include <linux/gpio.h> ++#include <linux/module.h> ++#include <linux/i2c.h> ++#include <linux/acpi.h> ++ ++#include "../codecs/rt286.h" ++ ++static struct snd_soc_jack cz_jack; ++static struct snd_soc_jack_pin cz_pins[] = { ++ { ++ .pin = "Analog Mic", ++ .mask = SND_JACK_MICROPHONE, ++ }, ++ { ++ .pin = "Headphones", ++ .mask = SND_JACK_HEADPHONE, ++ }, ++}; ++ ++static int cz_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ int ret; ++ struct snd_soc_card *card; ++ struct snd_soc_codec *codec; ++ struct snd_soc_dai *codec_dai = rtd->codec_dai; ++ ++ codec = rtd->codec; ++ card = rtd->card; ++ ++ ret = snd_soc_dai_set_sysclk(codec_dai, RT286_SCLK_S_PLL, 24000000, ++ SND_SOC_CLOCK_OUT); ++ if (ret < 0) { ++ dev_err(card->dev, "unable to set codec dai clock\n"); ++ return ret; ++ } ++ ret = snd_soc_card_jack_new(card, "Headset", ++ SND_JACK_HEADSET, &cz_jack, cz_pins, ARRAY_SIZE(cz_pins)); ++ ++ if (ret) ++ return ret; ++ ++ rt286_mic_detect(codec, &cz_jack); ++ return 0; ++} ++ ++static struct snd_soc_dai_link cz_dai_rt286[] = { ++ { ++ .name = "amd-rt286-play", ++ .stream_name = "RT286_AIF1", ++ .platform_name = "acp_audio_dma.0.auto", ++ .cpu_dai_name = "designware-i2s.1.auto", ++ .codec_dai_name = "rt286-aif1", ++ .codec_name = "i2c-RTK0000:00", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF ++ | SND_SOC_DAIFMT_CBM_CFM, ++ .init = cz_init, ++ }, ++ { ++ ++ .name = "amd-rt286-cap", ++ .stream_name = "RT286_AIF1", ++ .platform_name = "acp_audio_dma.0.auto", ++ .cpu_dai_name = "designware-i2s.2.auto", ++ .codec_dai_name = "rt286-aif1", ++ .codec_name = "i2c-RTK0000:00", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF ++ | SND_SOC_DAIFMT_CBM_CFM, ++ .init = cz_init, ++ }, ++ ++}; ++ ++static const struct snd_soc_dapm_widget cz_widgets[] = { ++ SND_SOC_DAPM_HP("Headphones", NULL), ++ SND_SOC_DAPM_MIC("Analog Mic", NULL), ++}; ++ ++static const struct snd_soc_dapm_route cz_audio_route[] = { ++ {"Headphones", NULL, "HPO L"}, ++ {"Headphones", NULL, "HPO R"}, ++ {"MIC1", NULL, "Analog Mic"}, ++}; ++ ++static struct snd_soc_card cz_card = { ++ .name = "acp-rt286", ++ .owner = THIS_MODULE, ++ .dai_link = cz_dai_rt286, ++ .num_links = 2, ++ ++ .dapm_widgets = cz_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(cz_widgets), ++ .dapm_routes = cz_audio_route, ++ .num_dapm_routes = ARRAY_SIZE(cz_audio_route), ++}; ++ ++static int cz_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct snd_soc_card *card; ++ ++ card = &cz_card; ++ cz_card.dev = &pdev->dev; ++ platform_set_drvdata(pdev, card); ++ ret = snd_soc_register_card(card); ++ if (ret) { ++ dev_err(&pdev->dev, ++ "snd_soc_register_card(%s) failed: %d\n", ++ cz_card.name, ret); ++ return ret; ++ } ++ return 0; ++} ++ ++static int cz_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_card *card; ++ ++ card = platform_get_drvdata(pdev); ++ snd_soc_unregister_card(card); ++ ++ return 0; ++} ++ ++static const struct acpi_device_id cz_audio_acpi_match[] = { ++ { "I2SC1002", 0 }, ++ {}, ++}; ++ ++static struct platform_driver cz_pcm_driver = { ++ .driver = { ++ .name = "cz-rt288", ++ .acpi_match_table = ACPI_PTR(cz_audio_acpi_match), ++ .pm = &snd_soc_pm_ops, ++ }, ++ .probe = cz_probe, ++ .remove = cz_remove, ++}; ++ ++module_platform_driver(cz_pcm_driver); ++ ++MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); ++MODULE_DESCRIPTION("cz-rt288 audio support"); ++MODULE_LICENSE("GPL v2"); +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1131-drm-amd-Adding-ACP-driver-support-for-AMDGPU.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1131-drm-amd-Adding-ACP-driver-support-for-AMDGPU.patch new file mode 100644 index 00000000..5ae2536d --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1131-drm-amd-Adding-ACP-driver-support-for-AMDGPU.patch @@ -0,0 +1,383 @@ +From 58e6e67a2e65c339cbb6803463b19aaab92303c5 Mon Sep 17 00:00:00 2001 +From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> +Date: Sat, 24 Sep 2016 12:57:36 +0530 +Subject: [PATCH 06/17] drm/amd: Adding ACP driver support for AMDGPU + +Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + drivers/gpu/drm/amd/acp/Kconfig | 1 + + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 216 ++----------------------------- + drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h | 2 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 4 +- + drivers/gpu/drm/amd/include/amd_shared.h | 2 + + 6 files changed, 18 insertions(+), 212 deletions(-) + +diff --git a/drivers/gpu/drm/amd/acp/Kconfig b/drivers/gpu/drm/amd/acp/Kconfig +index ca77ec1..b8a0605 100644 +--- a/drivers/gpu/drm/amd/acp/Kconfig ++++ b/drivers/gpu/drm/amd/acp/Kconfig +@@ -2,6 +2,7 @@ menu "ACP (Audio CoProcessor) Configuration" + + config DRM_AMD_ACP + bool "Enable AMD Audio CoProcessor IP support" ++ default y + select MFD_CORE + select PM_GENERIC_DOMAINS if PM + help +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index 551f763..86894ec 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1928,8 +1928,9 @@ struct amdgpu_atcs { + /* + * CGS + */ +-struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); +-void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); ++void *amdgpu_cgs_create_device(struct amdgpu_device *adev); ++void amdgpu_cgs_destroy_device(void *cgs_device); ++ + + + /* GPU virtualization */ +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +index 043ba60..cbbc31a8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +@@ -24,7 +24,6 @@ + */ + + #include <linux/irqdomain.h> +-#include <linux/pm_domain.h> + #include <linux/platform_device.h> + #include <sound/designware_i2s.h> + #include <sound/pcm.h> +@@ -103,153 +102,6 @@ static int acp_sw_fini(void *handle) + return 0; + } + +-/* power off a tile/block within ACP */ +-static int acp_suspend_tile(void *cgs_dev, int tile) +-{ +- u32 val = 0; +- u32 count = 0; +- +- if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) { +- pr_err("Invalid ACP tile : %d to suspend\n", tile); +- return -1; +- } +- +- val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile); +- val &= ACP_TILE_ON_MASK; +- +- if (val == 0x0) { +- val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG); +- val = val | (1 << tile); +- cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val); +- cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG, +- 0x500 + tile); +- +- count = ACP_TIMEOUT_LOOP; +- while (true) { +- val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 +- + tile); +- val = val & ACP_TILE_ON_MASK; +- if (val == ACP_TILE_OFF_MASK) +- break; +- if (--count == 0) { +- pr_err("Timeout reading ACP PGFSM status\n"); +- return -ETIMEDOUT; +- } +- udelay(100); +- } +- +- val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG); +- +- val |= ACP_TILE_OFF_RETAIN_REG_MASK; +- cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val); +- } +- return 0; +-} +- +-/* power on a tile/block within ACP */ +-static int acp_resume_tile(void *cgs_dev, int tile) +-{ +- u32 val = 0; +- u32 count = 0; +- +- if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) { +- pr_err("Invalid ACP tile to resume\n"); +- return -1; +- } +- +- val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile); +- val = val & ACP_TILE_ON_MASK; +- +- if (val != 0x0) { +- cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG, +- 0x600 + tile); +- count = ACP_TIMEOUT_LOOP; +- while (true) { +- val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 +- + tile); +- val = val & ACP_TILE_ON_MASK; +- if (val == 0x0) +- break; +- if (--count == 0) { +- pr_err("Timeout reading ACP PGFSM status\n"); +- return -ETIMEDOUT; +- } +- udelay(100); +- } +- val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG); +- if (tile == ACP_TILE_P1) +- val = val & (ACP_TILE_P1_MASK); +- else if (tile == ACP_TILE_P2) +- val = val & (ACP_TILE_P2_MASK); +- +- cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val); +- } +- return 0; +-} +- +-struct acp_pm_domain { +- void *cgs_dev; +- struct generic_pm_domain gpd; +-}; +- +-static int acp_poweroff(struct generic_pm_domain *genpd) +-{ +- int i, ret; +- struct acp_pm_domain *apd; +- +- apd = container_of(genpd, struct acp_pm_domain, gpd); +- if (apd != NULL) { +- /* Donot return abruptly if any of power tile fails to suspend. +- * Log it and continue powering off other tile +- */ +- for (i = 4; i >= 0 ; i--) { +- ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i); +- if (ret) +- pr_err("ACP tile %d tile suspend failed\n", i); +- } +- } +- return 0; +-} +- +-static int acp_poweron(struct generic_pm_domain *genpd) +-{ +- int i, ret; +- struct acp_pm_domain *apd; +- +- apd = container_of(genpd, struct acp_pm_domain, gpd); +- if (apd != NULL) { +- for (i = 0; i < 2; i++) { +- ret = acp_resume_tile(apd->cgs_dev, ACP_TILE_P1 + i); +- if (ret) { +- pr_err("ACP tile %d resume failed\n", i); +- break; +- } +- } +- +- /* Disable DSPs which are not going to be used */ +- for (i = 0; i < 3; i++) { +- ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_DSP0 + i); +- /* Continue suspending other DSP, even if one fails */ +- if (ret) +- pr_err("ACP DSP %d suspend failed\n", i); +- } +- } +- return 0; +-} +- +-static struct device *get_mfd_cell_dev(const char *device_name, int r) +-{ +- char auto_dev_name[25]; +- struct device *dev; +- +- snprintf(auto_dev_name, sizeof(auto_dev_name), +- "%s.%d.auto", device_name, r); +- dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name); +- dev_info(dev, "device %s added to pm domain\n", auto_dev_name); +- +- return dev; +-} +- + /** + * acp_hw_init - start and test ACP block + * +@@ -258,9 +110,8 @@ static struct device *get_mfd_cell_dev(const char *device_name, int r) + */ + static int acp_hw_init(void *handle) + { +- int r, i; ++ int r; + uint64_t acp_base; +- struct device *dev; + struct i2s_platform_data *i2s_pdata; + + struct amdgpu_device *adev = (struct amdgpu_device *)handle; +@@ -286,19 +137,6 @@ static int acp_hw_init(void *handle) + else if (r) + return r; + +- adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL); +- if (adev->acp.acp_genpd == NULL) +- return -ENOMEM; +- +- adev->acp.acp_genpd->gpd.name = "ACP_AUDIO"; +- adev->acp.acp_genpd->gpd.power_off = acp_poweroff; +- adev->acp.acp_genpd->gpd.power_on = acp_poweron; +- +- +- adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device; +- +- pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); +- + adev->acp.acp_cell = kzalloc(sizeof(struct mfd_cell) * ACP_DEVS, + GFP_KERNEL); + +@@ -373,15 +211,6 @@ static int acp_hw_init(void *handle) + if (r) + return r; + +- for (i = 0; i < ACP_DEVS ; i++) { +- dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); +- r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev); +- if (r) { +- dev_err(dev, "Failed to add dev to genpd\n"); +- return r; +- } +- } +- + return 0; + } + +@@ -393,22 +222,10 @@ static int acp_hw_init(void *handle) + */ + static int acp_hw_fini(void *handle) + { +- int i, ret; +- struct device *dev; +- + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- for (i = 0; i < ACP_DEVS ; i++) { +- dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); +- ret = pm_genpd_remove_device(&adev->acp.acp_genpd->gpd, dev); +- /* If removal fails, dont giveup and try rest */ +- if (ret) +- dev_err(dev, "remove dev from genpd failed\n"); +- } +- + mfd_remove_devices(adev->acp.parent); + kfree(adev->acp.acp_res); +- kfree(adev->acp.acp_genpd); + kfree(adev->acp.acp_cell); + + return 0; +@@ -421,29 +238,6 @@ static int acp_suspend(void *handle) + + static int acp_resume(void *handle) + { +- int i, ret; +- struct acp_pm_domain *apd; +- struct amdgpu_device *adev = (struct amdgpu_device *)handle; +- +- /* return early if no ACP */ +- if (!adev->acp.acp_genpd) +- return 0; +- +- /* SMU block will power on ACP irrespective of ACP runtime status. +- * Power off explicitly based on genpd ACP runtime status so that ACP +- * hw and ACP-genpd status are in sync. +- * 'suspend_power_off' represents "Power status before system suspend" +- */ +- if (adev->acp.acp_genpd->gpd.suspend_power_off == true) { +- apd = container_of(&adev->acp.acp_genpd->gpd, +- struct acp_pm_domain, gpd); +- +- for (i = 4; i >= 0 ; i--) { +- ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i); +- if (ret) +- pr_err("ACP tile %d tile suspend failed\n", i); +- } +- } + return 0; + } + +@@ -467,6 +261,13 @@ static int acp_soft_reset(void *handle) + return 0; + } + ++static void acp_print_status(void *handle) ++{ ++ struct amdgpu_device *adev = (struct amdgpu_device *)handle; ++ ++ dev_info(adev->dev, "ACP STATUS\n"); ++} ++ + static int acp_set_clockgating_state(void *handle, + enum amd_clockgating_state state) + { +@@ -492,6 +293,7 @@ const struct amd_ip_funcs acp_ip_funcs = { + .is_idle = acp_is_idle, + .wait_for_idle = acp_wait_for_idle, + .soft_reset = acp_soft_reset, ++ .print_status = acp_print_status, + .set_clockgating_state = acp_set_clockgating_state, + .set_powergating_state = acp_set_powergating_state, + }; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h +index 8a39631..f6e32a6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.h +@@ -30,7 +30,7 @@ + + struct amdgpu_acp { + struct device *parent; +- struct cgs_device *cgs_device; ++ void *cgs_device; + struct amd_acp_private *private; + struct mfd_cell *acp_cell; + struct resource *acp_res; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +index 490464e..88625b5 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +@@ -1141,7 +1141,7 @@ static const struct cgs_os_ops amdgpu_cgs_os_ops = { + amdgpu_cgs_irq_put + }; + +-struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev) ++void *amdgpu_cgs_create_device(struct amdgpu_device *adev) + { + struct amdgpu_cgs_device *cgs_device = + kmalloc(sizeof(*cgs_device), GFP_KERNEL); +@@ -1158,7 +1158,7 @@ struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev) + return (struct cgs_device *)cgs_device; + } + +-void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device) ++void amdgpu_cgs_destroy_device(void *cgs_device) + { + kfree(cgs_device); + } +diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h +index afce1ed..d83baf3 100644 +--- a/drivers/gpu/drm/amd/include/amd_shared.h ++++ b/drivers/gpu/drm/amd/include/amd_shared.h +@@ -168,6 +168,8 @@ struct amd_ip_funcs { + int (*wait_for_idle)(void *handle); + /* soft reset the IP block */ + int (*soft_reset)(void *handle); ++ /* dump the IP block status registers */ ++ void (*print_status)(void *handle); + /* enable/disable cg for the IP block */ + int (*set_clockgating_state)(void *handle, + enum amd_clockgating_state state); +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1132-drm-amd-Power-management-related-modifications-in-th.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1132-drm-amd-Power-management-related-modifications-in-th.patch new file mode 100644 index 00000000..f1a7886b --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1132-drm-amd-Power-management-related-modifications-in-th.patch @@ -0,0 +1,280 @@ +From 70cc896479d8491bb6892312b54613439af01316 Mon Sep 17 00:00:00 2001 +From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> +Date: Fri, 23 Sep 2016 17:35:10 +0530 +Subject: [PATCH 07/17] drm/amd: Power management related modifications in the + +amdgpu ACP driver. + +Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 206 +++++++++++++++++++++++++++++++- + 1 file changed, 205 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +index cbbc31a8..37ecc36 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +@@ -24,6 +24,7 @@ + */ + + #include <linux/irqdomain.h> ++#include <linux/pm_domain.h> + #include <linux/platform_device.h> + #include <sound/designware_i2s.h> + #include <sound/pcm.h> +@@ -102,6 +103,155 @@ static int acp_sw_fini(void *handle) + return 0; + } + ++/* power off a tile/block within ACP */ ++static int acp_suspend_tile(void *cgs_dev, int tile) ++{ ++ u32 val = 0; ++ u32 count = 0; ++ ++ if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) { ++ pr_err("Invalid ACP tile : %d to suspend\n", tile); ++ return -1; ++ } ++ ++ val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile); ++ val &= ACP_TILE_ON_MASK; ++ ++ if (val == 0x0) { ++ val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG); ++ val = val | (1 << tile); ++ cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val); ++ cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG, ++ 0x500 + tile); ++ ++ count = ACP_TIMEOUT_LOOP; ++ while (true) { ++ val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 ++ + tile); ++ val = val & ACP_TILE_ON_MASK; ++ if (val == ACP_TILE_OFF_MASK) ++ break; ++ if (--count == 0) { ++ pr_err("Timeout reading ACP PGFSM status\n"); ++ return -ETIMEDOUT; ++ } ++ udelay(100); ++ } ++ ++ val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG); ++ ++ val |= ACP_TILE_OFF_RETAIN_REG_MASK; ++ cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val); ++ } ++ return 0; ++} ++ ++/* power on a tile/block within ACP */ ++static int acp_resume_tile(void *cgs_dev, int tile) ++{ ++ u32 val = 0; ++ u32 count = 0; ++ ++ if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) { ++ pr_err("Invalid ACP tile to resume\n"); ++ return -1; ++ } ++ ++ val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile); ++ val = val & ACP_TILE_ON_MASK; ++ ++ if (val != 0x0) { ++ cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG, ++ 0x600 + tile); ++ count = ACP_TIMEOUT_LOOP; ++ while (true) { ++ val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 ++ + tile); ++ val = val & ACP_TILE_ON_MASK; ++ if (val == 0x0) ++ break; ++ if (--count == 0) { ++ pr_err("Timeout reading ACP PGFSM status\n"); ++ return -ETIMEDOUT; ++ } ++ udelay(100); ++ } ++ val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG); ++ if (tile == ACP_TILE_P1) ++ val = val & (ACP_TILE_P1_MASK); ++ else if (tile == ACP_TILE_P2) ++ val = val & (ACP_TILE_P2_MASK); ++ ++ cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val); ++ } ++ return 0; ++} ++ ++struct acp_pm_domain { ++ void *cgs_dev; ++ struct generic_pm_domain gpd; ++}; ++ ++static int acp_poweroff(struct generic_pm_domain *genpd) ++{ ++ int i, ret; ++ struct acp_pm_domain *apd; ++ ++ apd = container_of(genpd, struct acp_pm_domain, gpd); ++ if (apd != NULL) { ++ /* Donot return abruptly if any of power tile fails to suspend. ++ * Log it and continue powering off other tile ++ */ ++ for (i = 4; i >= 0 ; i--) { ++ ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i); ++ if (ret) ++ pr_err("ACP tile %d tile suspend failed\n", i); ++ } ++ } ++ return 0; ++} ++ ++static int acp_poweron(struct generic_pm_domain *genpd) ++{ ++ int i, ret; ++ struct acp_pm_domain *apd; ++ ++ apd = container_of(genpd, struct acp_pm_domain, gpd); ++ if (apd != NULL) { ++ for (i = 0; i < 2; i++) { ++ ret = acp_resume_tile(apd->cgs_dev, ACP_TILE_P1 + i); ++ if (ret) { ++ pr_err("ACP tile %d resume failed\n", i); ++ break; ++ } ++ } ++ ++ /* Disable DSPs which are not going to be used */ ++ for (i = 0; i < 3; i++) { ++ ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_DSP0 + i); ++ /* Continue suspending other DSP, even if one fails */ ++ if (ret) ++ pr_err("ACP DSP %d suspend failed\n", i); ++ } ++ } ++ return 0; ++} ++ ++static struct device *get_mfd_cell_dev(const char *device_name, int r) ++{ ++ char auto_dev_name[25]; ++ char buf[8]; ++ struct device *dev; ++ ++ sprintf(buf, ".%d.auto", r); ++ strcpy(auto_dev_name, device_name); ++ strcat(auto_dev_name, buf); ++ dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name); ++ dev_info(dev, "device %s added to pm domain\n", auto_dev_name); ++ ++ return dev; ++} ++ + /** + * acp_hw_init - start and test ACP block + * +@@ -110,8 +260,9 @@ static int acp_sw_fini(void *handle) + */ + static int acp_hw_init(void *handle) + { +- int r; ++ int r, i; + uint64_t acp_base; ++ struct device *dev; + struct i2s_platform_data *i2s_pdata; + + struct amdgpu_device *adev = (struct amdgpu_device *)handle; +@@ -137,6 +288,19 @@ static int acp_hw_init(void *handle) + else if (r) + return r; + ++ adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL); ++ if (adev->acp.acp_genpd == NULL) ++ return -ENOMEM; ++ ++ adev->acp.acp_genpd->gpd.name = "ACP_AUDIO"; ++ adev->acp.acp_genpd->gpd.power_off = acp_poweroff; ++ adev->acp.acp_genpd->gpd.power_on = acp_poweron; ++ ++ ++ adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device; ++ ++ pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); ++ + adev->acp.acp_cell = kzalloc(sizeof(struct mfd_cell) * ACP_DEVS, + GFP_KERNEL); + +@@ -211,6 +375,15 @@ static int acp_hw_init(void *handle) + if (r) + return r; + ++ for (i = 0; i < ACP_DEVS ; i++) { ++ dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); ++ r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev); ++ if (r) { ++ dev_err(dev, "Failed to add dev to genpd\n"); ++ return r; ++ } ++ } ++ + return 0; + } + +@@ -222,10 +395,22 @@ static int acp_hw_init(void *handle) + */ + static int acp_hw_fini(void *handle) + { ++ int i, ret; ++ struct device *dev; ++ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + ++ for (i = 0; i < ACP_DEVS ; i++) { ++ dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); ++ ret = pm_genpd_remove_device(&adev->acp.acp_genpd->gpd, dev); ++ /* If removal fails, dont giveup and try rest */ ++ if (ret) ++ dev_err(dev, "remove dev from genpd failed\n"); ++ } ++ + mfd_remove_devices(adev->acp.parent); + kfree(adev->acp.acp_res); ++ kfree(adev->acp.acp_genpd); + kfree(adev->acp.acp_cell); + + return 0; +@@ -238,6 +423,25 @@ static int acp_suspend(void *handle) + + static int acp_resume(void *handle) + { ++ int i, ret; ++ struct acp_pm_domain *apd; ++ struct amdgpu_device *adev = (struct amdgpu_device *)handle; ++ ++ /* SMU block will power on ACP irrespective of ACP runtime status. ++ * Power off explicitly based on genpd ACP runtime status so that ACP ++ * hw and ACP-genpd status are in sync. ++ * 'suspend_power_off' represents "Power status before system suspend" ++ */ ++ if (adev->acp.acp_genpd->gpd.suspend_power_off == true) { ++ apd = container_of(&adev->acp.acp_genpd->gpd, ++ struct acp_pm_domain, gpd); ++ ++ for (i = 4; i >= 0 ; i--) { ++ ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i); ++ if (ret) ++ pr_err("ACP tile %d tile suspend failed\n", i); ++ } ++ } + return 0; + } + +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1133-ASoC-dwc-add-quirk-for-different-register-offset.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1133-ASoC-dwc-add-quirk-for-different-register-offset.patch new file mode 100644 index 00000000..f0fc5753 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1133-ASoC-dwc-add-quirk-for-different-register-offset.patch @@ -0,0 +1,64 @@ +From c9d301e1d02d7b741f9f3d1799ad9b2306c393f1 Mon Sep 17 00:00:00 2001 +From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> +Date: Fri, 23 Sep 2016 17:51:13 +0530 +Subject: [PATCH 08/17] ASoC:dwc add quirk for different register offset + +Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + sound/soc/dwc/designware_i2s.c | 18 +++++++++++++++--- + 1 file changed, 15 insertions(+), 3 deletions(-) + +diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c +index 6e6a70c..4f8f074 100644 +--- a/sound/soc/dwc/designware_i2s.c ++++ b/sound/soc/dwc/designware_i2s.c +@@ -93,6 +93,10 @@ struct dw_i2s_dev { + struct clk *clk; + int active; + unsigned int capability; ++ #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0) ++ unsigned int quirks; ++ unsigned int i2s_reg_comp1; ++ unsigned int i2s_reg_comp2; + struct device *dev; + + /* data related to DMA transfers b/w i2s and DMAC */ +@@ -459,8 +463,8 @@ static int dw_configure_dai(struct dw_i2s_dev *dev, + * Read component parameter registers to extract + * the I2S block's configuration. + */ +- u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); +- u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); ++ u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); ++ u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); + u32 idx; + + if (COMP1_TX_ENABLED(comp1)) { +@@ -503,7 +507,7 @@ static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev, + struct resource *res, + const struct i2s_platform_data *pdata) + { +- u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); ++ u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); + u32 idx = COMP1_APB_DATA_WIDTH(comp1); + int ret; + +@@ -607,6 +611,14 @@ static int dw_i2s_probe(struct platform_device *pdev) + if (pdata) { + dev->capability = pdata->cap; + clk_id = NULL; ++ dev->quirks = pdata->quirks; ++ if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) { ++ dev->i2s_reg_comp1 = pdata->i2s_reg_comp1; ++ dev->i2s_reg_comp2 = pdata->i2s_reg_comp2; ++ } else { ++ dev->i2s_reg_comp1 = I2S_COMP_PARAM_1; ++ dev->i2s_reg_comp2 = I2S_COMP_PARAM_2; ++ } + ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata); + } else { + clk_id = "i2sclk"; +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1134-ASoC-dwc-reconfigure-dwc-in-resume-from-suspend.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1134-ASoC-dwc-reconfigure-dwc-in-resume-from-suspend.patch new file mode 100644 index 00000000..4ed5331c --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1134-ASoC-dwc-reconfigure-dwc-in-resume-from-suspend.patch @@ -0,0 +1,141 @@ +From ae2005698a4268461512386e741b489254e46915 Mon Sep 17 00:00:00 2001 +From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> +Date: Mon, 23 Nov 2015 20:08:21 +0530 +Subject: [PATCH 09/17] ASoC: dwc: reconfigure dwc in 'resume' from 'suspend' + +DWC IP can be powered off during system suspend in some platforms. +After system is resumed, dwc needs to be programmed again to continue +audio use case. + +Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + sound/soc/dwc/designware_i2s.c | 70 ++++++++++++++++++++++++++---------------- + 1 file changed, 43 insertions(+), 27 deletions(-) + +diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c +index 4f8f074..4e40a44 100644 +--- a/sound/soc/dwc/designware_i2s.c ++++ b/sound/soc/dwc/designware_i2s.c +@@ -98,6 +98,8 @@ struct dw_i2s_dev { + unsigned int i2s_reg_comp1; + unsigned int i2s_reg_comp2; + struct device *dev; ++ u32 ccr; ++ u32 xfer_resolution; + + /* data related to DMA transfers b/w i2s and DMAC */ + union dw_i2s_snd_dma_data play_dma_data; +@@ -217,31 +219,58 @@ static int dw_i2s_startup(struct snd_pcm_substream *substream, + return 0; + } + ++static void dw_i2s_config(struct dw_i2s_dev *dev, int stream) ++{ ++ u32 ch_reg, irq; ++ struct i2s_clk_config_data *config = &dev->config; ++ ++ ++ i2s_disable_channels(dev, stream); ++ ++ for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { ++ if (stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ i2s_write_reg(dev->i2s_base, TCR(ch_reg), ++ dev->xfer_resolution); ++ i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); ++ irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); ++ i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); ++ i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); ++ } else { ++ i2s_write_reg(dev->i2s_base, RCR(ch_reg), ++ dev->xfer_resolution); ++ i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); ++ irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); ++ i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03); ++ i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); ++ } ++ ++ } ++} ++ + static int dw_i2s_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) + { + struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); + struct i2s_clk_config_data *config = &dev->config; +- u32 ccr, xfer_resolution, ch_reg, irq; + int ret; + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + config->data_width = 16; +- ccr = 0x00; +- xfer_resolution = 0x02; ++ dev->ccr = 0x00; ++ dev->xfer_resolution = 0x02; + break; + + case SNDRV_PCM_FORMAT_S24_LE: + config->data_width = 24; +- ccr = 0x08; +- xfer_resolution = 0x04; ++ dev->ccr = 0x08; ++ dev->xfer_resolution = 0x04; + break; + + case SNDRV_PCM_FORMAT_S32_LE: + config->data_width = 32; +- ccr = 0x10; +- xfer_resolution = 0x05; ++ dev->ccr = 0x10; ++ dev->xfer_resolution = 0x05; + break; + + default: +@@ -262,27 +291,9 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream, + return -EINVAL; + } + +- i2s_disable_channels(dev, substream->stream); ++ dw_i2s_config(dev, substream->stream); + +- for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { +- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { +- i2s_write_reg(dev->i2s_base, TCR(ch_reg), +- xfer_resolution); +- i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); +- irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); +- i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); +- i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); +- } else { +- i2s_write_reg(dev->i2s_base, RCR(ch_reg), +- xfer_resolution); +- i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); +- irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); +- i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03); +- i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); +- } +- } +- +- i2s_write_reg(dev->i2s_base, CCR, ccr); ++ i2s_write_reg(dev->i2s_base, CCR, dev->ccr); + + config->sample_rate = params_rate(params); + +@@ -414,6 +425,11 @@ static int dw_i2s_resume(struct snd_soc_dai *dai) + + if (dev->capability & DW_I2S_MASTER) + clk_enable(dev->clk); ++ ++ if (dai->playback_active) ++ dw_i2s_config(dev, SNDRV_PCM_STREAM_PLAYBACK); ++ if (dai->capture_active) ++ dw_i2s_config(dev, SNDRV_PCM_STREAM_CAPTURE); + return 0; + } + +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1135-ASoC-dwc-add-quirk-to-override-COMP_PARAM_1-register.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1135-ASoC-dwc-add-quirk-to-override-COMP_PARAM_1-register.patch new file mode 100644 index 00000000..4458d8aa --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1135-ASoC-dwc-add-quirk-to-override-COMP_PARAM_1-register.patch @@ -0,0 +1,34 @@ +From 686d42a81aa86027c0232dd7caf5f0ae2a0984b6 Mon Sep 17 00:00:00 2001 +From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> +Date: Wed, 6 Jan 2016 20:37:15 +0530 +Subject: [PATCH 10/17] ASoC: dwc: add quirk to override COMP_PARAM_1 register + +DWC for capture in ACP 2.x IP reports playback and capture capabilities +though it supports only capture. Added a quirk to override default value +to represent capture capability only. + +Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + sound/soc/dwc/designware_i2s.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c +index 4e40a44..20156b4 100644 +--- a/sound/soc/dwc/designware_i2s.c ++++ b/sound/soc/dwc/designware_i2s.c +@@ -483,6 +483,10 @@ static int dw_configure_dai(struct dw_i2s_dev *dev, + u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); + u32 idx; + ++ if (dev->capability & DWC_I2S_RECORD && ++ dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) ++ comp1 = comp1 & ~BIT(5); ++ + if (COMP1_TX_ENABLED(comp1)) { + dev_dbg(dev->dev, " designware: play supported\n"); + idx = COMP1_TX_WORDSIZE_0(comp1); +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1136-ALSA-Soc-RT286Codec-Modifications-to-ALSA-SOC-Audio.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1136-ALSA-Soc-RT286Codec-Modifications-to-ALSA-SOC-Audio.patch new file mode 100644 index 00000000..8e1a80c0 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1136-ALSA-Soc-RT286Codec-Modifications-to-ALSA-SOC-Audio.patch @@ -0,0 +1,370 @@ +From b4b235644a4e6a1d81da5c40dc492f1be70dcaeb Mon Sep 17 00:00:00 2001 +From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> +Date: Fri, 1 Jul 2016 13:33:43 +0530 +Subject: [PATCH 11/17] ALSA:Soc:RT286Codec :Modifications to ALSA SOC Audio + +Codec Driver. + +Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + sound/soc/codecs/rt286.c | 197 ++++++++++++++++++++++++++++++++++++++++------- + 1 file changed, 169 insertions(+), 28 deletions(-) + +diff --git a/sound/soc/codecs/rt286.c b/sound/soc/codecs/rt286.c +index af2ed77..c67317b 100644 +--- a/sound/soc/codecs/rt286.c ++++ b/sound/soc/codecs/rt286.c +@@ -19,6 +19,7 @@ + #include <linux/spi/spi.h> + #include <linux/dmi.h> + #include <linux/acpi.h> ++#include <linux/gpio.h> + #include <sound/core.h> + #include <sound/pcm.h> + #include <sound/pcm_params.h> +@@ -29,16 +30,14 @@ + #include <sound/jack.h> + #include <linux/workqueue.h> + #include <sound/rt286.h> ++#include <sound/hda_verbs.h> + +-#include "rl6347a.h" + #include "rt286.h" + + #define RT286_VENDOR_ID 0x10ec0286 + #define RT288_VENDOR_ID 0x10ec0288 + + struct rt286_priv { +- struct reg_default *index_cache; +- int index_cache_size; + struct regmap *regmap; + struct snd_soc_codec *codec; + struct rt286_platform_data pdata; +@@ -47,9 +46,10 @@ struct rt286_priv { + struct delayed_work jack_detect_work; + int sys_clk; + int clk_id; ++ struct reg_default *index_cache; + }; + +-static const struct reg_default rt286_index_def[] = { ++static struct reg_default rt286_index_def[] = { + { 0x01, 0xaaaa }, + { 0x02, 0x8aaa }, + { 0x03, 0x0002 }, +@@ -186,6 +186,94 @@ static bool rt286_readable_register(struct device *dev, unsigned int reg) + } + } + ++static int rt286_hw_write(void *context, unsigned int reg, unsigned int value) ++{ ++ struct i2c_client *client = context; ++ struct rt286_priv *rt286 = i2c_get_clientdata(client); ++ u8 data[4]; ++ int ret, i; ++ ++ /* handle index registers */ ++ if (reg <= 0xff) { ++ rt286_hw_write(client, RT286_COEF_INDEX, reg); ++ for (i = 0; i < INDEX_CACHE_SIZE; i++) { ++ if (reg == rt286->index_cache[i].reg) { ++ rt286->index_cache[i].def = value; ++ break; ++ } ++ ++ } ++ reg = RT286_PROC_COEF; ++ } ++ ++ data[0] = (reg >> 24) & 0xff; ++ data[1] = (reg >> 16) & 0xff; ++ /* ++ * 4 bit VID: reg should be 0 ++ * 12 bit VID: value should be 0 ++ * So we use an OR operator to handle it rather than use if condition. ++ */ ++ data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff); ++ data[3] = value & 0xff; ++ ++ ret = i2c_master_send(client, data, 4); ++ ++ if (ret == 4) ++ return 0; ++ else ++ pr_err("ret=%d\n", ret); ++ if (ret < 0) ++ return ret; ++ else ++ return -EIO; ++} ++ ++static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value) ++{ ++ struct i2c_client *client = context; ++ struct i2c_msg xfer[2]; ++ int ret; ++ __be32 be_reg; ++ unsigned int index, vid, buf = 0x0; ++ ++ /* handle index registers */ ++ if (reg <= 0xff) { ++ rt286_hw_write(client, RT286_COEF_INDEX, reg); ++ reg = RT286_PROC_COEF; ++ } ++ ++ reg = reg | 0x80000; ++ vid = (reg >> 8) & 0xfff; ++ ++ if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) { ++ index = (reg >> 8) & 0xf; ++ reg = (reg & ~0xf0f) | index; ++ } ++ be_reg = cpu_to_be32(reg); ++ ++ /* Write register */ ++ xfer[0].addr = client->addr; ++ xfer[0].flags = 0; ++ xfer[0].len = 4; ++ xfer[0].buf = (u8 *)&be_reg; ++ ++ /* Read data */ ++ xfer[1].addr = client->addr; ++ xfer[1].flags = I2C_M_RD; ++ xfer[1].len = 4; ++ xfer[1].buf = (u8 *)&buf; ++ ++ ret = i2c_transfer(client->adapter, xfer, 2); ++ if (ret < 0) ++ return ret; ++ else if (ret != 2) ++ return -EIO; ++ ++ *value = be32_to_cpu(buf); ++ ++ return 0; ++} ++ + #ifdef CONFIG_PM + static void rt286_index_sync(struct snd_soc_codec *codec) + { +@@ -272,6 +360,15 @@ static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic) + *hp = buf & 0x80000000; + regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf); + *mic = buf & 0x80000000; ++ if (*mic) { ++ regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24); ++ msleep(50); ++ ++ regmap_update_bits(rt286->regmap, ++ RT286_CBJ_CTRL1, ++ 0xfcc0, 0xd400); ++ msleep(300); ++ } + } + + snd_soc_dapm_disable_pin(dapm, "HV"); +@@ -695,6 +792,7 @@ static int rt286_hw_params(struct snd_pcm_substream *substream, + unsigned int val = 0; + int d_len_code; + ++ pr_err("%s : rate : %d clk %d ch %d width %d\n",__func__,params_rate(params),rt286->sys_clk, params_channels(params), params_width(params)); + switch (params_rate(params)) { + /* bit 14 0:48K 1:44.1K */ + case 44100: +@@ -763,7 +861,8 @@ static int rt286_hw_params(struct snd_pcm_substream *substream, + + snd_soc_update_bits(codec, + RT286_I2S_CTRL1, 0x0018, d_len_code << 3); +- dev_dbg(codec->dev, "format val = 0x%x\n", val); ++ //dev_dbg(codec->dev, "format val = 0x%x\n", val); ++ pr_err("format val = 0x%x\n", val); + + snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val); + snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val); +@@ -927,6 +1026,7 @@ static int rt286_set_bias_level(struct snd_soc_codec *codec, + default: + break; + } ++ //codec->dapm.bias_level = level; + + return 0; + } +@@ -992,7 +1092,6 @@ static int rt286_suspend(struct snd_soc_codec *codec) + + regcache_cache_only(rt286->regmap, true); + regcache_mark_dirty(rt286->regmap); +- + return 0; + } + +@@ -1003,7 +1102,6 @@ static int rt286_resume(struct snd_soc_codec *codec) + regcache_cache_only(rt286->regmap, false); + rt286_index_sync(codec); + regcache_sync(rt286->regmap); +- + return 0; + } + #else +@@ -1013,7 +1111,8 @@ static int rt286_resume(struct snd_soc_codec *codec) + + #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) + #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ +- SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) ++ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) | \ ++ SNDRV_PCM_FMTBIT_S32_LE + + static const struct snd_soc_dai_ops rt286_aif_dai_ops = { + .hw_params = rt286_hw_params, +@@ -1087,8 +1186,8 @@ static const struct regmap_config rt286_regmap = { + .max_register = 0x02370100, + .volatile_reg = rt286_volatile_register, + .readable_reg = rt286_readable_register, +- .reg_write = rl6347a_hw_write, +- .reg_read = rl6347a_hw_read, ++ .reg_write = rt286_hw_write, ++ .reg_read = rt286_hw_read, + .cache_type = REGCACHE_RBTREE, + .reg_defaults = rt286_reg, + .num_reg_defaults = ARRAY_SIZE(rt286_reg), +@@ -1103,11 +1202,12 @@ MODULE_DEVICE_TABLE(i2c, rt286_i2c_id); + + static const struct acpi_device_id rt286_acpi_match[] = { + { "INT343A", 0 }, ++ { "RTK0000", 0}, + {}, + }; + MODULE_DEVICE_TABLE(acpi, rt286_acpi_match); + +-static const struct dmi_system_id force_combo_jack_table[] = { ++static struct dmi_system_id force_combo_jack_table[] = { + { + .ident = "Intel Wilson Beach", + .matches = { +@@ -1117,7 +1217,7 @@ static const struct dmi_system_id force_combo_jack_table[] = { + { } + }; + +-static const struct dmi_system_id dmi_dell_dino[] = { ++static struct dmi_system_id dmi_dell_dino[] = { + { + .ident = "Dell Dino", + .matches = { +@@ -1128,13 +1228,53 @@ static const struct dmi_system_id dmi_dell_dino[] = { + { } + }; + ++static struct rt286_platform_data rt286_acpi_data = { ++ .cbj_en = false, ++ .gpio2_en = false, ++}; ++ ++#if defined(CONFIG_ACPI) && defined(CONFIG_GPIOLIB) ++ ++static int get_gpio_irq(struct acpi_resource *ares, void *data) ++{ ++ if ((ares->type == ACPI_RESOURCE_GPIO_TYPE_INT) || ++ (ares->type == ACPI_RESOURCE_TYPE_GPIO)) { ++ int *irq = data; ++ *irq = gpio_to_irq(ares->data.gpio.pin_table[0]); ++ } ++ return 1; ++} ++ ++static int acpi_get_gpio_irq_res(struct device *idev) ++{ ++ int irq; ++ struct acpi_device *adev; ++ struct list_head resource_list; ++ acpi_handle handle; ++ ++ INIT_LIST_HEAD(&resource_list); ++ handle = ACPI_HANDLE(idev); ++ ++ if (!handle || acpi_bus_get_device(handle, &adev)) ++ return -ENODEV; ++ ++ acpi_dev_get_resources(adev, &resource_list, ++ get_gpio_irq, &irq); ++ acpi_dev_free_resource_list(&resource_list); ++ ++ return irq; ++} ++ ++#endif ++ + static int rt286_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *id) + { +- struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev); ++ struct rt286_platform_data *pdata = &rt286_acpi_data; + struct rt286_priv *rt286; + int i, ret, val; + ++ pr_err("%s : called\n",__func__); + rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286), + GFP_KERNEL); + if (NULL == rt286) +@@ -1156,16 +1296,11 @@ static int rt286_i2c_probe(struct i2c_client *i2c, + } + if (val != RT286_VENDOR_ID && val != RT288_VENDOR_ID) { + dev_err(&i2c->dev, +- "Device with ID register %#x is not rt286\n", val); ++ "Device with ID register %x is not rt286\n", val); + return -ENODEV; + } + +- rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def, +- sizeof(rt286_index_def), GFP_KERNEL); +- if (!rt286->index_cache) +- return -ENOMEM; +- +- rt286->index_cache_size = INDEX_CACHE_SIZE; ++ rt286->index_cache = rt286_index_def; + rt286->i2c = i2c; + i2c_set_clientdata(i2c, rt286); + +@@ -1231,19 +1366,24 @@ static int rt286_i2c_probe(struct i2c_client *i2c, + RT286_GPIO_CTRL, 0xc, 0x8); + } + +- if (rt286->i2c->irq) { +- ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq, +- IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286); +- if (ret != 0) { +- dev_err(&i2c->dev, +- "Failed to reguest IRQ: %d\n", ret); +- return ret; +- } ++ if (rt286->i2c->irq < 0) { ++ rt286->i2c->irq = acpi_get_gpio_irq_res(&rt286->i2c->dev); ++ if (rt286->i2c->irq < 0) ++ return -ENODEV; ++ } ++ ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq, ++ IRQF_TRIGGER_RISING | IRQF_ONESHOT, "rt286", rt286); ++ if (ret != 0) { ++ dev_err(&i2c->dev, ++ "Failed to reguest IRQ: %d\n", ret); ++ return ret; + } + + ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286, + rt286_dai, ARRAY_SIZE(rt286_dai)); + ++ pr_err("%s : ret = %d\n",__func__,ret); ++ + return ret; + } + +@@ -1262,6 +1402,7 @@ static int rt286_i2c_remove(struct i2c_client *i2c) + static struct i2c_driver rt286_i2c_driver = { + .driver = { + .name = "rt286", ++ .owner = THIS_MODULE, + .acpi_match_table = ACPI_PTR(rt286_acpi_match), + }, + .probe = rt286_i2c_probe, +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1137-drm-amdgpu-acp-fix-resume-on-CZ-systems-with-AZ-audi.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1137-drm-amdgpu-acp-fix-resume-on-CZ-systems-with-AZ-audi.patch new file mode 100644 index 00000000..2c2739b9 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1137-drm-amdgpu-acp-fix-resume-on-CZ-systems-with-AZ-audi.patch @@ -0,0 +1,31 @@ +From c0e62d528ca2557326eedc2f43460b6f4afcdf7b Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Wed, 13 Apr 2016 23:37:42 -0400 +Subject: [PATCH 17/17] drm/amdgpu/acp: fix resume on CZ systems with AZ audio + +Nothing to do on resume on systems with AZ audio. + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +index 37ecc36..6549b3c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +@@ -427,6 +427,10 @@ static int acp_resume(void *handle) + struct acp_pm_domain *apd; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + ++ /* return early if no ACP */ ++ if (!adev->acp.acp_genpd) ++ return 0; ++ + /* SMU block will power on ACP irrespective of ACP runtime status. + * Power off explicitly based on genpd ACP runtime status so that ACP + * hw and ACP-genpd status are in sync. +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1138-add-new-semaphore-object-in-kernel-side.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1138-add-new-semaphore-object-in-kernel-side.patch new file mode 100644 index 00000000..f27f1afc --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1138-add-new-semaphore-object-in-kernel-side.patch @@ -0,0 +1,504 @@ +From d29a89414316f4c54a1a619527398714b091d3db Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Mon, 14 Nov 2016 12:26:18 +0530 +Subject: [PATCH] add new semaphore object in kernel side + +So that semaphore can be shared across porcess across devices. + +Change-Id: Ie82cace6af81e2ddf45f4bbf9f3c0dafd6bcc499 +Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 + + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 6 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 267 ++++++++++++++++++++++ + drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h | 44 ++++ + drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 29 +++ + 8 files changed, 361 insertions(+), 4 deletions(-) + create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c + create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h + +diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile +index 28e8e4c..2acc7c1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/Makefile ++++ b/drivers/gpu/drm/amd/amdgpu/Makefile +@@ -31,7 +31,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ + amdgpu_pm.o atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \ + atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ + amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ +- amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o ++ amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \ ++ amdgpu_sem.o + + # add asic specific block + amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index d3de21d..3f5d2ad 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1000,6 +1000,8 @@ struct amdgpu_ctx_ring { + uint64_t sequence; + struct fence **fences; + struct amd_sched_entity entity; ++ struct list_head sem_list; ++ struct mutex sem_lock; + /* client id */ + u64 client_id; + }; +@@ -1699,6 +1701,8 @@ struct amdgpu_vce { + struct amdgpu_irq_src irq; + unsigned harvest_config; + struct amd_sched_entity entity; ++ struct list_head sem_list; ++ struct mutex sem_lock; + }; + + /* +@@ -1872,6 +1876,13 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, + int amdgpu_freesync_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + ++int amdgpu_sem_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *filp); ++ ++int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, ++ struct amdgpu_sync *sync); ++ ++ + /* VRAM scratch page for HDP bug, default vram page */ + struct amdgpu_vram_scratch { + struct amdgpu_bo *robj; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +index 0d1346c..bb6057a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +@@ -882,7 +882,7 @@ static int amdgpu_cs_dependencies(struct amdgpu_device *adev, + } + } + +- return 0; ++ return amdgpu_sem_add_cs(p->ctx, p->job->ring, &p->job->sync); + } + + static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +index 17e1362..a020e22 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +@@ -42,6 +42,8 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, struct amdgpu_ctx *ctx) + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { + ctx->rings[i].sequence = 1; + ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i]; ++ INIT_LIST_HEAD(&ctx->rings[i].sem_list); ++ mutex_init(&ctx->rings[i].sem_lock); + } + /* create context entity for each ring */ + for (i = 0; i < adev->num_rings; i++) { +@@ -74,8 +76,10 @@ static void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) + return; + + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) +- for (j = 0; j < amdgpu_sched_jobs; ++j) ++ for (j = 0; j < amdgpu_sched_jobs; ++j) { + fence_put(ctx->rings[i].fences[j]); ++ mutex_destroy(&ctx->rings[i].sem_lock); ++ } + kfree(ctx->fences); + + for (i = 0; i < adev->num_rings; i++) +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +index f6ae587..a48783e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +@@ -786,6 +786,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), +- DRM_IOCTL_DEF_DRV(AMDGPU_FREESYNC, amdgpu_freesync_ioctl, DRM_MASTER) ++ DRM_IOCTL_DEF_DRV(AMDGPU_FREESYNC, amdgpu_freesync_ioctl, DRM_MASTER), ++ DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + }; + const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c +new file mode 100644 +index 0000000..db16baa +--- /dev/null ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c +@@ -0,0 +1,267 @@ ++/* ++ * Copyright 2016 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: ++ * Chunming Zhou <david1.zhou@amd.com> ++ */ ++#include <linux/file.h> ++#include <linux/fs.h> ++#include <linux/kernel.h> ++#include <linux/poll.h> ++#include <linux/seq_file.h> ++#include <linux/export.h> ++#include <linux/sched.h> ++#include <linux/slab.h> ++#include <linux/uaccess.h> ++#include <linux/anon_inodes.h> ++#include "amdgpu_sem.h" ++#include "amdgpu.h" ++#include <drm/drmP.h> ++ ++static int amdgpu_sem_cring_add(struct amdgpu_fpriv *fpriv, ++ struct drm_amdgpu_sem_in *in, ++ struct amdgpu_sem *sem); ++ ++static const struct file_operations amdgpu_sem_fops; ++ ++static struct amdgpu_sem *amdgpu_sem_alloc(struct fence *fence) ++{ ++ struct amdgpu_sem *sem; ++ ++ sem = kzalloc(sizeof(struct amdgpu_sem), GFP_KERNEL); ++ if (!sem) ++ return NULL; ++ ++ sem->file = anon_inode_getfile("sem_file", ++ &amdgpu_sem_fops, ++ sem, 0); ++ if (IS_ERR(sem->file)) ++ goto err; ++ ++ kref_init(&sem->kref); ++ INIT_LIST_HEAD(&sem->list); ++ /* fence should be get before passing here */ ++ sem->fence = fence; ++ ++ return sem; ++err: ++ kfree(sem); ++ return NULL; ++} ++ ++static void amdgpu_sem_free(struct kref *kref) ++{ ++ struct amdgpu_sem *sem = container_of( ++ kref, struct amdgpu_sem, kref); ++ ++ fence_put(sem->fence); ++ kfree(sem); ++} ++ ++static int amdgpu_sem_release(struct inode *inode, struct file *file) ++{ ++ struct amdgpu_sem *sem = file->private_data; ++ ++ kref_put(&sem->kref, amdgpu_sem_free); ++ return 0; ++} ++ ++static unsigned int amdgpu_sem_poll(struct file *file, poll_table *wait) ++{ ++ return 0; ++} ++ ++static long amdgpu_sem_file_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ return 0; ++} ++ ++static const struct file_operations amdgpu_sem_fops = { ++ .release = amdgpu_sem_release, ++ .poll = amdgpu_sem_poll, ++ .unlocked_ioctl = amdgpu_sem_file_ioctl, ++ .compat_ioctl = amdgpu_sem_file_ioctl, ++}; ++ ++static int amdgpu_sem_create(void) ++{ ++ return get_unused_fd_flags(O_CLOEXEC); ++} ++ ++static int amdgpu_sem_signal(int fd, struct fence *fence) ++{ ++ struct amdgpu_sem *sem; ++ ++ sem = amdgpu_sem_alloc(fence); ++ if (!sem) ++ return -ENOMEM; ++ fd_install(fd, sem->file); ++ ++ return 0; ++} ++ ++static int amdgpu_sem_wait(int fd, struct amdgpu_fpriv *fpriv, ++ struct drm_amdgpu_sem_in *in) ++{ ++ struct file *file = fget(fd); ++ struct amdgpu_sem *sem; ++ int r; ++ ++ if (!file) ++ return -EINVAL; ++ ++ sem = file->private_data; ++ if (!sem) { ++ r = -EINVAL; ++ goto err; ++ } ++ r = amdgpu_sem_cring_add(fpriv, in, sem); ++err: ++ fput(file); ++ return r; ++} ++ ++static void amdgpu_sem_destroy(void) ++{ ++ /* userspace should close fd when they try to destroy sem, ++ * closing fd will free semaphore object. ++ */ ++} ++ ++static struct fence *amdgpu_sem_get_fence(struct amdgpu_fpriv *fpriv, ++ struct drm_amdgpu_sem_in *in) ++{ ++ struct amdgpu_ring *out_ring; ++ struct amdgpu_ctx *ctx; ++ struct fence *fence; ++ uint32_t ctx_id, ip_type, ip_instance, ring; ++ int r; ++ ++ ctx_id = in->ctx_id; ++ ip_type = in->ip_type; ++ ip_instance = in->ip_instance; ++ ring = in->ring; ++ ctx = amdgpu_ctx_get(fpriv, ctx_id); ++ if (!ctx) ++ return NULL; ++ r = amdgpu_cs_get_ring(ctx->adev, ip_type, ip_instance, ring, ++ &out_ring); ++ if (r) { ++ amdgpu_ctx_put(ctx); ++ return NULL; ++ } ++ /* get the last fence of this entity */ ++ fence = amdgpu_ctx_get_fence(ctx, out_ring, ++ in->seq ? in->seq : ++ ctx->rings[out_ring->idx].sequence - 1); ++ amdgpu_ctx_put(ctx); ++ ++ return fence; ++} ++ ++static int amdgpu_sem_cring_add(struct amdgpu_fpriv *fpriv, ++ struct drm_amdgpu_sem_in *in, ++ struct amdgpu_sem *sem) ++{ ++ struct amdgpu_ring *out_ring; ++ struct amdgpu_ctx *ctx; ++ uint32_t ctx_id, ip_type, ip_instance, ring; ++ int r; ++ ++ ctx_id = in->ctx_id; ++ ip_type = in->ip_type; ++ ip_instance = in->ip_instance; ++ ring = in->ring; ++ ctx = amdgpu_ctx_get(fpriv, ctx_id); ++ if (!ctx) ++ return -EINVAL; ++ r = amdgpu_cs_get_ring(ctx->adev, ip_type, ip_instance, ring, ++ &out_ring); ++ if (r) ++ goto err; ++ mutex_lock(&ctx->rings[out_ring->idx].sem_lock); ++ list_add(&sem->list, &ctx->rings[out_ring->idx].sem_list); ++ mutex_unlock(&ctx->rings[out_ring->idx].sem_lock); ++ ++err: ++ amdgpu_ctx_put(ctx); ++ return r; ++} ++ ++int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, ++ struct amdgpu_sync *sync) ++{ ++ struct amdgpu_sem *sem, *tmp; ++ int r = 0; ++ ++ if (list_empty(&ctx->rings[ring->idx].sem_list)) ++ return 0; ++ ++ mutex_lock(&ctx->rings[ring->idx].sem_lock); ++ list_for_each_entry_safe(sem, tmp, &ctx->rings[ring->idx].sem_list, ++ list) { ++ r = amdgpu_sync_fence(ctx->adev, sync, sem->fence); ++ fence_put(sem->fence); ++ if (r) ++ goto err; ++ list_del(&sem->list); ++ kfree(sem); ++ } ++err: ++ mutex_unlock(&ctx->rings[ring->idx].sem_lock); ++ return r; ++} ++ ++int amdgpu_sem_ioctl(struct drm_device *dev, void *data, ++ struct drm_file *filp) ++{ ++ union drm_amdgpu_sem *args = data; ++ struct amdgpu_fpriv *fpriv = filp->driver_priv; ++ struct fence *fence; ++ int r = 0; ++ int fd = args->in.fd; ++ ++ switch (args->in.op) { ++ case AMDGPU_SEM_OP_CREATE_SEM: ++ args->out.fd = amdgpu_sem_create(); ++ break; ++ case AMDGPU_SEM_OP_WAIT_SEM: ++ r = amdgpu_sem_wait(fd, fpriv, &args->in); ++ break; ++ case AMDGPU_SEM_OP_SIGNAL_SEM: ++ fence = amdgpu_sem_get_fence(fpriv, &args->in); ++ if (IS_ERR(fence)) { ++ r = PTR_ERR(fence); ++ return r; ++ } ++ r = amdgpu_sem_signal(fd, fence); ++ fence_put(fence); ++ break; ++ case AMDGPU_SEM_OP_DESTROY_SEM: ++ amdgpu_sem_destroy(); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return r; ++} +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h +new file mode 100644 +index 0000000..56d59d3 +--- /dev/null ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h +@@ -0,0 +1,44 @@ ++/* ++ * Copyright 2016 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Chunming Zhou <david1.zhou@amd.com> ++ * ++ */ ++ ++ ++#ifndef _LINUX_AMDGPU_SEM_H ++#define _LINUX_AMDGPU_SEM_H ++ ++#include <linux/types.h> ++#include <linux/kref.h> ++#include <linux/ktime.h> ++#include <linux/list.h> ++#include <linux/spinlock.h> ++#include <linux/fence.h> ++ ++struct amdgpu_sem { ++ struct file *file; ++ struct kref kref; ++ struct fence *fence; ++ struct list_head list; ++}; ++ ++#endif /* _LINUX_AMDGPU_SEM_H */ +diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +index b06e3dc..65153bf 100644 +--- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h ++++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +@@ -46,6 +46,7 @@ + #define DRM_AMDGPU_WAIT_CS 0x09 + #define DRM_AMDGPU_GEM_OP 0x10 + #define DRM_AMDGPU_GEM_USERPTR 0x11 ++#define DRM_AMDGPU_SEM 0x5b + #define DRM_AMDGPU_FREESYNC 0x14 + + #define DRM_AMDGPU_WAIT_FENCES 0x5e +@@ -64,6 +65,7 @@ + #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) + #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) + #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) ++#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) + + #define AMDGPU_GEM_DOMAIN_CPU 0x1 + #define AMDGPU_GEM_DOMAIN_GTT 0x2 +@@ -185,6 +187,33 @@ union drm_amdgpu_ctx { + union drm_amdgpu_ctx_out out; + }; + ++/* sem related */ ++#define AMDGPU_SEM_OP_CREATE_SEM 1 ++#define AMDGPU_SEM_OP_WAIT_SEM 2 ++#define AMDGPU_SEM_OP_SIGNAL_SEM 3 ++#define AMDGPU_SEM_OP_DESTROY_SEM 4 ++ ++struct drm_amdgpu_sem_in { ++ /** AMDGPU_SEM_OP_* */ ++ uint32_t op; ++ int32_t fd; ++ uint32_t ctx_id; ++ uint32_t ip_type; ++ uint32_t ip_instance; ++ uint32_t ring; ++ uint64_t seq; ++}; ++ ++union drm_amdgpu_sem_out { ++ int32_t fd; ++ uint32_t _pad; ++}; ++ ++union drm_amdgpu_sem { ++ struct drm_amdgpu_sem_in in; ++ union drm_amdgpu_sem_out out; ++}; ++ + /* + * This is not a reliable API and you should expect it to fail for any + * number of reasons and have fallback path that do not use userptr to +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1139-unify-memory-query-info-interface.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1139-unify-memory-query-info-interface.patch new file mode 100644 index 00000000..b7c965a3 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1139-unify-memory-query-info-interface.patch @@ -0,0 +1,113 @@ +From 314642915b4a2bda146fb9d900ca99eabeab36c0 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Mon, 14 Nov 2016 12:13:41 +0530 +Subject: [PATCH 01/10] unify memory query info interface +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Change-Id: I74d2b7379bc4febe714a91daf4e1786895de90f2 +Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> +Reviewed-by: Marek Olšák <marek.olsak@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 32 +++++++++++++++++++++++ + drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 32 +++++++++++++++++++++++ + 2 files changed, 64 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +index 31c20ba..a48783e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +@@ -390,6 +390,38 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file + return copy_to_user(out, &vram_gtt, + min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; + } ++ ++ case AMDGPU_INFO_MEMORY: { ++ struct drm_amdgpu_memory_info mem; ++ ++ memset(&mem, 0, sizeof(mem)); ++ mem.vram.total_heap_size = adev->mc.real_vram_size; ++ mem.vram.usable_heap_size = ++ adev->mc.real_vram_size - adev->vram_pin_size; ++ mem.vram.heap_usage = atomic64_read(&adev->vram_usage); ++ mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; ++ ++ mem.cpu_accessible_vram.total_heap_size = ++ adev->mc.visible_vram_size; ++ mem.cpu_accessible_vram.usable_heap_size = ++ adev->mc.visible_vram_size - ++ (adev->vram_pin_size - adev->invisible_pin_size); ++ mem.cpu_accessible_vram.heap_usage = ++ atomic64_read(&adev->vram_vis_usage); ++ mem.cpu_accessible_vram.max_allocation = ++ mem.cpu_accessible_vram.usable_heap_size * 3 / 4; ++ ++ mem.gtt.total_heap_size = adev->mc.gtt_size; ++ mem.gtt.usable_heap_size = ++ adev->mc.gtt_size - adev->gart_pin_size; ++ mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage); ++ mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; ++ ++ return copy_to_user(out, &mem, ++ min((size_t)size, sizeof(mem))) ++ ? -EFAULT : 0; ++ } ++ + case AMDGPU_INFO_READ_MMR_REG: { + unsigned n, alloc_size; + uint32_t *regs; +diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +index 4d7d982..3f13a87 100644 +--- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h ++++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +@@ -540,6 +540,10 @@ struct drm_amdgpu_cs_chunk_data { + #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 + /* virtual range */ + #define AMDGPU_INFO_VIRTUAL_RANGE 0x18 ++ ++/* Query memory about VRAM and GTT domains */ ++#define AMDGPU_INFO_MEMORY 0x19 ++ + /* gpu capability */ + #define AMDGPU_INFO_CAPABILITY 0x50 + /* query pin memory capability */ +@@ -705,6 +709,34 @@ struct drm_amdgpu_info_hw_ip { + __u32 _pad; + }; + ++struct drm_amdgpu_heap_info { ++ /** max. physical memory */ ++ __u64 total_heap_size; ++ ++ /** Theoretical max. available memory in the given heap */ ++ __u64 usable_heap_size; ++ ++ /** ++ * Number of bytes allocated in the heap. This includes all processes ++ * and private allocations in the kernel. It changes when new buffers ++ * are allocated, freed, and moved. It cannot be larger than ++ * heap_size. ++ */ ++ __u64 heap_usage; ++ ++ /** ++ * Theoretical possible max. size of buffer which ++ * could be allocated in the given heap ++ */ ++ __u64 max_allocation; ++}; ++ ++struct drm_amdgpu_memory_info { ++ struct drm_amdgpu_heap_info vram; ++ struct drm_amdgpu_heap_info cpu_accessible_vram; ++ struct drm_amdgpu_heap_info gtt; ++}; ++ + /* + * Supported GPU families + */ +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1140-dma-buf-return-index-of-the-first-signaled-fence.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1140-dma-buf-return-index-of-the-first-signaled-fence.patch new file mode 100644 index 00000000..76815764 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1140-dma-buf-return-index-of-the-first-signaled-fence.patch @@ -0,0 +1,188 @@ +From 7e06443930ab2fabda1977c20ff82ff6bc42e3be Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Tue, 15 Nov 2016 14:30:58 +0530 +Subject: [PATCH 02/10] dma-buf: return index of the first signaled fence + +Return the index of the first signaled fence. This information +is useful in some APIs like Vulkan. + +Signed-off-by: monk.liu <monk.liu@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Cc: Sumit Semwal <sumit.semwal@linaro.org> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/dma-buf/fence.c | 19 ++++++++++++++----- + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 +++- + drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | 2 +- + drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h | 21 +++++++++++---------- + include/linux/fence.h | 2 +- + 5 files changed, 30 insertions(+), 18 deletions(-) + +diff --git a/drivers/dma-buf/fence.c b/drivers/dma-buf/fence.c +index 7b05dbe..192f99b 100644 +--- a/drivers/dma-buf/fence.c ++++ b/drivers/dma-buf/fence.c +@@ -398,14 +398,17 @@ out: + EXPORT_SYMBOL(fence_default_wait); + + static bool +-fence_test_signaled_any(struct fence **fences, uint32_t count) ++fence_test_signaled_any(struct fence **fences, uint32_t count, uint32_t *idx) + { + int i; + + for (i = 0; i < count; ++i) { + struct fence *fence = fences[i]; +- if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags)) ++ if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { ++ if (idx) ++ *idx = i; + return true; ++ } + } + return false; + } +@@ -417,6 +420,7 @@ fence_test_signaled_any(struct fence **fences, uint32_t count) + * @count: [in] number of fences to wait on + * @intr: [in] if true, do an interruptible wait + * @timeout: [in] timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT ++ * @idx: [out] the first signaled fence index, meaninful only on Returns positive + * + * Returns -EINVAL on custom fence wait implementation, -ERESTARTSYS if + * interrupted, 0 if the wait timed out, or the remaining timeout in jiffies +@@ -428,7 +432,7 @@ fence_test_signaled_any(struct fence **fences, uint32_t count) + */ + signed long + fence_wait_any_timeout(struct fence **fences, uint32_t count, +- bool intr, signed long timeout) ++ bool intr, signed long timeout, uint32_t *idx) + { + struct default_wait_cb *cb; + signed long ret = timeout; +@@ -439,8 +443,11 @@ fence_wait_any_timeout(struct fence **fences, uint32_t count, + + if (timeout == 0) { + for (i = 0; i < count; ++i) +- if (fence_is_signaled(fences[i])) ++ if (fence_is_signaled(fences[i])) { ++ if (idx) ++ *idx = i; + return 1; ++ } + + return 0; + } +@@ -463,6 +470,8 @@ fence_wait_any_timeout(struct fence **fences, uint32_t count, + if (fence_add_callback(fence, &cb[i].base, + fence_default_wait_cb)) { + /* This fence is already signaled */ ++ if (idx) ++ *idx = i; + goto fence_rm_cb; + } + } +@@ -473,7 +482,7 @@ fence_wait_any_timeout(struct fence **fences, uint32_t count, + else + set_current_state(TASK_UNINTERRUPTIBLE); + +- if (fence_test_signaled_any(fences, count)) ++ if (fence_test_signaled_any(fences, count, idx)) + break; + + ret = schedule_timeout(ret); +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +index bb6057a..181e2b7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +@@ -1107,6 +1107,7 @@ static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev, + { + unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns); + uint32_t fence_count = wait->in.fence_count; ++ uint32_t first = ~0; + struct fence **array; + unsigned i; + long r; +@@ -1132,13 +1133,14 @@ static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev, + } + } + +- r = fence_wait_any_timeout(array, fence_count, true, timeout); ++ r = fence_wait_any_timeout(array, fence_count, true, timeout, &first); + if (r < 0) + goto err_free_fence_array; + + out: + memset(wait, 0, sizeof(*wait)); + wait->out.status = (r > 0); ++ wait->out.first_signaled = first; + /* set return value 0 to indicate success */ + r = 0; + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c +index 8bf84ef..9f4311c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c +@@ -360,7 +360,7 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, + if (count) { + spin_unlock(&sa_manager->wq.lock); + t = fence_wait_any_timeout(fences, count, false, +- MAX_SCHEDULE_TIMEOUT); ++ MAX_SCHEDULE_TIMEOUT, NULL); + for (i = 0; i < count; ++i) + fence_put(fences[i]); + +diff --git a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +index 3f13a87..c2f06eb 100644 +--- a/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h ++++ b/drivers/gpu/drm/amd/include/uapi/drm/amdgpu_drm.h +@@ -334,23 +334,24 @@ union drm_amdgpu_wait_cs { + }; + + struct drm_amdgpu_fence { +- uint32_t ctx_id; +- uint32_t ip_type; +- uint32_t ip_instance; +- uint32_t ring; +- uint64_t seq_no; ++ __u32 ctx_id; ++ __u32 ip_type; ++ __u32 ip_instance; ++ __u32 ring; ++ __u64 seq_no; + }; + + struct drm_amdgpu_wait_fences_in { + /** This points to uint64_t * which points to fences */ +- uint64_t fences; +- uint32_t fence_count; +- uint32_t wait_all; +- uint64_t timeout_ns; ++ __u64 fences; ++ __u32 fence_count; ++ __u32 wait_all; ++ __u64 timeout_ns; + }; + + struct drm_amdgpu_wait_fences_out { +- uint64_t status; ++ __u32 status; ++ __u32 first_signaled; + }; + + union drm_amdgpu_wait_fences { +diff --git a/include/linux/fence.h b/include/linux/fence.h +index bb52201..b8da489 100644 +--- a/include/linux/fence.h ++++ b/include/linux/fence.h +@@ -322,7 +322,7 @@ static inline struct fence *fence_later(struct fence *f1, struct fence *f2) + + signed long fence_wait_timeout(struct fence *, bool intr, signed long timeout); + signed long fence_wait_any_timeout(struct fence **fences, uint32_t count, +- bool intr, signed long timeout); ++ bool intr, signed long timeout, uint32_t *idx); + + /** + * fence_wait - sleep until the fence gets signaled +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1142-add-additional-cached-gca-config-variables.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1142-add-additional-cached-gca-config-variables.patch new file mode 100644 index 00000000..c9c426f9 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1142-add-additional-cached-gca-config-variables.patch @@ -0,0 +1,51 @@ +From caa6b72d0c01491114f017fe3bca7adc05194611 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Tue, 6 Dec 2016 17:07:10 +0530 +Subject: [PATCH 04/10] add additional cached gca config variables +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +We need to cache some additional values to handle SR-IOV +and PG. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index 3f5d2ad..40497c2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1135,6 +1135,16 @@ struct amdgpu_scratch { + /* + * GFX configurations + */ ++#define AMDGPU_GFX_MAX_SE 4 ++#define AMDGPU_GFX_MAX_SH_PER_SE 2 ++ ++struct amdgpu_rb_config { ++ uint32_t rb_backend_disable; ++ uint32_t user_rb_backend_disable; ++ uint32_t raster_config; ++ uint32_t raster_config_1; ++}; ++ + struct amdgpu_gca_config { + unsigned max_shader_engines; + unsigned max_tile_pipes; +@@ -1163,6 +1173,8 @@ struct amdgpu_gca_config { + + uint32_t tile_mode_array[32]; + uint32_t macrotile_mode_array[16]; ++ ++ struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; + }; + + struct amdgpu_gfx { +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1143-implement-raster-configuration-for-gfx-v8.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1143-implement-raster-configuration-for-gfx-v8.patch new file mode 100644 index 00000000..c1a271f2 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1143-implement-raster-configuration-for-gfx-v8.patch @@ -0,0 +1,262 @@ +From 705f105de150240594945703df70f82d5ab861ce Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Tue, 6 Dec 2016 19:33:01 +0530 +Subject: [PATCH 05/10] implement raster configuration for gfx v8 + +This patch is to implement the raster configuration and harvested +configuration of gfx v8. + +Signed-off-by: Huang Rui <ray.huang@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 168 +++++++++++++++++++++++++++++++++- + drivers/gpu/drm/amd/amdgpu/vid.h | 37 ++++++++ + 2 files changed, 204 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index c5a3d04..20ac07f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -3484,13 +3484,163 @@ static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev) + return (~data) & mask; + } + ++static void ++gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) ++{ ++ switch (adev->asic_type) { ++ case CHIP_FIJI: ++ *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) | ++ RB_XSEL2(1) | PKR_MAP(2) | ++ PKR_XSEL(1) | PKR_YSEL(1) | ++ SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3); ++ *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) | ++ SE_PAIR_YSEL(2); ++ break; ++ case CHIP_TONGA: ++ case CHIP_POLARIS10: ++ *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | ++ SE_XSEL(1) | SE_YSEL(1); ++ *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) | ++ SE_PAIR_YSEL(2); ++ break; ++ case CHIP_TOPAZ: ++ case CHIP_CARRIZO: ++ *rconf |= RB_MAP_PKR0(2); ++ *rconf1 |= 0x0; ++ break; ++ case CHIP_POLARIS11: ++ *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | ++ SE_XSEL(1) | SE_YSEL(1); ++ *rconf1 |= 0x0; ++ break; ++ case CHIP_STONEY: ++ *rconf |= 0x0; ++ *rconf1 |= 0x0; ++ break; ++ default: ++ DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); ++ break; ++ } ++} ++ ++static void ++gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev, ++ u32 raster_config, u32 raster_config_1, ++ unsigned rb_mask, unsigned num_rb) ++{ ++ unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); ++ unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); ++ unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); ++ unsigned rb_per_se = num_rb / num_se; ++ unsigned se_mask[4]; ++ unsigned se; ++ ++ se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; ++ se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; ++ se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; ++ se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; ++ ++ WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); ++ WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); ++ WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); ++ ++ if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || ++ (!se_mask[2] && !se_mask[3]))) { ++ raster_config_1 &= ~SE_PAIR_MAP_MASK; ++ ++ if (!se_mask[0] && !se_mask[1]) { ++ raster_config_1 |= ++ SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3); ++ } else { ++ raster_config_1 |= ++ SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0); ++ } ++ } ++ ++ for (se = 0; se < num_se; se++) { ++ unsigned raster_config_se = raster_config; ++ unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); ++ unsigned pkr1_mask = pkr0_mask << rb_per_pkr; ++ int idx = (se / 2) * 2; ++ ++ if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { ++ raster_config_se &= ~SE_MAP_MASK; ++ ++ if (!se_mask[idx]) { ++ raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); ++ } else { ++ raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); ++ } ++ } ++ ++ pkr0_mask &= rb_mask; ++ pkr1_mask &= rb_mask; ++ if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { ++ raster_config_se &= ~PKR_MAP_MASK; ++ ++ if (!pkr0_mask) { ++ raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); ++ } else { ++ raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); ++ } ++ } ++ ++ if (rb_per_se >= 2) { ++ unsigned rb0_mask = 1 << (se * rb_per_se); ++ unsigned rb1_mask = rb0_mask << 1; ++ ++ rb0_mask &= rb_mask; ++ rb1_mask &= rb_mask; ++ if (!rb0_mask || !rb1_mask) { ++ raster_config_se &= ~RB_MAP_PKR0_MASK; ++ ++ if (!rb0_mask) { ++ raster_config_se |= ++ RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); ++ } else { ++ raster_config_se |= ++ RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); ++ } ++ } ++ ++ if (rb_per_se > 2) { ++ rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); ++ rb1_mask = rb0_mask << 1; ++ rb0_mask &= rb_mask; ++ rb1_mask &= rb_mask; ++ if (!rb0_mask || !rb1_mask) { ++ raster_config_se &= ~RB_MAP_PKR1_MASK; ++ ++ if (!rb0_mask) { ++ raster_config_se |= ++ RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); ++ } else { ++ raster_config_se |= ++ RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); ++ } ++ } ++ } ++ } ++ ++ /* GRBM_GFX_INDEX has a different offset on VI */ ++ gfx_v8_0_select_se_sh(adev, se, 0xffffffff); ++ WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); ++ WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); ++ } ++ ++ /* GRBM_GFX_INDEX has a different offset on VI */ ++ gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); ++} ++ + static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) + { + int i, j; + u32 data; ++ u32 raster_config = 0, raster_config_1 = 0; + u32 active_rbs = 0; + u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / + adev->gfx.config.max_sh_per_se; ++ unsigned num_rb_pipes; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { +@@ -3502,10 +3652,26 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) + } + } + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); +- mutex_unlock(&adev->grbm_idx_mutex); + + adev->gfx.config.backend_enable_mask = active_rbs; + adev->gfx.config.num_rbs = hweight32(active_rbs); ++ ++ num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * ++ adev->gfx.config.max_shader_engines, 16); ++ ++ gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1); ++ ++ if (!adev->gfx.config.backend_enable_mask || ++ adev->gfx.config.num_rbs >= num_rb_pipes) { ++ WREG32(mmPA_SC_RASTER_CONFIG, raster_config); ++ WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); ++ } else { ++ gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, ++ adev->gfx.config.backend_enable_mask, ++ num_rb_pipes); ++ } ++ ++ mutex_unlock(&adev->grbm_idx_mutex); + } + + /** +diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h +index 3bf7172..4bd2bfd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vid.h ++++ b/drivers/gpu/drm/amd/amdgpu/vid.h +@@ -368,4 +368,41 @@ + #define VCE_CMD_IB_AUTO 0x00000005 + #define VCE_CMD_SEMAPHORE 0x00000006 + ++ ++/* mmPA_SC_RASTER_CONFIG mask */ ++#define RB_MAP_PKR0(x) ((x) << 0) ++#define RB_MAP_PKR0_MASK (0x3 << 0) ++#define RB_MAP_PKR1(x) ((x) << 2) ++#define RB_MAP_PKR1_MASK (0x3 << 2) ++#define RB_XSEL2(x) ((x) << 4) ++#define RB_XSEL2_MASK (0x3 << 4) ++#define RB_XSEL (1 << 6) ++#define RB_YSEL (1 << 7) ++#define PKR_MAP(x) ((x) << 8) ++#define PKR_MAP_MASK (0x3 << 8) ++#define PKR_XSEL(x) ((x) << 10) ++#define PKR_XSEL_MASK (0x3 << 10) ++#define PKR_YSEL(x) ((x) << 12) ++#define PKR_YSEL_MASK (0x3 << 12) ++#define SC_MAP(x) ((x) << 16) ++#define SC_MAP_MASK (0x3 << 16) ++#define SC_XSEL(x) ((x) << 18) ++#define SC_XSEL_MASK (0x3 << 18) ++#define SC_YSEL(x) ((x) << 20) ++#define SC_YSEL_MASK (0x3 << 20) ++#define SE_MAP(x) ((x) << 24) ++#define SE_MAP_MASK (0x3 << 24) ++#define SE_XSEL(x) ((x) << 26) ++#define SE_XSEL_MASK (0x3 << 26) ++#define SE_YSEL(x) ((x) << 28) ++#define SE_YSEL_MASK (0x3 << 28) ++ ++/* mmPA_SC_RASTER_CONFIG_1 mask */ ++#define SE_PAIR_MAP(x) ((x) << 0) ++#define SE_PAIR_MAP_MASK (0x3 << 0) ++#define SE_PAIR_XSEL(x) ((x) << 2) ++#define SE_PAIR_XSEL_MASK (0x3 << 2) ++#define SE_PAIR_YSEL(x) ((x) << 4) ++#define SE_PAIR_YSEL_MASK (0x3 << 4) ++ + #endif +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1144-cache-rb-config-values.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1144-cache-rb-config-values.patch new file mode 100644 index 00000000..0c8fe273 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1144-cache-rb-config-values.patch @@ -0,0 +1,46 @@ +From 0aaf3d10e376981da3d92f037c6e36a5c4e8d348 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Tue, 6 Dec 2016 19:40:46 +0530 +Subject: [PATCH 06/10] cache rb config values +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Needed when for SR-IOV and when PG is enabled. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 20ac07f..479047e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -3671,6 +3671,21 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) + num_rb_pipes); + } + ++ /* cache the values for userspace */ ++ for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { ++ for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { ++ gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); ++ adev->gfx.config.rb_config[i][j].rb_backend_disable = ++ RREG32(mmCC_RB_BACKEND_DISABLE); ++ adev->gfx.config.rb_config[i][j].user_rb_backend_disable = ++ RREG32(mmGC_USER_RB_BACKEND_DISABLE); ++ adev->gfx.config.rb_config[i][j].raster_config = ++ RREG32(mmPA_SC_RASTER_CONFIG); ++ adev->gfx.config.rb_config[i][j].raster_config_1 = ++ RREG32(mmPA_SC_RASTER_CONFIG_1); ++ } ++ } ++ gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + } + +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1145-use-cached-raster-config-values-in-csb.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1145-use-cached-raster-config-values-in-csb.patch new file mode 100644 index 00000000..b3b19e7b --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1145-use-cached-raster-config-values-in-csb.patch @@ -0,0 +1,61 @@ +From 9fcd43d6a79011dd9ab3837d38ba27454be747ad Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Tue, 6 Dec 2016 20:14:23 +0530 +Subject: [PATCH 07/10] use cached raster config values in csb +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Simplify the code and properly set the csb for harvest values. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 30 ++---------------------------- + 1 file changed, 2 insertions(+), 28 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 479047e..dcc59f3 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -1110,34 +1110,8 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); + buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - + PACKET3_SET_CONTEXT_REG_START); +- switch (adev->asic_type) { +- case CHIP_TONGA: +- case CHIP_POLARIS10: +- buffer[count++] = cpu_to_le32(0x16000012); +- buffer[count++] = cpu_to_le32(0x0000002A); +- break; +- case CHIP_POLARIS11: +- buffer[count++] = cpu_to_le32(0x16000012); +- buffer[count++] = cpu_to_le32(0x00000000); +- break; +- case CHIP_FIJI: +- buffer[count++] = cpu_to_le32(0x3a00161a); +- buffer[count++] = cpu_to_le32(0x0000002e); +- break; +- case CHIP_TOPAZ: +- case CHIP_CARRIZO: +- buffer[count++] = cpu_to_le32(0x00000002); +- buffer[count++] = cpu_to_le32(0x00000000); +- break; +- case CHIP_STONEY: +- buffer[count++] = cpu_to_le32(0x00000000); +- buffer[count++] = cpu_to_le32(0x00000000); +- break; +- default: +- buffer[count++] = cpu_to_le32(0x00000000); +- buffer[count++] = cpu_to_le32(0x00000000); +- break; +- } ++ buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); ++ buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); + + buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); + buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1146-used-cached-gca-values-for-vi_read_register.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1146-used-cached-gca-values-for-vi_read_register.patch new file mode 100644 index 00000000..ed7262c9 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1146-used-cached-gca-values-for-vi_read_register.patch @@ -0,0 +1,166 @@ +From 2ce0f44274368b2a6640c3062eb119a0de8c1056 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Wed, 7 Dec 2016 15:07:53 +0530 +Subject: [PATCH 08/10] used cached gca values for vi_read_register +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Using the cached values has less latency for bare metal +and SR-IOV, and prevents reading back bogus values if the +engine is powergated. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vi.c | 115 +++++++++++++++++++++++++++++++++------- + 1 file changed, 96 insertions(+), 19 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c +index 02ba429..3a42e83 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vi.c ++++ b/drivers/gpu/drm/amd/amdgpu/vi.c +@@ -513,21 +513,100 @@ static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = + {mmPA_SC_RASTER_CONFIG_1, false, true}, + }; + +-static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num, +- u32 sh_num, u32 reg_offset) ++static uint32_t vi_get_register_value(struct amdgpu_device *adev, ++ bool indexed, u32 se_num, ++ u32 sh_num, u32 reg_offset) + { +- uint32_t val; ++ if (indexed) { ++ uint32_t val; ++ unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; ++ unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; ++ ++ switch (reg_offset) { ++ case mmCC_RB_BACKEND_DISABLE: ++ return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; ++ case mmGC_USER_RB_BACKEND_DISABLE: ++ return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; ++ case mmPA_SC_RASTER_CONFIG: ++ return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; ++ case mmPA_SC_RASTER_CONFIG_1: ++ return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; ++ } + +- mutex_lock(&adev->grbm_idx_mutex); +- if (se_num != 0xffffffff || sh_num != 0xffffffff) +- gfx_v8_0_select_se_sh(adev, se_num, sh_num); ++ mutex_lock(&adev->grbm_idx_mutex); ++ if (se_num != 0xffffffff || sh_num != 0xffffffff) ++ gfx_v8_0_select_se_sh(adev, se_num, sh_num); + +- val = RREG32(reg_offset); ++ val = RREG32(reg_offset); + +- if (se_num != 0xffffffff || sh_num != 0xffffffff) +- gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); +- mutex_unlock(&adev->grbm_idx_mutex); +- return val; ++ if (se_num != 0xffffffff || sh_num != 0xffffffff) ++ gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); ++ mutex_unlock(&adev->grbm_idx_mutex); ++ return val; ++ } else { ++ unsigned idx; ++ ++ switch (reg_offset) { ++ case mmGB_ADDR_CONFIG: ++ return adev->gfx.config.gb_addr_config; ++ case mmMC_ARB_RAMCFG: ++ return adev->gfx.config.mc_arb_ramcfg; ++ case mmGB_TILE_MODE0: ++ case mmGB_TILE_MODE1: ++ case mmGB_TILE_MODE2: ++ case mmGB_TILE_MODE3: ++ case mmGB_TILE_MODE4: ++ case mmGB_TILE_MODE5: ++ case mmGB_TILE_MODE6: ++ case mmGB_TILE_MODE7: ++ case mmGB_TILE_MODE8: ++ case mmGB_TILE_MODE9: ++ case mmGB_TILE_MODE10: ++ case mmGB_TILE_MODE11: ++ case mmGB_TILE_MODE12: ++ case mmGB_TILE_MODE13: ++ case mmGB_TILE_MODE14: ++ case mmGB_TILE_MODE15: ++ case mmGB_TILE_MODE16: ++ case mmGB_TILE_MODE17: ++ case mmGB_TILE_MODE18: ++ case mmGB_TILE_MODE19: ++ case mmGB_TILE_MODE20: ++ case mmGB_TILE_MODE21: ++ case mmGB_TILE_MODE22: ++ case mmGB_TILE_MODE23: ++ case mmGB_TILE_MODE24: ++ case mmGB_TILE_MODE25: ++ case mmGB_TILE_MODE26: ++ case mmGB_TILE_MODE27: ++ case mmGB_TILE_MODE28: ++ case mmGB_TILE_MODE29: ++ case mmGB_TILE_MODE30: ++ case mmGB_TILE_MODE31: ++ idx = (reg_offset - mmGB_TILE_MODE0); ++ return adev->gfx.config.tile_mode_array[idx]; ++ case mmGB_MACROTILE_MODE0: ++ case mmGB_MACROTILE_MODE1: ++ case mmGB_MACROTILE_MODE2: ++ case mmGB_MACROTILE_MODE3: ++ case mmGB_MACROTILE_MODE4: ++ case mmGB_MACROTILE_MODE5: ++ case mmGB_MACROTILE_MODE6: ++ case mmGB_MACROTILE_MODE7: ++ case mmGB_MACROTILE_MODE8: ++ case mmGB_MACROTILE_MODE9: ++ case mmGB_MACROTILE_MODE10: ++ case mmGB_MACROTILE_MODE11: ++ case mmGB_MACROTILE_MODE12: ++ case mmGB_MACROTILE_MODE13: ++ case mmGB_MACROTILE_MODE14: ++ case mmGB_MACROTILE_MODE15: ++ idx = (reg_offset - mmGB_MACROTILE_MODE0); ++ return adev->gfx.config.macrotile_mode_array[idx]; ++ default: ++ return RREG32(reg_offset); ++ } ++ } + } + + static int vi_read_register(struct amdgpu_device *adev, u32 se_num, +@@ -562,10 +641,9 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, + if (reg_offset != asic_register_entry->reg_offset) + continue; + if (!asic_register_entry->untouched) +- *value = asic_register_entry->grbm_indexed ? +- vi_read_indexed_register(adev, se_num, +- sh_num, reg_offset) : +- RREG32(reg_offset); ++ *value = vi_get_register_value(adev, ++ asic_register_entry->grbm_indexed, ++ se_num, sh_num, reg_offset); + return 0; + } + } +@@ -575,10 +653,9 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, + continue; + + if (!vi_allowed_read_registers[i].untouched) +- *value = vi_allowed_read_registers[i].grbm_indexed ? +- vi_read_indexed_register(adev, se_num, +- sh_num, reg_offset) : +- RREG32(reg_offset); ++ *value = vi_get_register_value(adev, ++ vi_allowed_read_registers[i].grbm_indexed, ++ se_num, sh_num, reg_offset); + return 0; + } + return -EINVAL; +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1147-Removed-extra-parameter.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1147-Removed-extra-parameter.patch new file mode 100644 index 00000000..3ee7aa52 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1147-Removed-extra-parameter.patch @@ -0,0 +1,26 @@ +From 7dc74a872ca0a5502f2c8e56fdfd9af97b8da1b6 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Wed, 7 Dec 2016 21:00:00 +0530 +Subject: [PATCH 09/10] Removed extra parameter + +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index dcc59f3..d1cb4db 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -3648,7 +3648,7 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) + /* cache the values for userspace */ + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { +- gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); ++ gfx_v8_0_select_se_sh(adev, i, j); + adev->gfx.config.rb_config[i][j].rb_backend_disable = + RREG32(mmCC_RB_BACKEND_DISABLE); + adev->gfx.config.rb_config[i][j].user_rb_backend_disable = +-- +2.7.4 + diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc index 9241e243..aa2b0095 100644 --- a/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc +++ b/meta-amdfalconx86/recipes-kernel/linux/files/amdfalconx86-user-patches.scc @@ -1,3 +1,39 @@ +patch 1113-enable-UVD-context-buffer-for-older-HW-MIME-Version-.patch +patch 1114-fix-default-UVD-context-size.patch +patch 1115-fix-IB-alignment-for-UVD.patch +patch 1116-fix-VCE-ib-alignment-value.patch +patch 1117-add-support-for-UVD_NO_OP-register.patch +patch 1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch +patch 1119-move-amdgpu_drm.h-to-driver-include-dir.patch +patch 1120-fix-amdgpu_drm.h-include-problem.patch +patch 1121-add-the-interface-of-waiting-multiple-fences-v2.patch +patch 1122-Fix-for-vulkan-decode-fail.patch +patch 1123-ioctl-number-modified-DRM_AMDGPU_WAIT_FENCES.patch +patch 1124-add-amdgpu.cg_mask-and-amdgpu.pg_mask-parameters.patch +patch 1125-drm-amdgpu-gfx8-disable-EDC.patch +patch 1126-ASoC-AMD-add-ACP-2.2-register-headers.patch +patch 1127-ASoC-AMD-add-AMD-ASoC-ACP-2.x-DMA-driver.patch +patch 1128-ASoC-AMD-add-pm-ops.patch +patch 1129-ASoC-AMD-Manage-ACP-2.x-SRAM-banks-power.patch +patch 1130-ASoc-AMD-Machine-driver-for-AMD-ACP-Audio-engine-usi.patch +patch 1131-drm-amd-Adding-ACP-driver-support-for-AMDGPU.patch +patch 1132-drm-amd-Power-management-related-modifications-in-th.patch +patch 1133-ASoC-dwc-add-quirk-for-different-register-offset.patch +patch 1134-ASoC-dwc-reconfigure-dwc-in-resume-from-suspend.patch +patch 1135-ASoC-dwc-add-quirk-to-override-COMP_PARAM_1-register.patch +patch 1136-ALSA-Soc-RT286Codec-Modifications-to-ALSA-SOC-Audio.patch +patch 1137-drm-amdgpu-acp-fix-resume-on-CZ-systems-with-AZ-audi.patch +patch 0001-amdgpu-fix-various-compilation-issues.patch +patch 1138-add-new-semaphore-object-in-kernel-side.patch +patch 1139-unify-memory-query-info-interface.patch +patch 1140-dma-buf-return-index-of-the-first-signaled-fence.patch +patch 1142-add-additional-cached-gca-config-variables.patch +patch 1143-implement-raster-configuration-for-gfx-v8.patch +patch 1144-cache-rb-config-values.patch +patch 1145-use-cached-raster-config-values-in-csb.patch +patch 1146-used-cached-gca-values-for-vi_read_register.patch +patch 1147-Removed-extra-parameter.patch +patch 0001-fix-hang-issue-when-enable-CONFIG_DRM_AMD_ACP.patch patch 0001-ethernet-integrate-r8168-driver.patch patch 0002-r8168-incorporate-changes-from-the-8.041.01-version.patch patch 0001-PATCH-amdgpu-get-maximum-and-used-UVD-handles.patch |