diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/1126-ASoC-AMD-add-ACP-2.2-register-headers.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/1126-ASoC-AMD-add-ACP-2.2-register-headers.patch | 4049 |
1 files changed, 4049 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1126-ASoC-AMD-add-ACP-2.2-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1126-ASoC-AMD-add-ACP-2.2-register-headers.patch new file mode 100644 index 00000000..d625d781 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1126-ASoC-AMD-add-ACP-2.2-register-headers.patch @@ -0,0 +1,4049 @@ +From dd2944623f22469b05842032d161e522c1fca725 Mon Sep 17 00:00:00 2001 +From: Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> +Date: Fri, 18 Sep 2015 13:11:22 +0530 +Subject: [PATCH 01/17] ASoC : AMD : add ACP 2.2 register headers + +These are register headers for the ACP (Audio CoProcessor) v2.2 + +Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + drivers/base/power/domain.c | 2 + + include/sound/designware_i2s.h | 6 + + sound/soc/amd/include/acp_2_2_d.h | 609 ++++++++ + sound/soc/amd/include/acp_2_2_enum.h | 1068 ++++++++++++++ + sound/soc/amd/include/acp_2_2_sh_mask.h | 2292 +++++++++++++++++++++++++++++++ + 5 files changed, 3977 insertions(+) + create mode 100644 sound/soc/amd/include/acp_2_2_d.h + create mode 100644 sound/soc/amd/include/acp_2_2_enum.h + create mode 100644 sound/soc/amd/include/acp_2_2_sh_mask.h + +diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c +index a48824d..ac913f8 100644 +--- a/drivers/base/power/domain.c ++++ b/drivers/base/power/domain.c +@@ -1263,6 +1263,7 @@ int __pm_genpd_add_device(struct generic_pm_domain *genpd, struct device *dev, + + return ret; + } ++EXPORT_SYMBOL_GPL(__pm_genpd_add_device); + + /** + * pm_genpd_remove_device - Remove a device from an I/O PM domain. +@@ -1313,6 +1314,7 @@ int pm_genpd_remove_device(struct generic_pm_domain *genpd, + + return ret; + } ++EXPORT_SYMBOL_GPL(pm_genpd_remove_device); + + /** + * pm_genpd_add_subdomain - Add a subdomain to an I/O PM domain. +diff --git a/include/sound/designware_i2s.h b/include/sound/designware_i2s.h +index 8966ba7..f919a9b 100644 +--- a/include/sound/designware_i2s.h ++++ b/include/sound/designware_i2s.h +@@ -45,6 +45,12 @@ struct i2s_platform_data { + u32 snd_fmts; + u32 snd_rates; + ++ #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0) ++ #define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1) ++ unsigned int quirks; ++ unsigned int i2s_reg_comp1; ++ unsigned int i2s_reg_comp2; ++ + void *play_dma_data; + void *capture_dma_data; + bool (*filter)(struct dma_chan *chan, void *slave); +diff --git a/sound/soc/amd/include/acp_2_2_d.h b/sound/soc/amd/include/acp_2_2_d.h +new file mode 100644 +index 0000000..0118fe9 +--- /dev/null ++++ b/sound/soc/amd/include/acp_2_2_d.h +@@ -0,0 +1,609 @@ ++/* ++ * ACP_2_2 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef ACP_2_2_D_H ++#define ACP_2_2_D_H ++ ++#define mmACP_DMA_CNTL_0 0x5000 ++#define mmACP_DMA_CNTL_1 0x5001 ++#define mmACP_DMA_CNTL_2 0x5002 ++#define mmACP_DMA_CNTL_3 0x5003 ++#define mmACP_DMA_CNTL_4 0x5004 ++#define mmACP_DMA_CNTL_5 0x5005 ++#define mmACP_DMA_CNTL_6 0x5006 ++#define mmACP_DMA_CNTL_7 0x5007 ++#define mmACP_DMA_CNTL_8 0x5008 ++#define mmACP_DMA_CNTL_9 0x5009 ++#define mmACP_DMA_CNTL_10 0x500a ++#define mmACP_DMA_CNTL_11 0x500b ++#define mmACP_DMA_CNTL_12 0x500c ++#define mmACP_DMA_CNTL_13 0x500d ++#define mmACP_DMA_CNTL_14 0x500e ++#define mmACP_DMA_CNTL_15 0x500f ++#define mmACP_DMA_DSCR_STRT_IDX_0 0x5010 ++#define mmACP_DMA_DSCR_STRT_IDX_1 0x5011 ++#define mmACP_DMA_DSCR_STRT_IDX_2 0x5012 ++#define mmACP_DMA_DSCR_STRT_IDX_3 0x5013 ++#define mmACP_DMA_DSCR_STRT_IDX_4 0x5014 ++#define mmACP_DMA_DSCR_STRT_IDX_5 0x5015 ++#define mmACP_DMA_DSCR_STRT_IDX_6 0x5016 ++#define mmACP_DMA_DSCR_STRT_IDX_7 0x5017 ++#define mmACP_DMA_DSCR_STRT_IDX_8 0x5018 ++#define mmACP_DMA_DSCR_STRT_IDX_9 0x5019 ++#define mmACP_DMA_DSCR_STRT_IDX_10 0x501a ++#define mmACP_DMA_DSCR_STRT_IDX_11 0x501b ++#define mmACP_DMA_DSCR_STRT_IDX_12 0x501c ++#define mmACP_DMA_DSCR_STRT_IDX_13 0x501d ++#define mmACP_DMA_DSCR_STRT_IDX_14 0x501e ++#define mmACP_DMA_DSCR_STRT_IDX_15 0x501f ++#define mmACP_DMA_DSCR_CNT_0 0x5020 ++#define mmACP_DMA_DSCR_CNT_1 0x5021 ++#define mmACP_DMA_DSCR_CNT_2 0x5022 ++#define mmACP_DMA_DSCR_CNT_3 0x5023 ++#define mmACP_DMA_DSCR_CNT_4 0x5024 ++#define mmACP_DMA_DSCR_CNT_5 0x5025 ++#define mmACP_DMA_DSCR_CNT_6 0x5026 ++#define mmACP_DMA_DSCR_CNT_7 0x5027 ++#define mmACP_DMA_DSCR_CNT_8 0x5028 ++#define mmACP_DMA_DSCR_CNT_9 0x5029 ++#define mmACP_DMA_DSCR_CNT_10 0x502a ++#define mmACP_DMA_DSCR_CNT_11 0x502b ++#define mmACP_DMA_DSCR_CNT_12 0x502c ++#define mmACP_DMA_DSCR_CNT_13 0x502d ++#define mmACP_DMA_DSCR_CNT_14 0x502e ++#define mmACP_DMA_DSCR_CNT_15 0x502f ++#define mmACP_DMA_PRIO_0 0x5030 ++#define mmACP_DMA_PRIO_1 0x5031 ++#define mmACP_DMA_PRIO_2 0x5032 ++#define mmACP_DMA_PRIO_3 0x5033 ++#define mmACP_DMA_PRIO_4 0x5034 ++#define mmACP_DMA_PRIO_5 0x5035 ++#define mmACP_DMA_PRIO_6 0x5036 ++#define mmACP_DMA_PRIO_7 0x5037 ++#define mmACP_DMA_PRIO_8 0x5038 ++#define mmACP_DMA_PRIO_9 0x5039 ++#define mmACP_DMA_PRIO_10 0x503a ++#define mmACP_DMA_PRIO_11 0x503b ++#define mmACP_DMA_PRIO_12 0x503c ++#define mmACP_DMA_PRIO_13 0x503d ++#define mmACP_DMA_PRIO_14 0x503e ++#define mmACP_DMA_PRIO_15 0x503f ++#define mmACP_DMA_CUR_DSCR_0 0x5040 ++#define mmACP_DMA_CUR_DSCR_1 0x5041 ++#define mmACP_DMA_CUR_DSCR_2 0x5042 ++#define mmACP_DMA_CUR_DSCR_3 0x5043 ++#define mmACP_DMA_CUR_DSCR_4 0x5044 ++#define mmACP_DMA_CUR_DSCR_5 0x5045 ++#define mmACP_DMA_CUR_DSCR_6 0x5046 ++#define mmACP_DMA_CUR_DSCR_7 0x5047 ++#define mmACP_DMA_CUR_DSCR_8 0x5048 ++#define mmACP_DMA_CUR_DSCR_9 0x5049 ++#define mmACP_DMA_CUR_DSCR_10 0x504a ++#define mmACP_DMA_CUR_DSCR_11 0x504b ++#define mmACP_DMA_CUR_DSCR_12 0x504c ++#define mmACP_DMA_CUR_DSCR_13 0x504d ++#define mmACP_DMA_CUR_DSCR_14 0x504e ++#define mmACP_DMA_CUR_DSCR_15 0x504f ++#define mmACP_DMA_CUR_TRANS_CNT_0 0x5050 ++#define mmACP_DMA_CUR_TRANS_CNT_1 0x5051 ++#define mmACP_DMA_CUR_TRANS_CNT_2 0x5052 ++#define mmACP_DMA_CUR_TRANS_CNT_3 0x5053 ++#define mmACP_DMA_CUR_TRANS_CNT_4 0x5054 ++#define mmACP_DMA_CUR_TRANS_CNT_5 0x5055 ++#define mmACP_DMA_CUR_TRANS_CNT_6 0x5056 ++#define mmACP_DMA_CUR_TRANS_CNT_7 0x5057 ++#define mmACP_DMA_CUR_TRANS_CNT_8 0x5058 ++#define mmACP_DMA_CUR_TRANS_CNT_9 0x5059 ++#define mmACP_DMA_CUR_TRANS_CNT_10 0x505a ++#define mmACP_DMA_CUR_TRANS_CNT_11 0x505b ++#define mmACP_DMA_CUR_TRANS_CNT_12 0x505c ++#define mmACP_DMA_CUR_TRANS_CNT_13 0x505d ++#define mmACP_DMA_CUR_TRANS_CNT_14 0x505e ++#define mmACP_DMA_CUR_TRANS_CNT_15 0x505f ++#define mmACP_DMA_ERR_STS_0 0x5060 ++#define mmACP_DMA_ERR_STS_1 0x5061 ++#define mmACP_DMA_ERR_STS_2 0x5062 ++#define mmACP_DMA_ERR_STS_3 0x5063 ++#define mmACP_DMA_ERR_STS_4 0x5064 ++#define mmACP_DMA_ERR_STS_5 0x5065 ++#define mmACP_DMA_ERR_STS_6 0x5066 ++#define mmACP_DMA_ERR_STS_7 0x5067 ++#define mmACP_DMA_ERR_STS_8 0x5068 ++#define mmACP_DMA_ERR_STS_9 0x5069 ++#define mmACP_DMA_ERR_STS_10 0x506a ++#define mmACP_DMA_ERR_STS_11 0x506b ++#define mmACP_DMA_ERR_STS_12 0x506c ++#define mmACP_DMA_ERR_STS_13 0x506d ++#define mmACP_DMA_ERR_STS_14 0x506e ++#define mmACP_DMA_ERR_STS_15 0x506f ++#define mmACP_DMA_DESC_BASE_ADDR 0x5070 ++#define mmACP_DMA_DESC_MAX_NUM_DSCR 0x5071 ++#define mmACP_DMA_CH_STS 0x5072 ++#define mmACP_DMA_CH_GROUP 0x5073 ++#define mmACP_DSP0_CACHE_OFFSET0 0x5078 ++#define mmACP_DSP0_CACHE_SIZE0 0x5079 ++#define mmACP_DSP0_CACHE_OFFSET1 0x507a ++#define mmACP_DSP0_CACHE_SIZE1 0x507b ++#define mmACP_DSP0_CACHE_OFFSET2 0x507c ++#define mmACP_DSP0_CACHE_SIZE2 0x507d ++#define mmACP_DSP0_CACHE_OFFSET3 0x507e ++#define mmACP_DSP0_CACHE_SIZE3 0x507f ++#define mmACP_DSP0_CACHE_OFFSET4 0x5080 ++#define mmACP_DSP0_CACHE_SIZE4 0x5081 ++#define mmACP_DSP0_CACHE_OFFSET5 0x5082 ++#define mmACP_DSP0_CACHE_SIZE5 0x5083 ++#define mmACP_DSP0_CACHE_OFFSET6 0x5084 ++#define mmACP_DSP0_CACHE_SIZE6 0x5085 ++#define mmACP_DSP0_CACHE_OFFSET7 0x5086 ++#define mmACP_DSP0_CACHE_SIZE7 0x5087 ++#define mmACP_DSP0_CACHE_OFFSET8 0x5088 ++#define mmACP_DSP0_CACHE_SIZE8 0x5089 ++#define mmACP_DSP0_NONCACHE_OFFSET0 0x508a ++#define mmACP_DSP0_NONCACHE_SIZE0 0x508b ++#define mmACP_DSP0_NONCACHE_OFFSET1 0x508c ++#define mmACP_DSP0_NONCACHE_SIZE1 0x508d ++#define mmACP_DSP0_DEBUG_PC 0x508e ++#define mmACP_DSP0_NMI_SEL 0x508f ++#define mmACP_DSP0_CLKRST_CNTL 0x5090 ++#define mmACP_DSP0_RUNSTALL 0x5091 ++#define mmACP_DSP0_OCD_HALT_ON_RST 0x5092 ++#define mmACP_DSP0_WAIT_MODE 0x5093 ++#define mmACP_DSP0_VECT_SEL 0x5094 ++#define mmACP_DSP0_DEBUG_REG1 0x5095 ++#define mmACP_DSP0_DEBUG_REG2 0x5096 ++#define mmACP_DSP0_DEBUG_REG3 0x5097 ++#define mmACP_DSP1_CACHE_OFFSET0 0x509d ++#define mmACP_DSP1_CACHE_SIZE0 0x509e ++#define mmACP_DSP1_CACHE_OFFSET1 0x509f ++#define mmACP_DSP1_CACHE_SIZE1 0x50a0 ++#define mmACP_DSP1_CACHE_OFFSET2 0x50a1 ++#define mmACP_DSP1_CACHE_SIZE2 0x50a2 ++#define mmACP_DSP1_CACHE_OFFSET3 0x50a3 ++#define mmACP_DSP1_CACHE_SIZE3 0x50a4 ++#define mmACP_DSP1_CACHE_OFFSET4 0x50a5 ++#define mmACP_DSP1_CACHE_SIZE4 0x50a6 ++#define mmACP_DSP1_CACHE_OFFSET5 0x50a7 ++#define mmACP_DSP1_CACHE_SIZE5 0x50a8 ++#define mmACP_DSP1_CACHE_OFFSET6 0x50a9 ++#define mmACP_DSP1_CACHE_SIZE6 0x50aa ++#define mmACP_DSP1_CACHE_OFFSET7 0x50ab ++#define mmACP_DSP1_CACHE_SIZE7 0x50ac ++#define mmACP_DSP1_CACHE_OFFSET8 0x50ad ++#define mmACP_DSP1_CACHE_SIZE8 0x50ae ++#define mmACP_DSP1_NONCACHE_OFFSET0 0x50af ++#define mmACP_DSP1_NONCACHE_SIZE0 0x50b0 ++#define mmACP_DSP1_NONCACHE_OFFSET1 0x50b1 ++#define mmACP_DSP1_NONCACHE_SIZE1 0x50b2 ++#define mmACP_DSP1_DEBUG_PC 0x50b3 ++#define mmACP_DSP1_NMI_SEL 0x50b4 ++#define mmACP_DSP1_CLKRST_CNTL 0x50b5 ++#define mmACP_DSP1_RUNSTALL 0x50b6 ++#define mmACP_DSP1_OCD_HALT_ON_RST 0x50b7 ++#define mmACP_DSP1_WAIT_MODE 0x50b8 ++#define mmACP_DSP1_VECT_SEL 0x50b9 ++#define mmACP_DSP1_DEBUG_REG1 0x50ba ++#define mmACP_DSP1_DEBUG_REG2 0x50bb ++#define mmACP_DSP1_DEBUG_REG3 0x50bc ++#define mmACP_DSP2_CACHE_OFFSET0 0x50c2 ++#define mmACP_DSP2_CACHE_SIZE0 0x50c3 ++#define mmACP_DSP2_CACHE_OFFSET1 0x50c4 ++#define mmACP_DSP2_CACHE_SIZE1 0x50c5 ++#define mmACP_DSP2_CACHE_OFFSET2 0x50c6 ++#define mmACP_DSP2_CACHE_SIZE2 0x50c7 ++#define mmACP_DSP2_CACHE_OFFSET3 0x50c8 ++#define mmACP_DSP2_CACHE_SIZE3 0x50c9 ++#define mmACP_DSP2_CACHE_OFFSET4 0x50ca ++#define mmACP_DSP2_CACHE_SIZE4 0x50cb ++#define mmACP_DSP2_CACHE_OFFSET5 0x50cc ++#define mmACP_DSP2_CACHE_SIZE5 0x50cd ++#define mmACP_DSP2_CACHE_OFFSET6 0x50ce ++#define mmACP_DSP2_CACHE_SIZE6 0x50cf ++#define mmACP_DSP2_CACHE_OFFSET7 0x50d0 ++#define mmACP_DSP2_CACHE_SIZE7 0x50d1 ++#define mmACP_DSP2_CACHE_OFFSET8 0x50d2 ++#define mmACP_DSP2_CACHE_SIZE8 0x50d3 ++#define mmACP_DSP2_NONCACHE_OFFSET0 0x50d4 ++#define mmACP_DSP2_NONCACHE_SIZE0 0x50d5 ++#define mmACP_DSP2_NONCACHE_OFFSET1 0x50d6 ++#define mmACP_DSP2_NONCACHE_SIZE1 0x50d7 ++#define mmACP_DSP2_DEBUG_PC 0x50d8 ++#define mmACP_DSP2_NMI_SEL 0x50d9 ++#define mmACP_DSP2_CLKRST_CNTL 0x50da ++#define mmACP_DSP2_RUNSTALL 0x50db ++#define mmACP_DSP2_OCD_HALT_ON_RST 0x50dc ++#define mmACP_DSP2_WAIT_MODE 0x50dd ++#define mmACP_DSP2_VECT_SEL 0x50de ++#define mmACP_DSP2_DEBUG_REG1 0x50df ++#define mmACP_DSP2_DEBUG_REG2 0x50e0 ++#define mmACP_DSP2_DEBUG_REG3 0x50e1 ++#define mmACP_AXI2DAGB_ONION_CNTL 0x50e7 ++#define mmACP_AXI2DAGB_ONION_ERR_STATUS_WR 0x50e8 ++#define mmACP_AXI2DAGB_ONION_ERR_STATUS_RD 0x50e9 ++#define mmACP_DAGB_Onion_TransPerf_Counter_Control 0x50ea ++#define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Current 0x50eb ++#define mmACP_DAGB_Onion_Wr_TransPerf_Counter_Peak 0x50ec ++#define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Current 0x50ed ++#define mmACP_DAGB_Onion_Rd_TransPerf_Counter_Peak 0x50ee ++#define mmACP_AXI2DAGB_GARLIC_CNTL 0x50f3 ++#define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_WR 0x50f4 ++#define mmACP_AXI2DAGB_GARLIC_ERR_STATUS_RD 0x50f5 ++#define mmACP_DAGB_Garlic_TransPerf_Counter_Control 0x50f6 ++#define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Current 0x50f7 ++#define mmACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak 0x50f8 ++#define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Current 0x50f9 ++#define mmACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak 0x50fa ++#define mmACP_DAGB_PAGE_SIZE_GRP_1 0x50ff ++#define mmACP_DAGB_BASE_ADDR_GRP_1 0x5100 ++#define mmACP_DAGB_PAGE_SIZE_GRP_2 0x5101 ++#define mmACP_DAGB_BASE_ADDR_GRP_2 0x5102 ++#define mmACP_DAGB_PAGE_SIZE_GRP_3 0x5103 ++#define mmACP_DAGB_BASE_ADDR_GRP_3 0x5104 ++#define mmACP_DAGB_PAGE_SIZE_GRP_4 0x5105 ++#define mmACP_DAGB_BASE_ADDR_GRP_4 0x5106 ++#define mmACP_DAGB_PAGE_SIZE_GRP_5 0x5107 ++#define mmACP_DAGB_BASE_ADDR_GRP_5 0x5108 ++#define mmACP_DAGB_PAGE_SIZE_GRP_6 0x5109 ++#define mmACP_DAGB_BASE_ADDR_GRP_6 0x510a ++#define mmACP_DAGB_PAGE_SIZE_GRP_7 0x510b ++#define mmACP_DAGB_BASE_ADDR_GRP_7 0x510c ++#define mmACP_DAGB_PAGE_SIZE_GRP_8 0x510d ++#define mmACP_DAGB_BASE_ADDR_GRP_8 0x510e ++#define mmACP_DAGB_ATU_CTRL 0x510f ++#define mmACP_CONTROL 0x5131 ++#define mmACP_STATUS 0x5133 ++#define mmACP_SOFT_RESET 0x5134 ++#define mmACP_PwrMgmt_CNTL 0x5135 ++#define mmACP_CAC_INDICATOR_CONTROL 0x5136 ++#define mmACP_SMU_MAILBOX 0x5137 ++#define mmACP_FUTURE_REG_SCLK_0 0x5138 ++#define mmACP_FUTURE_REG_SCLK_1 0x5139 ++#define mmACP_FUTURE_REG_SCLK_2 0x513a ++#define mmACP_FUTURE_REG_SCLK_3 0x513b ++#define mmACP_FUTURE_REG_SCLK_4 0x513c ++#define mmACP_DAGB_DEBUG_CNT_ENABLE 0x513d ++#define mmACP_DAGBG_WR_ASK_CNT 0x513e ++#define mmACP_DAGBG_WR_GO_CNT 0x513f ++#define mmACP_DAGBG_WR_EXP_RESP_CNT 0x5140 ++#define mmACP_DAGBG_WR_ACTUAL_RESP_CNT 0x5141 ++#define mmACP_DAGBG_RD_ASK_CNT 0x5142 ++#define mmACP_DAGBG_RD_GO_CNT 0x5143 ++#define mmACP_DAGBG_RD_EXP_RESP_CNT 0x5144 ++#define mmACP_DAGBG_RD_ACTUAL_RESP_CNT 0x5145 ++#define mmACP_DAGBO_WR_ASK_CNT 0x5146 ++#define mmACP_DAGBO_WR_GO_CNT 0x5147 ++#define mmACP_DAGBO_WR_EXP_RESP_CNT 0x5148 ++#define mmACP_DAGBO_WR_ACTUAL_RESP_CNT 0x5149 ++#define mmACP_DAGBO_RD_ASK_CNT 0x514a ++#define mmACP_DAGBO_RD_GO_CNT 0x514b ++#define mmACP_DAGBO_RD_EXP_RESP_CNT 0x514c ++#define mmACP_DAGBO_RD_ACTUAL_RESP_CNT 0x514d ++#define mmACP_BRB_CONTROL 0x5156 ++#define mmACP_EXTERNAL_INTR_ENB 0x5157 ++#define mmACP_EXTERNAL_INTR_CNTL 0x5158 ++#define mmACP_ERROR_SOURCE_STS 0x5159 ++#define mmACP_DSP_SW_INTR_TRIG 0x515a ++#define mmACP_DSP_SW_INTR_CNTL 0x515b ++#define mmACP_DAGBG_TIMEOUT_CNTL 0x515c ++#define mmACP_DAGBO_TIMEOUT_CNTL 0x515d ++#define mmACP_EXTERNAL_INTR_STAT 0x515e ++#define mmACP_DSP_SW_INTR_STAT 0x515f ++#define mmACP_DSP0_INTR_CNTL 0x5160 ++#define mmACP_DSP0_INTR_STAT 0x5161 ++#define mmACP_DSP0_TIMEOUT_CNTL 0x5162 ++#define mmACP_DSP1_INTR_CNTL 0x5163 ++#define mmACP_DSP1_INTR_STAT 0x5164 ++#define mmACP_DSP1_TIMEOUT_CNTL 0x5165 ++#define mmACP_DSP2_INTR_CNTL 0x5166 ++#define mmACP_DSP2_INTR_STAT 0x5167 ++#define mmACP_DSP2_TIMEOUT_CNTL 0x5168 ++#define mmACP_DSP0_EXT_TIMER_CNTL 0x5169 ++#define mmACP_DSP1_EXT_TIMER_CNTL 0x516a ++#define mmACP_DSP2_EXT_TIMER_CNTL 0x516b ++#define mmACP_AXI2DAGB_SEM_0 0x516c ++#define mmACP_AXI2DAGB_SEM_1 0x516d ++#define mmACP_AXI2DAGB_SEM_2 0x516e ++#define mmACP_AXI2DAGB_SEM_3 0x516f ++#define mmACP_AXI2DAGB_SEM_4 0x5170 ++#define mmACP_AXI2DAGB_SEM_5 0x5171 ++#define mmACP_AXI2DAGB_SEM_6 0x5172 ++#define mmACP_AXI2DAGB_SEM_7 0x5173 ++#define mmACP_AXI2DAGB_SEM_8 0x5174 ++#define mmACP_AXI2DAGB_SEM_9 0x5175 ++#define mmACP_AXI2DAGB_SEM_10 0x5176 ++#define mmACP_AXI2DAGB_SEM_11 0x5177 ++#define mmACP_AXI2DAGB_SEM_12 0x5178 ++#define mmACP_AXI2DAGB_SEM_13 0x5179 ++#define mmACP_AXI2DAGB_SEM_14 0x517a ++#define mmACP_AXI2DAGB_SEM_15 0x517b ++#define mmACP_AXI2DAGB_SEM_16 0x517c ++#define mmACP_AXI2DAGB_SEM_17 0x517d ++#define mmACP_AXI2DAGB_SEM_18 0x517e ++#define mmACP_AXI2DAGB_SEM_19 0x517f ++#define mmACP_AXI2DAGB_SEM_20 0x5180 ++#define mmACP_AXI2DAGB_SEM_21 0x5181 ++#define mmACP_AXI2DAGB_SEM_22 0x5182 ++#define mmACP_AXI2DAGB_SEM_23 0x5183 ++#define mmACP_AXI2DAGB_SEM_24 0x5184 ++#define mmACP_AXI2DAGB_SEM_25 0x5185 ++#define mmACP_AXI2DAGB_SEM_26 0x5186 ++#define mmACP_AXI2DAGB_SEM_27 0x5187 ++#define mmACP_AXI2DAGB_SEM_28 0x5188 ++#define mmACP_AXI2DAGB_SEM_29 0x5189 ++#define mmACP_AXI2DAGB_SEM_30 0x518a ++#define mmACP_AXI2DAGB_SEM_31 0x518b ++#define mmACP_AXI2DAGB_SEM_32 0x518c ++#define mmACP_AXI2DAGB_SEM_33 0x518d ++#define mmACP_AXI2DAGB_SEM_34 0x518e ++#define mmACP_AXI2DAGB_SEM_35 0x518f ++#define mmACP_AXI2DAGB_SEM_36 0x5190 ++#define mmACP_AXI2DAGB_SEM_37 0x5191 ++#define mmACP_AXI2DAGB_SEM_38 0x5192 ++#define mmACP_AXI2DAGB_SEM_39 0x5193 ++#define mmACP_AXI2DAGB_SEM_40 0x5194 ++#define mmACP_AXI2DAGB_SEM_41 0x5195 ++#define mmACP_AXI2DAGB_SEM_42 0x5196 ++#define mmACP_AXI2DAGB_SEM_43 0x5197 ++#define mmACP_AXI2DAGB_SEM_44 0x5198 ++#define mmACP_AXI2DAGB_SEM_45 0x5199 ++#define mmACP_AXI2DAGB_SEM_46 0x519a ++#define mmACP_AXI2DAGB_SEM_47 0x519b ++#define mmACP_SRBM_Client_Base_Addr 0x519c ++#define mmACP_SRBM_Client_RDDATA 0x519d ++#define mmACP_SRBM_Cycle_Sts 0x519e ++#define mmACP_SRBM_Targ_Idx_Addr 0x519f ++#define mmACP_SRBM_Targ_Idx_Data 0x51a0 ++#define mmACP_SEMA_ADDR_LOW 0x51a1 ++#define mmACP_SEMA_ADDR_HIGH 0x51a2 ++#define mmACP_SEMA_CMD 0x51a3 ++#define mmACP_SEMA_STS 0x51a4 ++#define mmACP_SEMA_REQ 0x51a5 ++#define mmACP_FW_STATUS 0x51a6 ++#define mmACP_FUTURE_REG_ACLK_0 0x51a7 ++#define mmACP_FUTURE_REG_ACLK_1 0x51a8 ++#define mmACP_FUTURE_REG_ACLK_2 0x51a9 ++#define mmACP_FUTURE_REG_ACLK_3 0x51aa ++#define mmACP_FUTURE_REG_ACLK_4 0x51ab ++#define mmACP_TIMER 0x51ac ++#define mmACP_TIMER_CNTL 0x51ad ++#define mmACP_DSP0_TIMER 0x51ae ++#define mmACP_DSP1_TIMER 0x51af ++#define mmACP_DSP2_TIMER 0x51b0 ++#define mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH 0x51b1 ++#define mmACP_I2S_TRANSMIT_BYTE_CNT_LOW 0x51b2 ++#define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH 0x51b3 ++#define mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW 0x51b4 ++#define mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH 0x51b5 ++#define mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW 0x51b6 ++#define mmACP_DSP0_CS_STATE 0x51b7 ++#define mmACP_DSP1_CS_STATE 0x51b8 ++#define mmACP_DSP2_CS_STATE 0x51b9 ++#define mmACP_SCRATCH_REG_BASE_ADDR 0x51ba ++#define mmCC_ACP_EFUSE 0x51c8 ++#define mmACP_PGFSM_RETAIN_REG 0x51c9 ++#define mmACP_PGFSM_CONFIG_REG 0x51ca ++#define mmACP_PGFSM_WRITE_REG 0x51cb ++#define mmACP_PGFSM_READ_REG_0 0x51cc ++#define mmACP_PGFSM_READ_REG_1 0x51cd ++#define mmACP_PGFSM_READ_REG_2 0x51ce ++#define mmACP_PGFSM_READ_REG_3 0x51cf ++#define mmACP_PGFSM_READ_REG_4 0x51d0 ++#define mmACP_PGFSM_READ_REG_5 0x51d1 ++#define mmACP_IP_PGFSM_ENABLE 0x51d2 ++#define mmACP_I2S_PIN_CONFIG 0x51d3 ++#define mmACP_AZALIA_I2S_SELECT 0x51d4 ++#define mmACP_CHIP_PKG_FOR_PAD_ISOLATION 0x51d5 ++#define mmACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL 0x51d6 ++#define mmACP_BT_UART_PAD_SEL 0x51d7 ++#define mmACP_SCRATCH_REG_0 0x52c0 ++#define mmACP_SCRATCH_REG_1 0x52c1 ++#define mmACP_SCRATCH_REG_2 0x52c2 ++#define mmACP_SCRATCH_REG_3 0x52c3 ++#define mmACP_SCRATCH_REG_4 0x52c4 ++#define mmACP_SCRATCH_REG_5 0x52c5 ++#define mmACP_SCRATCH_REG_6 0x52c6 ++#define mmACP_SCRATCH_REG_7 0x52c7 ++#define mmACP_SCRATCH_REG_8 0x52c8 ++#define mmACP_SCRATCH_REG_9 0x52c9 ++#define mmACP_SCRATCH_REG_10 0x52ca ++#define mmACP_SCRATCH_REG_11 0x52cb ++#define mmACP_SCRATCH_REG_12 0x52cc ++#define mmACP_SCRATCH_REG_13 0x52cd ++#define mmACP_SCRATCH_REG_14 0x52ce ++#define mmACP_SCRATCH_REG_15 0x52cf ++#define mmACP_SCRATCH_REG_16 0x52d0 ++#define mmACP_SCRATCH_REG_17 0x52d1 ++#define mmACP_SCRATCH_REG_18 0x52d2 ++#define mmACP_SCRATCH_REG_19 0x52d3 ++#define mmACP_SCRATCH_REG_20 0x52d4 ++#define mmACP_SCRATCH_REG_21 0x52d5 ++#define mmACP_SCRATCH_REG_22 0x52d6 ++#define mmACP_SCRATCH_REG_23 0x52d7 ++#define mmACP_SCRATCH_REG_24 0x52d8 ++#define mmACP_SCRATCH_REG_25 0x52d9 ++#define mmACP_SCRATCH_REG_26 0x52da ++#define mmACP_SCRATCH_REG_27 0x52db ++#define mmACP_SCRATCH_REG_28 0x52dc ++#define mmACP_SCRATCH_REG_29 0x52dd ++#define mmACP_SCRATCH_REG_30 0x52de ++#define mmACP_SCRATCH_REG_31 0x52df ++#define mmACP_SCRATCH_REG_32 0x52e0 ++#define mmACP_SCRATCH_REG_33 0x52e1 ++#define mmACP_SCRATCH_REG_34 0x52e2 ++#define mmACP_SCRATCH_REG_35 0x52e3 ++#define mmACP_SCRATCH_REG_36 0x52e4 ++#define mmACP_SCRATCH_REG_37 0x52e5 ++#define mmACP_SCRATCH_REG_38 0x52e6 ++#define mmACP_SCRATCH_REG_39 0x52e7 ++#define mmACP_SCRATCH_REG_40 0x52e8 ++#define mmACP_SCRATCH_REG_41 0x52e9 ++#define mmACP_SCRATCH_REG_42 0x52ea ++#define mmACP_SCRATCH_REG_43 0x52eb ++#define mmACP_SCRATCH_REG_44 0x52ec ++#define mmACP_SCRATCH_REG_45 0x52ed ++#define mmACP_SCRATCH_REG_46 0x52ee ++#define mmACP_SCRATCH_REG_47 0x52ef ++#define mmACP_VOICE_WAKEUP_ENABLE 0x51e8 ++#define mmACP_VOICE_WAKEUP_STATUS 0x51e9 ++#define mmI2S_VOICE_WAKEUP_LOWER_THRESHOLD 0x51ea ++#define mmI2S_VOICE_WAKEUP_HIGHER_THRESHOLD 0x51eb ++#define mmI2S_VOICE_WAKEUP_NO_OF_SAMPLES 0x51ec ++#define mmI2S_VOICE_WAKEUP_NO_OF_PEAKS 0x51ed ++#define mmI2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS 0x51ee ++#define mmI2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION 0x51ef ++#define mmI2S_VOICE_WAKEUP_DATA_PATH_SWITCH 0x51f0 ++#define mmI2S_VOICE_WAKEUP_DATA_POINTER 0x51f1 ++#define mmI2S_VOICE_WAKEUP_AUTH_MATCH 0x51f2 ++#define mmI2S_VOICE_WAKEUP_8KB_WRAP 0x51f3 ++#define mmACP_I2S_RECEIVED_BYTE_CNT_HIGH 0x51f4 ++#define mmACP_I2S_RECEIVED_BYTE_CNT_LOW 0x51f5 ++#define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH 0x51f6 ++#define mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW 0x51f7 ++#define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8 ++#define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9 ++#define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa ++#define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb ++#define mmACP_MEM_DEEP_SLEEP_REQ_LO 0x51fc ++#define mmACP_MEM_DEEP_SLEEP_REQ_HI 0x51fd ++#define mmACP_MEM_DEEP_SLEEP_STS_LO 0x51fe ++#define mmACP_MEM_DEEP_SLEEP_STS_HI 0x51ff ++#define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO 0x5200 ++#define mmACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI 0x5201 ++#define mmACP_MEM_WAKEUP_FROM_SLEEP_LO 0x5202 ++#define mmACP_MEM_WAKEUP_FROM_SLEEP_HI 0x5203 ++#define mmACP_I2SSP_IER 0x5210 ++#define mmACP_I2SSP_IRER 0x5211 ++#define mmACP_I2SSP_ITER 0x5212 ++#define mmACP_I2SSP_CER 0x5213 ++#define mmACP_I2SSP_CCR 0x5214 ++#define mmACP_I2SSP_RXFFR 0x5215 ++#define mmACP_I2SSP_TXFFR 0x5216 ++#define mmACP_I2SSP_LRBR0 0x5218 ++#define mmACP_I2SSP_RRBR0 0x5219 ++#define mmACP_I2SSP_RER0 0x521a ++#define mmACP_I2SSP_TER0 0x521b ++#define mmACP_I2SSP_RCR0 0x521c ++#define mmACP_I2SSP_TCR0 0x521d ++#define mmACP_I2SSP_ISR0 0x521e ++#define mmACP_I2SSP_IMR0 0x521f ++#define mmACP_I2SSP_ROR0 0x5220 ++#define mmACP_I2SSP_TOR0 0x5221 ++#define mmACP_I2SSP_RFCR0 0x5222 ++#define mmACP_I2SSP_TFCR0 0x5223 ++#define mmACP_I2SSP_RFF0 0x5224 ++#define mmACP_I2SSP_TFF0 0x5225 ++#define mmACP_I2SSP_RXDMA 0x5226 ++#define mmACP_I2SSP_RRXDMA 0x5227 ++#define mmACP_I2SSP_TXDMA 0x5228 ++#define mmACP_I2SSP_RTXDMA 0x5229 ++#define mmACP_I2SSP_COMP_PARAM_2 0x522a ++#define mmACP_I2SSP_COMP_PARAM_1 0x522b ++#define mmACP_I2SSP_COMP_VERSION 0x522c ++#define mmACP_I2SSP_COMP_TYPE 0x522d ++#define mmACP_I2SMICSP_IER 0x522e ++#define mmACP_I2SMICSP_IRER 0x522f ++#define mmACP_I2SMICSP_ITER 0x5230 ++#define mmACP_I2SMICSP_CER 0x5231 ++#define mmACP_I2SMICSP_CCR 0x5232 ++#define mmACP_I2SMICSP_RXFFR 0x5233 ++#define mmACP_I2SMICSP_TXFFR 0x5234 ++#define mmACP_I2SMICSP_LRBR0 0x5236 ++#define mmACP_I2SMICSP_RRBR0 0x5237 ++#define mmACP_I2SMICSP_RER0 0x5238 ++#define mmACP_I2SMICSP_TER0 0x5239 ++#define mmACP_I2SMICSP_RCR0 0x523a ++#define mmACP_I2SMICSP_TCR0 0x523b ++#define mmACP_I2SMICSP_ISR0 0x523c ++#define mmACP_I2SMICSP_IMR0 0x523d ++#define mmACP_I2SMICSP_ROR0 0x523e ++#define mmACP_I2SMICSP_TOR0 0x523f ++#define mmACP_I2SMICSP_RFCR0 0x5240 ++#define mmACP_I2SMICSP_TFCR0 0x5241 ++#define mmACP_I2SMICSP_RFF0 0x5242 ++#define mmACP_I2SMICSP_TFF0 0x5243 ++#define mmACP_I2SMICSP_LRBR1 0x5246 ++#define mmACP_I2SMICSP_RRBR1 0x5247 ++#define mmACP_I2SMICSP_RER1 0x5248 ++#define mmACP_I2SMICSP_TER1 0x5249 ++#define mmACP_I2SMICSP_RCR1 0x524a ++#define mmACP_I2SMICSP_TCR1 0x524b ++#define mmACP_I2SMICSP_ISR1 0x524c ++#define mmACP_I2SMICSP_IMR1 0x524d ++#define mmACP_I2SMICSP_ROR1 0x524e ++#define mmACP_I2SMICSP_TOR1 0x524f ++#define mmACP_I2SMICSP_RFCR1 0x5250 ++#define mmACP_I2SMICSP_TFCR1 0x5251 ++#define mmACP_I2SMICSP_RFF1 0x5252 ++#define mmACP_I2SMICSP_TFF1 0x5253 ++#define mmACP_I2SMICSP_RXDMA 0x5254 ++#define mmACP_I2SMICSP_RRXDMA 0x5255 ++#define mmACP_I2SMICSP_TXDMA 0x5256 ++#define mmACP_I2SMICSP_RTXDMA 0x5257 ++#define mmACP_I2SMICSP_COMP_PARAM_2 0x5258 ++#define mmACP_I2SMICSP_COMP_PARAM_1 0x5259 ++#define mmACP_I2SMICSP_COMP_VERSION 0x525a ++#define mmACP_I2SMICSP_COMP_TYPE 0x525b ++#define mmACP_I2SBT_IER 0x525c ++#define mmACP_I2SBT_IRER 0x525d ++#define mmACP_I2SBT_ITER 0x525e ++#define mmACP_I2SBT_CER 0x525f ++#define mmACP_I2SBT_CCR 0x5260 ++#define mmACP_I2SBT_RXFFR 0x5261 ++#define mmACP_I2SBT_TXFFR 0x5262 ++#define mmACP_I2SBT_LRBR0 0x5264 ++#define mmACP_I2SBT_RRBR0 0x5265 ++#define mmACP_I2SBT_RER0 0x5266 ++#define mmACP_I2SBT_TER0 0x5267 ++#define mmACP_I2SBT_RCR0 0x5268 ++#define mmACP_I2SBT_TCR0 0x5269 ++#define mmACP_I2SBT_ISR0 0x526a ++#define mmACP_I2SBT_IMR0 0x526b ++#define mmACP_I2SBT_ROR0 0x526c ++#define mmACP_I2SBT_TOR0 0x526d ++#define mmACP_I2SBT_RFCR0 0x526e ++#define mmACP_I2SBT_TFCR0 0x526f ++#define mmACP_I2SBT_RFF0 0x5270 ++#define mmACP_I2SBT_TFF0 0x5271 ++#define mmACP_I2SBT_LRBR1 0x5274 ++#define mmACP_I2SBT_RRBR1 0x5275 ++#define mmACP_I2SBT_RER1 0x5276 ++#define mmACP_I2SBT_TER1 0x5277 ++#define mmACP_I2SBT_RCR1 0x5278 ++#define mmACP_I2SBT_TCR1 0x5279 ++#define mmACP_I2SBT_ISR1 0x527a ++#define mmACP_I2SBT_IMR1 0x527b ++#define mmACP_I2SBT_ROR1 0x527c ++#define mmACP_I2SBT_TOR1 0x527d ++#define mmACP_I2SBT_RFCR1 0x527e ++#define mmACP_I2SBT_TFCR1 0x527f ++#define mmACP_I2SBT_RFF1 0x5280 ++#define mmACP_I2SBT_TFF1 0x5281 ++#define mmACP_I2SBT_RXDMA 0x5282 ++#define mmACP_I2SBT_RRXDMA 0x5283 ++#define mmACP_I2SBT_TXDMA 0x5284 ++#define mmACP_I2SBT_RTXDMA 0x5285 ++#define mmACP_I2SBT_COMP_PARAM_2 0x5286 ++#define mmACP_I2SBT_COMP_PARAM_1 0x5287 ++#define mmACP_I2SBT_COMP_VERSION 0x5288 ++#define mmACP_I2SBT_COMP_TYPE 0x5289 ++ ++#endif /* ACP_2_2_D_H */ +diff --git a/sound/soc/amd/include/acp_2_2_enum.h b/sound/soc/amd/include/acp_2_2_enum.h +new file mode 100644 +index 0000000..f3577c8 +--- /dev/null ++++ b/sound/soc/amd/include/acp_2_2_enum.h +@@ -0,0 +1,1068 @@ ++/* ++ * ACP_2_2 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef ACP_2_2_ENUM_H ++#define ACP_2_2_ENUM_H ++ ++typedef enum DebugBlockId { ++ DBG_BLOCK_ID_RESERVED = 0x0, ++ DBG_BLOCK_ID_DBG = 0x1, ++ DBG_BLOCK_ID_VMC = 0x2, ++ DBG_BLOCK_ID_PDMA = 0x3, ++ DBG_BLOCK_ID_CG = 0x4, ++ DBG_BLOCK_ID_SRBM = 0x5, ++ DBG_BLOCK_ID_GRBM = 0x6, ++ DBG_BLOCK_ID_RLC = 0x7, ++ DBG_BLOCK_ID_CSC = 0x8, ++ DBG_BLOCK_ID_SEM = 0x9, ++ DBG_BLOCK_ID_IH = 0xa, ++ DBG_BLOCK_ID_SC = 0xb, ++ DBG_BLOCK_ID_SQ = 0xc, ++ DBG_BLOCK_ID_UVDU = 0xd, ++ DBG_BLOCK_ID_SQA = 0xe, ++ DBG_BLOCK_ID_SDMA0 = 0xf, ++ DBG_BLOCK_ID_SDMA1 = 0x10, ++ DBG_BLOCK_ID_SPIM = 0x11, ++ DBG_BLOCK_ID_GDS = 0x12, ++ DBG_BLOCK_ID_VC0 = 0x13, ++ DBG_BLOCK_ID_VC1 = 0x14, ++ DBG_BLOCK_ID_PA0 = 0x15, ++ DBG_BLOCK_ID_PA1 = 0x16, ++ DBG_BLOCK_ID_CP0 = 0x17, ++ DBG_BLOCK_ID_CP1 = 0x18, ++ DBG_BLOCK_ID_CP2 = 0x19, ++ DBG_BLOCK_ID_XBR = 0x1a, ++ DBG_BLOCK_ID_UVDM = 0x1b, ++ DBG_BLOCK_ID_VGT0 = 0x1c, ++ DBG_BLOCK_ID_VGT1 = 0x1d, ++ DBG_BLOCK_ID_IA = 0x1e, ++ DBG_BLOCK_ID_SXM0 = 0x1f, ++ DBG_BLOCK_ID_SXM1 = 0x20, ++ DBG_BLOCK_ID_SCT0 = 0x21, ++ DBG_BLOCK_ID_SCT1 = 0x22, ++ DBG_BLOCK_ID_SPM0 = 0x23, ++ DBG_BLOCK_ID_SPM1 = 0x24, ++ DBG_BLOCK_ID_UNUSED0 = 0x25, ++ DBG_BLOCK_ID_UNUSED1 = 0x26, ++ DBG_BLOCK_ID_TCAA = 0x27, ++ DBG_BLOCK_ID_TCAB = 0x28, ++ DBG_BLOCK_ID_TCCA = 0x29, ++ DBG_BLOCK_ID_TCCB = 0x2a, ++ DBG_BLOCK_ID_MCC0 = 0x2b, ++ DBG_BLOCK_ID_MCC1 = 0x2c, ++ DBG_BLOCK_ID_MCC2 = 0x2d, ++ DBG_BLOCK_ID_MCC3 = 0x2e, ++ DBG_BLOCK_ID_SXS0 = 0x2f, ++ DBG_BLOCK_ID_SXS1 = 0x30, ++ DBG_BLOCK_ID_SXS2 = 0x31, ++ DBG_BLOCK_ID_SXS3 = 0x32, ++ DBG_BLOCK_ID_SXS4 = 0x33, ++ DBG_BLOCK_ID_SXS5 = 0x34, ++ DBG_BLOCK_ID_SXS6 = 0x35, ++ DBG_BLOCK_ID_SXS7 = 0x36, ++ DBG_BLOCK_ID_SXS8 = 0x37, ++ DBG_BLOCK_ID_SXS9 = 0x38, ++ DBG_BLOCK_ID_BCI0 = 0x39, ++ DBG_BLOCK_ID_BCI1 = 0x3a, ++ DBG_BLOCK_ID_BCI2 = 0x3b, ++ DBG_BLOCK_ID_BCI3 = 0x3c, ++ DBG_BLOCK_ID_MCB = 0x3d, ++ DBG_BLOCK_ID_UNUSED6 = 0x3e, ++ DBG_BLOCK_ID_SQA00 = 0x3f, ++ DBG_BLOCK_ID_SQA01 = 0x40, ++ DBG_BLOCK_ID_SQA02 = 0x41, ++ DBG_BLOCK_ID_SQA10 = 0x42, ++ DBG_BLOCK_ID_SQA11 = 0x43, ++ DBG_BLOCK_ID_SQA12 = 0x44, ++ DBG_BLOCK_ID_UNUSED7 = 0x45, ++ DBG_BLOCK_ID_UNUSED8 = 0x46, ++ DBG_BLOCK_ID_SQB00 = 0x47, ++ DBG_BLOCK_ID_SQB01 = 0x48, ++ DBG_BLOCK_ID_SQB10 = 0x49, ++ DBG_BLOCK_ID_SQB11 = 0x4a, ++ DBG_BLOCK_ID_SQ00 = 0x4b, ++ DBG_BLOCK_ID_SQ01 = 0x4c, ++ DBG_BLOCK_ID_SQ10 = 0x4d, ++ DBG_BLOCK_ID_SQ11 = 0x4e, ++ DBG_BLOCK_ID_CB00 = 0x4f, ++ DBG_BLOCK_ID_CB01 = 0x50, ++ DBG_BLOCK_ID_CB02 = 0x51, ++ DBG_BLOCK_ID_CB03 = 0x52, ++ DBG_BLOCK_ID_CB04 = 0x53, ++ DBG_BLOCK_ID_UNUSED9 = 0x54, ++ DBG_BLOCK_ID_UNUSED10 = 0x55, ++ DBG_BLOCK_ID_UNUSED11 = 0x56, ++ DBG_BLOCK_ID_CB10 = 0x57, ++ DBG_BLOCK_ID_CB11 = 0x58, ++ DBG_BLOCK_ID_CB12 = 0x59, ++ DBG_BLOCK_ID_CB13 = 0x5a, ++ DBG_BLOCK_ID_CB14 = 0x5b, ++ DBG_BLOCK_ID_UNUSED12 = 0x5c, ++ DBG_BLOCK_ID_UNUSED13 = 0x5d, ++ DBG_BLOCK_ID_UNUSED14 = 0x5e, ++ DBG_BLOCK_ID_TCP0 = 0x5f, ++ DBG_BLOCK_ID_TCP1 = 0x60, ++ DBG_BLOCK_ID_TCP2 = 0x61, ++ DBG_BLOCK_ID_TCP3 = 0x62, ++ DBG_BLOCK_ID_TCP4 = 0x63, ++ DBG_BLOCK_ID_TCP5 = 0x64, ++ DBG_BLOCK_ID_TCP6 = 0x65, ++ DBG_BLOCK_ID_TCP7 = 0x66, ++ DBG_BLOCK_ID_TCP8 = 0x67, ++ DBG_BLOCK_ID_TCP9 = 0x68, ++ DBG_BLOCK_ID_TCP10 = 0x69, ++ DBG_BLOCK_ID_TCP11 = 0x6a, ++ DBG_BLOCK_ID_TCP12 = 0x6b, ++ DBG_BLOCK_ID_TCP13 = 0x6c, ++ DBG_BLOCK_ID_TCP14 = 0x6d, ++ DBG_BLOCK_ID_TCP15 = 0x6e, ++ DBG_BLOCK_ID_TCP16 = 0x6f, ++ DBG_BLOCK_ID_TCP17 = 0x70, ++ DBG_BLOCK_ID_TCP18 = 0x71, ++ DBG_BLOCK_ID_TCP19 = 0x72, ++ DBG_BLOCK_ID_TCP20 = 0x73, ++ DBG_BLOCK_ID_TCP21 = 0x74, ++ DBG_BLOCK_ID_TCP22 = 0x75, ++ DBG_BLOCK_ID_TCP23 = 0x76, ++ DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, ++ DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, ++ DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, ++ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, ++ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, ++ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, ++ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, ++ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, ++ DBG_BLOCK_ID_DB00 = 0x7f, ++ DBG_BLOCK_ID_DB01 = 0x80, ++ DBG_BLOCK_ID_DB02 = 0x81, ++ DBG_BLOCK_ID_DB03 = 0x82, ++ DBG_BLOCK_ID_DB04 = 0x83, ++ DBG_BLOCK_ID_UNUSED15 = 0x84, ++ DBG_BLOCK_ID_UNUSED16 = 0x85, ++ DBG_BLOCK_ID_UNUSED17 = 0x86, ++ DBG_BLOCK_ID_DB10 = 0x87, ++ DBG_BLOCK_ID_DB11 = 0x88, ++ DBG_BLOCK_ID_DB12 = 0x89, ++ DBG_BLOCK_ID_DB13 = 0x8a, ++ DBG_BLOCK_ID_DB14 = 0x8b, ++ DBG_BLOCK_ID_UNUSED18 = 0x8c, ++ DBG_BLOCK_ID_UNUSED19 = 0x8d, ++ DBG_BLOCK_ID_UNUSED20 = 0x8e, ++ DBG_BLOCK_ID_TCC0 = 0x8f, ++ DBG_BLOCK_ID_TCC1 = 0x90, ++ DBG_BLOCK_ID_TCC2 = 0x91, ++ DBG_BLOCK_ID_TCC3 = 0x92, ++ DBG_BLOCK_ID_TCC4 = 0x93, ++ DBG_BLOCK_ID_TCC5 = 0x94, ++ DBG_BLOCK_ID_TCC6 = 0x95, ++ DBG_BLOCK_ID_TCC7 = 0x96, ++ DBG_BLOCK_ID_SPS00 = 0x97, ++ DBG_BLOCK_ID_SPS01 = 0x98, ++ DBG_BLOCK_ID_SPS02 = 0x99, ++ DBG_BLOCK_ID_SPS10 = 0x9a, ++ DBG_BLOCK_ID_SPS11 = 0x9b, ++ DBG_BLOCK_ID_SPS12 = 0x9c, ++ DBG_BLOCK_ID_UNUSED21 = 0x9d, ++ DBG_BLOCK_ID_UNUSED22 = 0x9e, ++ DBG_BLOCK_ID_TA00 = 0x9f, ++ DBG_BLOCK_ID_TA01 = 0xa0, ++ DBG_BLOCK_ID_TA02 = 0xa1, ++ DBG_BLOCK_ID_TA03 = 0xa2, ++ DBG_BLOCK_ID_TA04 = 0xa3, ++ DBG_BLOCK_ID_TA05 = 0xa4, ++ DBG_BLOCK_ID_TA06 = 0xa5, ++ DBG_BLOCK_ID_TA07 = 0xa6, ++ DBG_BLOCK_ID_TA08 = 0xa7, ++ DBG_BLOCK_ID_TA09 = 0xa8, ++ DBG_BLOCK_ID_TA0A = 0xa9, ++ DBG_BLOCK_ID_TA0B = 0xaa, ++ DBG_BLOCK_ID_UNUSED23 = 0xab, ++ DBG_BLOCK_ID_UNUSED24 = 0xac, ++ DBG_BLOCK_ID_UNUSED25 = 0xad, ++ DBG_BLOCK_ID_UNUSED26 = 0xae, ++ DBG_BLOCK_ID_TA10 = 0xaf, ++ DBG_BLOCK_ID_TA11 = 0xb0, ++ DBG_BLOCK_ID_TA12 = 0xb1, ++ DBG_BLOCK_ID_TA13 = 0xb2, ++ DBG_BLOCK_ID_TA14 = 0xb3, ++ DBG_BLOCK_ID_TA15 = 0xb4, ++ DBG_BLOCK_ID_TA16 = 0xb5, ++ DBG_BLOCK_ID_TA17 = 0xb6, ++ DBG_BLOCK_ID_TA18 = 0xb7, ++ DBG_BLOCK_ID_TA19 = 0xb8, ++ DBG_BLOCK_ID_TA1A = 0xb9, ++ DBG_BLOCK_ID_TA1B = 0xba, ++ DBG_BLOCK_ID_UNUSED27 = 0xbb, ++ DBG_BLOCK_ID_UNUSED28 = 0xbc, ++ DBG_BLOCK_ID_UNUSED29 = 0xbd, ++ DBG_BLOCK_ID_UNUSED30 = 0xbe, ++ DBG_BLOCK_ID_TD00 = 0xbf, ++ DBG_BLOCK_ID_TD01 = 0xc0, ++ DBG_BLOCK_ID_TD02 = 0xc1, ++ DBG_BLOCK_ID_TD03 = 0xc2, ++ DBG_BLOCK_ID_TD04 = 0xc3, ++ DBG_BLOCK_ID_TD05 = 0xc4, ++ DBG_BLOCK_ID_TD06 = 0xc5, ++ DBG_BLOCK_ID_TD07 = 0xc6, ++ DBG_BLOCK_ID_TD08 = 0xc7, ++ DBG_BLOCK_ID_TD09 = 0xc8, ++ DBG_BLOCK_ID_TD0A = 0xc9, ++ DBG_BLOCK_ID_TD0B = 0xca, ++ DBG_BLOCK_ID_UNUSED31 = 0xcb, ++ DBG_BLOCK_ID_UNUSED32 = 0xcc, ++ DBG_BLOCK_ID_UNUSED33 = 0xcd, ++ DBG_BLOCK_ID_UNUSED34 = 0xce, ++ DBG_BLOCK_ID_TD10 = 0xcf, ++ DBG_BLOCK_ID_TD11 = 0xd0, ++ DBG_BLOCK_ID_TD12 = 0xd1, ++ DBG_BLOCK_ID_TD13 = 0xd2, ++ DBG_BLOCK_ID_TD14 = 0xd3, ++ DBG_BLOCK_ID_TD15 = 0xd4, ++ DBG_BLOCK_ID_TD16 = 0xd5, ++ DBG_BLOCK_ID_TD17 = 0xd6, ++ DBG_BLOCK_ID_TD18 = 0xd7, ++ DBG_BLOCK_ID_TD19 = 0xd8, ++ DBG_BLOCK_ID_TD1A = 0xd9, ++ DBG_BLOCK_ID_TD1B = 0xda, ++ DBG_BLOCK_ID_UNUSED35 = 0xdb, ++ DBG_BLOCK_ID_UNUSED36 = 0xdc, ++ DBG_BLOCK_ID_UNUSED37 = 0xdd, ++ DBG_BLOCK_ID_UNUSED38 = 0xde, ++ DBG_BLOCK_ID_LDS00 = 0xdf, ++ DBG_BLOCK_ID_LDS01 = 0xe0, ++ DBG_BLOCK_ID_LDS02 = 0xe1, ++ DBG_BLOCK_ID_LDS03 = 0xe2, ++ DBG_BLOCK_ID_LDS04 = 0xe3, ++ DBG_BLOCK_ID_LDS05 = 0xe4, ++ DBG_BLOCK_ID_LDS06 = 0xe5, ++ DBG_BLOCK_ID_LDS07 = 0xe6, ++ DBG_BLOCK_ID_LDS08 = 0xe7, ++ DBG_BLOCK_ID_LDS09 = 0xe8, ++ DBG_BLOCK_ID_LDS0A = 0xe9, ++ DBG_BLOCK_ID_LDS0B = 0xea, ++ DBG_BLOCK_ID_UNUSED39 = 0xeb, ++ DBG_BLOCK_ID_UNUSED40 = 0xec, ++ DBG_BLOCK_ID_UNUSED41 = 0xed, ++ DBG_BLOCK_ID_UNUSED42 = 0xee, ++ DBG_BLOCK_ID_LDS10 = 0xef, ++ DBG_BLOCK_ID_LDS11 = 0xf0, ++ DBG_BLOCK_ID_LDS12 = 0xf1, ++ DBG_BLOCK_ID_LDS13 = 0xf2, ++ DBG_BLOCK_ID_LDS14 = 0xf3, ++ DBG_BLOCK_ID_LDS15 = 0xf4, ++ DBG_BLOCK_ID_LDS16 = 0xf5, ++ DBG_BLOCK_ID_LDS17 = 0xf6, ++ DBG_BLOCK_ID_LDS18 = 0xf7, ++ DBG_BLOCK_ID_LDS19 = 0xf8, ++ DBG_BLOCK_ID_LDS1A = 0xf9, ++ DBG_BLOCK_ID_LDS1B = 0xfa, ++ DBG_BLOCK_ID_UNUSED43 = 0xfb, ++ DBG_BLOCK_ID_UNUSED44 = 0xfc, ++ DBG_BLOCK_ID_UNUSED45 = 0xfd, ++ DBG_BLOCK_ID_UNUSED46 = 0xfe, ++} DebugBlockId; ++typedef enum DebugBlockId_BY2 { ++ DBG_BLOCK_ID_RESERVED_BY2 = 0x0, ++ DBG_BLOCK_ID_VMC_BY2 = 0x1, ++ DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, ++ DBG_BLOCK_ID_GRBM_BY2 = 0x3, ++ DBG_BLOCK_ID_CSC_BY2 = 0x4, ++ DBG_BLOCK_ID_IH_BY2 = 0x5, ++ DBG_BLOCK_ID_SQ_BY2 = 0x6, ++ DBG_BLOCK_ID_UVD_BY2 = 0x7, ++ DBG_BLOCK_ID_SDMA0_BY2 = 0x8, ++ DBG_BLOCK_ID_SPIM_BY2 = 0x9, ++ DBG_BLOCK_ID_VC0_BY2 = 0xa, ++ DBG_BLOCK_ID_PA_BY2 = 0xb, ++ DBG_BLOCK_ID_CP0_BY2 = 0xc, ++ DBG_BLOCK_ID_CP2_BY2 = 0xd, ++ DBG_BLOCK_ID_PC0_BY2 = 0xe, ++ DBG_BLOCK_ID_BCI0_BY2 = 0xf, ++ DBG_BLOCK_ID_SXM0_BY2 = 0x10, ++ DBG_BLOCK_ID_SCT0_BY2 = 0x11, ++ DBG_BLOCK_ID_SPM0_BY2 = 0x12, ++ DBG_BLOCK_ID_BCI2_BY2 = 0x13, ++ DBG_BLOCK_ID_TCA_BY2 = 0x14, ++ DBG_BLOCK_ID_TCCA_BY2 = 0x15, ++ DBG_BLOCK_ID_MCC_BY2 = 0x16, ++ DBG_BLOCK_ID_MCC2_BY2 = 0x17, ++ DBG_BLOCK_ID_MCD_BY2 = 0x18, ++ DBG_BLOCK_ID_MCD2_BY2 = 0x19, ++ DBG_BLOCK_ID_MCD4_BY2 = 0x1a, ++ DBG_BLOCK_ID_MCB_BY2 = 0x1b, ++ DBG_BLOCK_ID_SQA_BY2 = 0x1c, ++ DBG_BLOCK_ID_SQA02_BY2 = 0x1d, ++ DBG_BLOCK_ID_SQA11_BY2 = 0x1e, ++ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, ++ DBG_BLOCK_ID_SQB_BY2 = 0x20, ++ DBG_BLOCK_ID_SQB10_BY2 = 0x21, ++ DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, ++ DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, ++ DBG_BLOCK_ID_CB_BY2 = 0x24, ++ DBG_BLOCK_ID_CB02_BY2 = 0x25, ++ DBG_BLOCK_ID_CB10_BY2 = 0x26, ++ DBG_BLOCK_ID_CB12_BY2 = 0x27, ++ DBG_BLOCK_ID_SXS_BY2 = 0x28, ++ DBG_BLOCK_ID_SXS2_BY2 = 0x29, ++ DBG_BLOCK_ID_SXS4_BY2 = 0x2a, ++ DBG_BLOCK_ID_SXS6_BY2 = 0x2b, ++ DBG_BLOCK_ID_DB_BY2 = 0x2c, ++ DBG_BLOCK_ID_DB02_BY2 = 0x2d, ++ DBG_BLOCK_ID_DB10_BY2 = 0x2e, ++ DBG_BLOCK_ID_DB12_BY2 = 0x2f, ++ DBG_BLOCK_ID_TCP_BY2 = 0x30, ++ DBG_BLOCK_ID_TCP2_BY2 = 0x31, ++ DBG_BLOCK_ID_TCP4_BY2 = 0x32, ++ DBG_BLOCK_ID_TCP6_BY2 = 0x33, ++ DBG_BLOCK_ID_TCP8_BY2 = 0x34, ++ DBG_BLOCK_ID_TCP10_BY2 = 0x35, ++ DBG_BLOCK_ID_TCP12_BY2 = 0x36, ++ DBG_BLOCK_ID_TCP14_BY2 = 0x37, ++ DBG_BLOCK_ID_TCP16_BY2 = 0x38, ++ DBG_BLOCK_ID_TCP18_BY2 = 0x39, ++ DBG_BLOCK_ID_TCP20_BY2 = 0x3a, ++ DBG_BLOCK_ID_TCP22_BY2 = 0x3b, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, ++ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, ++ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, ++ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, ++ DBG_BLOCK_ID_TCC_BY2 = 0x40, ++ DBG_BLOCK_ID_TCC2_BY2 = 0x41, ++ DBG_BLOCK_ID_TCC4_BY2 = 0x42, ++ DBG_BLOCK_ID_TCC6_BY2 = 0x43, ++ DBG_BLOCK_ID_SPS_BY2 = 0x44, ++ DBG_BLOCK_ID_SPS02_BY2 = 0x45, ++ DBG_BLOCK_ID_SPS11_BY2 = 0x46, ++ DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, ++ DBG_BLOCK_ID_TA_BY2 = 0x48, ++ DBG_BLOCK_ID_TA02_BY2 = 0x49, ++ DBG_BLOCK_ID_TA04_BY2 = 0x4a, ++ DBG_BLOCK_ID_TA06_BY2 = 0x4b, ++ DBG_BLOCK_ID_TA08_BY2 = 0x4c, ++ DBG_BLOCK_ID_TA0A_BY2 = 0x4d, ++ DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, ++ DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, ++ DBG_BLOCK_ID_TA10_BY2 = 0x50, ++ DBG_BLOCK_ID_TA12_BY2 = 0x51, ++ DBG_BLOCK_ID_TA14_BY2 = 0x52, ++ DBG_BLOCK_ID_TA16_BY2 = 0x53, ++ DBG_BLOCK_ID_TA18_BY2 = 0x54, ++ DBG_BLOCK_ID_TA1A_BY2 = 0x55, ++ DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, ++ DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, ++ DBG_BLOCK_ID_TD_BY2 = 0x58, ++ DBG_BLOCK_ID_TD02_BY2 = 0x59, ++ DBG_BLOCK_ID_TD04_BY2 = 0x5a, ++ DBG_BLOCK_ID_TD06_BY2 = 0x5b, ++ DBG_BLOCK_ID_TD08_BY2 = 0x5c, ++ DBG_BLOCK_ID_TD0A_BY2 = 0x5d, ++ DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, ++ DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, ++ DBG_BLOCK_ID_TD10_BY2 = 0x60, ++ DBG_BLOCK_ID_TD12_BY2 = 0x61, ++ DBG_BLOCK_ID_TD14_BY2 = 0x62, ++ DBG_BLOCK_ID_TD16_BY2 = 0x63, ++ DBG_BLOCK_ID_TD18_BY2 = 0x64, ++ DBG_BLOCK_ID_TD1A_BY2 = 0x65, ++ DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, ++ DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, ++ DBG_BLOCK_ID_LDS_BY2 = 0x68, ++ DBG_BLOCK_ID_LDS02_BY2 = 0x69, ++ DBG_BLOCK_ID_LDS04_BY2 = 0x6a, ++ DBG_BLOCK_ID_LDS06_BY2 = 0x6b, ++ DBG_BLOCK_ID_LDS08_BY2 = 0x6c, ++ DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, ++ DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, ++ DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, ++ DBG_BLOCK_ID_LDS10_BY2 = 0x70, ++ DBG_BLOCK_ID_LDS12_BY2 = 0x71, ++ DBG_BLOCK_ID_LDS14_BY2 = 0x72, ++ DBG_BLOCK_ID_LDS16_BY2 = 0x73, ++ DBG_BLOCK_ID_LDS18_BY2 = 0x74, ++ DBG_BLOCK_ID_LDS1A_BY2 = 0x75, ++ DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, ++ DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, ++} DebugBlockId_BY2; ++typedef enum DebugBlockId_BY4 { ++ DBG_BLOCK_ID_RESERVED_BY4 = 0x0, ++ DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, ++ DBG_BLOCK_ID_CSC_BY4 = 0x2, ++ DBG_BLOCK_ID_SQ_BY4 = 0x3, ++ DBG_BLOCK_ID_SDMA0_BY4 = 0x4, ++ DBG_BLOCK_ID_VC0_BY4 = 0x5, ++ DBG_BLOCK_ID_CP0_BY4 = 0x6, ++ DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, ++ DBG_BLOCK_ID_SXM0_BY4 = 0x8, ++ DBG_BLOCK_ID_SPM0_BY4 = 0x9, ++ DBG_BLOCK_ID_TCAA_BY4 = 0xa, ++ DBG_BLOCK_ID_MCC_BY4 = 0xb, ++ DBG_BLOCK_ID_MCD_BY4 = 0xc, ++ DBG_BLOCK_ID_MCD4_BY4 = 0xd, ++ DBG_BLOCK_ID_SQA_BY4 = 0xe, ++ DBG_BLOCK_ID_SQA11_BY4 = 0xf, ++ DBG_BLOCK_ID_SQB_BY4 = 0x10, ++ DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, ++ DBG_BLOCK_ID_CB_BY4 = 0x12, ++ DBG_BLOCK_ID_CB10_BY4 = 0x13, ++ DBG_BLOCK_ID_SXS_BY4 = 0x14, ++ DBG_BLOCK_ID_SXS4_BY4 = 0x15, ++ DBG_BLOCK_ID_DB_BY4 = 0x16, ++ DBG_BLOCK_ID_DB10_BY4 = 0x17, ++ DBG_BLOCK_ID_TCP_BY4 = 0x18, ++ DBG_BLOCK_ID_TCP4_BY4 = 0x19, ++ DBG_BLOCK_ID_TCP8_BY4 = 0x1a, ++ DBG_BLOCK_ID_TCP12_BY4 = 0x1b, ++ DBG_BLOCK_ID_TCP16_BY4 = 0x1c, ++ DBG_BLOCK_ID_TCP20_BY4 = 0x1d, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, ++ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, ++ DBG_BLOCK_ID_TCC_BY4 = 0x20, ++ DBG_BLOCK_ID_TCC4_BY4 = 0x21, ++ DBG_BLOCK_ID_SPS_BY4 = 0x22, ++ DBG_BLOCK_ID_SPS11_BY4 = 0x23, ++ DBG_BLOCK_ID_TA_BY4 = 0x24, ++ DBG_BLOCK_ID_TA04_BY4 = 0x25, ++ DBG_BLOCK_ID_TA08_BY4 = 0x26, ++ DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, ++ DBG_BLOCK_ID_TA10_BY4 = 0x28, ++ DBG_BLOCK_ID_TA14_BY4 = 0x29, ++ DBG_BLOCK_ID_TA18_BY4 = 0x2a, ++ DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, ++ DBG_BLOCK_ID_TD_BY4 = 0x2c, ++ DBG_BLOCK_ID_TD04_BY4 = 0x2d, ++ DBG_BLOCK_ID_TD08_BY4 = 0x2e, ++ DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, ++ DBG_BLOCK_ID_TD10_BY4 = 0x30, ++ DBG_BLOCK_ID_TD14_BY4 = 0x31, ++ DBG_BLOCK_ID_TD18_BY4 = 0x32, ++ DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, ++ DBG_BLOCK_ID_LDS_BY4 = 0x34, ++ DBG_BLOCK_ID_LDS04_BY4 = 0x35, ++ DBG_BLOCK_ID_LDS08_BY4 = 0x36, ++ DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, ++ DBG_BLOCK_ID_LDS10_BY4 = 0x38, ++ DBG_BLOCK_ID_LDS14_BY4 = 0x39, ++ DBG_BLOCK_ID_LDS18_BY4 = 0x3a, ++ DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, ++} DebugBlockId_BY4; ++typedef enum DebugBlockId_BY8 { ++ DBG_BLOCK_ID_RESERVED_BY8 = 0x0, ++ DBG_BLOCK_ID_CSC_BY8 = 0x1, ++ DBG_BLOCK_ID_SDMA0_BY8 = 0x2, ++ DBG_BLOCK_ID_CP0_BY8 = 0x3, ++ DBG_BLOCK_ID_SXM0_BY8 = 0x4, ++ DBG_BLOCK_ID_TCA_BY8 = 0x5, ++ DBG_BLOCK_ID_MCD_BY8 = 0x6, ++ DBG_BLOCK_ID_SQA_BY8 = 0x7, ++ DBG_BLOCK_ID_SQB_BY8 = 0x8, ++ DBG_BLOCK_ID_CB_BY8 = 0x9, ++ DBG_BLOCK_ID_SXS_BY8 = 0xa, ++ DBG_BLOCK_ID_DB_BY8 = 0xb, ++ DBG_BLOCK_ID_TCP_BY8 = 0xc, ++ DBG_BLOCK_ID_TCP8_BY8 = 0xd, ++ DBG_BLOCK_ID_TCP16_BY8 = 0xe, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, ++ DBG_BLOCK_ID_TCC_BY8 = 0x10, ++ DBG_BLOCK_ID_SPS_BY8 = 0x11, ++ DBG_BLOCK_ID_TA_BY8 = 0x12, ++ DBG_BLOCK_ID_TA08_BY8 = 0x13, ++ DBG_BLOCK_ID_TA10_BY8 = 0x14, ++ DBG_BLOCK_ID_TA18_BY8 = 0x15, ++ DBG_BLOCK_ID_TD_BY8 = 0x16, ++ DBG_BLOCK_ID_TD08_BY8 = 0x17, ++ DBG_BLOCK_ID_TD10_BY8 = 0x18, ++ DBG_BLOCK_ID_TD18_BY8 = 0x19, ++ DBG_BLOCK_ID_LDS_BY8 = 0x1a, ++ DBG_BLOCK_ID_LDS08_BY8 = 0x1b, ++ DBG_BLOCK_ID_LDS10_BY8 = 0x1c, ++ DBG_BLOCK_ID_LDS18_BY8 = 0x1d, ++} DebugBlockId_BY8; ++typedef enum DebugBlockId_BY16 { ++ DBG_BLOCK_ID_RESERVED_BY16 = 0x0, ++ DBG_BLOCK_ID_SDMA0_BY16 = 0x1, ++ DBG_BLOCK_ID_SXM_BY16 = 0x2, ++ DBG_BLOCK_ID_MCD_BY16 = 0x3, ++ DBG_BLOCK_ID_SQB_BY16 = 0x4, ++ DBG_BLOCK_ID_SXS_BY16 = 0x5, ++ DBG_BLOCK_ID_TCP_BY16 = 0x6, ++ DBG_BLOCK_ID_TCP16_BY16 = 0x7, ++ DBG_BLOCK_ID_TCC_BY16 = 0x8, ++ DBG_BLOCK_ID_TA_BY16 = 0x9, ++ DBG_BLOCK_ID_TA10_BY16 = 0xa, ++ DBG_BLOCK_ID_TD_BY16 = 0xb, ++ DBG_BLOCK_ID_TD10_BY16 = 0xc, ++ DBG_BLOCK_ID_LDS_BY16 = 0xd, ++ DBG_BLOCK_ID_LDS10_BY16 = 0xe, ++} DebugBlockId_BY16; ++typedef enum SurfaceEndian { ++ ENDIAN_NONE = 0x0, ++ ENDIAN_8IN16 = 0x1, ++ ENDIAN_8IN32 = 0x2, ++ ENDIAN_8IN64 = 0x3, ++} SurfaceEndian; ++typedef enum ArrayMode { ++ ARRAY_LINEAR_GENERAL = 0x0, ++ ARRAY_LINEAR_ALIGNED = 0x1, ++ ARRAY_1D_TILED_THIN1 = 0x2, ++ ARRAY_1D_TILED_THICK = 0x3, ++ ARRAY_2D_TILED_THIN1 = 0x4, ++ ARRAY_PRT_TILED_THIN1 = 0x5, ++ ARRAY_PRT_2D_TILED_THIN1 = 0x6, ++ ARRAY_2D_TILED_THICK = 0x7, ++ ARRAY_2D_TILED_XTHICK = 0x8, ++ ARRAY_PRT_TILED_THICK = 0x9, ++ ARRAY_PRT_2D_TILED_THICK = 0xa, ++ ARRAY_PRT_3D_TILED_THIN1 = 0xb, ++ ARRAY_3D_TILED_THIN1 = 0xc, ++ ARRAY_3D_TILED_THICK = 0xd, ++ ARRAY_3D_TILED_XTHICK = 0xe, ++ ARRAY_PRT_3D_TILED_THICK = 0xf, ++} ArrayMode; ++typedef enum PipeTiling { ++ CONFIG_1_PIPE = 0x0, ++ CONFIG_2_PIPE = 0x1, ++ CONFIG_4_PIPE = 0x2, ++ CONFIG_8_PIPE = 0x3, ++} PipeTiling; ++typedef enum BankTiling { ++ CONFIG_4_BANK = 0x0, ++ CONFIG_8_BANK = 0x1, ++} BankTiling; ++typedef enum GroupInterleave { ++ CONFIG_256B_GROUP = 0x0, ++ CONFIG_512B_GROUP = 0x1, ++} GroupInterleave; ++typedef enum RowTiling { ++ CONFIG_1KB_ROW = 0x0, ++ CONFIG_2KB_ROW = 0x1, ++ CONFIG_4KB_ROW = 0x2, ++ CONFIG_8KB_ROW = 0x3, ++ CONFIG_1KB_ROW_OPT = 0x4, ++ CONFIG_2KB_ROW_OPT = 0x5, ++ CONFIG_4KB_ROW_OPT = 0x6, ++ CONFIG_8KB_ROW_OPT = 0x7, ++} RowTiling; ++typedef enum BankSwapBytes { ++ CONFIG_128B_SWAPS = 0x0, ++ CONFIG_256B_SWAPS = 0x1, ++ CONFIG_512B_SWAPS = 0x2, ++ CONFIG_1KB_SWAPS = 0x3, ++} BankSwapBytes; ++typedef enum SampleSplitBytes { ++ CONFIG_1KB_SPLIT = 0x0, ++ CONFIG_2KB_SPLIT = 0x1, ++ CONFIG_4KB_SPLIT = 0x2, ++ CONFIG_8KB_SPLIT = 0x3, ++} SampleSplitBytes; ++typedef enum NumPipes { ++ ADDR_CONFIG_1_PIPE = 0x0, ++ ADDR_CONFIG_2_PIPE = 0x1, ++ ADDR_CONFIG_4_PIPE = 0x2, ++ ADDR_CONFIG_8_PIPE = 0x3, ++} NumPipes; ++typedef enum PipeInterleaveSize { ++ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, ++ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, ++} PipeInterleaveSize; ++typedef enum BankInterleaveSize { ++ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, ++ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, ++ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, ++ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, ++} BankInterleaveSize; ++typedef enum NumShaderEngines { ++ ADDR_CONFIG_1_SHADER_ENGINE = 0x0, ++ ADDR_CONFIG_2_SHADER_ENGINE = 0x1, ++} NumShaderEngines; ++typedef enum ShaderEngineTileSize { ++ ADDR_CONFIG_SE_TILE_16 = 0x0, ++ ADDR_CONFIG_SE_TILE_32 = 0x1, ++} ShaderEngineTileSize; ++typedef enum NumGPUs { ++ ADDR_CONFIG_1_GPU = 0x0, ++ ADDR_CONFIG_2_GPU = 0x1, ++ ADDR_CONFIG_4_GPU = 0x2, ++} NumGPUs; ++typedef enum MultiGPUTileSize { ++ ADDR_CONFIG_GPU_TILE_16 = 0x0, ++ ADDR_CONFIG_GPU_TILE_32 = 0x1, ++ ADDR_CONFIG_GPU_TILE_64 = 0x2, ++ ADDR_CONFIG_GPU_TILE_128 = 0x3, ++} MultiGPUTileSize; ++typedef enum RowSize { ++ ADDR_CONFIG_1KB_ROW = 0x0, ++ ADDR_CONFIG_2KB_ROW = 0x1, ++ ADDR_CONFIG_4KB_ROW = 0x2, ++} RowSize; ++typedef enum NumLowerPipes { ++ ADDR_CONFIG_1_LOWER_PIPES = 0x0, ++ ADDR_CONFIG_2_LOWER_PIPES = 0x1, ++} NumLowerPipes; ++typedef enum ColorTransform { ++ DCC_CT_AUTO = 0x0, ++ DCC_CT_NONE = 0x1, ++ ABGR_TO_A_BG_G_RB = 0x2, ++ BGRA_TO_BG_G_RB_A = 0x3, ++} ColorTransform; ++typedef enum CompareRef { ++ REF_NEVER = 0x0, ++ REF_LESS = 0x1, ++ REF_EQUAL = 0x2, ++ REF_LEQUAL = 0x3, ++ REF_GREATER = 0x4, ++ REF_NOTEQUAL = 0x5, ++ REF_GEQUAL = 0x6, ++ REF_ALWAYS = 0x7, ++} CompareRef; ++typedef enum ReadSize { ++ READ_256_BITS = 0x0, ++ READ_512_BITS = 0x1, ++} ReadSize; ++typedef enum DepthFormat { ++ DEPTH_INVALID = 0x0, ++ DEPTH_16 = 0x1, ++ DEPTH_X8_24 = 0x2, ++ DEPTH_8_24 = 0x3, ++ DEPTH_X8_24_FLOAT = 0x4, ++ DEPTH_8_24_FLOAT = 0x5, ++ DEPTH_32_FLOAT = 0x6, ++ DEPTH_X24_8_32_FLOAT = 0x7, ++} DepthFormat; ++typedef enum ZFormat { ++ Z_INVALID = 0x0, ++ Z_16 = 0x1, ++ Z_24 = 0x2, ++ Z_32_FLOAT = 0x3, ++} ZFormat; ++typedef enum StencilFormat { ++ STENCIL_INVALID = 0x0, ++ STENCIL_8 = 0x1, ++} StencilFormat; ++typedef enum CmaskMode { ++ CMASK_CLEAR_NONE = 0x0, ++ CMASK_CLEAR_ONE = 0x1, ++ CMASK_CLEAR_ALL = 0x2, ++ CMASK_ANY_EXPANDED = 0x3, ++ CMASK_ALPHA0_FRAG1 = 0x4, ++ CMASK_ALPHA0_FRAG2 = 0x5, ++ CMASK_ALPHA0_FRAG4 = 0x6, ++ CMASK_ALPHA0_FRAGS = 0x7, ++ CMASK_ALPHA1_FRAG1 = 0x8, ++ CMASK_ALPHA1_FRAG2 = 0x9, ++ CMASK_ALPHA1_FRAG4 = 0xa, ++ CMASK_ALPHA1_FRAGS = 0xb, ++ CMASK_ALPHAX_FRAG1 = 0xc, ++ CMASK_ALPHAX_FRAG2 = 0xd, ++ CMASK_ALPHAX_FRAG4 = 0xe, ++ CMASK_ALPHAX_FRAGS = 0xf, ++} CmaskMode; ++typedef enum QuadExportFormat { ++ EXPORT_UNUSED = 0x0, ++ EXPORT_32_R = 0x1, ++ EXPORT_32_GR = 0x2, ++ EXPORT_32_AR = 0x3, ++ EXPORT_FP16_ABGR = 0x4, ++ EXPORT_UNSIGNED16_ABGR = 0x5, ++ EXPORT_SIGNED16_ABGR = 0x6, ++ EXPORT_32_ABGR = 0x7, ++} QuadExportFormat; ++typedef enum QuadExportFormatOld { ++ EXPORT_4P_32BPC_ABGR = 0x0, ++ EXPORT_4P_16BPC_ABGR = 0x1, ++ EXPORT_4P_32BPC_GR = 0x2, ++ EXPORT_4P_32BPC_AR = 0x3, ++ EXPORT_2P_32BPC_ABGR = 0x4, ++ EXPORT_8P_32BPC_R = 0x5, ++} QuadExportFormatOld; ++typedef enum ColorFormat { ++ COLOR_INVALID = 0x0, ++ COLOR_8 = 0x1, ++ COLOR_16 = 0x2, ++ COLOR_8_8 = 0x3, ++ COLOR_32 = 0x4, ++ COLOR_16_16 = 0x5, ++ COLOR_10_11_11 = 0x6, ++ COLOR_11_11_10 = 0x7, ++ COLOR_10_10_10_2 = 0x8, ++ COLOR_2_10_10_10 = 0x9, ++ COLOR_8_8_8_8 = 0xa, ++ COLOR_32_32 = 0xb, ++ COLOR_16_16_16_16 = 0xc, ++ COLOR_RESERVED_13 = 0xd, ++ COLOR_32_32_32_32 = 0xe, ++ COLOR_RESERVED_15 = 0xf, ++ COLOR_5_6_5 = 0x10, ++ COLOR_1_5_5_5 = 0x11, ++ COLOR_5_5_5_1 = 0x12, ++ COLOR_4_4_4_4 = 0x13, ++ COLOR_8_24 = 0x14, ++ COLOR_24_8 = 0x15, ++ COLOR_X24_8_32_FLOAT = 0x16, ++ COLOR_RESERVED_23 = 0x17, ++} ColorFormat; ++typedef enum SurfaceFormat { ++ FMT_INVALID = 0x0, ++ FMT_8 = 0x1, ++ FMT_16 = 0x2, ++ FMT_8_8 = 0x3, ++ FMT_32 = 0x4, ++ FMT_16_16 = 0x5, ++ FMT_10_11_11 = 0x6, ++ FMT_11_11_10 = 0x7, ++ FMT_10_10_10_2 = 0x8, ++ FMT_2_10_10_10 = 0x9, ++ FMT_8_8_8_8 = 0xa, ++ FMT_32_32 = 0xb, ++ FMT_16_16_16_16 = 0xc, ++ FMT_32_32_32 = 0xd, ++ FMT_32_32_32_32 = 0xe, ++ FMT_RESERVED_4 = 0xf, ++ FMT_5_6_5 = 0x10, ++ FMT_1_5_5_5 = 0x11, ++ FMT_5_5_5_1 = 0x12, ++ FMT_4_4_4_4 = 0x13, ++ FMT_8_24 = 0x14, ++ FMT_24_8 = 0x15, ++ FMT_X24_8_32_FLOAT = 0x16, ++ FMT_RESERVED_33 = 0x17, ++ FMT_11_11_10_FLOAT = 0x18, ++ FMT_16_FLOAT = 0x19, ++ FMT_32_FLOAT = 0x1a, ++ FMT_16_16_FLOAT = 0x1b, ++ FMT_8_24_FLOAT = 0x1c, ++ FMT_24_8_FLOAT = 0x1d, ++ FMT_32_32_FLOAT = 0x1e, ++ FMT_10_11_11_FLOAT = 0x1f, ++ FMT_16_16_16_16_FLOAT = 0x20, ++ FMT_3_3_2 = 0x21, ++ FMT_6_5_5 = 0x22, ++ FMT_32_32_32_32_FLOAT = 0x23, ++ FMT_RESERVED_36 = 0x24, ++ FMT_1 = 0x25, ++ FMT_1_REVERSED = 0x26, ++ FMT_GB_GR = 0x27, ++ FMT_BG_RG = 0x28, ++ FMT_32_AS_8 = 0x29, ++ FMT_32_AS_8_8 = 0x2a, ++ FMT_5_9_9_9_SHAREDEXP = 0x2b, ++ FMT_8_8_8 = 0x2c, ++ FMT_16_16_16 = 0x2d, ++ FMT_16_16_16_FLOAT = 0x2e, ++ FMT_4_4 = 0x2f, ++ FMT_32_32_32_FLOAT = 0x30, ++ FMT_BC1 = 0x31, ++ FMT_BC2 = 0x32, ++ FMT_BC3 = 0x33, ++ FMT_BC4 = 0x34, ++ FMT_BC5 = 0x35, ++ FMT_BC6 = 0x36, ++ FMT_BC7 = 0x37, ++ FMT_32_AS_32_32_32_32 = 0x38, ++ FMT_APC3 = 0x39, ++ FMT_APC4 = 0x3a, ++ FMT_APC5 = 0x3b, ++ FMT_APC6 = 0x3c, ++ FMT_APC7 = 0x3d, ++ FMT_CTX1 = 0x3e, ++ FMT_RESERVED_63 = 0x3f, ++} SurfaceFormat; ++typedef enum BUF_DATA_FORMAT { ++ BUF_DATA_FORMAT_INVALID = 0x0, ++ BUF_DATA_FORMAT_8 = 0x1, ++ BUF_DATA_FORMAT_16 = 0x2, ++ BUF_DATA_FORMAT_8_8 = 0x3, ++ BUF_DATA_FORMAT_32 = 0x4, ++ BUF_DATA_FORMAT_16_16 = 0x5, ++ BUF_DATA_FORMAT_10_11_11 = 0x6, ++ BUF_DATA_FORMAT_11_11_10 = 0x7, ++ BUF_DATA_FORMAT_10_10_10_2 = 0x8, ++ BUF_DATA_FORMAT_2_10_10_10 = 0x9, ++ BUF_DATA_FORMAT_8_8_8_8 = 0xa, ++ BUF_DATA_FORMAT_32_32 = 0xb, ++ BUF_DATA_FORMAT_16_16_16_16 = 0xc, ++ BUF_DATA_FORMAT_32_32_32 = 0xd, ++ BUF_DATA_FORMAT_32_32_32_32 = 0xe, ++ BUF_DATA_FORMAT_RESERVED_15 = 0xf, ++} BUF_DATA_FORMAT; ++typedef enum IMG_DATA_FORMAT { ++ IMG_DATA_FORMAT_INVALID = 0x0, ++ IMG_DATA_FORMAT_8 = 0x1, ++ IMG_DATA_FORMAT_16 = 0x2, ++ IMG_DATA_FORMAT_8_8 = 0x3, ++ IMG_DATA_FORMAT_32 = 0x4, ++ IMG_DATA_FORMAT_16_16 = 0x5, ++ IMG_DATA_FORMAT_10_11_11 = 0x6, ++ IMG_DATA_FORMAT_11_11_10 = 0x7, ++ IMG_DATA_FORMAT_10_10_10_2 = 0x8, ++ IMG_DATA_FORMAT_2_10_10_10 = 0x9, ++ IMG_DATA_FORMAT_8_8_8_8 = 0xa, ++ IMG_DATA_FORMAT_32_32 = 0xb, ++ IMG_DATA_FORMAT_16_16_16_16 = 0xc, ++ IMG_DATA_FORMAT_32_32_32 = 0xd, ++ IMG_DATA_FORMAT_32_32_32_32 = 0xe, ++ IMG_DATA_FORMAT_RESERVED_15 = 0xf, ++ IMG_DATA_FORMAT_5_6_5 = 0x10, ++ IMG_DATA_FORMAT_1_5_5_5 = 0x11, ++ IMG_DATA_FORMAT_5_5_5_1 = 0x12, ++ IMG_DATA_FORMAT_4_4_4_4 = 0x13, ++ IMG_DATA_FORMAT_8_24 = 0x14, ++ IMG_DATA_FORMAT_24_8 = 0x15, ++ IMG_DATA_FORMAT_X24_8_32 = 0x16, ++ IMG_DATA_FORMAT_RESERVED_23 = 0x17, ++ IMG_DATA_FORMAT_RESERVED_24 = 0x18, ++ IMG_DATA_FORMAT_RESERVED_25 = 0x19, ++ IMG_DATA_FORMAT_RESERVED_26 = 0x1a, ++ IMG_DATA_FORMAT_RESERVED_27 = 0x1b, ++ IMG_DATA_FORMAT_RESERVED_28 = 0x1c, ++ IMG_DATA_FORMAT_RESERVED_29 = 0x1d, ++ IMG_DATA_FORMAT_RESERVED_30 = 0x1e, ++ IMG_DATA_FORMAT_RESERVED_31 = 0x1f, ++ IMG_DATA_FORMAT_GB_GR = 0x20, ++ IMG_DATA_FORMAT_BG_RG = 0x21, ++ IMG_DATA_FORMAT_5_9_9_9 = 0x22, ++ IMG_DATA_FORMAT_BC1 = 0x23, ++ IMG_DATA_FORMAT_BC2 = 0x24, ++ IMG_DATA_FORMAT_BC3 = 0x25, ++ IMG_DATA_FORMAT_BC4 = 0x26, ++ IMG_DATA_FORMAT_BC5 = 0x27, ++ IMG_DATA_FORMAT_BC6 = 0x28, ++ IMG_DATA_FORMAT_BC7 = 0x29, ++ IMG_DATA_FORMAT_RESERVED_42 = 0x2a, ++ IMG_DATA_FORMAT_RESERVED_43 = 0x2b, ++ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, ++ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, ++ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, ++ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, ++ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, ++ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, ++ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, ++ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, ++ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, ++ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, ++ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, ++ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, ++ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, ++ IMG_DATA_FORMAT_4_4 = 0x39, ++ IMG_DATA_FORMAT_6_5_5 = 0x3a, ++ IMG_DATA_FORMAT_1 = 0x3b, ++ IMG_DATA_FORMAT_1_REVERSED = 0x3c, ++ IMG_DATA_FORMAT_32_AS_8 = 0x3d, ++ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, ++ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, ++} IMG_DATA_FORMAT; ++typedef enum BUF_NUM_FORMAT { ++ BUF_NUM_FORMAT_UNORM = 0x0, ++ BUF_NUM_FORMAT_SNORM = 0x1, ++ BUF_NUM_FORMAT_USCALED = 0x2, ++ BUF_NUM_FORMAT_SSCALED = 0x3, ++ BUF_NUM_FORMAT_UINT = 0x4, ++ BUF_NUM_FORMAT_SINT = 0x5, ++ BUF_NUM_FORMAT_RESERVED_6 = 0x6, ++ BUF_NUM_FORMAT_FLOAT = 0x7, ++} BUF_NUM_FORMAT; ++typedef enum IMG_NUM_FORMAT { ++ IMG_NUM_FORMAT_UNORM = 0x0, ++ IMG_NUM_FORMAT_SNORM = 0x1, ++ IMG_NUM_FORMAT_USCALED = 0x2, ++ IMG_NUM_FORMAT_SSCALED = 0x3, ++ IMG_NUM_FORMAT_UINT = 0x4, ++ IMG_NUM_FORMAT_SINT = 0x5, ++ IMG_NUM_FORMAT_RESERVED_6 = 0x6, ++ IMG_NUM_FORMAT_FLOAT = 0x7, ++ IMG_NUM_FORMAT_RESERVED_8 = 0x8, ++ IMG_NUM_FORMAT_SRGB = 0x9, ++ IMG_NUM_FORMAT_RESERVED_10 = 0xa, ++ IMG_NUM_FORMAT_RESERVED_11 = 0xb, ++ IMG_NUM_FORMAT_RESERVED_12 = 0xc, ++ IMG_NUM_FORMAT_RESERVED_13 = 0xd, ++ IMG_NUM_FORMAT_RESERVED_14 = 0xe, ++ IMG_NUM_FORMAT_RESERVED_15 = 0xf, ++} IMG_NUM_FORMAT; ++typedef enum TileType { ++ ARRAY_COLOR_TILE = 0x0, ++ ARRAY_DEPTH_TILE = 0x1, ++} TileType; ++typedef enum NonDispTilingOrder { ++ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, ++ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, ++} NonDispTilingOrder; ++typedef enum MicroTileMode { ++ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, ++ ADDR_SURF_THIN_MICRO_TILING = 0x1, ++ ADDR_SURF_DEPTH_MICRO_TILING = 0x2, ++ ADDR_SURF_ROTATED_MICRO_TILING = 0x3, ++ ADDR_SURF_THICK_MICRO_TILING = 0x4, ++} MicroTileMode; ++typedef enum TileSplit { ++ ADDR_SURF_TILE_SPLIT_64B = 0x0, ++ ADDR_SURF_TILE_SPLIT_128B = 0x1, ++ ADDR_SURF_TILE_SPLIT_256B = 0x2, ++ ADDR_SURF_TILE_SPLIT_512B = 0x3, ++ ADDR_SURF_TILE_SPLIT_1KB = 0x4, ++ ADDR_SURF_TILE_SPLIT_2KB = 0x5, ++ ADDR_SURF_TILE_SPLIT_4KB = 0x6, ++} TileSplit; ++typedef enum SampleSplit { ++ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, ++ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, ++ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, ++ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, ++} SampleSplit; ++typedef enum PipeConfig { ++ ADDR_SURF_P2 = 0x0, ++ ADDR_SURF_P2_RESERVED0 = 0x1, ++ ADDR_SURF_P2_RESERVED1 = 0x2, ++ ADDR_SURF_P2_RESERVED2 = 0x3, ++ ADDR_SURF_P4_8x16 = 0x4, ++ ADDR_SURF_P4_16x16 = 0x5, ++ ADDR_SURF_P4_16x32 = 0x6, ++ ADDR_SURF_P4_32x32 = 0x7, ++ ADDR_SURF_P8_16x16_8x16 = 0x8, ++ ADDR_SURF_P8_16x32_8x16 = 0x9, ++ ADDR_SURF_P8_32x32_8x16 = 0xa, ++ ADDR_SURF_P8_16x32_16x16 = 0xb, ++ ADDR_SURF_P8_32x32_16x16 = 0xc, ++ ADDR_SURF_P8_32x32_16x32 = 0xd, ++ ADDR_SURF_P8_32x64_32x32 = 0xe, ++ ADDR_SURF_P8_RESERVED0 = 0xf, ++ ADDR_SURF_P16_32x32_8x16 = 0x10, ++ ADDR_SURF_P16_32x32_16x16 = 0x11, ++} PipeConfig; ++typedef enum NumBanks { ++ ADDR_SURF_2_BANK = 0x0, ++ ADDR_SURF_4_BANK = 0x1, ++ ADDR_SURF_8_BANK = 0x2, ++ ADDR_SURF_16_BANK = 0x3, ++} NumBanks; ++typedef enum BankWidth { ++ ADDR_SURF_BANK_WIDTH_1 = 0x0, ++ ADDR_SURF_BANK_WIDTH_2 = 0x1, ++ ADDR_SURF_BANK_WIDTH_4 = 0x2, ++ ADDR_SURF_BANK_WIDTH_8 = 0x3, ++} BankWidth; ++typedef enum BankHeight { ++ ADDR_SURF_BANK_HEIGHT_1 = 0x0, ++ ADDR_SURF_BANK_HEIGHT_2 = 0x1, ++ ADDR_SURF_BANK_HEIGHT_4 = 0x2, ++ ADDR_SURF_BANK_HEIGHT_8 = 0x3, ++} BankHeight; ++typedef enum BankWidthHeight { ++ ADDR_SURF_BANK_WH_1 = 0x0, ++ ADDR_SURF_BANK_WH_2 = 0x1, ++ ADDR_SURF_BANK_WH_4 = 0x2, ++ ADDR_SURF_BANK_WH_8 = 0x3, ++} BankWidthHeight; ++typedef enum MacroTileAspect { ++ ADDR_SURF_MACRO_ASPECT_1 = 0x0, ++ ADDR_SURF_MACRO_ASPECT_2 = 0x1, ++ ADDR_SURF_MACRO_ASPECT_4 = 0x2, ++ ADDR_SURF_MACRO_ASPECT_8 = 0x3, ++} MacroTileAspect; ++typedef enum GATCL1RequestType { ++ GATCL1_TYPE_NORMAL = 0x0, ++ GATCL1_TYPE_SHOOTDOWN = 0x1, ++ GATCL1_TYPE_BYPASS = 0x2, ++} GATCL1RequestType; ++typedef enum TCC_CACHE_POLICIES { ++ TCC_CACHE_POLICY_LRU = 0x0, ++ TCC_CACHE_POLICY_STREAM = 0x1, ++} TCC_CACHE_POLICIES; ++typedef enum MTYPE { ++ MTYPE_NC_NV = 0x0, ++ MTYPE_NC = 0x1, ++ MTYPE_CC = 0x2, ++ MTYPE_UC = 0x3, ++} MTYPE; ++typedef enum PERFMON_COUNTER_MODE { ++ PERFMON_COUNTER_MODE_ACCUM = 0x0, ++ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, ++ PERFMON_COUNTER_MODE_MAX = 0x2, ++ PERFMON_COUNTER_MODE_DIRTY = 0x3, ++ PERFMON_COUNTER_MODE_SAMPLE = 0x4, ++ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, ++ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, ++ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, ++ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, ++ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, ++ PERFMON_COUNTER_MODE_RESERVED = 0xf, ++} PERFMON_COUNTER_MODE; ++typedef enum PERFMON_SPM_MODE { ++ PERFMON_SPM_MODE_OFF = 0x0, ++ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, ++ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, ++ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, ++ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, ++ PERFMON_SPM_MODE_RESERVED_5 = 0x5, ++ PERFMON_SPM_MODE_RESERVED_6 = 0x6, ++ PERFMON_SPM_MODE_RESERVED_7 = 0x7, ++ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, ++ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, ++ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, ++} PERFMON_SPM_MODE; ++typedef enum SurfaceTiling { ++ ARRAY_LINEAR = 0x0, ++ ARRAY_TILED = 0x1, ++} SurfaceTiling; ++typedef enum SurfaceArray { ++ ARRAY_1D = 0x0, ++ ARRAY_2D = 0x1, ++ ARRAY_3D = 0x2, ++ ARRAY_3D_SLICE = 0x3, ++} SurfaceArray; ++typedef enum ColorArray { ++ ARRAY_2D_ALT_COLOR = 0x0, ++ ARRAY_2D_COLOR = 0x1, ++ ARRAY_3D_SLICE_COLOR = 0x3, ++} ColorArray; ++typedef enum DepthArray { ++ ARRAY_2D_ALT_DEPTH = 0x0, ++ ARRAY_2D_DEPTH = 0x1, ++} DepthArray; ++typedef enum ENUM_NUM_SIMD_PER_CU { ++ NUM_SIMD_PER_CU = 0x4, ++} ENUM_NUM_SIMD_PER_CU; ++typedef enum MEM_PWR_FORCE_CTRL { ++ NO_FORCE_REQUEST = 0x0, ++ FORCE_LIGHT_SLEEP_REQUEST = 0x1, ++ FORCE_DEEP_SLEEP_REQUEST = 0x2, ++ FORCE_SHUT_DOWN_REQUEST = 0x3, ++} MEM_PWR_FORCE_CTRL; ++typedef enum MEM_PWR_FORCE_CTRL2 { ++ NO_FORCE_REQ = 0x0, ++ FORCE_LIGHT_SLEEP_REQ = 0x1, ++} MEM_PWR_FORCE_CTRL2; ++typedef enum MEM_PWR_DIS_CTRL { ++ ENABLE_MEM_PWR_CTRL = 0x0, ++ DISABLE_MEM_PWR_CTRL = 0x1, ++} MEM_PWR_DIS_CTRL; ++typedef enum MEM_PWR_SEL_CTRL { ++ DYNAMIC_SHUT_DOWN_ENABLE = 0x0, ++ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, ++ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, ++} MEM_PWR_SEL_CTRL; ++typedef enum MEM_PWR_SEL_CTRL2 { ++ DYNAMIC_DEEP_SLEEP_EN = 0x0, ++ DYNAMIC_LIGHT_SLEEP_EN = 0x1, ++} MEM_PWR_SEL_CTRL2; ++ ++#endif /* ACP_2_2_ENUM_H */ +diff --git a/sound/soc/amd/include/acp_2_2_sh_mask.h b/sound/soc/amd/include/acp_2_2_sh_mask.h +new file mode 100644 +index 0000000..32d2d41 +--- /dev/null ++++ b/sound/soc/amd/include/acp_2_2_sh_mask.h +@@ -0,0 +1,2292 @@ ++/* ++ * ACP_2_2 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef ACP_2_2_SH_MASK_H ++#define ACP_2_2_SH_MASK_H ++ ++#define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_1__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_1__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_1__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_1__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_1__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_1__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_1__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_1__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_1__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_1__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_2__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_2__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_2__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_2__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_2__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_2__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_2__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_2__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_2__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_2__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_3__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_3__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_3__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_3__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_3__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_3__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_3__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_3__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_3__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_3__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_4__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_4__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_4__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_4__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_4__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_4__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_4__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_4__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_4__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_4__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_5__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_5__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_5__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_5__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_5__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_5__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_5__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_5__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_5__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_5__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_6__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_6__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_6__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_6__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_6__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_6__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_6__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_6__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_6__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_6__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_7__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_7__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_7__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_7__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_7__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_7__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_7__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_7__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_7__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_7__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_8__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_8__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_8__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_8__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_8__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_8__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_8__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_8__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_8__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_8__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_9__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_9__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_9__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_9__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_9__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_9__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_9__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_9__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_9__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_9__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_10__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_10__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_10__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_10__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_10__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_10__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_10__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_10__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_10__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_10__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_11__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_11__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_11__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_11__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_11__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_11__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_11__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_11__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_11__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_11__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_12__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_12__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_12__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_12__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_12__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_12__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_12__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_12__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_12__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_12__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_13__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_13__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_13__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_13__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_13__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_13__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_13__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_13__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_13__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_13__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_14__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_14__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_14__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_14__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_14__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_14__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_14__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_14__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_14__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_14__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_CNTL_15__DMAChRst_MASK 0x1 ++#define ACP_DMA_CNTL_15__DMAChRst__SHIFT 0x0 ++#define ACP_DMA_CNTL_15__DMAChRun_MASK 0x2 ++#define ACP_DMA_CNTL_15__DMAChRun__SHIFT 0x1 ++#define ACP_DMA_CNTL_15__DMAChIOCEn_MASK 0x4 ++#define ACP_DMA_CNTL_15__DMAChIOCEn__SHIFT 0x2 ++#define ACP_DMA_CNTL_15__Circular_DMA_En_MASK 0x8 ++#define ACP_DMA_CNTL_15__Circular_DMA_En__SHIFT 0x3 ++#define ACP_DMA_CNTL_15__DMAChGracefulRstEn_MASK 0x10 ++#define ACP_DMA_CNTL_15__DMAChGracefulRstEn__SHIFT 0x4 ++#define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx_MASK 0x3ff ++#define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt_MASK 0x3ff ++#define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt__SHIFT 0x0 ++#define ACP_DMA_PRIO_0__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_0__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_1__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_1__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_2__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_2__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_3__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_3__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_4__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_4__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_5__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_5__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_6__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_6__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_7__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_7__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_8__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_8__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_9__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_9__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_10__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_10__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_11__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_11__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_12__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_12__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_13__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_13__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_14__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_14__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_PRIO_15__DMAChPrioLvl_MASK 0x1 ++#define ACP_DMA_PRIO_15__DMAChPrioLvl__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx_MASK 0x3ff ++#define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt_MASK 0x1ffff ++#define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_0__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_0__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_0__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_0__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_1__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_1__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_1__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_1__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_2__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_2__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_2__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_2__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_3__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_3__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_3__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_3__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_4__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_4__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_4__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_4__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_5__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_5__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_5__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_5__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_6__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_6__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_6__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_6__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_7__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_7__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_7__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_7__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_8__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_8__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_8__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_8__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_9__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_9__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_9__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_9__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_10__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_10__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_10__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_10__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_11__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_11__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_11__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_11__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_12__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_12__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_12__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_12__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_13__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_13__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_13__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_13__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_14__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_14__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_14__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_14__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_ERR_STS_15__DMAChTermErr_MASK 0x1 ++#define ACP_DMA_ERR_STS_15__DMAChTermErr__SHIFT 0x0 ++#define ACP_DMA_ERR_STS_15__DMAChErrCode_MASK 0x1e ++#define ACP_DMA_ERR_STS_15__DMAChErrCode__SHIFT 0x1 ++#define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr_MASK 0xffffffff ++#define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr__SHIFT 0x0 ++#define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr_MASK 0xf ++#define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr__SHIFT 0x0 ++#define ACP_DMA_CH_STS__DMAChSts_MASK 0xffff ++#define ACP_DMA_CH_STS__DMAChSts__SHIFT 0x0 ++#define ACP_DMA_CH_GROUP__DMAChanelGrouping_MASK 0x1 ++#define ACP_DMA_CH_GROUP__DMAChanelGrouping__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET0__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET0__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE0__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE0__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE0__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE0__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET1__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET1__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE1__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE1__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE1__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE1__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET2__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET2__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE2__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE2__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE2__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE2__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET3__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET3__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE3__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE3__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE3__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE3__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET4__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET4__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE4__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE4__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE4__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE4__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET5__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET5__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE5__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE5__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE5__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE5__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET6__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET6__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE6__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE6__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE6__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE6__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET7__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET7__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE7__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE7__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE7__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE7__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_CACHE_OFFSET8__Offset_MASK 0xfffffff ++#define ACP_DSP0_CACHE_OFFSET8__Offset__SHIFT 0x0 ++#define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_CACHE_SIZE8__Size_MASK 0xffffff ++#define ACP_DSP0_CACHE_SIZE8__Size__SHIFT 0x0 ++#define ACP_DSP0_CACHE_SIZE8__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_CACHE_SIZE8__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_NONCACHE_OFFSET0__Offset_MASK 0xfffffff ++#define ACP_DSP0_NONCACHE_OFFSET0__Offset__SHIFT 0x0 ++#define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_NONCACHE_SIZE0__Size_MASK 0xffffff ++#define ACP_DSP0_NONCACHE_SIZE0__Size__SHIFT 0x0 ++#define ACP_DSP0_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_NONCACHE_OFFSET1__Offset_MASK 0xfffffff ++#define ACP_DSP0_NONCACHE_OFFSET1__Offset__SHIFT 0x0 ++#define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP0_NONCACHE_SIZE1__Size_MASK 0xffffff ++#define ACP_DSP0_NONCACHE_SIZE1__Size__SHIFT 0x0 ++#define ACP_DSP0_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 ++#define ACP_DSP0_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f ++#define ACP_DSP0_DEBUG_PC__DebugPC_MASK 0xffffffff ++#define ACP_DSP0_DEBUG_PC__DebugPC__SHIFT 0x0 ++#define ACP_DSP0_NMI_SEL__NMISel_MASK 0x1 ++#define ACP_DSP0_NMI_SEL__NMISel__SHIFT 0x0 ++#define ACP_DSP0_CLKRST_CNTL__ClkEn_MASK 0x1 ++#define ACP_DSP0_CLKRST_CNTL__ClkEn__SHIFT 0x0 ++#define ACP_DSP0_CLKRST_CNTL__SoftResetDSP_MASK 0x2 ++#define ACP_DSP0_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 ++#define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 ++#define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 ++#define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 ++#define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 ++#define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 ++#define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 ++#define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 ++#define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 ++#define ACP_DSP0_RUNSTALL__RunStallCntl_MASK 0x1 ++#define ACP_DSP0_RUNSTALL__RunStallCntl__SHIFT 0x0 ++#define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 ++#define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 ++#define ACP_DSP0_WAIT_MODE__WaitMode_MASK 0x1 ++#define ACP_DSP0_WAIT_MODE__WaitMode__SHIFT 0x0 ++#define ACP_DSP0_VECT_SEL__StaticVectorSel_MASK 0x1 ++#define ACP_DSP0_VECT_SEL__StaticVectorSel__SHIFT 0x0 ++#define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff ++#define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 ++#define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff ++#define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 ++#define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff ++#define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET0__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET0__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE0__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE0__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE0__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE0__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET1__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET1__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE1__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE1__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE1__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE1__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET2__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET2__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE2__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE2__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE2__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE2__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET3__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET3__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE3__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE3__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE3__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE3__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET4__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET4__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE4__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE4__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE4__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE4__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET5__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET5__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE5__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE5__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE5__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE5__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET6__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET6__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE6__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE6__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE6__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE6__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET7__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET7__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE7__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE7__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE7__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE7__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_CACHE_OFFSET8__Offset_MASK 0xfffffff ++#define ACP_DSP1_CACHE_OFFSET8__Offset__SHIFT 0x0 ++#define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_CACHE_SIZE8__Size_MASK 0xffffff ++#define ACP_DSP1_CACHE_SIZE8__Size__SHIFT 0x0 ++#define ACP_DSP1_CACHE_SIZE8__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_CACHE_SIZE8__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_NONCACHE_OFFSET0__Offset_MASK 0xfffffff ++#define ACP_DSP1_NONCACHE_OFFSET0__Offset__SHIFT 0x0 ++#define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_NONCACHE_SIZE0__Size_MASK 0xffffff ++#define ACP_DSP1_NONCACHE_SIZE0__Size__SHIFT 0x0 ++#define ACP_DSP1_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_NONCACHE_OFFSET1__Offset_MASK 0xfffffff ++#define ACP_DSP1_NONCACHE_OFFSET1__Offset__SHIFT 0x0 ++#define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP1_NONCACHE_SIZE1__Size_MASK 0xffffff ++#define ACP_DSP1_NONCACHE_SIZE1__Size__SHIFT 0x0 ++#define ACP_DSP1_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 ++#define ACP_DSP1_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f ++#define ACP_DSP1_DEBUG_PC__DebugPC_MASK 0xffffffff ++#define ACP_DSP1_DEBUG_PC__DebugPC__SHIFT 0x0 ++#define ACP_DSP1_NMI_SEL__NMISel_MASK 0x1 ++#define ACP_DSP1_NMI_SEL__NMISel__SHIFT 0x0 ++#define ACP_DSP1_CLKRST_CNTL__ClkEn_MASK 0x1 ++#define ACP_DSP1_CLKRST_CNTL__ClkEn__SHIFT 0x0 ++#define ACP_DSP1_CLKRST_CNTL__SoftResetDSP_MASK 0x2 ++#define ACP_DSP1_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 ++#define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 ++#define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 ++#define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 ++#define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 ++#define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 ++#define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 ++#define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 ++#define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 ++#define ACP_DSP1_RUNSTALL__RunStallCntl_MASK 0x1 ++#define ACP_DSP1_RUNSTALL__RunStallCntl__SHIFT 0x0 ++#define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 ++#define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 ++#define ACP_DSP1_WAIT_MODE__WaitMode_MASK 0x1 ++#define ACP_DSP1_WAIT_MODE__WaitMode__SHIFT 0x0 ++#define ACP_DSP1_VECT_SEL__StaticVectorSel_MASK 0x1 ++#define ACP_DSP1_VECT_SEL__StaticVectorSel__SHIFT 0x0 ++#define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff ++#define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 ++#define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff ++#define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 ++#define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff ++#define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET0__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET0__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE0__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE0__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE0__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE0__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET1__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET1__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE1__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE1__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE1__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE1__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET2__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET2__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE2__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE2__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE2__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE2__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET3__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET3__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE3__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE3__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE3__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE3__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET4__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET4__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE4__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE4__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE4__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE4__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET5__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET5__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE5__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE5__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE5__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE5__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET6__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET6__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE6__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE6__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE6__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE6__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET7__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET7__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE7__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE7__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE7__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE7__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_CACHE_OFFSET8__Offset_MASK 0xfffffff ++#define ACP_DSP2_CACHE_OFFSET8__Offset__SHIFT 0x0 ++#define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_CACHE_SIZE8__Size_MASK 0xffffff ++#define ACP_DSP2_CACHE_SIZE8__Size__SHIFT 0x0 ++#define ACP_DSP2_CACHE_SIZE8__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_CACHE_SIZE8__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_NONCACHE_OFFSET0__Offset_MASK 0xfffffff ++#define ACP_DSP2_NONCACHE_OFFSET0__Offset__SHIFT 0x0 ++#define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_NONCACHE_SIZE0__Size_MASK 0xffffff ++#define ACP_DSP2_NONCACHE_SIZE0__Size__SHIFT 0x0 ++#define ACP_DSP2_NONCACHE_SIZE0__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_NONCACHE_OFFSET1__Offset_MASK 0xfffffff ++#define ACP_DSP2_NONCACHE_OFFSET1__Offset__SHIFT 0x0 ++#define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000 ++#define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f ++#define ACP_DSP2_NONCACHE_SIZE1__Size_MASK 0xffffff ++#define ACP_DSP2_NONCACHE_SIZE1__Size__SHIFT 0x0 ++#define ACP_DSP2_NONCACHE_SIZE1__PageEnable_MASK 0x80000000 ++#define ACP_DSP2_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f ++#define ACP_DSP2_DEBUG_PC__DebugPC_MASK 0xffffffff ++#define ACP_DSP2_DEBUG_PC__DebugPC__SHIFT 0x0 ++#define ACP_DSP2_NMI_SEL__NMISel_MASK 0x1 ++#define ACP_DSP2_NMI_SEL__NMISel__SHIFT 0x0 ++#define ACP_DSP2_CLKRST_CNTL__ClkEn_MASK 0x1 ++#define ACP_DSP2_CLKRST_CNTL__ClkEn__SHIFT 0x0 ++#define ACP_DSP2_CLKRST_CNTL__SoftResetDSP_MASK 0x2 ++#define ACP_DSP2_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1 ++#define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4 ++#define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2 ++#define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8 ++#define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3 ++#define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10 ++#define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4 ++#define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status_MASK 0x20 ++#define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5 ++#define ACP_DSP2_RUNSTALL__RunStallCntl_MASK 0x1 ++#define ACP_DSP2_RUNSTALL__RunStallCntl__SHIFT 0x0 ++#define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1 ++#define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0 ++#define ACP_DSP2_WAIT_MODE__WaitMode_MASK 0x1 ++#define ACP_DSP2_WAIT_MODE__WaitMode__SHIFT 0x0 ++#define ACP_DSP2_VECT_SEL__StaticVectorSel_MASK 0x1 ++#define ACP_DSP2_VECT_SEL__StaticVectorSel__SHIFT 0x0 ++#define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff ++#define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0 ++#define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff ++#define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0 ++#define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff ++#define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap_MASK 0x3 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap__SHIFT 0x0 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb_MASK 0x80 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb__SHIFT 0x7 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb_MASK 0x100 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb_MASK 0x400 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode_MASK 0x2000 ++#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode__SHIFT 0xd ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000 ++#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f ++#define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1 ++#define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0 ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap_MASK 0x3 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap__SHIFT 0x0 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb_MASK 0x80 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb__SHIFT 0x7 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb_MASK 0x100 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb_MASK 0x400 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode_MASK 0x2000 ++#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode__SHIFT 0xd ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000 ++#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f ++#define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1 ++#define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0 ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0 ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000 ++#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize_MASK 0x3 ++#define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr_MASK 0xfffffff ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr__SHIFT 0x0 ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel_MASK 0x20000000 ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel__SHIFT 0x1d ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel_MASK 0x40000000 ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel__SHIFT 0x1e ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable_MASK 0x80000000 ++#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable__SHIFT 0x1f ++#define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate_MASK 0x1 ++#define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate__SHIFT 0x0 ++#define ACP_CONTROL__ClkEn_MASK 0x1 ++#define ACP_CONTROL__ClkEn__SHIFT 0x0 ++#define ACP_CONTROL__JtagEn_MASK 0x400 ++#define ACP_CONTROL__JtagEn__SHIFT 0xa ++#define ACP_STATUS__ClkOn_MASK 0x1 ++#define ACP_STATUS__ClkOn__SHIFT 0x0 ++#define ACP_STATUS__ACPRefClkSpd_MASK 0x2 ++#define ACP_STATUS__ACPRefClkSpd__SHIFT 0x1 ++#define ACP_STATUS__SMUStutterLastEdge_MASK 0x4 ++#define ACP_STATUS__SMUStutterLastEdge__SHIFT 0x2 ++#define ACP_STATUS__MCStutterLastEdge_MASK 0x8 ++#define ACP_STATUS__MCStutterLastEdge__SHIFT 0x3 ++#define ACP_SOFT_RESET__SoftResetAud_MASK 0x100 ++#define ACP_SOFT_RESET__SoftResetAud__SHIFT 0x8 ++#define ACP_SOFT_RESET__SoftResetDMA_MASK 0x200 ++#define ACP_SOFT_RESET__SoftResetDMA__SHIFT 0x9 ++#define ACP_SOFT_RESET__InternalSoftResetMode_MASK 0x4000 ++#define ACP_SOFT_RESET__InternalSoftResetMode__SHIFT 0xe ++#define ACP_SOFT_RESET__ExternalSoftResetMode_MASK 0x8000 ++#define ACP_SOFT_RESET__ExternalSoftResetMode__SHIFT 0xf ++#define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000 ++#define ACP_SOFT_RESET__SoftResetAudDone__SHIFT 0x18 ++#define ACP_SOFT_RESET__SoftResetDMADone_MASK 0x2000000 ++#define ACP_SOFT_RESET__SoftResetDMADone__SHIFT 0x19 ++#define ACP_PwrMgmt_CNTL__SCLKSleepCntl_MASK 0x3 ++#define ACP_PwrMgmt_CNTL__SCLKSleepCntl__SHIFT 0x0 ++#define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter_MASK 0xffff ++#define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter__SHIFT 0x0 ++#define ACP_SMU_MAILBOX__ACP_SMU_Mailbox_MASK 0xffffffff ++#define ACP_SMU_MAILBOX__ACP_SMU_Mailbox__SHIFT 0x0 ++#define ACP_FUTURE_REG_SCLK_0__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_SCLK_0__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_SCLK_1__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_SCLK_1__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_SCLK_2__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_SCLK_2__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_SCLK_3__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_SCLK_3__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_SCLK_4__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_SCLK_4__ACPFutureReg__SHIFT 0x0 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable_MASK 0x1 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable__SHIFT 0x0 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable_MASK 0x2 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable__SHIFT 0x1 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable_MASK 0x4 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable__SHIFT 0x2 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable_MASK 0x8 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable__SHIFT 0x3 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable_MASK 0x10 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable__SHIFT 0x4 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable_MASK 0x20 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable__SHIFT 0x5 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable_MASK 0x40 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable__SHIFT 0x6 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable_MASK 0x80 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable__SHIFT 0x7 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable_MASK 0x100 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable__SHIFT 0x8 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable_MASK 0x200 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable__SHIFT 0x9 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable_MASK 0x400 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable__SHIFT 0xa ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable_MASK 0x800 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable__SHIFT 0xb ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable_MASK 0x1000 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable__SHIFT 0xc ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable_MASK 0x2000 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable__SHIFT 0xd ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable_MASK 0x4000 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable__SHIFT 0xe ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable_MASK 0x8000 ++#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable__SHIFT 0xf ++#define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt_MASK 0xffff ++#define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt__SHIFT 0x0 ++#define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt_MASK 0xffff ++#define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt__SHIFT 0x0 ++#define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt_MASK 0xffff ++#define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt_MASK 0xffff ++#define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt_MASK 0xffff ++#define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt__SHIFT 0x0 ++#define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt_MASK 0xffff ++#define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt__SHIFT 0x0 ++#define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt_MASK 0xffff ++#define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt_MASK 0xffff ++#define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt_MASK 0xffff ++#define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt__SHIFT 0x0 ++#define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt_MASK 0xffff ++#define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt__SHIFT 0x0 ++#define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt_MASK 0xffff ++#define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt_MASK 0xffff ++#define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt_MASK 0xffff ++#define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt__SHIFT 0x0 ++#define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt_MASK 0xffff ++#define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt__SHIFT 0x0 ++#define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt_MASK 0xffff ++#define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt__SHIFT 0x0 ++#define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt_MASK 0xffff ++#define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt__SHIFT 0x0 ++#define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl_MASK 0xf ++#define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl__SHIFT 0x0 ++#define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb_MASK 0x1 ++#define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb__SHIFT 0x0 ++#define ACP_EXTERNAL_INTR_CNTL__ACPErrMask_MASK 0x1 ++#define ACP_EXTERNAL_INTR_CNTL__ACPErrMask__SHIFT 0x0 ++#define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 ++#define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 ++#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 ++#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 ++#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 ++#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 ++#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 ++#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 ++#define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask_MASK 0x40 ++#define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 ++#define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask_MASK 0x100 ++#define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask__SHIFT 0x8 ++#define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask_MASK 0x200 ++#define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask__SHIFT 0x9 ++#define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask_MASK 0x400 ++#define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask__SHIFT 0xa ++#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x800 ++#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xb ++#define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 ++#define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask__SHIFT 0x10 ++#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr_MASK 0x1 ++#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr__SHIFT 0x0 ++#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource_MASK 0xe ++#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource__SHIFT 0x1 ++#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver_MASK 0x10 ++#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver__SHIFT 0x4 ++#define ACP_ERROR_SOURCE_STS__BRBAddrErr_MASK 0x20 ++#define ACP_ERROR_SOURCE_STS__BRBAddrErr__SHIFT 0x5 ++#define ACP_ERROR_SOURCE_STS__BRBAddrErrSource_MASK 0x3c0 ++#define ACP_ERROR_SOURCE_STS__BRBAddrErrSource__SHIFT 0x6 ++#define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver_MASK 0x400 ++#define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver__SHIFT 0xa ++#define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr_MASK 0x800 ++#define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr__SHIFT 0xb ++#define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr_MASK 0x1000 ++#define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr__SHIFT 0xc ++#define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr_MASK 0x2000 ++#define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr__SHIFT 0xd ++#define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr_MASK 0x4000 ++#define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr__SHIFT 0xe ++#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr_MASK 0x8000 ++#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr__SHIFT 0xf ++#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource_MASK 0x70000 ++#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource__SHIFT 0x10 ++#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver_MASK 0x80000 ++#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver__SHIFT 0x13 ++#define ACP_ERROR_SOURCE_STS__DAGBErr_MASK 0x100000 ++#define ACP_ERROR_SOURCE_STS__DAGBErr__SHIFT 0x14 ++#define ACP_ERROR_SOURCE_STS__DAGBErrSource_MASK 0x1e00000 ++#define ACP_ERROR_SOURCE_STS__DAGBErrSource__SHIFT 0x15 ++#define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver_MASK 0x2000000 ++#define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver__SHIFT 0x19 ++#define ACP_ERROR_SOURCE_STS__DMATermOnErr_MASK 0x4000000 ++#define ACP_ERROR_SOURCE_STS__DMATermOnErr__SHIFT 0x1a ++#define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr_MASK 0x10000000 ++#define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr__SHIFT 0x1c ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0_MASK 0x1 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0__SHIFT 0x0 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1_MASK 0x2 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1__SHIFT 0x1 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2_MASK 0x4 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2__SHIFT 0x2 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0_MASK 0x100 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0__SHIFT 0x8 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1_MASK 0x200 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1__SHIFT 0x9 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2_MASK 0x400 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2__SHIFT 0xa ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host_MASK 0x10000 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host__SHIFT 0x10 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host_MASK 0x20000 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host__SHIFT 0x11 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host_MASK 0x40000 ++#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host__SHIFT 0x12 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0_MASK 0x1 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0__SHIFT 0x0 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1_MASK 0x2 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1__SHIFT 0x1 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2_MASK 0x4 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2__SHIFT 0x2 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0_MASK 0x100 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0__SHIFT 0x8 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1_MASK 0x200 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1__SHIFT 0x9 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2_MASK 0x400 ++#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2__SHIFT 0xa ++#define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask_MASK 0x10000 ++#define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask__SHIFT 0x10 ++#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask_MASK 0x20000 ++#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask__SHIFT 0x11 ++#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask_MASK 0x40000 ++#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask__SHIFT 0x12 ++#define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue_MASK 0x3ffff ++#define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue__SHIFT 0x0 ++#define ACP_DAGBG_TIMEOUT_CNTL__CntEn_MASK 0x80000000 ++#define ACP_DAGBG_TIMEOUT_CNTL__CntEn__SHIFT 0x1f ++#define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue_MASK 0x3ffff ++#define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue__SHIFT 0x0 ++#define ACP_DAGBO_TIMEOUT_CNTL__CntEn_MASK 0x80000000 ++#define ACP_DAGBO_TIMEOUT_CNTL__CntEn__SHIFT 0x1f ++#define ACP_EXTERNAL_INTR_STAT__ACPErrStat_MASK 0x1 ++#define ACP_EXTERNAL_INTR_STAT__ACPErrStat__SHIFT 0x0 ++#define ACP_EXTERNAL_INTR_STAT__ACPErrAck_MASK 0x1 ++#define ACP_EXTERNAL_INTR_STAT__ACPErrAck__SHIFT 0x0 ++#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat_MASK 0x2 ++#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 ++#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck_MASK 0x2 ++#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 ++#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat_MASK 0x10 ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck_MASK 0x10 ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 ++#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat_MASK 0x40 ++#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 ++#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck_MASK 0x40 ++#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 ++#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat_MASK 0x100 ++#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat__SHIFT 0x8 ++#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck_MASK 0x100 ++#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck__SHIFT 0x8 ++#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat_MASK 0x200 ++#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat__SHIFT 0x9 ++#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck_MASK 0x200 ++#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck__SHIFT 0x9 ++#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat_MASK 0x400 ++#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat__SHIFT 0xa ++#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck_MASK 0x400 ++#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck__SHIFT 0xa ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat_MASK 0x800 ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xb ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck_MASK 0x800 ++#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xb ++#define ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK 0xffff0000 ++#define ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT 0x10 ++#define ACP_EXTERNAL_INTR_STAT__DMAIOCAck_MASK 0xffff0000 ++#define ACP_EXTERNAL_INTR_STAT__DMAIOCAck__SHIFT 0x10 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat_MASK 0x1 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat__SHIFT 0x0 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack_MASK 0x1 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack__SHIFT 0x0 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat_MASK 0x2 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat__SHIFT 0x1 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack_MASK 0x2 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack__SHIFT 0x1 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat_MASK 0x4 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat__SHIFT 0x2 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack_MASK 0x4 ++#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack__SHIFT 0x2 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat_MASK 0x100 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat__SHIFT 0x8 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack_MASK 0x100 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack__SHIFT 0x8 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat_MASK 0x200 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat__SHIFT 0x9 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack_MASK 0x200 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack__SHIFT 0x9 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat_MASK 0x400 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat__SHIFT 0xa ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack_MASK 0x400 ++#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack__SHIFT 0xa ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat_MASK 0x10000 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat__SHIFT 0x10 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack_MASK 0x10000 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack__SHIFT 0x10 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat_MASK 0x20000 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat__SHIFT 0x11 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack_MASK 0x20000 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack__SHIFT 0x11 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat_MASK 0x40000 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat__SHIFT 0x12 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack_MASK 0x40000 ++#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack__SHIFT 0x12 ++#define ACP_DSP0_INTR_CNTL__ACPErrMask_MASK 0x1 ++#define ACP_DSP0_INTR_CNTL__ACPErrMask__SHIFT 0x0 ++#define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 ++#define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 ++#define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 ++#define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 ++#define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 ++#define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 ++#define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 ++#define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 ++#define ACP_DSP0_INTR_CNTL__AzaliaIntrMask_MASK 0x40 ++#define ACP_DSP0_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 ++#define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 ++#define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 ++#define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 ++#define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 ++#define ACP_DSP0_INTR_CNTL__MCStutterStatusMask_MASK 0x400 ++#define ACP_DSP0_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa ++#define ACP_DSP0_INTR_CNTL__DSPExtTimerMask_MASK 0x800 ++#define ACP_DSP0_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb ++#define ACP_DSP0_INTR_CNTL__DSPSemRespMask_MASK 0x1000 ++#define ACP_DSP0_INTR_CNTL__DSPSemRespMask__SHIFT 0xc ++#define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 ++#define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd ++#define ACP_DSP0_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 ++#define ACP_DSP0_INTR_CNTL__DMAIOCMask__SHIFT 0x10 ++#define ACP_DSP0_INTR_STAT__ACPErrStat_MASK 0x1 ++#define ACP_DSP0_INTR_STAT__ACPErrStat__SHIFT 0x0 ++#define ACP_DSP0_INTR_STAT__ACPErrAck_MASK 0x1 ++#define ACP_DSP0_INTR_STAT__ACPErrAck__SHIFT 0x0 ++#define ACP_DSP0_INTR_STAT__I2SMicDataAvStat_MASK 0x2 ++#define ACP_DSP0_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 ++#define ACP_DSP0_INTR_STAT__I2SMicDataAvAck_MASK 0x2 ++#define ACP_DSP0_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 ++#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 ++#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 ++#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 ++#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 ++#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 ++#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 ++#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 ++#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 ++#define ACP_DSP0_INTR_STAT__I2SBTDataAvStat_MASK 0x10 ++#define ACP_DSP0_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 ++#define ACP_DSP0_INTR_STAT__I2SBTDataAvAck_MASK 0x10 ++#define ACP_DSP0_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 ++#define ACP_DSP0_INTR_STAT__AzaliaIntrStat_MASK 0x40 ++#define ACP_DSP0_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 ++#define ACP_DSP0_INTR_STAT__AzaliaIntrAck_MASK 0x40 ++#define ACP_DSP0_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 ++#define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 ++#define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 ++#define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 ++#define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 ++#define ACP_DSP0_INTR_STAT__SMUStutterStatusStat_MASK 0x200 ++#define ACP_DSP0_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 ++#define ACP_DSP0_INTR_STAT__SMUStutterStatusAck_MASK 0x200 ++#define ACP_DSP0_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 ++#define ACP_DSP0_INTR_STAT__MCStutterStatusStat_MASK 0x400 ++#define ACP_DSP0_INTR_STAT__MCStutterStatusStat__SHIFT 0xa ++#define ACP_DSP0_INTR_STAT__MCStutterStatusAck_MASK 0x400 ++#define ACP_DSP0_INTR_STAT__MCStutterStatusAck__SHIFT 0xa ++#define ACP_DSP0_INTR_STAT__DSPExtTimerStat_MASK 0x800 ++#define ACP_DSP0_INTR_STAT__DSPExtTimerStat__SHIFT 0xb ++#define ACP_DSP0_INTR_STAT__DSPExtTimerAck_MASK 0x800 ++#define ACP_DSP0_INTR_STAT__DSPExtTimerAck__SHIFT 0xb ++#define ACP_DSP0_INTR_STAT__DSPSemRespStat_MASK 0x1000 ++#define ACP_DSP0_INTR_STAT__DSPSemRespStat__SHIFT 0xc ++#define ACP_DSP0_INTR_STAT__DSPSemRespAck_MASK 0x1000 ++#define ACP_DSP0_INTR_STAT__DSPSemRespAck__SHIFT 0xc ++#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 ++#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd ++#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 ++#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd ++#define ACP_DSP0_INTR_STAT__DMAIOCStat_MASK 0xffff0000 ++#define ACP_DSP0_INTR_STAT__DMAIOCStat__SHIFT 0x10 ++#define ACP_DSP0_INTR_STAT__DMAIOCAck_MASK 0xffff0000 ++#define ACP_DSP0_INTR_STAT__DMAIOCAck__SHIFT 0x10 ++#define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue_MASK 0x3ffff ++#define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue__SHIFT 0x0 ++#define ACP_DSP0_TIMEOUT_CNTL__CntEn_MASK 0x80000000 ++#define ACP_DSP0_TIMEOUT_CNTL__CntEn__SHIFT 0x1f ++#define ACP_DSP1_INTR_CNTL__ACPErrMask_MASK 0x1 ++#define ACP_DSP1_INTR_CNTL__ACPErrMask__SHIFT 0x0 ++#define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 ++#define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 ++#define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 ++#define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 ++#define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 ++#define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 ++#define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 ++#define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 ++#define ACP_DSP1_INTR_CNTL__AzaliaIntrMask_MASK 0x40 ++#define ACP_DSP1_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 ++#define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 ++#define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 ++#define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 ++#define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 ++#define ACP_DSP1_INTR_CNTL__MCStutterStatusMask_MASK 0x400 ++#define ACP_DSP1_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa ++#define ACP_DSP1_INTR_CNTL__DSPExtTimerMask_MASK 0x800 ++#define ACP_DSP1_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb ++#define ACP_DSP1_INTR_CNTL__DSPSemRespMask_MASK 0x1000 ++#define ACP_DSP1_INTR_CNTL__DSPSemRespMask__SHIFT 0xc ++#define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 ++#define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd ++#define ACP_DSP1_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 ++#define ACP_DSP1_INTR_CNTL__DMAIOCMask__SHIFT 0x10 ++#define ACP_DSP1_INTR_STAT__ACPErrStat_MASK 0x1 ++#define ACP_DSP1_INTR_STAT__ACPErrStat__SHIFT 0x0 ++#define ACP_DSP1_INTR_STAT__ACPErrAck_MASK 0x1 ++#define ACP_DSP1_INTR_STAT__ACPErrAck__SHIFT 0x0 ++#define ACP_DSP1_INTR_STAT__I2SMicDataAvStat_MASK 0x2 ++#define ACP_DSP1_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 ++#define ACP_DSP1_INTR_STAT__I2SMicDataAvAck_MASK 0x2 ++#define ACP_DSP1_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 ++#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 ++#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 ++#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 ++#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 ++#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 ++#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 ++#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 ++#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 ++#define ACP_DSP1_INTR_STAT__I2SBTDataAvStat_MASK 0x10 ++#define ACP_DSP1_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 ++#define ACP_DSP1_INTR_STAT__I2SBTDataAvAck_MASK 0x10 ++#define ACP_DSP1_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 ++#define ACP_DSP1_INTR_STAT__AzaliaIntrStat_MASK 0x40 ++#define ACP_DSP1_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 ++#define ACP_DSP1_INTR_STAT__AzaliaIntrAck_MASK 0x40 ++#define ACP_DSP1_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 ++#define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 ++#define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 ++#define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 ++#define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 ++#define ACP_DSP1_INTR_STAT__SMUStutterStatusStat_MASK 0x200 ++#define ACP_DSP1_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 ++#define ACP_DSP1_INTR_STAT__SMUStutterStatusAck_MASK 0x200 ++#define ACP_DSP1_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 ++#define ACP_DSP1_INTR_STAT__MCStutterStatusStat_MASK 0x400 ++#define ACP_DSP1_INTR_STAT__MCStutterStatusStat__SHIFT 0xa ++#define ACP_DSP1_INTR_STAT__MCStutterStatusAck_MASK 0x400 ++#define ACP_DSP1_INTR_STAT__MCStutterStatusAck__SHIFT 0xa ++#define ACP_DSP1_INTR_STAT__DSPExtTimerStat_MASK 0x800 ++#define ACP_DSP1_INTR_STAT__DSPExtTimerStat__SHIFT 0xb ++#define ACP_DSP1_INTR_STAT__DSPExtTimerAck_MASK 0x800 ++#define ACP_DSP1_INTR_STAT__DSPExtTimerAck__SHIFT 0xb ++#define ACP_DSP1_INTR_STAT__DSPSemRespStat_MASK 0x1000 ++#define ACP_DSP1_INTR_STAT__DSPSemRespStat__SHIFT 0xc ++#define ACP_DSP1_INTR_STAT__DSPSemRespAck_MASK 0x1000 ++#define ACP_DSP1_INTR_STAT__DSPSemRespAck__SHIFT 0xc ++#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 ++#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd ++#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 ++#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd ++#define ACP_DSP1_INTR_STAT__DMAIOCStat_MASK 0xffff0000 ++#define ACP_DSP1_INTR_STAT__DMAIOCStat__SHIFT 0x10 ++#define ACP_DSP1_INTR_STAT__DMAIOCAck_MASK 0xffff0000 ++#define ACP_DSP1_INTR_STAT__DMAIOCAck__SHIFT 0x10 ++#define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue_MASK 0x3ffff ++#define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue__SHIFT 0x0 ++#define ACP_DSP1_TIMEOUT_CNTL__CntEn_MASK 0x80000000 ++#define ACP_DSP1_TIMEOUT_CNTL__CntEn__SHIFT 0x1f ++#define ACP_DSP2_INTR_CNTL__ACPErrMask_MASK 0x1 ++#define ACP_DSP2_INTR_CNTL__ACPErrMask__SHIFT 0x0 ++#define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask_MASK 0x2 ++#define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1 ++#define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4 ++#define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2 ++#define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8 ++#define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3 ++#define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask_MASK 0x10 ++#define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4 ++#define ACP_DSP2_INTR_CNTL__AzaliaIntrMask_MASK 0x40 ++#define ACP_DSP2_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6 ++#define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100 ++#define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8 ++#define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask_MASK 0x200 ++#define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9 ++#define ACP_DSP2_INTR_CNTL__MCStutterStatusMask_MASK 0x400 ++#define ACP_DSP2_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa ++#define ACP_DSP2_INTR_CNTL__DSPExtTimerMask_MASK 0x800 ++#define ACP_DSP2_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb ++#define ACP_DSP2_INTR_CNTL__DSPSemRespMask_MASK 0x1000 ++#define ACP_DSP2_INTR_CNTL__DSPSemRespMask__SHIFT 0xc ++#define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000 ++#define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd ++#define ACP_DSP2_INTR_CNTL__DMAIOCMask_MASK 0xffff0000 ++#define ACP_DSP2_INTR_CNTL__DMAIOCMask__SHIFT 0x10 ++#define ACP_DSP2_INTR_STAT__ACPErrStat_MASK 0x1 ++#define ACP_DSP2_INTR_STAT__ACPErrStat__SHIFT 0x0 ++#define ACP_DSP2_INTR_STAT__ACPErrAck_MASK 0x1 ++#define ACP_DSP2_INTR_STAT__ACPErrAck__SHIFT 0x0 ++#define ACP_DSP2_INTR_STAT__I2SMicDataAvStat_MASK 0x2 ++#define ACP_DSP2_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1 ++#define ACP_DSP2_INTR_STAT__I2SMicDataAvAck_MASK 0x2 ++#define ACP_DSP2_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1 ++#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4 ++#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2 ++#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4 ++#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2 ++#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8 ++#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3 ++#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8 ++#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3 ++#define ACP_DSP2_INTR_STAT__I2SBTDataAvStat_MASK 0x10 ++#define ACP_DSP2_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4 ++#define ACP_DSP2_INTR_STAT__I2SBTDataAvAck_MASK 0x10 ++#define ACP_DSP2_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4 ++#define ACP_DSP2_INTR_STAT__AzaliaIntrStat_MASK 0x40 ++#define ACP_DSP2_INTR_STAT__AzaliaIntrStat__SHIFT 0x6 ++#define ACP_DSP2_INTR_STAT__AzaliaIntrAck_MASK 0x40 ++#define ACP_DSP2_INTR_STAT__AzaliaIntrAck__SHIFT 0x6 ++#define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat_MASK 0x100 ++#define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8 ++#define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck_MASK 0x100 ++#define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8 ++#define ACP_DSP2_INTR_STAT__SMUStutterStatusStat_MASK 0x200 ++#define ACP_DSP2_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9 ++#define ACP_DSP2_INTR_STAT__SMUStutterStatusAck_MASK 0x200 ++#define ACP_DSP2_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9 ++#define ACP_DSP2_INTR_STAT__MCStutterStatusStat_MASK 0x400 ++#define ACP_DSP2_INTR_STAT__MCStutterStatusStat__SHIFT 0xa ++#define ACP_DSP2_INTR_STAT__MCStutterStatusAck_MASK 0x400 ++#define ACP_DSP2_INTR_STAT__MCStutterStatusAck__SHIFT 0xa ++#define ACP_DSP2_INTR_STAT__DSPExtTimerStat_MASK 0x800 ++#define ACP_DSP2_INTR_STAT__DSPExtTimerStat__SHIFT 0xb ++#define ACP_DSP2_INTR_STAT__DSPExtTimerAck_MASK 0x800 ++#define ACP_DSP2_INTR_STAT__DSPExtTimerAck__SHIFT 0xb ++#define ACP_DSP2_INTR_STAT__DSPSemRespStat_MASK 0x1000 ++#define ACP_DSP2_INTR_STAT__DSPSemRespStat__SHIFT 0xc ++#define ACP_DSP2_INTR_STAT__DSPSemRespAck_MASK 0x1000 ++#define ACP_DSP2_INTR_STAT__DSPSemRespAck__SHIFT 0xc ++#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000 ++#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd ++#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000 ++#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd ++#define ACP_DSP2_INTR_STAT__DMAIOCStat_MASK 0xffff0000 ++#define ACP_DSP2_INTR_STAT__DMAIOCStat__SHIFT 0x10 ++#define ACP_DSP2_INTR_STAT__DMAIOCAck_MASK 0xffff0000 ++#define ACP_DSP2_INTR_STAT__DMAIOCAck__SHIFT 0x10 ++#define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue_MASK 0x3ffff ++#define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue__SHIFT 0x0 ++#define ACP_DSP2_TIMEOUT_CNTL__CntEn_MASK 0x80000000 ++#define ACP_DSP2_TIMEOUT_CNTL__CntEn__SHIFT 0x1f ++#define ACP_DSP0_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff ++#define ACP_DSP0_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 ++#define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 ++#define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e ++#define ACP_DSP1_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff ++#define ACP_DSP1_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 ++#define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 ++#define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e ++#define ACP_DSP2_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff ++#define ACP_DSP2_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0 ++#define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000 ++#define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e ++#define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg_MASK 0x1 ++#define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg__SHIFT 0x0 ++#define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr_MASK 0xff ++#define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr__SHIFT 0x0 ++#define ACP_SRBM_Client_RDDATA__ReadData_MASK 0xffffffff ++#define ACP_SRBM_Client_RDDATA__ReadData__SHIFT 0x0 ++#define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts_MASK 0x1 ++#define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts__SHIFT 0x0 ++#define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr_MASK 0x7ffffff ++#define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr__SHIFT 0x0 ++#define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data_MASK 0xffffffff ++#define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data__SHIFT 0x0 ++#define ACP_SEMA_ADDR_LOW__ADDR_9_3_MASK 0x7f ++#define ACP_SEMA_ADDR_LOW__ADDR_9_3__SHIFT 0x0 ++#define ACP_SEMA_ADDR_HIGH__ADDR_39_10_MASK 0x3fffffff ++#define ACP_SEMA_ADDR_HIGH__ADDR_39_10__SHIFT 0x0 ++#define ACP_SEMA_CMD__REQ_CMD_MASK 0xf ++#define ACP_SEMA_CMD__REQ_CMD__SHIFT 0x0 ++#define ACP_SEMA_CMD__WR_PHASE_MASK 0x30 ++#define ACP_SEMA_CMD__WR_PHASE__SHIFT 0x4 ++#define ACP_SEMA_CMD__VMID_EN_MASK 0x80 ++#define ACP_SEMA_CMD__VMID_EN__SHIFT 0x7 ++#define ACP_SEMA_CMD__VMID_MASK 0xf00 ++#define ACP_SEMA_CMD__VMID__SHIFT 0x8 ++#define ACP_SEMA_CMD__ATC_MASK 0x1000 ++#define ACP_SEMA_CMD__ATC__SHIFT 0xc ++#define ACP_SEMA_STS__REQ_STS_MASK 0x3 ++#define ACP_SEMA_STS__REQ_STS__SHIFT 0x0 ++#define ACP_SEMA_STS__REQ_RESP_AVAIL_MASK 0x100 ++#define ACP_SEMA_STS__REQ_RESP_AVAIL__SHIFT 0x8 ++#define ACP_SEMA_REQ__ISSUE_POLL_REQ_MASK 0x1 ++#define ACP_SEMA_REQ__ISSUE_POLL_REQ__SHIFT 0x0 ++#define ACP_FW_STATUS__RUN_MASK 0x1 ++#define ACP_FW_STATUS__RUN__SHIFT 0x0 ++#define ACP_FUTURE_REG_ACLK_0__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_ACLK_0__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_ACLK_1__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_ACLK_1__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_ACLK_2__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_ACLK_2__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_ACLK_3__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_ACLK_3__ACPFutureReg__SHIFT 0x0 ++#define ACP_FUTURE_REG_ACLK_4__ACPFutureReg_MASK 0xffffffff ++#define ACP_FUTURE_REG_ACLK_4__ACPFutureReg__SHIFT 0x0 ++#define ACP_TIMER__ACP_Timer_count_MASK 0xffffffff ++#define ACP_TIMER__ACP_Timer_count__SHIFT 0x0 ++#define ACP_TIMER_CNTL__ACP_Timer_control_MASK 0x1 ++#define ACP_TIMER_CNTL__ACP_Timer_control__SHIFT 0x0 ++#define ACP_DSP0_TIMER__ACP_DSP0_timer_MASK 0xffffff ++#define ACP_DSP0_TIMER__ACP_DSP0_timer__SHIFT 0x0 ++#define ACP_DSP1_TIMER__ACP_DSP1_timer_MASK 0xffffff ++#define ACP_DSP1_TIMER__ACP_DSP1_timer__SHIFT 0x0 ++#define ACP_DSP2_TIMER__ACP_DSP2_timer_MASK 0xffffff ++#define ACP_DSP2_TIMER__ACP_DSP2_timer__SHIFT 0x0 ++#define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high_MASK 0xffffffff ++#define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high__SHIFT 0x0 ++#define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low_MASK 0xffffffff ++#define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low__SHIFT 0x0 ++#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high_MASK 0xffffffff ++#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high__SHIFT 0x0 ++#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low_MASK 0xffffffff ++#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low__SHIFT 0x0 ++#define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high_MASK 0xffffffff ++#define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high__SHIFT 0x0 ++#define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low_MASK 0xffffffff ++#define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low__SHIFT 0x0 ++#define ACP_DSP0_CS_STATE__DSP0_CS_state_MASK 0x1 ++#define ACP_DSP0_CS_STATE__DSP0_CS_state__SHIFT 0x0 ++#define ACP_DSP1_CS_STATE__DSP1_CS_state_MASK 0x1 ++#define ACP_DSP1_CS_STATE__DSP1_CS_state__SHIFT 0x0 ++#define ACP_DSP2_CS_STATE__DSP2_CS_state_MASK 0x1 ++#define ACP_DSP2_CS_STATE__DSP2_CS_state__SHIFT 0x0 ++#define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR_MASK 0x7ffff ++#define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR__SHIFT 0x0 ++#define CC_ACP_EFUSE__DSP0_DISABLE_MASK 0x2 ++#define CC_ACP_EFUSE__DSP0_DISABLE__SHIFT 0x1 ++#define CC_ACP_EFUSE__DSP1_DISABLE_MASK 0x4 ++#define CC_ACP_EFUSE__DSP1_DISABLE__SHIFT 0x2 ++#define CC_ACP_EFUSE__DSP2_DISABLE_MASK 0x8 ++#define CC_ACP_EFUSE__DSP2_DISABLE__SHIFT 0x3 ++#define CC_ACP_EFUSE__ACP_DISABLE_MASK 0x10 ++#define CC_ACP_EFUSE__ACP_DISABLE__SHIFT 0x4 ++#define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF_MASK 0x1 ++#define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF__SHIFT 0x0 ++#define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF_MASK 0x2 ++#define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF__SHIFT 0x1 ++#define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF_MASK 0x4 ++#define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF__SHIFT 0x2 ++#define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF_MASK 0x8 ++#define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF__SHIFT 0x3 ++#define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF_MASK 0x10 ++#define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF__SHIFT 0x4 ++#define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF_MASK 0x20 ++#define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF__SHIFT 0x5 ++#define ACP_PGFSM_CONFIG_REG__FSM_ADDR_MASK 0xff ++#define ACP_PGFSM_CONFIG_REG__FSM_ADDR__SHIFT 0x0 ++#define ACP_PGFSM_CONFIG_REG__Power_Down_MASK 0x100 ++#define ACP_PGFSM_CONFIG_REG__Power_Down__SHIFT 0x8 ++#define ACP_PGFSM_CONFIG_REG__Power_Up_MASK 0x200 ++#define ACP_PGFSM_CONFIG_REG__Power_Up__SHIFT 0x9 ++#define ACP_PGFSM_CONFIG_REG__P1_Select_MASK 0x400 ++#define ACP_PGFSM_CONFIG_REG__P1_Select__SHIFT 0xa ++#define ACP_PGFSM_CONFIG_REG__P2_Select_MASK 0x800 ++#define ACP_PGFSM_CONFIG_REG__P2_Select__SHIFT 0xb ++#define ACP_PGFSM_CONFIG_REG__Wr_MASK 0x1000 ++#define ACP_PGFSM_CONFIG_REG__Wr__SHIFT 0xc ++#define ACP_PGFSM_CONFIG_REG__Rd_MASK 0x2000 ++#define ACP_PGFSM_CONFIG_REG__Rd__SHIFT 0xd ++#define ACP_PGFSM_CONFIG_REG__RdData_Reset_MASK 0x4000 ++#define ACP_PGFSM_CONFIG_REG__RdData_Reset__SHIFT 0xe ++#define ACP_PGFSM_CONFIG_REG__Short_Format_MASK 0x8000 ++#define ACP_PGFSM_CONFIG_REG__Short_Format__SHIFT 0xf ++#define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG_MASK 0x3ff0000 ++#define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG__SHIFT 0x10 ++#define ACP_PGFSM_CONFIG_REG__SRBM_override_MASK 0x4000000 ++#define ACP_PGFSM_CONFIG_REG__SRBM_override__SHIFT 0x1a ++#define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr_MASK 0x8000000 ++#define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr__SHIFT 0x1b ++#define ACP_PGFSM_CONFIG_REG__REG_ADDR_MASK 0xf0000000 ++#define ACP_PGFSM_CONFIG_REG__REG_ADDR__SHIFT 0x1c ++#define ACP_PGFSM_WRITE_REG__Write_value_MASK 0xffffffff ++#define ACP_PGFSM_WRITE_REG__Write_value__SHIFT 0x0 ++#define ACP_PGFSM_READ_REG_0__Read_value_MASK 0xffffff ++#define ACP_PGFSM_READ_REG_0__Read_value__SHIFT 0x0 ++#define ACP_PGFSM_READ_REG_1__Read_value_MASK 0xffffff ++#define ACP_PGFSM_READ_REG_1__Read_value__SHIFT 0x0 ++#define ACP_PGFSM_READ_REG_2__Read_value_MASK 0xffffff ++#define ACP_PGFSM_READ_REG_2__Read_value__SHIFT 0x0 ++#define ACP_PGFSM_READ_REG_3__Read_value_MASK 0xffffff ++#define ACP_PGFSM_READ_REG_3__Read_value__SHIFT 0x0 ++#define ACP_PGFSM_READ_REG_4__Read_value_MASK 0xffffff ++#define ACP_PGFSM_READ_REG_4__Read_value__SHIFT 0x0 ++#define ACP_PGFSM_READ_REG_5__Read_value_MASK 0xffffff ++#define ACP_PGFSM_READ_REG_5__Read_value__SHIFT 0x0 ++#define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS_MASK 0x1 ++#define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS__SHIFT 0x0 ++#define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG_MASK 0x3 ++#define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG__SHIFT 0x0 ++#define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT_MASK 0x1 ++#define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT__SHIFT 0x0 ++#define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package_MASK 0x1 ++#define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package__SHIFT 0x0 ++#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable_MASK 0x7ff ++#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable__SHIFT 0x0 ++#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable_MASK 0x7ff0000 ++#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable__SHIFT 0x10 ++#define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL_MASK 0x1 ++#define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL__SHIFT 0x0 ++#define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG_MASK 0xffffffff ++#define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG__SHIFT 0x0 ++#define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable_MASK 0x1 ++#define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable__SHIFT 0x0 ++#define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status_MASK 0x1 ++#define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold_MASK 0xffffffff ++#define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold_MASK 0xffffffff ++#define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples_MASK 0xffff ++#define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks_MASK 0xffff ++#define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks_MASK 0xffffffff ++#define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en_MASK 0x1 ++#define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req_MASK 0x1 ++#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack_MASK 0x2 ++#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack__SHIFT 0x1 ++#define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer_MASK 0xffffffff ++#define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid_MASK 0x1 ++#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid__SHIFT 0x0 ++#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match_MASK 0x2 ++#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match__SHIFT 0x1 ++#define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap_MASK 0x1 ++#define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap__SHIFT 0x0 ++#define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high_MASK 0xffffffff ++#define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high__SHIFT 0x0 ++#define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low_MASK 0xffffffff ++#define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low__SHIFT 0x0 ++#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high_MASK 0xffffffff ++#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high__SHIFT 0x0 ++#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low_MASK 0xffffffff ++#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low__SHIFT 0x0 ++#define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML_MASK 0xffffffff ++#define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML__SHIFT 0x0 ++#define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH_MASK 0xffff ++#define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH__SHIFT 0x0 ++#define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML_MASK 0xffffffff ++#define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML__SHIFT 0x0 ++#define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH_MASK 0xffff ++#define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH__SHIFT 0x0 ++#define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML_MASK 0xffffffff ++#define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML__SHIFT 0x0 ++#define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH_MASK 0xffff ++#define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH__SHIFT 0x0 ++#define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML_MASK 0xffffffff ++#define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML__SHIFT 0x0 ++#define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH_MASK 0xffff ++#define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH__SHIFT 0x0 ++#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo_MASK 0xffffffff ++#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo__SHIFT 0x0 ++#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi_MASK 0xffff ++#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi__SHIFT 0x0 ++#define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo_MASK 0xffffffff ++#define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo__SHIFT 0x0 ++#define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi_MASK 0xffff ++#define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi__SHIFT 0x0 ++#define ACP_I2SSP_IER__I2SSP_IEN_MASK 0x1 ++#define ACP_I2SSP_IER__I2SSP_IEN__SHIFT 0x0 ++#define ACP_I2SSP_IRER__I2SSP_RXEN_MASK 0x1 ++#define ACP_I2SSP_IRER__I2SSP_RXEN__SHIFT 0x0 ++#define ACP_I2SSP_ITER__I2SSP_TXEN_MASK 0x1 ++#define ACP_I2SSP_ITER__I2SSP_TXEN__SHIFT 0x0 ++#define ACP_I2SSP_CER__I2SSP_CLKEN_MASK 0x1 ++#define ACP_I2SSP_CER__I2SSP_CLKEN__SHIFT 0x0 ++#define ACP_I2SSP_CCR__I2SSP_SCLKG_MASK 0x7 ++#define ACP_I2SSP_CCR__I2SSP_SCLKG__SHIFT 0x0 ++#define ACP_I2SSP_CCR__I2SSP_WSS_MASK 0x18 ++#define ACP_I2SSP_CCR__I2SSP_WSS__SHIFT 0x3 ++#define ACP_I2SSP_RXFFR__I2SSP_RXFFR_MASK 0x1 ++#define ACP_I2SSP_RXFFR__I2SSP_RXFFR__SHIFT 0x0 ++#define ACP_I2SSP_TXFFR__I2SSP_TXFFR_MASK 0x1 ++#define ACP_I2SSP_TXFFR__I2SSP_TXFFR__SHIFT 0x0 ++#define ACP_I2SSP_LRBR0__I2SSP_LRBR0_MASK 0xffffffff ++#define ACP_I2SSP_LRBR0__I2SSP_LRBR0__SHIFT 0x0 ++#define ACP_I2SSP_RRBR0__I2SSP_RRBR0_MASK 0xffffffff ++#define ACP_I2SSP_RRBR0__I2SSP_RRBR0__SHIFT 0x0 ++#define ACP_I2SSP_RER0__I2SSP_RXCHEN0_MASK 0x1 ++#define ACP_I2SSP_RER0__I2SSP_RXCHEN0__SHIFT 0x0 ++#define ACP_I2SSP_TER0__I2SSP_TXCHEN0_MASK 0x1 ++#define ACP_I2SSP_TER0__I2SSP_TXCHEN0__SHIFT 0x0 ++#define ACP_I2SSP_RCR0__I2SSP_WLEN_MASK 0x7 ++#define ACP_I2SSP_RCR0__I2SSP_WLEN__SHIFT 0x0 ++#define ACP_I2SSP_TCR0__I2SSP_WLEN_MASK 0x7 ++#define ACP_I2SSP_TCR0__I2SSP_WLEN__SHIFT 0x0 ++#define ACP_I2SSP_ISR0__I2SSP_RXDA_MASK 0x1 ++#define ACP_I2SSP_ISR0__I2SSP_RXDA__SHIFT 0x0 ++#define ACP_I2SSP_ISR0__I2SSP_RXFO_MASK 0x2 ++#define ACP_I2SSP_ISR0__I2SSP_RXFO__SHIFT 0x1 ++#define ACP_I2SSP_ISR0__I2SSP_TXFE_MASK 0x10 ++#define ACP_I2SSP_ISR0__I2SSP_TXFE__SHIFT 0x4 ++#define ACP_I2SSP_ISR0__I2SSP_TXFO_MASK 0x20 ++#define ACP_I2SSP_ISR0__I2SSP_TXFO__SHIFT 0x5 ++#define ACP_I2SSP_IMR0__I2SSP_RXDAM_MASK 0x1 ++#define ACP_I2SSP_IMR0__I2SSP_RXDAM__SHIFT 0x0 ++#define ACP_I2SSP_IMR0__I2SSP_RXFOM_MASK 0x2 ++#define ACP_I2SSP_IMR0__I2SSP_RXFOM__SHIFT 0x1 ++#define ACP_I2SSP_IMR0__I2SSP_TXFEM_MASK 0x10 ++#define ACP_I2SSP_IMR0__I2SSP_TXFEM__SHIFT 0x4 ++#define ACP_I2SSP_IMR0__I2SSP_TXFOM_MASK 0x20 ++#define ACP_I2SSP_IMR0__I2SSP_TXFOM__SHIFT 0x5 ++#define ACP_I2SSP_ROR0__I2SSP_RXCHO_MASK 0x1 ++#define ACP_I2SSP_ROR0__I2SSP_RXCHO__SHIFT 0x0 ++#define ACP_I2SSP_TOR0__I2SSP_TXCHO_MASK 0x1 ++#define ACP_I2SSP_TOR0__I2SSP_TXCHO__SHIFT 0x0 ++#define ACP_I2SSP_RFCR0__I2SSP_RXCHDT_MASK 0xf ++#define ACP_I2SSP_RFCR0__I2SSP_RXCHDT__SHIFT 0x0 ++#define ACP_I2SSP_TFCR0__I2SSP_TXCHET_MASK 0xf ++#define ACP_I2SSP_TFCR0__I2SSP_TXCHET__SHIFT 0x0 ++#define ACP_I2SSP_RFF0__I2SSP_RXCHFR_MASK 0x1 ++#define ACP_I2SSP_RFF0__I2SSP_RXCHFR__SHIFT 0x0 ++#define ACP_I2SSP_TFF0__I2SSP_TXCHFR_MASK 0x1 ++#define ACP_I2SSP_TFF0__I2SSP_TXCHFR__SHIFT 0x0 ++#define ACP_I2SSP_RXDMA__I2SSP_RXDMA_MASK 0xffffffff ++#define ACP_I2SSP_RXDMA__I2SSP_RXDMA__SHIFT 0x0 ++#define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA_MASK 0x1 ++#define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA__SHIFT 0x0 ++#define ACP_I2SSP_TXDMA__I2SSP_TXDMA_MASK 0xffffffff ++#define ACP_I2SSP_TXDMA__I2SSP_TXDMA__SHIFT 0x0 ++#define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA_MASK 0x1 ++#define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA__SHIFT 0x0 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0_MASK 0x7 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0__SHIFT 0x0 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1_MASK 0x38 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1__SHIFT 0x3 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2_MASK 0x380 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2__SHIFT 0x7 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3_MASK 0x1c00 ++#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3__SHIFT 0xa ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH_MASK 0x3 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH__SHIFT 0x0 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL_MASK 0xc ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL__SHIFT 0x2 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN_MASK 0x10 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN__SHIFT 0x4 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK_MASK 0x20 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK__SHIFT 0x5 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK_MASK 0x40 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK__SHIFT 0x6 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES_MASK 0x180 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES__SHIFT 0x7 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES_MASK 0x600 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES__SHIFT 0x9 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0_MASK 0x70000 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0__SHIFT 0x10 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1_MASK 0x380000 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1__SHIFT 0x13 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2_MASK 0x1c00000 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2__SHIFT 0x16 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3_MASK 0xe000000 ++#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3__SHIFT 0x19 ++#define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH_MASK 0xffffffff ++#define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH__SHIFT 0x0 ++#define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE_MASK 0xffffffff ++#define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE__SHIFT 0x0 ++#define ACP_I2SMICSP_IER__I2SMICSP_IEN_MASK 0x1 ++#define ACP_I2SMICSP_IER__I2SMICSP_IEN__SHIFT 0x0 ++#define ACP_I2SMICSP_IRER__I2SMICSP_RXEN_MASK 0x1 ++#define ACP_I2SMICSP_IRER__I2SMICSP_RXEN__SHIFT 0x0 ++#define ACP_I2SMICSP_ITER__I2SMICSP_TXEN_MASK 0x1 ++#define ACP_I2SMICSP_ITER__I2SMICSP_TXEN__SHIFT 0x0 ++#define ACP_I2SMICSP_CER__I2SMICSP_CLKEN_MASK 0x1 ++#define ACP_I2SMICSP_CER__I2SMICSP_CLKEN__SHIFT 0x0 ++#define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG_MASK 0x7 ++#define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG__SHIFT 0x0 ++#define ACP_I2SMICSP_CCR__I2SMICSP_WSS_MASK 0x18 ++#define ACP_I2SMICSP_CCR__I2SMICSP_WSS__SHIFT 0x3 ++#define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR_MASK 0x1 ++#define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR__SHIFT 0x0 ++#define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR_MASK 0x1 ++#define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR__SHIFT 0x0 ++#define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0_MASK 0xffffffff ++#define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0__SHIFT 0x0 ++#define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0_MASK 0xffffffff ++#define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0__SHIFT 0x0 ++#define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0_MASK 0x1 ++#define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0__SHIFT 0x0 ++#define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0_MASK 0x1 ++#define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0__SHIFT 0x0 ++#define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN_MASK 0x7 ++#define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN__SHIFT 0x0 ++#define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN_MASK 0x7 ++#define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN__SHIFT 0x0 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA_MASK 0x1 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA__SHIFT 0x0 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO_MASK 0x2 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO__SHIFT 0x1 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE_MASK 0x10 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE__SHIFT 0x4 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO_MASK 0x20 ++#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO__SHIFT 0x5 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM_MASK 0x1 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM__SHIFT 0x0 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM_MASK 0x2 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM__SHIFT 0x1 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM_MASK 0x10 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM__SHIFT 0x4 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM_MASK 0x20 ++#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM__SHIFT 0x5 ++#define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO_MASK 0x1 ++#define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO__SHIFT 0x0 ++#define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO_MASK 0x1 ++#define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO__SHIFT 0x0 ++#define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT_MASK 0xf ++#define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT__SHIFT 0x0 ++#define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET_MASK 0xf ++#define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET__SHIFT 0x0 ++#define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR_MASK 0x1 ++#define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR__SHIFT 0x0 ++#define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR_MASK 0x1 ++#define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR__SHIFT 0x0 ++#define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1_MASK 0xffffffff ++#define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1__SHIFT 0x0 ++#define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1_MASK 0xffffffff ++#define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1__SHIFT 0x0 ++#define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1_MASK 0x1 ++#define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1__SHIFT 0x0 ++#define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1_MASK 0x1 ++#define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1__SHIFT 0x0 ++#define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN_MASK 0x7 ++#define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN__SHIFT 0x0 ++#define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN_MASK 0x7 ++#define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN__SHIFT 0x0 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA_MASK 0x1 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA__SHIFT 0x0 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO_MASK 0x2 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO__SHIFT 0x1 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE_MASK 0x10 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE__SHIFT 0x4 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO_MASK 0x20 ++#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO__SHIFT 0x5 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK 0x1 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM__SHIFT 0x0 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK 0x2 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM__SHIFT 0x1 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM_MASK 0x10 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM__SHIFT 0x4 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM_MASK 0x20 ++#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM__SHIFT 0x5 ++#define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO_MASK 0x1 ++#define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO__SHIFT 0x0 ++#define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO_MASK 0x1 ++#define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO__SHIFT 0x0 ++#define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT_MASK 0xf ++#define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT__SHIFT 0x0 ++#define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET_MASK 0xf ++#define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET__SHIFT 0x0 ++#define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR_MASK 0x1 ++#define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR__SHIFT 0x0 ++#define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR_MASK 0x1 ++#define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR__SHIFT 0x0 ++#define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA_MASK 0xffffffff ++#define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA__SHIFT 0x0 ++#define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA_MASK 0x1 ++#define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA__SHIFT 0x0 ++#define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA_MASK 0xffffffff ++#define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA__SHIFT 0x0 ++#define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA_MASK 0x1 ++#define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA__SHIFT 0x0 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0_MASK 0x7 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0__SHIFT 0x0 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1_MASK 0x38 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1__SHIFT 0x3 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2_MASK 0x380 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2__SHIFT 0x7 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3_MASK 0x1c00 ++#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3__SHIFT 0xa ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH_MASK 0x3 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x0 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL_MASK 0xc ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL__SHIFT 0x2 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN_MASK 0x10 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN__SHIFT 0x4 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK_MASK 0x20 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK__SHIFT 0x5 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK_MASK 0x40 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK__SHIFT 0x6 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES_MASK 0x180 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES__SHIFT 0x7 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES_MASK 0x600 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES__SHIFT 0x9 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0_MASK 0x70000 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0__SHIFT 0x10 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1_MASK 0x380000 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1__SHIFT 0x13 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2_MASK 0x1c00000 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2__SHIFT 0x16 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3_MASK 0xe000000 ++#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3__SHIFT 0x19 ++#define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH_MASK 0xffffffff ++#define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x0 ++#define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE_MASK 0xffffffff ++#define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE__SHIFT 0x0 ++#define ACP_I2SBT_IER__I2SBT_IEN_MASK 0x1 ++#define ACP_I2SBT_IER__I2SBT_IEN__SHIFT 0x0 ++#define ACP_I2SBT_IRER__I2SBT_RXEN_MASK 0x1 ++#define ACP_I2SBT_IRER__I2SBT_RXEN__SHIFT 0x0 ++#define ACP_I2SBT_ITER__I2SBT_TXEN_MASK 0x1 ++#define ACP_I2SBT_ITER__I2SBT_TXEN__SHIFT 0x0 ++#define ACP_I2SBT_CER__I2SBT_CLKEN_MASK 0x1 ++#define ACP_I2SBT_CER__I2SBT_CLKEN__SHIFT 0x0 ++#define ACP_I2SBT_CCR__I2SBT_SCLKG_MASK 0x7 ++#define ACP_I2SBT_CCR__I2SBT_SCLKG__SHIFT 0x0 ++#define ACP_I2SBT_CCR__I2SBT_WSS_MASK 0x18 ++#define ACP_I2SBT_CCR__I2SBT_WSS__SHIFT 0x3 ++#define ACP_I2SBT_RXFFR__I2SBT_RXFFR_MASK 0x1 ++#define ACP_I2SBT_RXFFR__I2SBT_RXFFR__SHIFT 0x0 ++#define ACP_I2SBT_TXFFR__I2SBT_TXFFR_MASK 0x1 ++#define ACP_I2SBT_TXFFR__I2SBT_TXFFR__SHIFT 0x0 ++#define ACP_I2SBT_LRBR0__I2SBT_LRBR0_MASK 0xffffffff ++#define ACP_I2SBT_LRBR0__I2SBT_LRBR0__SHIFT 0x0 ++#define ACP_I2SBT_RRBR0__I2SBT_RRBR0_MASK 0xffffffff ++#define ACP_I2SBT_RRBR0__I2SBT_RRBR0__SHIFT 0x0 ++#define ACP_I2SBT_RER0__I2SBT_RXCHEN0_MASK 0x1 ++#define ACP_I2SBT_RER0__I2SBT_RXCHEN0__SHIFT 0x0 ++#define ACP_I2SBT_TER0__I2SBT_TXCHEN0_MASK 0x1 ++#define ACP_I2SBT_TER0__I2SBT_TXCHEN0__SHIFT 0x0 ++#define ACP_I2SBT_RCR0__I2SBT_WLEN_MASK 0x7 ++#define ACP_I2SBT_RCR0__I2SBT_WLEN__SHIFT 0x0 ++#define ACP_I2SBT_TCR0__I2SBT_WLEN_MASK 0x7 ++#define ACP_I2SBT_TCR0__I2SBT_WLEN__SHIFT 0x0 ++#define ACP_I2SBT_ISR0__I2SBT_RXDA_MASK 0x1 ++#define ACP_I2SBT_ISR0__I2SBT_RXDA__SHIFT 0x0 ++#define ACP_I2SBT_ISR0__I2SBT_RXFO_MASK 0x2 ++#define ACP_I2SBT_ISR0__I2SBT_RXFO__SHIFT 0x1 ++#define ACP_I2SBT_ISR0__I2SBT_TXFE_MASK 0x10 ++#define ACP_I2SBT_ISR0__I2SBT_TXFE__SHIFT 0x4 ++#define ACP_I2SBT_ISR0__I2SBT_TXFO_MASK 0x20 ++#define ACP_I2SBT_ISR0__I2SBT_TXFO__SHIFT 0x5 ++#define ACP_I2SBT_IMR0__I2SBT_RXDAM_MASK 0x1 ++#define ACP_I2SBT_IMR0__I2SBT_RXDAM__SHIFT 0x0 ++#define ACP_I2SBT_IMR0__I2SBT_RXFOM_MASK 0x2 ++#define ACP_I2SBT_IMR0__I2SBT_RXFOM__SHIFT 0x1 ++#define ACP_I2SBT_IMR0__I2SBT_TXFEM_MASK 0x10 ++#define ACP_I2SBT_IMR0__I2SBT_TXFEM__SHIFT 0x4 ++#define ACP_I2SBT_IMR0__I2SBT_TXFOM_MASK 0x20 ++#define ACP_I2SBT_IMR0__I2SBT_TXFOM__SHIFT 0x5 ++#define ACP_I2SBT_ROR0__I2SBT_RXCHO_MASK 0x1 ++#define ACP_I2SBT_ROR0__I2SBT_RXCHO__SHIFT 0x0 ++#define ACP_I2SBT_TOR0__I2SBT_TXCHO_MASK 0x1 ++#define ACP_I2SBT_TOR0__I2SBT_TXCHO__SHIFT 0x0 ++#define ACP_I2SBT_RFCR0__I2SBT_RXCHDT_MASK 0xf ++#define ACP_I2SBT_RFCR0__I2SBT_RXCHDT__SHIFT 0x0 ++#define ACP_I2SBT_TFCR0__I2SBT_TXCHET_MASK 0xf ++#define ACP_I2SBT_TFCR0__I2SBT_TXCHET__SHIFT 0x0 ++#define ACP_I2SBT_RFF0__I2SBT_RXCHFR_MASK 0x1 ++#define ACP_I2SBT_RFF0__I2SBT_RXCHFR__SHIFT 0x0 ++#define ACP_I2SBT_TFF0__I2SBT_TXCHFR_MASK 0x1 ++#define ACP_I2SBT_TFF0__I2SBT_TXCHFR__SHIFT 0x0 ++#define ACP_I2SBT_LRBR1__I2SBT_LRBR1_MASK 0xffffffff ++#define ACP_I2SBT_LRBR1__I2SBT_LRBR1__SHIFT 0x0 ++#define ACP_I2SBT_RRBR1__I2SBT_RRBR1_MASK 0xffffffff ++#define ACP_I2SBT_RRBR1__I2SBT_RRBR1__SHIFT 0x0 ++#define ACP_I2SBT_RER1__I2SBT_RXCHEN1_MASK 0x1 ++#define ACP_I2SBT_RER1__I2SBT_RXCHEN1__SHIFT 0x0 ++#define ACP_I2SBT_TER1__I2SBT_TXCHEN1_MASK 0x1 ++#define ACP_I2SBT_TER1__I2SBT_TXCHEN1__SHIFT 0x0 ++#define ACP_I2SBT_RCR1__I2SBT_WLEN_MASK 0x7 ++#define ACP_I2SBT_RCR1__I2SBT_WLEN__SHIFT 0x0 ++#define ACP_I2SBT_TCR1__I2SBT_WLEN_MASK 0x7 ++#define ACP_I2SBT_TCR1__I2SBT_WLEN__SHIFT 0x0 ++#define ACP_I2SBT_ISR1__I2SBT_RXDA_MASK 0x1 ++#define ACP_I2SBT_ISR1__I2SBT_RXDA__SHIFT 0x0 ++#define ACP_I2SBT_ISR1__I2SBT_RXFO_MASK 0x2 ++#define ACP_I2SBT_ISR1__I2SBT_RXFO__SHIFT 0x1 ++#define ACP_I2SBT_ISR1__I2SBT_TXFE_MASK 0x10 ++#define ACP_I2SBT_ISR1__I2SBT_TXFE__SHIFT 0x4 ++#define ACP_I2SBT_ISR1__I2SBT_TXFO_MASK 0x20 ++#define ACP_I2SBT_ISR1__I2SBT_TXFO__SHIFT 0x5 ++#define ACP_I2SBT_IMR1__I2SBT_RXDAM_MASK 0x1 ++#define ACP_I2SBT_IMR1__I2SBT_RXDAM__SHIFT 0x0 ++#define ACP_I2SBT_IMR1__I2SBT_RXFOM_MASK 0x2 ++#define ACP_I2SBT_IMR1__I2SBT_RXFOM__SHIFT 0x1 ++#define ACP_I2SBT_IMR1__I2SBT_TXFEM_MASK 0x10 ++#define ACP_I2SBT_IMR1__I2SBT_TXFEM__SHIFT 0x4 ++#define ACP_I2SBT_IMR1__I2SBT_TXFOM_MASK 0x20 ++#define ACP_I2SBT_IMR1__I2SBT_TXFOM__SHIFT 0x5 ++#define ACP_I2SBT_ROR1__I2SBT_RXCHO_MASK 0x1 ++#define ACP_I2SBT_ROR1__I2SBT_RXCHO__SHIFT 0x0 ++#define ACP_I2SBT_TOR1__I2SBT_TXCHO_MASK 0x1 ++#define ACP_I2SBT_TOR1__I2SBT_TXCHO__SHIFT 0x0 ++#define ACP_I2SBT_RFCR1__I2SBT_RXCHDT_MASK 0xf ++#define ACP_I2SBT_RFCR1__I2SBT_RXCHDT__SHIFT 0x0 ++#define ACP_I2SBT_TFCR1__I2SBT_TXCHET_MASK 0xf ++#define ACP_I2SBT_TFCR1__I2SBT_TXCHET__SHIFT 0x0 ++#define ACP_I2SBT_RFF1__I2SBT_RXCHFR_MASK 0x1 ++#define ACP_I2SBT_RFF1__I2SBT_RXCHFR__SHIFT 0x0 ++#define ACP_I2SBT_TFF1__I2SBT_TXCHFR_MASK 0x1 ++#define ACP_I2SBT_TFF1__I2SBT_TXCHFR__SHIFT 0x0 ++#define ACP_I2SBT_RXDMA__I2SBT_RXDMA_MASK 0xffffffff ++#define ACP_I2SBT_RXDMA__I2SBT_RXDMA__SHIFT 0x0 ++#define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA_MASK 0x1 ++#define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA__SHIFT 0x0 ++#define ACP_I2SBT_TXDMA__I2SBT_TXDMA_MASK 0xffffffff ++#define ACP_I2SBT_TXDMA__I2SBT_TXDMA__SHIFT 0x0 ++#define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA_MASK 0x1 ++#define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA__SHIFT 0x0 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0_MASK 0x7 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0__SHIFT 0x0 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1_MASK 0x38 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1__SHIFT 0x3 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2_MASK 0x380 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2__SHIFT 0x7 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3_MASK 0x1c00 ++#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3__SHIFT 0xa ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH_MASK 0x3 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH__SHIFT 0x0 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL_MASK 0xc ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL__SHIFT 0x2 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN_MASK 0x10 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN__SHIFT 0x4 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK_MASK 0x20 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK__SHIFT 0x5 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK_MASK 0x40 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK__SHIFT 0x6 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES_MASK 0x180 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES__SHIFT 0x7 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES_MASK 0x600 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES__SHIFT 0x9 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0_MASK 0x70000 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0__SHIFT 0x10 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1_MASK 0x380000 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1__SHIFT 0x13 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2_MASK 0x1c00000 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2__SHIFT 0x16 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3_MASK 0xe000000 ++#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3__SHIFT 0x19 ++#define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH_MASK 0xffffffff ++#define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH__SHIFT 0x0 ++#define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE_MASK 0xffffffff ++#define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE__SHIFT 0x0 ++ ++#endif /* ACP_2_2_SH_MASK_H */ +-- +2.7.4 + |