diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch | 106 |
1 files changed, 106 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch new file mode 100644 index 00000000..36737218 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/1118-switch-UVD-code-to-use-UVD_NO_OP-for-padding.patch @@ -0,0 +1,106 @@ +From f60f754ee9efe8d43beadccb7bf0b169f77a6247 Mon Sep 17 00:00:00 2001 +From: Sanjay R Mehta <sanju.mehta@amd.com> +Date: Sat, 17 Sep 2016 15:13:33 +0530 +Subject: [PATCH 08/12] switch UVD code to use UVD_NO_OP for padding +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Replace packet2's with packet0 writes to UVD_NO_OP. The +value written to UVD_NO_OP does not matter. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 6 ++++-- + drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 2 +- + drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +- + drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h | 1 + + drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h | 1 + + 6 files changed, 9 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +index 2ca93a4..f14e4aa 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +@@ -964,8 +964,10 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, + ib->ptr[3] = addr >> 32; + ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); + ib->ptr[5] = 0; +- for (i = 6; i < 16; ++i) +- ib->ptr[i] = PACKET2(0); ++ for (i = 6; i < 16; i += 2) { ++ ib->ptr[i] = PACKET0(mmUVD_NO_OP, 0); ++ ib->ptr[i+1] = 0; ++ } + ib->length_dw = 16; + + if (direct) { +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +index a75ffb5b..ab4857d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +@@ -114,7 +114,7 @@ static int uvd_v4_2_sw_init(void *handle) + + ring = &adev->uvd.ring; + sprintf(ring->name, "uvd"); +- r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, ++ r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, + &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + + return r; +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +index ecb8101..2b115bd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +@@ -111,7 +111,7 @@ static int uvd_v5_0_sw_init(void *handle) + + ring = &adev->uvd.ring; + sprintf(ring->name, "uvd"); +- r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, ++ r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, + &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + + return r; +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +index 0887ea9..e33e3f4 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +@@ -115,7 +115,7 @@ static int uvd_v6_0_sw_init(void *handle) + + ring = &adev->uvd.ring; + sprintf(ring->name, "uvd"); +- r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf, ++ r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, + &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + + return r; +diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h +index eb4cf53..cc972d2 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h +@@ -34,6 +34,7 @@ + #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 + #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 + #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 ++#define mmUVD_NO_OP 0x3bff + #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69 + #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68 + #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67 +diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h +index 6f6fb34..d24d086 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h +@@ -35,6 +35,7 @@ + #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 + #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 + #define mmUVD_POWER_STATUS_U 0x3bfd ++#define mmUVD_NO_OP 0x3bff + #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69 + #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68 + #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67 +-- +2.7.4 + |