diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/1117-add-support-for-UVD_NO_OP-register.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/1117-add-support-for-UVD_NO_OP-register.patch | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1117-add-support-for-UVD_NO_OP-register.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1117-add-support-for-UVD_NO_OP-register.patch deleted file mode 100644 index 6d1b4da9..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1117-add-support-for-UVD_NO_OP-register.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 56c8ca5434ce175d98e33cffcfe554cc7e3cb70a Mon Sep 17 00:00:00 2001 -From: Sanjay R Mehta <sanju.mehta@amd.com> -Date: Sat, 17 Sep 2016 15:10:08 +0530 -Subject: [PATCH 07/12] add support for UVD_NO_OP register -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Writes to this register are the preferred way to do NOPs. - -Reviewed-by: Christian König <christian.koenig@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> -Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 1 + - drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -index ddc487d..2ca93a4 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c -@@ -823,6 +823,7 @@ static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, - return r; - break; - case mmUVD_ENGINE_CNTL: -+ case mmUVD_NO_OP: - break; - default: - DRM_ERROR("Invalid reg 0x%X!\n", reg); -diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h -index f3e53b1..19802e9 100644 ---- a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h -+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_d.h -@@ -34,6 +34,7 @@ - #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 - #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 - #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 -+#define mmUVD_NO_OP 0x3bff - #define mmUVD_SEMA_CNTL 0x3d00 - #define mmUVD_LMI_EXT40_ADDR 0x3d26 - #define mmUVD_CTX_INDEX 0x3d28 --- -2.7.4 - |