diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/1037-drm-amd-powerplay-ensure-clock-level-set-by-user-is-.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/1037-drm-amd-powerplay-ensure-clock-level-set-by-user-is-.patch | 128 |
1 files changed, 0 insertions, 128 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/1037-drm-amd-powerplay-ensure-clock-level-set-by-user-is-.patch b/meta-amdfalconx86/recipes-kernel/linux/files/1037-drm-amd-powerplay-ensure-clock-level-set-by-user-is-.patch deleted file mode 100644 index fb9cdf84..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/1037-drm-amd-powerplay-ensure-clock-level-set-by-user-is-.patch +++ /dev/null @@ -1,128 +0,0 @@ -From 7c2dd404575e941111d71b7b340c8e635e01f256 Mon Sep 17 00:00:00 2001 -From: Rex Zhu <Rex.Zhu@amd.com> -Date: Wed, 20 Apr 2016 15:59:49 +0800 -Subject: [PATCH 1037/1110] drm/amd/powerplay: ensure clock level set by user - is valid. - -Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> -Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 16 +++++++++++++--- - drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 14 +++++++++++--- - drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 14 +++++++++++--- - 3 files changed, 35 insertions(+), 9 deletions(-) - -diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c -index 3334a89..55e877c 100644 ---- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c -+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c -@@ -5153,20 +5153,30 @@ static int fiji_force_clock_level(struct pp_hwmgr *hwmgr, - if (!data->sclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SCLKDPM_SetEnabledMask, -- mask); -+ data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); - break; -+ - case PP_MCLK: - if (!data->mclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_MCLKDPM_SetEnabledMask, -- mask); -+ data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); - break; -+ - case PP_PCIE: -+ { -+ uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; -+ uint32_t level = 0; -+ -+ while (tmp >>= 1) -+ level++; -+ - if (!data->pcie_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_PCIeDPM_ForceLevel, -- mask); -+ level); - break; -+ } - default: - break; - } -diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c -index d9948c0..b146ec8 100644 ---- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c -+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c -@@ -4802,20 +4802,28 @@ static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr, - if (!data->sclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SCLKDPM_SetEnabledMask, -- mask); -+ data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); - break; - case PP_MCLK: - if (!data->mclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_MCLKDPM_SetEnabledMask, -- mask); -+ data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); - break; - case PP_PCIE: -+ { -+ uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; -+ uint32_t level = 0; -+ -+ while (tmp >>= 1) -+ level++; -+ - if (!data->pcie_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_PCIeDPM_ForceLevel, -- mask); -+ level); - break; -+ } - default: - break; - } -diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c -index bc61c07..28f5c65 100644 ---- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c -+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c -@@ -6100,20 +6100,28 @@ static int tonga_force_clock_level(struct pp_hwmgr *hwmgr, - if (!data->sclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SCLKDPM_SetEnabledMask, -- mask); -+ data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); - break; - case PP_MCLK: - if (!data->mclk_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_MCLKDPM_SetEnabledMask, -- mask); -+ data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); - break; - case PP_PCIE: -+ { -+ uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; -+ uint32_t level = 0; -+ -+ while (tmp >>= 1) -+ level++; -+ - if (!data->pcie_dpm_key_disabled) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_PCIeDPM_ForceLevel, -- mask); -+ level); - break; -+ } - default: - break; - } --- -2.7.4 - |