diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/0747-drm-amd-dal-Abstract-tiling_info-params.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/0747-drm-amd-dal-Abstract-tiling_info-params.patch | 440 |
1 files changed, 0 insertions, 440 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0747-drm-amd-dal-Abstract-tiling_info-params.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0747-drm-amd-dal-Abstract-tiling_info-params.patch deleted file mode 100644 index 0fcef70a..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/0747-drm-amd-dal-Abstract-tiling_info-params.patch +++ /dev/null @@ -1,440 +0,0 @@ -From c3c479b7aa28af6851b5870e7e02209d575dd87c Mon Sep 17 00:00:00 2001 -From: Jordan Lazare <Jordan.Lazare@amd.com> -Date: Thu, 28 Jan 2016 12:23:23 -0500 -Subject: [PATCH 0747/1110] drm/amd/dal: Abstract tiling_info params - -Also cleaned up unused plane types - -Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com> -Acked-by: Harry Wentland <harry.wentland@amd.com> ---- - .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 34 ++-- - drivers/gpu/drm/amd/dal/dc/core/dc_target.c | 4 +- - drivers/gpu/drm/amd/dal/dc/dc.h | 2 +- - drivers/gpu/drm/amd/dal/dc/dc_types.h | 192 ++++++++------------- - .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 23 ++- - .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 2 +- - drivers/gpu/drm/amd/dal/dc/inc/mem_input.h | 2 +- - 7 files changed, 102 insertions(+), 157 deletions(-) - -diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c -index af71e87..d09f0ad 100644 ---- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c -+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c -@@ -37,10 +37,6 @@ - #undef FRAME_SIZE - #undef DEPRECATED - --#include "dce/dce_11_0_d.h" --#include "dce/dce_11_0_sh_mask.h" --#include "dce/dce_11_0_enum.h" -- - #include "dc.h" - - #include "amdgpu_dm_types.h" -@@ -442,9 +438,9 @@ static void fill_plane_attributes_from_fb( - return; - } - -- surface->tiling_info.value = 0; -+ memset(&surface->tiling_info, 0, sizeof(surface->tiling_info)); - -- if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) -+ if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) - { - unsigned bankw, bankh, mtaspect, tile_split, num_banks; - -@@ -456,21 +452,21 @@ static void fill_plane_attributes_from_fb( - - - /* XXX fix me for VI */ -- surface->tiling_info.grph.NUM_BANKS = num_banks; -- surface->tiling_info.grph.ARRAY_MODE = -- ARRAY_2D_TILED_THIN1; -- surface->tiling_info.grph.TILE_SPLIT = tile_split; -- surface->tiling_info.grph.BANK_WIDTH = bankw; -- surface->tiling_info.grph.BANK_HEIGHT = bankh; -- surface->tiling_info.grph.TILE_ASPECT = mtaspect; -- surface->tiling_info.grph.TILE_MODE = -- ADDR_SURF_MICRO_TILING_DISPLAY; -+ surface->tiling_info.num_banks = num_banks; -+ surface->tiling_info.array_mode = -+ DC_ARRAY_2D_TILED_THIN1; -+ surface->tiling_info.tile_split = tile_split; -+ surface->tiling_info.bank_width = bankw; -+ surface->tiling_info.bank_height = bankh; -+ surface->tiling_info.tile_aspect = mtaspect; -+ surface->tiling_info.tile_mode = -+ DC_ADDR_SURF_MICRO_TILING_DISPLAY; - } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) -- == ARRAY_1D_TILED_THIN1) { -- surface->tiling_info.grph.ARRAY_MODE = ARRAY_1D_TILED_THIN1; -+ == DC_ARRAY_1D_TILED_THIN1) { -+ surface->tiling_info.array_mode = DC_ARRAY_1D_TILED_THIN1; - } - -- surface->tiling_info.grph.PIPE_CONFIG = -+ surface->tiling_info.pipe_config = - AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); - - surface->plane_size.grph.surface_size.x = 0; -@@ -484,7 +480,7 @@ static void fill_plane_attributes_from_fb( - surface->scaling_quality.h_taps_c = 2; - surface->scaling_quality.v_taps_c = 2; - --/* TODO: unhardcode */ -+ /* TODO: unhardcode */ - surface->colorimetry.limited_range = false; - surface->colorimetry.color_space = SURFACE_COLOR_SPACE_SRGB; - surface->scaling_quality.h_taps = 2; -diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c -index 2756e7b..f114fc4 100644 ---- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c -+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c -@@ -211,12 +211,10 @@ static bool validate_surface_address( - } - break; - case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: -- case PLN_ADDR_TYPE_VIDEO_INTERLACED: -- case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE_STEREO: -- case PLN_ADDR_TYPE_VIDEO_INTERLACED_STEREO: - default: - /* not supported */ - BREAK_TO_DEBUGGER(); -+ break; - } - - return is_valid_address; -diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h -index fcc79ed..1cd0883 100644 ---- a/drivers/gpu/drm/amd/dal/dc/dc.h -+++ b/drivers/gpu/drm/amd/dal/dc/dc.h -@@ -68,7 +68,7 @@ struct dc_surface { - struct rect clip_rect; - - union plane_size plane_size; -- union dc_tiling_info tiling_info; -+ struct dc_tiling_info tiling_info; - struct plane_colorimetry colorimetry; - - enum surface_pixel_format format; -diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h -index fe7046f..0a48ef4 100644 ---- a/drivers/gpu/drm/amd/dal/dc/dc_types.h -+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h -@@ -605,9 +605,6 @@ enum dc_plane_addr_type { - PLN_ADDR_TYPE_GRAPHICS = 0, - PLN_ADDR_TYPE_GRPH_STEREO, - PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, -- PLN_ADDR_TYPE_VIDEO_INTERLACED, -- PLN_ADDR_TYPE_VIDEO_PROGRESSIVE_STEREO, -- PLN_ADDR_TYPE_VIDEO_INTERLACED_STEREO - }; - - struct dc_plane_address { -@@ -628,35 +625,6 @@ struct dc_plane_address { - PHYSICAL_ADDRESS_LOC chroma_addr; - PHYSICAL_ADDRESS_LOC luma_addr; - } video_progressive; -- -- /*video interlaced*/ -- struct { -- PHYSICAL_ADDRESS_LOC chroma_addr; -- PHYSICAL_ADDRESS_LOC luma_addr; -- PHYSICAL_ADDRESS_LOC chroma_bottom_addr; -- PHYSICAL_ADDRESS_LOC luma_bottom_addr; -- } video_interlaced; -- -- /*video Progressive Stereo*/ -- struct { -- PHYSICAL_ADDRESS_LOC left_chroma_addr; -- PHYSICAL_ADDRESS_LOC left_luma_addr; -- PHYSICAL_ADDRESS_LOC right_chroma_addr; -- PHYSICAL_ADDRESS_LOC right_luma_addr; -- } video_progressive_stereo; -- -- /*video interlaced stereo*/ -- struct { -- PHYSICAL_ADDRESS_LOC left_chroma_addr; -- PHYSICAL_ADDRESS_LOC left_luma_addr; -- PHYSICAL_ADDRESS_LOC left_chroma_bottom_addr; -- PHYSICAL_ADDRESS_LOC left_luma_bottom_addr; -- -- PHYSICAL_ADDRESS_LOC right_chroma_addr; -- PHYSICAL_ADDRESS_LOC right_luma_addr; -- PHYSICAL_ADDRESS_LOC right_chroma_bottom_addr; -- PHYSICAL_ADDRESS_LOC right_luma_bottom_addr; -- } video_interlaced_stereo; - }; - }; - -@@ -852,98 +820,84 @@ struct stereo_3d_view { - } flags; - }; - --/* TODO: Rename to dc_tiling_info */ --union dc_tiling_info { -+/* TODO: These values come from hardware spec. We need to readdress this -+ * if they ever change. -+ */ -+enum array_mode_values { -+ DC_ARRAY_UNDEFINED = 0, -+ DC_ARRAY_1D_TILED_THIN1 = 0x2, -+ DC_ARRAY_2D_TILED_THIN1 = 0x4, -+}; - -- struct { -- /* Specifies the number of memory banks for tiling -- * purposes. -- * Only applies to 2D and 3D tiling modes. -- * POSSIBLE VALUES: 2,4,8,16 -- */ -- uint32_t NUM_BANKS:5; -- /* Specifies the number of tiles in the x direction -- * to be incorporated into the same bank. -- * Only applies to 2D and 3D tiling modes. -- * POSSIBLE VALUES: 1,2,4,8 -- */ -- uint32_t BANK_WIDTH:4; -- /* Specifies the number of tiles in the y direction to -- * be incorporated into the same bank. -- * Only applies to 2D and 3D tiling modes. -- * POSSIBLE VALUES: 1,2,4,8 -- */ -- uint32_t BANK_HEIGHT:4; -- /* Specifies the macro tile aspect ratio. Only applies -- * to 2D and 3D tiling modes. -- */ -- uint32_t TILE_ASPECT:3; -- /* Specifies the number of bytes that will be stored -- * contiguously for each tile. -- * If the tile data requires more storage than this -- * amount, it is split into multiple slices. -- * This field must not be larger than -- * GB_ADDR_CONFIG.DRAM_ROW_SIZE. -- * Only applies to 2D and 3D tiling modes. -- * For color render targets, TILE_SPLIT >= 256B. -- */ -- uint32_t TILE_SPLIT:3; -- /* Specifies the addressing within a tile. -- * 0x0 - DISPLAY_MICRO_TILING -- * 0x1 - THIN_MICRO_TILING -- * 0x2 - DEPTH_MICRO_TILING -- * 0x3 - ROTATED_MICRO_TILING -- */ -- uint32_t TILE_MODE:2; -- /* Specifies the number of pipes and how they are -- * interleaved in the surface. -- * Refer to memory addressing document for complete -- * details and constraints. -- */ -- uint32_t PIPE_CONFIG:5; -- /* Specifies the tiling mode of the surface. -- * THIN tiles use an 8x8x1 tile size. -- * THICK tiles use an 8x8x4 tile size. -- * 2D tiling modes rotate banks for successive Z slices -- * 3D tiling modes rotate pipes and banks for Z slices -- * Refer to memory addressing document for complete -- * details and constraints. -- */ -- uint32_t ARRAY_MODE:4; -- } grph; - -+enum tile_mode_values { -+ DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, -+ DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, -+}; - -- struct { -- /*possible values: 2,4,8,16*/ -- uint32_t NUM_BANKS:5; -- /*must use enum video_array_mode*/ -- uint32_t ARRAY_MODE:4; -- /*must use enum addr_pipe_config*/ -- uint32_t PIPE_CONFIG:5; -- /*possible values 1,2,4,8 */ -- uint32_t BANK_WIDTH_LUMA:4; -- /*possible values 1,2,4,8 */ -- uint32_t BANK_HEIGHT_LUMA:4; -- /*must use enum macro_tile_aspect*/ -- uint32_t TILE_ASPECT_LUMA:3; -- /*must use enum tile_split*/ -- uint32_t TILE_SPLIT_LUMA:3; -- /*must use micro_tile_mode */ -- uint32_t TILE_MODE_LUMA:2; -- /*possible values: 1,2,4,8*/ -- uint32_t BANK_WIDTH_CHROMA:4; -- /*possible values: 1,2,4,8*/ -- uint32_t BANK_HEIGHT_CHROMA:4; -- /*must use enum macro_tile_aspect*/ -- uint32_t TILE_ASPECT_CHROMA:3; -- /*must use enum tile_split*/ -- uint32_t TILE_SPLIT_CHROMA:3; -- /*must use enum micro_tile_mode*/ -- uint32_t TILE_MODE_CHROMA:2; -+enum tile_split_values { -+ DC_DISPLAY_MICRO_TILING = 0x0, -+ DC_THIN_MICRO_TILING = 0x1, -+ DC_DEPTH_MICRO_TILING = 0x2, -+ DC_ROTATED_MICRO_TILING = 0x3, -+}; - -- } video; -+struct dc_tiling_info { - -- uint64_t value; -+ /* Specifies the number of memory banks for tiling -+ * purposes. -+ * Only applies to 2D and 3D tiling modes. -+ * POSSIBLE VALUES: 2,4,8,16 -+ */ -+ unsigned int num_banks; -+ /* Specifies the number of tiles in the x direction -+ * to be incorporated into the same bank. -+ * Only applies to 2D and 3D tiling modes. -+ * POSSIBLE VALUES: 1,2,4,8 -+ */ -+ unsigned int bank_width; -+ /* Specifies the number of tiles in the y direction to -+ * be incorporated into the same bank. -+ * Only applies to 2D and 3D tiling modes. -+ * POSSIBLE VALUES: 1,2,4,8 -+ */ -+ unsigned int bank_height; -+ /* Specifies the macro tile aspect ratio. Only applies -+ * to 2D and 3D tiling modes. -+ */ -+ unsigned int tile_aspect; -+ /* Specifies the number of bytes that will be stored -+ * contiguously for each tile. -+ * If the tile data requires more storage than this -+ * amount, it is split into multiple slices. -+ * This field must not be larger than -+ * GB_ADDR_CONFIG.DRAM_ROW_SIZE. -+ * Only applies to 2D and 3D tiling modes. -+ * For color render targets, TILE_SPLIT >= 256B. -+ */ -+ enum tile_split_values tile_split; -+ /* Specifies the addressing within a tile. -+ * 0x0 - DISPLAY_MICRO_TILING -+ * 0x1 - THIN_MICRO_TILING -+ * 0x2 - DEPTH_MICRO_TILING -+ * 0x3 - ROTATED_MICRO_TILING -+ */ -+ enum tile_mode_values tile_mode; -+ /* Specifies the number of pipes and how they are -+ * interleaved in the surface. -+ * Refer to memory addressing document for complete -+ * details and constraints. -+ */ -+ unsigned int pipe_config; -+ /* Specifies the tiling mode of the surface. -+ * THIN tiles use an 8x8x1 tile size. -+ * THICK tiles use an 8x8x4 tile size. -+ * 2D tiling modes rotate banks for successive Z slices -+ * 3D tiling modes rotate pipes and banks for Z slices -+ * Refer to memory addressing document for complete -+ * details and constraints. -+ */ -+ enum array_mode_values array_mode; - }; - - union plane_size { -diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c -index b70c8e1..5d3d0f7 100644 ---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c -+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c -@@ -157,9 +157,6 @@ static void program_addr( - addr->grph_stereo.right_addr); - break; - case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: -- case PLN_ADDR_TYPE_VIDEO_INTERLACED: -- case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE_STEREO: -- case PLN_ADDR_TYPE_VIDEO_INTERLACED_STEREO: - default: - /* not supported */ - BREAK_TO_DEBUGGER(); -@@ -179,7 +176,7 @@ static void enable(struct dce110_mem_input *mem_input110) - - static void program_tiling( - struct dce110_mem_input *mem_input110, -- const union dc_tiling_info *info, -+ const struct dc_tiling_info *info, - const enum surface_pixel_format pixel_format) - { - uint32_t value = 0; -@@ -188,28 +185,28 @@ static void program_tiling( - mem_input110->base.ctx, - DCP_REG(mmGRPH_CONTROL)); - -- set_reg_field_value(value, info->grph.NUM_BANKS, -+ set_reg_field_value(value, info->num_banks, - GRPH_CONTROL, GRPH_NUM_BANKS); - -- set_reg_field_value(value, info->grph.BANK_WIDTH, -+ set_reg_field_value(value, info->bank_width, - GRPH_CONTROL, GRPH_BANK_WIDTH); - -- set_reg_field_value(value, info->grph.BANK_HEIGHT, -+ set_reg_field_value(value, info->bank_height, - GRPH_CONTROL, GRPH_BANK_HEIGHT); - -- set_reg_field_value(value, info->grph.TILE_ASPECT, -+ set_reg_field_value(value, info->tile_aspect, - GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT); - -- set_reg_field_value(value, info->grph.TILE_SPLIT, -+ set_reg_field_value(value, info->tile_split, - GRPH_CONTROL, GRPH_TILE_SPLIT); - -- set_reg_field_value(value, info->grph.TILE_MODE, -+ set_reg_field_value(value, info->tile_mode, - GRPH_CONTROL, GRPH_MICRO_TILE_MODE); - -- set_reg_field_value(value, info->grph.PIPE_CONFIG, -+ set_reg_field_value(value, info->pipe_config, - GRPH_CONTROL, GRPH_PIPE_CONFIG); - -- set_reg_field_value(value, info->grph.ARRAY_MODE, -+ set_reg_field_value(value, info->array_mode, - GRPH_CONTROL, GRPH_ARRAY_MODE); - - set_reg_field_value(value, 1, -@@ -458,7 +455,7 @@ bool dce110_mem_input_program_surface_flip_and_addr( - bool dce110_mem_input_program_surface_config( - struct mem_input *mem_input, - enum surface_pixel_format format, -- union dc_tiling_info *tiling_info, -+ struct dc_tiling_info *tiling_info, - union plane_size *plane_size, - enum dc_rotation_angle rotation) - { -diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h -index cd19169..5a4e5fe 100644 ---- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h -+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h -@@ -109,7 +109,7 @@ bool dce110_mem_input_program_surface_flip_and_addr( - bool dce110_mem_input_program_surface_config( - struct mem_input *mem_input, - enum surface_pixel_format format, -- union dc_tiling_info *tiling_info, -+ struct dc_tiling_info *tiling_info, - union plane_size *plane_size, - enum dc_rotation_angle rotation); - -diff --git a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h -index 4d653ab..7d6335d 100644 ---- a/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h -+++ b/drivers/gpu/drm/amd/dal/dc/inc/mem_input.h -@@ -57,7 +57,7 @@ struct mem_input_funcs { - bool (*mem_input_program_surface_config)( - struct mem_input *mem_input, - enum surface_pixel_format format, -- union dc_tiling_info *tiling_info, -+ struct dc_tiling_info *tiling_info, - union plane_size *plane_size, - enum dc_rotation_angle rotation); - }; --- -2.7.4 - |