diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/0295-drm-amdgpu-gfx7-Reduce-linecount-in-table-init.patch')
-rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/0295-drm-amdgpu-gfx7-Reduce-linecount-in-table-init.patch | 1389 |
1 files changed, 0 insertions, 1389 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0295-drm-amdgpu-gfx7-Reduce-linecount-in-table-init.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0295-drm-amdgpu-gfx7-Reduce-linecount-in-table-init.patch deleted file mode 100644 index 6869eea3..00000000 --- a/meta-amdfalconx86/recipes-kernel/linux/files/0295-drm-amdgpu-gfx7-Reduce-linecount-in-table-init.patch +++ /dev/null @@ -1,1389 +0,0 @@ -From 7138ed10984deb0ccd7a2c78a0750fbd7f61257d Mon Sep 17 00:00:00 2001 -From: Tom St Denis <tom.stdenis@amd.com> -Date: Mon, 8 Feb 2016 09:55:13 -0500 -Subject: [PATCH 0295/1110] drm/amdgpu/gfx7: Reduce linecount in table init - -Replaces switch statements with direct assignments to -reduce line count significantly. - -Signed-off-by: Tom St Denis <tom.stdenis@amd.com> -Reviewed-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1345 +++++++++++++-------------------- - 1 file changed, 525 insertions(+), 820 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c -index 99d85f6..1543240 100644 ---- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c -@@ -1006,9 +1006,15 @@ out: - */ - static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) - { -- const u32 num_tile_mode_states = 32; -- const u32 num_secondary_tile_mode_states = 16; -- u32 reg_offset, gb_tile_moden, split_equal_to_row_size; -+ const u32 num_tile_mode_states = -+ ARRAY_SIZE(adev->gfx.config.tile_mode_array); -+ const u32 num_secondary_tile_mode_states = -+ ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); -+ u32 reg_offset, split_equal_to_row_size; -+ uint32_t *tile, *macrotile; -+ -+ tile = adev->gfx.config.tile_mode_array; -+ macrotile = adev->gfx.config.macrotile_mode_array; - - switch (adev->gfx.config.mem_row_size_in_kb) { - case 1: -@@ -1023,832 +1029,531 @@ static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) - break; - } - -+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) -+ tile[reg_offset] = 0; -+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) -+ macrotile[reg_offset] = 0; -+ - switch (adev->asic_type) { - case CHIP_BONAIRE: -- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { -- switch (reg_offset) { -- case 0: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 1: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 2: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 3: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 4: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -- TILE_SPLIT(split_equal_to_row_size)); -- break; -- case 5: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 6: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -- TILE_SPLIT(split_equal_to_row_size)); -- break; -- case 7: -- gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); -- break; -- -- case 8: -- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16)); -- break; -- case 9: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); -- break; -- case 10: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -- break; -- case 11: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -- break; -- case 12: -- gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); -- break; -- case 13: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); -- break; -- case 14: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -- break; -- case 15: -- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -- break; -- case 16: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -- break; -- case 17: -- gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); -- break; -- case 18: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 19: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); -- break; -- case 20: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 21: -- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 22: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 23: -- gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); -- break; -- case 24: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 25: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 26: -- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 27: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); -- break; -- case 28: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -- break; -- case 29: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -- break; -- case 30: -- gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); -- break; -- default: -- gb_tile_moden = 0; -- break; -- } -- adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; -- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); -- } -- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { -- switch (reg_offset) { -- case 0: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 1: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 2: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 3: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 4: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 5: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_8_BANK)); -- break; -- case 6: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -- NUM_BANKS(ADDR_SURF_4_BANK)); -- break; -- case 8: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 9: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 10: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 11: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 12: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 13: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_8_BANK)); -- break; -- case 14: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -- NUM_BANKS(ADDR_SURF_4_BANK)); -- break; -- default: -- gb_tile_moden = 0; -- break; -- } -- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; -- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); -- } -+ tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -+ TILE_SPLIT(split_equal_to_row_size)); -+ tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -+ TILE_SPLIT(split_equal_to_row_size)); -+ tile[7] = (TILE_SPLIT(split_equal_to_row_size)); -+ tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16)); -+ tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); -+ tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -+ tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -+ tile[12] = (TILE_SPLIT(split_equal_to_row_size)); -+ tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); -+ tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -+ tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -+ tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -+ tile[17] = (TILE_SPLIT(split_equal_to_row_size)); -+ tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); -+ tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[23] = (TILE_SPLIT(split_equal_to_row_size)); -+ tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); -+ tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -+ tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -+ tile[30] = (TILE_SPLIT(split_equal_to_row_size)); -+ -+ macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_8_BANK)); -+ macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -+ NUM_BANKS(ADDR_SURF_4_BANK)); -+ macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_8_BANK)); -+ macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -+ NUM_BANKS(ADDR_SURF_4_BANK)); -+ -+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) -+ WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); -+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) -+ if (reg_offset != 7) -+ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); - break; - case CHIP_HAWAII: -- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { -- switch (reg_offset) { -- case 0: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 1: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 2: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 3: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 4: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -- TILE_SPLIT(split_equal_to_row_size)); -- break; -- case 5: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -- TILE_SPLIT(split_equal_to_row_size)); -- break; -- case 6: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -- TILE_SPLIT(split_equal_to_row_size)); -- break; -- case 7: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -- TILE_SPLIT(split_equal_to_row_size)); -- break; -- -- case 8: -- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); -- break; -- case 9: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); -- break; -- case 10: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -- break; -- case 11: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -- break; -- case 12: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -- break; -- case 13: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); -- break; -- case 14: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -- break; -- case 15: -- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -- break; -- case 16: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -- break; -- case 17: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -- break; -- case 18: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 19: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); -- break; -- case 20: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 21: -- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 22: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 23: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 24: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 25: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 26: -- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 27: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); -- break; -- case 28: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -- break; -- case 29: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -- break; -- case 30: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P4_16x16) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -- break; -- default: -- gb_tile_moden = 0; -- break; -- } -- adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; -- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); -- } -- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { -- switch (reg_offset) { -- case 0: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 1: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 2: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 3: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 4: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -- NUM_BANKS(ADDR_SURF_8_BANK)); -- break; -- case 5: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -- NUM_BANKS(ADDR_SURF_4_BANK)); -- break; -- case 6: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -- NUM_BANKS(ADDR_SURF_4_BANK)); -- break; -- case 8: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 9: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 10: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 11: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -- NUM_BANKS(ADDR_SURF_8_BANK)); -- break; -- case 12: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 13: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_8_BANK)); -- break; -- case 14: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -- NUM_BANKS(ADDR_SURF_4_BANK)); -- break; -- default: -- gb_tile_moden = 0; -- break; -- } -- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; -- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); -- } -+ tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -+ TILE_SPLIT(split_equal_to_row_size)); -+ tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -+ TILE_SPLIT(split_equal_to_row_size)); -+ tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -+ TILE_SPLIT(split_equal_to_row_size)); -+ tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -+ TILE_SPLIT(split_equal_to_row_size)); -+ tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); -+ tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); -+ tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -+ tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -+ tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -+ tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); -+ tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -+ tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -+ tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -+ tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -+ tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); -+ tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); -+ tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -+ tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -+ tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P4_16x16) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -+ -+ macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -+ NUM_BANKS(ADDR_SURF_8_BANK)); -+ macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -+ NUM_BANKS(ADDR_SURF_4_BANK)); -+ macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -+ NUM_BANKS(ADDR_SURF_4_BANK)); -+ macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -+ NUM_BANKS(ADDR_SURF_8_BANK)); -+ macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_8_BANK)); -+ macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | -+ NUM_BANKS(ADDR_SURF_4_BANK)); -+ -+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) -+ WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); -+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) -+ if (reg_offset != 7) -+ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); - break; - case CHIP_KABINI: - case CHIP_KAVERI: - case CHIP_MULLINS: - default: -- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { -- switch (reg_offset) { -- case 0: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 1: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 2: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 3: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 4: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -- TILE_SPLIT(split_equal_to_row_size)); -- break; -- case 5: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -- break; -- case 6: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -- TILE_SPLIT(split_equal_to_row_size)); -- break; -- case 7: -- gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); -- break; -- -- case 8: -- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | -- PIPE_CONFIG(ADDR_SURF_P2)); -- break; -- case 9: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); -- break; -- case 10: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -- break; -- case 11: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -- break; -- case 12: -- gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); -- break; -- case 13: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); -- break; -- case 14: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -- break; -- case 15: -- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -- break; -- case 16: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -- break; -- case 17: -- gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); -- break; -- case 18: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 19: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); -- break; -- case 20: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 21: -- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 22: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 23: -- gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); -- break; -- case 24: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 25: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 26: -- gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -- break; -- case 27: -- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); -- break; -- case 28: -- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -- break; -- case 29: -- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -- PIPE_CONFIG(ADDR_SURF_P2) | -- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -- break; -- case 30: -- gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); -- break; -- default: -- gb_tile_moden = 0; -- break; -- } -- adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; -- WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); -- } -- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { -- switch (reg_offset) { -- case 0: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_8_BANK)); -- break; -- case 1: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_8_BANK)); -- break; -- case 2: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_8_BANK)); -- break; -- case 3: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_8_BANK)); -- break; -- case 4: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_8_BANK)); -- break; -- case 5: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_8_BANK)); -- break; -- case 6: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_8_BANK)); -- break; -- case 8: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 9: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 10: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 11: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 12: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 13: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -- NUM_BANKS(ADDR_SURF_16_BANK)); -- break; -- case 14: -- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -- NUM_BANKS(ADDR_SURF_8_BANK)); -- break; -- default: -- gb_tile_moden = 0; -- break; -- } -- adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; -- WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); -- } -+ tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -+ TILE_SPLIT(split_equal_to_row_size)); -+ tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); -+ tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | -+ TILE_SPLIT(split_equal_to_row_size)); -+ tile[7] = (TILE_SPLIT(split_equal_to_row_size)); -+ tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | -+ PIPE_CONFIG(ADDR_SURF_P2)); -+ tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); -+ tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -+ tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -+ tile[12] = (TILE_SPLIT(split_equal_to_row_size)); -+ tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); -+ tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -+ tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -+ tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -+ tile[17] = (TILE_SPLIT(split_equal_to_row_size)); -+ tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); -+ tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[23] = (TILE_SPLIT(split_equal_to_row_size)); -+ tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); -+ tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); -+ tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); -+ tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | -+ PIPE_CONFIG(ADDR_SURF_P2) | -+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | -+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); -+ tile[30] = (TILE_SPLIT(split_equal_to_row_size)); -+ -+ macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_8_BANK)); -+ macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_8_BANK)); -+ macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_8_BANK)); -+ macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_8_BANK)); -+ macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_8_BANK)); -+ macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_8_BANK)); -+ macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_8_BANK)); -+ macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | -+ NUM_BANKS(ADDR_SURF_16_BANK)); -+ macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | -+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | -+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | -+ NUM_BANKS(ADDR_SURF_8_BANK)); -+ -+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) -+ WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); -+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) -+ if (reg_offset != 7) -+ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); - break; - } - } --- -2.7.4 - |