diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/0016-yocto-amd-drm-amdgpu-add-UVD-6-0-register-headers.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/0016-yocto-amd-drm-amdgpu-add-UVD-6-0-register-headers.patch | 5877 |
1 files changed, 5877 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0016-yocto-amd-drm-amdgpu-add-UVD-6-0-register-headers.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0016-yocto-amd-drm-amdgpu-add-UVD-6-0-register-headers.patch new file mode 100644 index 00000000..f793147c --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/0016-yocto-amd-drm-amdgpu-add-UVD-6-0-register-headers.patch @@ -0,0 +1,5877 @@ +From fe8e4443319e4c3f6fdefe2c9c3da2e4cd38867d Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 16 Apr 2015 15:27:33 -0400 +Subject: drm/amdgpu: add OSS 3.0 register headers + +These are register headers for the OSS (OS Services) +block on the GPU. + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com> + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h +new file mode 100644 +index 0000000..f56c68b +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_d.h +@@ -0,0 +1,688 @@ ++/* ++ * OSS_3_0 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef OSS_3_0_D_H ++#define OSS_3_0_D_H ++ ++#define mmIH_VMID_0_LUT 0xe00 ++#define mmIH_VMID_1_LUT 0xe01 ++#define mmIH_VMID_2_LUT 0xe02 ++#define mmIH_VMID_3_LUT 0xe03 ++#define mmIH_VMID_4_LUT 0xe04 ++#define mmIH_VMID_5_LUT 0xe05 ++#define mmIH_VMID_6_LUT 0xe06 ++#define mmIH_VMID_7_LUT 0xe07 ++#define mmIH_VMID_8_LUT 0xe08 ++#define mmIH_VMID_9_LUT 0xe09 ++#define mmIH_VMID_10_LUT 0xe0a ++#define mmIH_VMID_11_LUT 0xe0b ++#define mmIH_VMID_12_LUT 0xe0c ++#define mmIH_VMID_13_LUT 0xe0d ++#define mmIH_VMID_14_LUT 0xe0e ++#define mmIH_VMID_15_LUT 0xe0f ++#define mmIH_RB_CNTL 0xe30 ++#define mmIH_RB_BASE 0xe31 ++#define mmIH_RB_RPTR 0xe32 ++#define mmIH_RB_WPTR 0xe33 ++#define mmIH_RB_WPTR_ADDR_HI 0xe34 ++#define mmIH_RB_WPTR_ADDR_LO 0xe35 ++#define mmIH_CNTL 0xe36 ++#define mmIH_LEVEL_STATUS 0xe37 ++#define mmIH_STATUS 0xe38 ++#define mmIH_PERFMON_CNTL 0xe39 ++#define mmIH_PERFCOUNTER0_RESULT 0xe3a ++#define mmIH_PERFCOUNTER1_RESULT 0xe3b ++#define mmIH_DEBUG 0xe3c ++#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d ++#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e ++#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f ++#define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40 ++#define mmIH_DSM_MATCH_DATA_CONTROL 0xe41 ++#define mmIH_DOORBELL_RPTR 0xe42 ++#define mmIH_ACTIVE_FCN_ID 0xe43 ++#define mmIH_VF_RB_STATUS 0xe44 ++#define mmIH_VF_ENABLE 0xe45 ++#define mmIH_VIRT_RESET_REQ 0xe46 ++#define mmIH_VF_RB_BIF_STATUS 0xe47 ++#define mmIH_VERSION 0xe48 ++#define mmIH_LEVEL_INTR_MASK 0xe49 ++#define mmIH_RESET_INCOMPLETE_INT_CNTL 0xe4a ++#define mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT 0xe4b ++#define mmSEM_MCIF_CONFIG 0xf90 ++#define mmSDMA_CONFIG 0xf91 ++#define mmSDMA1_CONFIG 0xf92 ++#define mmUVD_CONFIG 0xf93 ++#define mmVCE_CONFIG 0xf94 ++#define mmSEM_VF_ENABLE 0xf95 ++#define mmCP_CONFIG 0xf96 ++#define mmSEM_ACTIVE_FCN_ID 0xf97 ++#define mmSEM_VIRT_RESET_REQ 0xf98 ++#define mmSEM_STATUS 0xf99 ++#define mmSEM_EDC_CONFIG 0xf9a ++#define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b ++#define mmSEM_MAILBOX 0xf9c ++#define mmSEM_MAILBOX_CONTROL 0xf9d ++#define mmSEM_CHICKEN_BITS 0xf9e ++#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0xf9f ++#define mmSRBM_CNTL 0x390 ++#define mmSRBM_GFX_CNTL 0x391 ++#define mmSRBM_READ_CNTL 0x392 ++#define mmSRBM_STATUS2 0x393 ++#define mmSRBM_STATUS 0x394 ++#define mmSRBM_STATUS3 0x395 ++#define mmSRBM_SOFT_RESET 0x398 ++#define mmSRBM_DEBUG_CNTL 0x399 ++#define mmSRBM_DEBUG_DATA 0x39a ++#define mmSRBM_CHIP_REVISION 0x39b ++#define mmSRBM_CREDIT_RECOVER_CNTL 0x39c ++#define mmSRBM_CREDIT_RECOVER 0x39d ++#define mmSRBM_CREDIT_RESET 0x39e ++#define mmCC_SYS_RB_REDUNDANCY 0x39f ++#define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0 ++#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1 ++#define mmSRBM_MC_CLKEN_CNTL 0x3b3 ++#define mmSRBM_SYS_CLKEN_CNTL 0x3b4 ++#define mmSRBM_VCE_CLKEN_CNTL 0x3b5 ++#define mmSRBM_UVD_CLKEN_CNTL 0x3b6 ++#define mmSRBM_SDMA_CLKEN_CNTL 0x3b7 ++#define mmSRBM_SAM_CLKEN_CNTL 0x3b8 ++#define mmSRBM_ISP_CLKEN_CNTL 0x3b9 ++#define mmSRBM_VP8_CLKEN_CNTL 0x3ba ++#define mmSRBM_DEBUG 0x3a4 ++#define mmSRBM_DEBUG_SNAPSHOT 0x3a5 ++#define mmSRBM_DEBUG_SNAPSHOT2 0x3ad ++#define mmSRBM_READ_ERROR 0x3a6 ++#define mmSRBM_READ_ERROR2 0x3ae ++#define mmSRBM_INT_CNTL 0x3a8 ++#define mmSRBM_INT_STATUS 0x3a9 ++#define mmSRBM_INT_ACK 0x3aa ++#define mmSRBM_FIREWALL_ERROR_SRC 0x3ab ++#define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac ++#define mmSRBM_DSM_TRIG_CNTL0 0x3af ++#define mmSRBM_DSM_TRIG_CNTL1 0x3b0 ++#define mmSRBM_DSM_TRIG_MASK0 0x3b1 ++#define mmSRBM_DSM_TRIG_MASK1 0x3b2 ++#define mmSRBM_PERFMON_CNTL 0x7c00 ++#define mmSRBM_PERFCOUNTER0_SELECT 0x7c01 ++#define mmSRBM_PERFCOUNTER1_SELECT 0x7c02 ++#define mmSRBM_PERFCOUNTER0_LO 0x7c03 ++#define mmSRBM_PERFCOUNTER0_HI 0x7c04 ++#define mmSRBM_PERFCOUNTER1_LO 0x7c05 ++#define mmSRBM_PERFCOUNTER1_HI 0x7c06 ++#define mmSRBM_CAM_INDEX 0xfe34 ++#define mmSRBM_CAM_DATA 0xfe35 ++#define mmSRBM_MC_DOMAIN_ADDR0 0xfa00 ++#define mmSRBM_MC_DOMAIN_ADDR1 0xfa01 ++#define mmSRBM_MC_DOMAIN_ADDR2 0xfa02 ++#define mmSRBM_MC_DOMAIN_ADDR3 0xfa03 ++#define mmSRBM_MC_DOMAIN_ADDR4 0xfa04 ++#define mmSRBM_MC_DOMAIN_ADDR5 0xfa05 ++#define mmSRBM_MC_DOMAIN_ADDR6 0xfa06 ++#define mmSRBM_SYS_DOMAIN_ADDR0 0xfa08 ++#define mmSRBM_SYS_DOMAIN_ADDR1 0xfa09 ++#define mmSRBM_SYS_DOMAIN_ADDR2 0xfa0a ++#define mmSRBM_SYS_DOMAIN_ADDR3 0xfa0b ++#define mmSRBM_SYS_DOMAIN_ADDR4 0xfa0c ++#define mmSRBM_SYS_DOMAIN_ADDR5 0xfa0d ++#define mmSRBM_SYS_DOMAIN_ADDR6 0xfa0e ++#define mmSRBM_SDMA_DOMAIN_ADDR0 0xfa10 ++#define mmSRBM_SDMA_DOMAIN_ADDR1 0xfa11 ++#define mmSRBM_SDMA_DOMAIN_ADDR2 0xfa12 ++#define mmSRBM_SDMA_DOMAIN_ADDR3 0xfa13 ++#define mmSRBM_UVD_DOMAIN_ADDR0 0xfa14 ++#define mmSRBM_UVD_DOMAIN_ADDR1 0xfa15 ++#define mmSRBM_UVD_DOMAIN_ADDR2 0xfa16 ++#define mmSRBM_VCE_DOMAIN_ADDR0 0xfa18 ++#define mmSRBM_VCE_DOMAIN_ADDR1 0xfa19 ++#define mmSRBM_VCE_DOMAIN_ADDR2 0xfa1a ++#define mmSRBM_SAM_DOMAIN_ADDR0 0xfa1c ++#define mmSRBM_SAM_DOMAIN_ADDR1 0xfa1d ++#define mmSRBM_SAM_DOMAIN_ADDR2 0xfa1e ++#define mmSRBM_ISP_DOMAIN_ADDR0 0xfa20 ++#define mmSRBM_ISP_DOMAIN_ADDR1 0xfa21 ++#define mmSRBM_ISP_DOMAIN_ADDR2 0xfa22 ++#define mmSRBM_VP8_DOMAIN_ADDR0 0xfa24 ++#define mmSYS_GRBM_GFX_INDEX_SELECT 0xfa2c ++#define mmSYS_GRBM_GFX_INDEX_DATA 0xfa2d ++#define mmSRBM_GFX_CNTL_SELECT 0xfa2e ++#define mmSRBM_GFX_CNTL_DATA 0xfa2f ++#define mmSRBM_VF_ENABLE 0xfa30 ++#define mmSRBM_VIRT_CNTL 0xfa31 ++#define mmSRBM_VIRT_RESET_REQ 0xfa32 ++#define mmCC_DRM_ID_STRAPS 0x1559 ++#define mmCGTT_DRM_CLK_CTRL0 0x1579 ++#define ixDH_TEST 0x0 ++#define ixKHFS0 0x4 ++#define ixKHFS1 0x8 ++#define ixKHFS2 0xc ++#define ixKHFS3 0x10 ++#define ixKSESSION0 0x14 ++#define ixKSESSION1 0x18 ++#define ixKSESSION2 0x1c ++#define ixKSESSION3 0x20 ++#define ixKSIG0 0x24 ++#define ixKSIG1 0x28 ++#define ixKSIG2 0x2c ++#define ixKSIG3 0x30 ++#define ixEXP0 0x34 ++#define ixEXP1 0x38 ++#define ixEXP2 0x3c ++#define ixEXP3 0x40 ++#define ixEXP4 0x44 ++#define ixEXP5 0x48 ++#define ixEXP6 0x4c ++#define ixEXP7 0x50 ++#define ixLX0 0x54 ++#define ixLX1 0x58 ++#define ixLX2 0x5c ++#define ixLX3 0x60 ++#define ixCLIENT2_K0 0x1b4 ++#define ixCLIENT2_K1 0x1b8 ++#define ixCLIENT2_K2 0x1bc ++#define ixCLIENT2_K3 0x1c0 ++#define ixCLIENT2_CK0 0x1c4 ++#define ixCLIENT2_CK1 0x1c8 ++#define ixCLIENT2_CK2 0x1cc ++#define ixCLIENT2_CK3 0x1d0 ++#define ixCLIENT2_CD0 0x1d4 ++#define ixCLIENT2_CD1 0x1d8 ++#define ixCLIENT2_CD2 0x1dc ++#define ixCLIENT2_CD3 0x1e0 ++#define ixCLIENT2_BM 0x1e4 ++#define ixCLIENT2_OFFSET 0x1e8 ++#define ixCLIENT2_STATUS 0x1ec ++#define ixCLIENT0_K0 0x1f0 ++#define ixCLIENT0_K1 0x1f4 ++#define ixCLIENT0_K2 0x1f8 ++#define ixCLIENT0_K3 0x1fc ++#define ixCLIENT0_CK0 0x200 ++#define ixCLIENT0_CK1 0x204 ++#define ixCLIENT0_CK2 0x208 ++#define ixCLIENT0_CK3 0x20c ++#define ixCLIENT0_CD0 0x210 ++#define ixCLIENT0_CD1 0x214 ++#define ixCLIENT0_CD2 0x218 ++#define ixCLIENT0_CD3 0x21c ++#define ixCLIENT0_BM 0x220 ++#define ixCLIENT0_OFFSET 0x224 ++#define ixCLIENT0_STATUS 0x228 ++#define ixCLIENT1_K0 0x22c ++#define ixCLIENT1_K1 0x230 ++#define ixCLIENT1_K2 0x234 ++#define ixCLIENT1_K3 0x238 ++#define ixCLIENT1_CK0 0x23c ++#define ixCLIENT1_CK1 0x240 ++#define ixCLIENT1_CK2 0x244 ++#define ixCLIENT1_CK3 0x248 ++#define ixCLIENT1_CD0 0x24c ++#define ixCLIENT1_CD1 0x250 ++#define ixCLIENT1_CD2 0x254 ++#define ixCLIENT1_CD3 0x258 ++#define ixCLIENT1_BM 0x25c ++#define ixCLIENT1_OFFSET 0x260 ++#define ixCLIENT1_PORT_STATUS 0x264 ++#define ixKEFUSE0 0x268 ++#define ixKEFUSE1 0x26c ++#define ixKEFUSE2 0x270 ++#define ixKEFUSE3 0x274 ++#define ixHFS_SEED0 0x278 ++#define ixHFS_SEED1 0x27c ++#define ixHFS_SEED2 0x280 ++#define ixHFS_SEED3 0x284 ++#define ixRINGOSC_MASK 0x288 ++#define ixCLIENT0_OFFSET_HI 0x290 ++#define ixCLIENT1_OFFSET_HI 0x294 ++#define ixCLIENT2_OFFSET_HI 0x298 ++#define ixSPU_PORT_STATUS 0x29c ++#define ixCLIENT3_OFFSET_HI 0x2a0 ++#define ixCLIENT3_K0 0x2a4 ++#define ixCLIENT3_K1 0x2a8 ++#define ixCLIENT3_K2 0x2ac ++#define ixCLIENT3_K3 0x2b0 ++#define ixCLIENT3_CK0 0x2b4 ++#define ixCLIENT3_CK1 0x2b8 ++#define ixCLIENT3_CK2 0x2bc ++#define ixCLIENT3_CK3 0x2c0 ++#define ixCLIENT3_CD0 0x2c4 ++#define ixCLIENT3_CD1 0x2c8 ++#define ixCLIENT3_CD2 0x2cc ++#define ixCLIENT3_CD3 0x2d0 ++#define ixCLIENT3_BM 0x2d4 ++#define ixCLIENT3_OFFSET 0x2d8 ++#define ixCLIENT3_STATUS 0x2dc ++#define ixCLIENT4_OFFSET_HI 0x2e0 ++#define ixCLIENT4_K0 0x2e4 ++#define ixCLIENT4_K1 0x2e8 ++#define ixCLIENT4_K2 0x2ec ++#define ixCLIENT4_K3 0x2f0 ++#define ixCLIENT4_CK0 0x2f4 ++#define ixCLIENT4_CK1 0x2f8 ++#define ixCLIENT4_CK2 0x2fc ++#define ixCLIENT4_CK3 0x300 ++#define ixCLIENT4_CD0 0x304 ++#define ixCLIENT4_CD1 0x308 ++#define ixCLIENT4_CD2 0x30c ++#define ixCLIENT4_CD3 0x310 ++#define ixCLIENT4_BM 0x314 ++#define ixCLIENT4_OFFSET 0x318 ++#define ixCLIENT4_STATUS 0x31c ++#define mmDC_TEST_DEBUG_INDEX 0x157c ++#define mmDC_TEST_DEBUG_DATA 0x157d ++#define mmSDMA0_UCODE_ADDR 0x3400 ++#define mmSDMA0_UCODE_DATA 0x3401 ++#define mmSDMA0_POWER_CNTL 0x3402 ++#define mmSDMA0_CLK_CTRL 0x3403 ++#define mmSDMA0_CNTL 0x3404 ++#define mmSDMA0_CHICKEN_BITS 0x3405 ++#define mmSDMA0_TILING_CONFIG 0x3406 ++#define mmSDMA0_HASH 0x3407 ++#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409 ++#define mmSDMA0_RB_RPTR_FETCH 0x340a ++#define mmSDMA0_IB_OFFSET_FETCH 0x340b ++#define mmSDMA0_PROGRAM 0x340c ++#define mmSDMA0_STATUS_REG 0x340d ++#define mmSDMA0_STATUS1_REG 0x340e ++#define mmSDMA0_RD_BURST_CNTL 0x340f ++#define mmSDMA0_PERFMON_CNTL 0x9000 ++#define mmSDMA0_PERFCOUNTER0_RESULT 0x9001 ++#define mmSDMA0_PERFCOUNTER1_RESULT 0x9002 ++#define mmSDMA0_F32_CNTL 0x3412 ++#define mmSDMA0_FREEZE 0x3413 ++#define mmSDMA0_PHASE0_QUANTUM 0x3414 ++#define mmSDMA0_PHASE1_QUANTUM 0x3415 ++#define mmSDMA_POWER_GATING 0x3416 ++#define mmSDMA_PGFSM_CONFIG 0x3417 ++#define mmSDMA_PGFSM_WRITE 0x3418 ++#define mmSDMA_PGFSM_READ 0x3419 ++#define mmSDMA0_EDC_CONFIG 0x341a ++#define mmSDMA0_VM_CNTL 0x3420 ++#define mmSDMA0_VM_CTX_LO 0x3421 ++#define mmSDMA0_VM_CTX_HI 0x3422 ++#define mmSDMA0_STATUS2_REG 0x3423 ++#define mmSDMA0_ACTIVE_FCN_ID 0x3424 ++#define mmSDMA0_VM_CTX_CNTL 0x3425 ++#define mmSDMA0_VIRT_RESET_REQ 0x3426 ++#define mmSDMA0_VF_ENABLE 0x3427 ++#define mmSDMA0_BA_THRESHOLD 0x341b ++#define mmSDMA0_ID 0x341c ++#define mmSDMA0_VERSION 0x341d ++#define mmSDMA0_ATOMIC_CNTL 0x3428 ++#define mmSDMA0_ATOMIC_PREOP_LO 0x3429 ++#define mmSDMA0_ATOMIC_PREOP_HI 0x342a ++#define mmSDMA0_POWER_CNTL_IDLE 0x342c ++#define mmSDMA0_PERF_REG_TYPE0 0x3477 ++#define mmSDMA0_CONTEXT_REG_TYPE0 0x3478 ++#define mmSDMA0_CONTEXT_REG_TYPE1 0x3479 ++#define mmSDMA0_CONTEXT_REG_TYPE2 0x347a ++#define mmSDMA0_PUB_REG_TYPE0 0x347c ++#define mmSDMA0_PUB_REG_TYPE1 0x347d ++#define mmSDMA0_GFX_RB_CNTL 0x3480 ++#define mmSDMA0_GFX_RB_BASE 0x3481 ++#define mmSDMA0_GFX_RB_BASE_HI 0x3482 ++#define mmSDMA0_GFX_RB_RPTR 0x3483 ++#define mmSDMA0_GFX_RB_WPTR 0x3484 ++#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485 ++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 ++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 ++#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488 ++#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489 ++#define mmSDMA0_GFX_IB_CNTL 0x348a ++#define mmSDMA0_GFX_IB_RPTR 0x348b ++#define mmSDMA0_GFX_IB_OFFSET 0x348c ++#define mmSDMA0_GFX_IB_BASE_LO 0x348d ++#define mmSDMA0_GFX_IB_BASE_HI 0x348e ++#define mmSDMA0_GFX_IB_SIZE 0x348f ++#define mmSDMA0_GFX_SKIP_CNTL 0x3490 ++#define mmSDMA0_GFX_CONTEXT_STATUS 0x3491 ++#define mmSDMA0_GFX_DOORBELL 0x3492 ++#define mmSDMA0_GFX_CONTEXT_CNTL 0x3493 ++#define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7 ++#define mmSDMA0_GFX_APE1_CNTL 0x34a8 ++#define mmSDMA0_GFX_DOORBELL_LOG 0x34a9 ++#define mmSDMA0_GFX_WATERMARK 0x34aa ++#define mmSDMA0_GFX_CSA_ADDR_LO 0x34ac ++#define mmSDMA0_GFX_CSA_ADDR_HI 0x34ad ++#define mmSDMA0_GFX_IB_SUB_REMAIN 0x34af ++#define mmSDMA0_GFX_PREEMPT 0x34b0 ++#define mmSDMA0_GFX_DUMMY_REG 0x34b1 ++#define mmSDMA0_GFX_MIDCMD_DATA0 0x34c1 ++#define mmSDMA0_GFX_MIDCMD_DATA1 0x34c2 ++#define mmSDMA0_GFX_MIDCMD_DATA2 0x34c3 ++#define mmSDMA0_GFX_MIDCMD_DATA3 0x34c4 ++#define mmSDMA0_GFX_MIDCMD_DATA4 0x34c5 ++#define mmSDMA0_GFX_MIDCMD_DATA5 0x34c6 ++#define mmSDMA0_GFX_MIDCMD_CNTL 0x34c7 ++#define mmSDMA0_RLC0_RB_CNTL 0x3500 ++#define mmSDMA0_RLC0_RB_BASE 0x3501 ++#define mmSDMA0_RLC0_RB_BASE_HI 0x3502 ++#define mmSDMA0_RLC0_RB_RPTR 0x3503 ++#define mmSDMA0_RLC0_RB_WPTR 0x3504 ++#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 ++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506 ++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507 ++#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508 ++#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509 ++#define mmSDMA0_RLC0_IB_CNTL 0x350a ++#define mmSDMA0_RLC0_IB_RPTR 0x350b ++#define mmSDMA0_RLC0_IB_OFFSET 0x350c ++#define mmSDMA0_RLC0_IB_BASE_LO 0x350d ++#define mmSDMA0_RLC0_IB_BASE_HI 0x350e ++#define mmSDMA0_RLC0_IB_SIZE 0x350f ++#define mmSDMA0_RLC0_SKIP_CNTL 0x3510 ++#define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511 ++#define mmSDMA0_RLC0_DOORBELL 0x3512 ++#define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527 ++#define mmSDMA0_RLC0_APE1_CNTL 0x3528 ++#define mmSDMA0_RLC0_DOORBELL_LOG 0x3529 ++#define mmSDMA0_RLC0_WATERMARK 0x352a ++#define mmSDMA0_RLC0_CSA_ADDR_LO 0x352c ++#define mmSDMA0_RLC0_CSA_ADDR_HI 0x352d ++#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x352f ++#define mmSDMA0_RLC0_PREEMPT 0x3530 ++#define mmSDMA0_RLC0_DUMMY_REG 0x3531 ++#define mmSDMA0_RLC0_MIDCMD_DATA0 0x3541 ++#define mmSDMA0_RLC0_MIDCMD_DATA1 0x3542 ++#define mmSDMA0_RLC0_MIDCMD_DATA2 0x3543 ++#define mmSDMA0_RLC0_MIDCMD_DATA3 0x3544 ++#define mmSDMA0_RLC0_MIDCMD_DATA4 0x3545 ++#define mmSDMA0_RLC0_MIDCMD_DATA5 0x3546 ++#define mmSDMA0_RLC0_MIDCMD_CNTL 0x3547 ++#define mmSDMA0_RLC1_RB_CNTL 0x3580 ++#define mmSDMA0_RLC1_RB_BASE 0x3581 ++#define mmSDMA0_RLC1_RB_BASE_HI 0x3582 ++#define mmSDMA0_RLC1_RB_RPTR 0x3583 ++#define mmSDMA0_RLC1_RB_WPTR 0x3584 ++#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585 ++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586 ++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587 ++#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588 ++#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589 ++#define mmSDMA0_RLC1_IB_CNTL 0x358a ++#define mmSDMA0_RLC1_IB_RPTR 0x358b ++#define mmSDMA0_RLC1_IB_OFFSET 0x358c ++#define mmSDMA0_RLC1_IB_BASE_LO 0x358d ++#define mmSDMA0_RLC1_IB_BASE_HI 0x358e ++#define mmSDMA0_RLC1_IB_SIZE 0x358f ++#define mmSDMA0_RLC1_SKIP_CNTL 0x3590 ++#define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591 ++#define mmSDMA0_RLC1_DOORBELL 0x3592 ++#define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7 ++#define mmSDMA0_RLC1_APE1_CNTL 0x35a8 ++#define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9 ++#define mmSDMA0_RLC1_WATERMARK 0x35aa ++#define mmSDMA0_RLC1_CSA_ADDR_LO 0x35ac ++#define mmSDMA0_RLC1_CSA_ADDR_HI 0x35ad ++#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x35af ++#define mmSDMA0_RLC1_PREEMPT 0x35b0 ++#define mmSDMA0_RLC1_DUMMY_REG 0x35b1 ++#define mmSDMA0_RLC1_MIDCMD_DATA0 0x35c1 ++#define mmSDMA0_RLC1_MIDCMD_DATA1 0x35c2 ++#define mmSDMA0_RLC1_MIDCMD_DATA2 0x35c3 ++#define mmSDMA0_RLC1_MIDCMD_DATA3 0x35c4 ++#define mmSDMA0_RLC1_MIDCMD_DATA4 0x35c5 ++#define mmSDMA0_RLC1_MIDCMD_DATA5 0x35c6 ++#define mmSDMA0_RLC1_MIDCMD_CNTL 0x35c7 ++#define mmSDMA1_UCODE_ADDR 0x3600 ++#define mmSDMA1_UCODE_DATA 0x3601 ++#define mmSDMA1_POWER_CNTL 0x3602 ++#define mmSDMA1_CLK_CTRL 0x3603 ++#define mmSDMA1_CNTL 0x3604 ++#define mmSDMA1_CHICKEN_BITS 0x3605 ++#define mmSDMA1_TILING_CONFIG 0x3606 ++#define mmSDMA1_HASH 0x3607 ++#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609 ++#define mmSDMA1_RB_RPTR_FETCH 0x360a ++#define mmSDMA1_IB_OFFSET_FETCH 0x360b ++#define mmSDMA1_PROGRAM 0x360c ++#define mmSDMA1_STATUS_REG 0x360d ++#define mmSDMA1_STATUS1_REG 0x360e ++#define mmSDMA1_RD_BURST_CNTL 0x360f ++#define mmSDMA1_PERFMON_CNTL 0x9010 ++#define mmSDMA1_PERFCOUNTER0_RESULT 0x9011 ++#define mmSDMA1_PERFCOUNTER1_RESULT 0x9012 ++#define mmSDMA1_F32_CNTL 0x3612 ++#define mmSDMA1_FREEZE 0x3613 ++#define mmSDMA1_PHASE0_QUANTUM 0x3614 ++#define mmSDMA1_PHASE1_QUANTUM 0x3615 ++#define mmSDMA1_EDC_CONFIG 0x361a ++#define mmSDMA1_VM_CNTL 0x3620 ++#define mmSDMA1_VM_CTX_LO 0x3621 ++#define mmSDMA1_VM_CTX_HI 0x3622 ++#define mmSDMA1_STATUS2_REG 0x3623 ++#define mmSDMA1_ACTIVE_FCN_ID 0x3624 ++#define mmSDMA1_VM_CTX_CNTL 0x3625 ++#define mmSDMA1_VIRT_RESET_REQ 0x3626 ++#define mmSDMA1_VF_ENABLE 0x3627 ++#define mmSDMA1_BA_THRESHOLD 0x361b ++#define mmSDMA1_ID 0x361c ++#define mmSDMA1_VERSION 0x361d ++#define mmSDMA1_ATOMIC_CNTL 0x3628 ++#define mmSDMA1_ATOMIC_PREOP_LO 0x3629 ++#define mmSDMA1_ATOMIC_PREOP_HI 0x362a ++#define mmSDMA1_POWER_CNTL_IDLE 0x362c ++#define mmSDMA1_PERF_REG_TYPE0 0x3677 ++#define mmSDMA1_CONTEXT_REG_TYPE0 0x3678 ++#define mmSDMA1_CONTEXT_REG_TYPE1 0x3679 ++#define mmSDMA1_CONTEXT_REG_TYPE2 0x367a ++#define mmSDMA1_PUB_REG_TYPE0 0x367c ++#define mmSDMA1_PUB_REG_TYPE1 0x367d ++#define mmSDMA1_GFX_RB_CNTL 0x3680 ++#define mmSDMA1_GFX_RB_BASE 0x3681 ++#define mmSDMA1_GFX_RB_BASE_HI 0x3682 ++#define mmSDMA1_GFX_RB_RPTR 0x3683 ++#define mmSDMA1_GFX_RB_WPTR 0x3684 ++#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685 ++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686 ++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687 ++#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688 ++#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689 ++#define mmSDMA1_GFX_IB_CNTL 0x368a ++#define mmSDMA1_GFX_IB_RPTR 0x368b ++#define mmSDMA1_GFX_IB_OFFSET 0x368c ++#define mmSDMA1_GFX_IB_BASE_LO 0x368d ++#define mmSDMA1_GFX_IB_BASE_HI 0x368e ++#define mmSDMA1_GFX_IB_SIZE 0x368f ++#define mmSDMA1_GFX_SKIP_CNTL 0x3690 ++#define mmSDMA1_GFX_CONTEXT_STATUS 0x3691 ++#define mmSDMA1_GFX_DOORBELL 0x3692 ++#define mmSDMA1_GFX_CONTEXT_CNTL 0x3693 ++#define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7 ++#define mmSDMA1_GFX_APE1_CNTL 0x36a8 ++#define mmSDMA1_GFX_DOORBELL_LOG 0x36a9 ++#define mmSDMA1_GFX_WATERMARK 0x36aa ++#define mmSDMA1_GFX_CSA_ADDR_LO 0x36ac ++#define mmSDMA1_GFX_CSA_ADDR_HI 0x36ad ++#define mmSDMA1_GFX_IB_SUB_REMAIN 0x36af ++#define mmSDMA1_GFX_PREEMPT 0x36b0 ++#define mmSDMA1_GFX_DUMMY_REG 0x36b1 ++#define mmSDMA1_GFX_MIDCMD_DATA0 0x36c1 ++#define mmSDMA1_GFX_MIDCMD_DATA1 0x36c2 ++#define mmSDMA1_GFX_MIDCMD_DATA2 0x36c3 ++#define mmSDMA1_GFX_MIDCMD_DATA3 0x36c4 ++#define mmSDMA1_GFX_MIDCMD_DATA4 0x36c5 ++#define mmSDMA1_GFX_MIDCMD_DATA5 0x36c6 ++#define mmSDMA1_GFX_MIDCMD_CNTL 0x36c7 ++#define mmSDMA1_RLC0_RB_CNTL 0x3700 ++#define mmSDMA1_RLC0_RB_BASE 0x3701 ++#define mmSDMA1_RLC0_RB_BASE_HI 0x3702 ++#define mmSDMA1_RLC0_RB_RPTR 0x3703 ++#define mmSDMA1_RLC0_RB_WPTR 0x3704 ++#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 ++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706 ++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707 ++#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708 ++#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709 ++#define mmSDMA1_RLC0_IB_CNTL 0x370a ++#define mmSDMA1_RLC0_IB_RPTR 0x370b ++#define mmSDMA1_RLC0_IB_OFFSET 0x370c ++#define mmSDMA1_RLC0_IB_BASE_LO 0x370d ++#define mmSDMA1_RLC0_IB_BASE_HI 0x370e ++#define mmSDMA1_RLC0_IB_SIZE 0x370f ++#define mmSDMA1_RLC0_SKIP_CNTL 0x3710 ++#define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711 ++#define mmSDMA1_RLC0_DOORBELL 0x3712 ++#define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727 ++#define mmSDMA1_RLC0_APE1_CNTL 0x3728 ++#define mmSDMA1_RLC0_DOORBELL_LOG 0x3729 ++#define mmSDMA1_RLC0_WATERMARK 0x372a ++#define mmSDMA1_RLC0_CSA_ADDR_LO 0x372c ++#define mmSDMA1_RLC0_CSA_ADDR_HI 0x372d ++#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x372f ++#define mmSDMA1_RLC0_PREEMPT 0x3730 ++#define mmSDMA1_RLC0_DUMMY_REG 0x3731 ++#define mmSDMA1_RLC0_MIDCMD_DATA0 0x3741 ++#define mmSDMA1_RLC0_MIDCMD_DATA1 0x3742 ++#define mmSDMA1_RLC0_MIDCMD_DATA2 0x3743 ++#define mmSDMA1_RLC0_MIDCMD_DATA3 0x3744 ++#define mmSDMA1_RLC0_MIDCMD_DATA4 0x3745 ++#define mmSDMA1_RLC0_MIDCMD_DATA5 0x3746 ++#define mmSDMA1_RLC0_MIDCMD_CNTL 0x3747 ++#define mmSDMA1_RLC1_RB_CNTL 0x3780 ++#define mmSDMA1_RLC1_RB_BASE 0x3781 ++#define mmSDMA1_RLC1_RB_BASE_HI 0x3782 ++#define mmSDMA1_RLC1_RB_RPTR 0x3783 ++#define mmSDMA1_RLC1_RB_WPTR 0x3784 ++#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785 ++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786 ++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787 ++#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788 ++#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789 ++#define mmSDMA1_RLC1_IB_CNTL 0x378a ++#define mmSDMA1_RLC1_IB_RPTR 0x378b ++#define mmSDMA1_RLC1_IB_OFFSET 0x378c ++#define mmSDMA1_RLC1_IB_BASE_LO 0x378d ++#define mmSDMA1_RLC1_IB_BASE_HI 0x378e ++#define mmSDMA1_RLC1_IB_SIZE 0x378f ++#define mmSDMA1_RLC1_SKIP_CNTL 0x3790 ++#define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791 ++#define mmSDMA1_RLC1_DOORBELL 0x3792 ++#define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7 ++#define mmSDMA1_RLC1_APE1_CNTL 0x37a8 ++#define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9 ++#define mmSDMA1_RLC1_WATERMARK 0x37aa ++#define mmSDMA1_RLC1_CSA_ADDR_LO 0x37ac ++#define mmSDMA1_RLC1_CSA_ADDR_HI 0x37ad ++#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x37af ++#define mmSDMA1_RLC1_PREEMPT 0x37b0 ++#define mmSDMA1_RLC1_DUMMY_REG 0x37b1 ++#define mmSDMA1_RLC1_MIDCMD_DATA0 0x37c1 ++#define mmSDMA1_RLC1_MIDCMD_DATA1 0x37c2 ++#define mmSDMA1_RLC1_MIDCMD_DATA2 0x37c3 ++#define mmSDMA1_RLC1_MIDCMD_DATA3 0x37c4 ++#define mmSDMA1_RLC1_MIDCMD_DATA4 0x37c5 ++#define mmSDMA1_RLC1_MIDCMD_DATA5 0x37c6 ++#define mmSDMA1_RLC1_MIDCMD_CNTL 0x37c7 ++#define mmHDP_HOST_PATH_CNTL 0xb00 ++#define mmHDP_NONSURFACE_BASE 0xb01 ++#define mmHDP_NONSURFACE_INFO 0xb02 ++#define mmHDP_NONSURFACE_SIZE 0xb03 ++#define mmHDP_NONSURF_FLAGS 0xbc9 ++#define mmHDP_NONSURF_FLAGS_CLR 0xbca ++#define mmHDP_SW_SEMAPHORE 0xbcb ++#define mmHDP_DEBUG0 0xbcc ++#define mmHDP_DEBUG1 0xbcd ++#define mmHDP_LAST_SURFACE_HIT 0xbce ++#define mmHDP_TILING_CONFIG 0xbcf ++#define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0 ++#define mmHDP_OUTSTANDING_REQ 0xbd1 ++#define mmHDP_ADDR_CONFIG 0xbd2 ++#define mmHDP_MISC_CNTL 0xbd3 ++#define mmHDP_MEM_POWER_LS 0xbd4 ++#define mmHDP_NONSURFACE_PREFETCH 0xbd5 ++#define mmHDP_MEMIO_CNTL 0xbf6 ++#define mmHDP_MEMIO_ADDR 0xbf7 ++#define mmHDP_MEMIO_STATUS 0xbf8 ++#define mmHDP_MEMIO_WR_DATA 0xbf9 ++#define mmHDP_MEMIO_RD_DATA 0xbfa ++#define mmHDP_VF_ENABLE 0xbfb ++#define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00 ++#define mmHDP_XDP_D2H_FLUSH 0xc01 ++#define mmHDP_XDP_D2H_BAR_UPDATE 0xc02 ++#define mmHDP_XDP_D2H_RSVD_3 0xc03 ++#define mmHDP_XDP_D2H_RSVD_4 0xc04 ++#define mmHDP_XDP_D2H_RSVD_5 0xc05 ++#define mmHDP_XDP_D2H_RSVD_6 0xc06 ++#define mmHDP_XDP_D2H_RSVD_7 0xc07 ++#define mmHDP_XDP_D2H_RSVD_8 0xc08 ++#define mmHDP_XDP_D2H_RSVD_9 0xc09 ++#define mmHDP_XDP_D2H_RSVD_10 0xc0a ++#define mmHDP_XDP_D2H_RSVD_11 0xc0b ++#define mmHDP_XDP_D2H_RSVD_12 0xc0c ++#define mmHDP_XDP_D2H_RSVD_13 0xc0d ++#define mmHDP_XDP_D2H_RSVD_14 0xc0e ++#define mmHDP_XDP_D2H_RSVD_15 0xc0f ++#define mmHDP_XDP_D2H_RSVD_16 0xc10 ++#define mmHDP_XDP_D2H_RSVD_17 0xc11 ++#define mmHDP_XDP_D2H_RSVD_18 0xc12 ++#define mmHDP_XDP_D2H_RSVD_19 0xc13 ++#define mmHDP_XDP_D2H_RSVD_20 0xc14 ++#define mmHDP_XDP_D2H_RSVD_21 0xc15 ++#define mmHDP_XDP_D2H_RSVD_22 0xc16 ++#define mmHDP_XDP_D2H_RSVD_23 0xc17 ++#define mmHDP_XDP_D2H_RSVD_24 0xc18 ++#define mmHDP_XDP_D2H_RSVD_25 0xc19 ++#define mmHDP_XDP_D2H_RSVD_26 0xc1a ++#define mmHDP_XDP_D2H_RSVD_27 0xc1b ++#define mmHDP_XDP_D2H_RSVD_28 0xc1c ++#define mmHDP_XDP_D2H_RSVD_29 0xc1d ++#define mmHDP_XDP_D2H_RSVD_30 0xc1e ++#define mmHDP_XDP_D2H_RSVD_31 0xc1f ++#define mmHDP_XDP_D2H_RSVD_32 0xc20 ++#define mmHDP_XDP_D2H_RSVD_33 0xc21 ++#define mmHDP_XDP_D2H_RSVD_34 0xc22 ++#define mmHDP_XDP_DIRECT2HDP_LAST 0xc23 ++#define mmHDP_XDP_P2P_BAR_CFG 0xc24 ++#define mmHDP_XDP_P2P_MBX_OFFSET 0xc25 ++#define mmHDP_XDP_P2P_MBX_ADDR0 0xc26 ++#define mmHDP_XDP_P2P_MBX_ADDR1 0xc27 ++#define mmHDP_XDP_P2P_MBX_ADDR2 0xc28 ++#define mmHDP_XDP_P2P_MBX_ADDR3 0xc29 ++#define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a ++#define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b ++#define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c ++#define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d ++#define mmHDP_XDP_HDP_MC_CFG 0xc2e ++#define mmHDP_XDP_HST_CFG 0xc2f ++#define mmHDP_XDP_SID_CFG 0xc30 ++#define mmHDP_XDP_HDP_IPH_CFG 0xc31 ++#define mmHDP_XDP_SRBM_CFG 0xc32 ++#define mmHDP_XDP_CGTT_BLK_CTRL 0xc33 ++#define mmHDP_XDP_P2P_BAR0 0xc34 ++#define mmHDP_XDP_P2P_BAR1 0xc35 ++#define mmHDP_XDP_P2P_BAR2 0xc36 ++#define mmHDP_XDP_P2P_BAR3 0xc37 ++#define mmHDP_XDP_P2P_BAR4 0xc38 ++#define mmHDP_XDP_P2P_BAR5 0xc39 ++#define mmHDP_XDP_P2P_BAR6 0xc3a ++#define mmHDP_XDP_P2P_BAR7 0xc3b ++#define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c ++#define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d ++#define mmHDP_XDP_BUSY_STS 0xc3e ++#define mmHDP_XDP_STICKY 0xc3f ++#define mmHDP_XDP_CHKN 0xc40 ++#define mmHDP_XDP_DBG_ADDR 0xc41 ++#define mmHDP_XDP_DBG_DATA 0xc42 ++#define mmHDP_XDP_DBG_MASK 0xc43 ++#define mmHDP_XDP_BARS_ADDR_39_36 0xc44 ++ ++#endif /* OSS_3_0_D_H */ +diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h +new file mode 100644 +index 0000000..09338d8 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h +@@ -0,0 +1,1497 @@ ++/* ++ * OSS_3_0 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef OSS_3_0_ENUM_H ++#define OSS_3_0_ENUM_H ++ ++typedef enum IH_CLIENT_ID { ++ DC_IH_SRC_ID_START = 0x1, ++ DC_IH_SRC_ID_END = 0x1f, ++ VGA_IH_SRC_ID_START = 0x20, ++ VGA_IH_SRC_ID_END = 0x27, ++ CAP_IH_SRC_ID_START = 0x28, ++ CAP_IH_SRC_ID_END = 0x2f, ++ VIP_IH_SRC_ID_START = 0x30, ++ VIP_IH_SRC_ID_END = 0x3f, ++ ROM_IH_SRC_ID_START = 0x40, ++ ROM_IH_SRC_ID_END = 0x5d, ++ BIF_IH_SRC_ID_START = 0x5e, ++ SAM_IH_SRC_ID_START = 0x5f, ++ SRBM_IH_SRC_ID_START = 0x60, ++ SRBM_IH_SRC_ID_END = 0x67, ++ UVD_IH_SRC_ID_START = 0x72, ++ UVD_IH_SRC_ID_END = 0x85, ++ VMC_IH_SRC_ID_START = 0x86, ++ VMC_IH_SRC_ID_END = 0x8f, ++ RLC_IH_SRC_ID_START = 0x90, ++ RLC_IH_SRC_ID_END = 0xf3, ++ PDMA_IH_SRC_ID_START = 0xf4, ++ PDMA_IH_SRC_ID_END = 0xf7, ++ CG_IH_SRC_ID_START = 0xf8, ++ CG_IH_SRC_ID_END = 0xff, ++} IH_CLIENT_ID; ++typedef enum IH_PERF_SEL { ++ IH_PERF_SEL_CYCLE = 0x0, ++ IH_PERF_SEL_IDLE = 0x1, ++ IH_PERF_SEL_INPUT_IDLE = 0x2, ++ IH_PERF_SEL_CLIENT0_IH_STALL = 0x3, ++ IH_PERF_SEL_CLIENT1_IH_STALL = 0x4, ++ IH_PERF_SEL_CLIENT2_IH_STALL = 0x5, ++ IH_PERF_SEL_CLIENT3_IH_STALL = 0x6, ++ IH_PERF_SEL_CLIENT4_IH_STALL = 0x7, ++ IH_PERF_SEL_CLIENT5_IH_STALL = 0x8, ++ IH_PERF_SEL_CLIENT6_IH_STALL = 0x9, ++ IH_PERF_SEL_CLIENT7_IH_STALL = 0xa, ++ IH_PERF_SEL_RB_IDLE = 0xb, ++ IH_PERF_SEL_RB_FULL = 0xc, ++ IH_PERF_SEL_RB_OVERFLOW = 0xd, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK = 0xe, ++ IH_PERF_SEL_RB_WPTR_WRAP = 0xf, ++ IH_PERF_SEL_RB_RPTR_WRAP = 0x10, ++ IH_PERF_SEL_MC_WR_IDLE = 0x11, ++ IH_PERF_SEL_MC_WR_COUNT = 0x12, ++ IH_PERF_SEL_MC_WR_STALL = 0x13, ++ IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x14, ++ IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x15, ++ IH_PERF_SEL_BIF_RISING = 0x16, ++ IH_PERF_SEL_BIF_FALLING = 0x17, ++ IH_PERF_SEL_CLIENT8_IH_STALL = 0x18, ++ IH_PERF_SEL_CLIENT9_IH_STALL = 0x19, ++ IH_PERF_SEL_CLIENT10_IH_STALL = 0x1a, ++ IH_PERF_SEL_CLIENT11_IH_STALL = 0x1b, ++ IH_PERF_SEL_CLIENT12_IH_STALL = 0x1c, ++ IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d, ++ IH_PERF_SEL_CLIENT14_IH_STALL = 0x1e, ++ IH_PERF_SEL_CLIENT15_IH_STALL = 0x1f, ++ IH_PERF_SEL_CLIENT16_IH_STALL = 0x20, ++ IH_PERF_SEL_CLIENT17_IH_STALL = 0x21, ++ IH_PERF_SEL_CLIENT18_IH_STALL = 0x22, ++ IH_PERF_SEL_CLIENT19_IH_STALL = 0x23, ++ IH_PERF_SEL_CLIENT20_IH_STALL = 0x24, ++ IH_PERF_SEL_CLIENT21_IH_STALL = 0x25, ++ IH_PERF_SEL_CLIENT22_IH_STALL = 0x26, ++ IH_PERF_SEL_RB_FULL_VF0 = 0x27, ++ IH_PERF_SEL_RB_FULL_VF1 = 0x28, ++ IH_PERF_SEL_RB_FULL_VF2 = 0x29, ++ IH_PERF_SEL_RB_FULL_VF3 = 0x2a, ++ IH_PERF_SEL_RB_FULL_VF4 = 0x2b, ++ IH_PERF_SEL_RB_FULL_VF5 = 0x2c, ++ IH_PERF_SEL_RB_FULL_VF6 = 0x2d, ++ IH_PERF_SEL_RB_FULL_VF7 = 0x2e, ++ IH_PERF_SEL_RB_FULL_VF8 = 0x2f, ++ IH_PERF_SEL_RB_FULL_VF9 = 0x30, ++ IH_PERF_SEL_RB_FULL_VF10 = 0x31, ++ IH_PERF_SEL_RB_FULL_VF11 = 0x32, ++ IH_PERF_SEL_RB_FULL_VF12 = 0x33, ++ IH_PERF_SEL_RB_FULL_VF13 = 0x34, ++ IH_PERF_SEL_RB_FULL_VF14 = 0x35, ++ IH_PERF_SEL_RB_FULL_VF15 = 0x36, ++ IH_PERF_SEL_RB_OVERFLOW_VF0 = 0x37, ++ IH_PERF_SEL_RB_OVERFLOW_VF1 = 0x38, ++ IH_PERF_SEL_RB_OVERFLOW_VF2 = 0x39, ++ IH_PERF_SEL_RB_OVERFLOW_VF3 = 0x3a, ++ IH_PERF_SEL_RB_OVERFLOW_VF4 = 0x3b, ++ IH_PERF_SEL_RB_OVERFLOW_VF5 = 0x3c, ++ IH_PERF_SEL_RB_OVERFLOW_VF6 = 0x3d, ++ IH_PERF_SEL_RB_OVERFLOW_VF7 = 0x3e, ++ IH_PERF_SEL_RB_OVERFLOW_VF8 = 0x3f, ++ IH_PERF_SEL_RB_OVERFLOW_VF9 = 0x40, ++ IH_PERF_SEL_RB_OVERFLOW_VF10 = 0x41, ++ IH_PERF_SEL_RB_OVERFLOW_VF11 = 0x42, ++ IH_PERF_SEL_RB_OVERFLOW_VF12 = 0x43, ++ IH_PERF_SEL_RB_OVERFLOW_VF13 = 0x44, ++ IH_PERF_SEL_RB_OVERFLOW_VF14 = 0x45, ++ IH_PERF_SEL_RB_OVERFLOW_VF15 = 0x46, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF0 = 0x47, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF1 = 0x48, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF2 = 0x49, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF3 = 0x4a, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF4 = 0x4b, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF5 = 0x4c, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF6 = 0x4d, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF7 = 0x4e, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF8 = 0x4f, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF9 = 0x50, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF10 = 0x51, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF11 = 0x52, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF12 = 0x53, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF13 = 0x54, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF14 = 0x55, ++ IH_PERF_SEL_RB_WPTR_WRITEBACK_VF15 = 0x56, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF0 = 0x57, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF1 = 0x58, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF2 = 0x59, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF3 = 0x5a, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF4 = 0x5b, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF5 = 0x5c, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF6 = 0x5d, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF7 = 0x5e, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF8 = 0x5f, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF9 = 0x60, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF10 = 0x61, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF11 = 0x62, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF12 = 0x63, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF13 = 0x64, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF14 = 0x65, ++ IH_PERF_SEL_RB_WPTR_WRAP_VF15 = 0x66, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF0 = 0x67, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF1 = 0x68, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF2 = 0x69, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF3 = 0x6a, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF4 = 0x6b, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF5 = 0x6c, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF6 = 0x6d, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF7 = 0x6e, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF8 = 0x6f, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF9 = 0x70, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF10 = 0x71, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF11 = 0x72, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF12 = 0x73, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF13 = 0x74, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF14 = 0x75, ++ IH_PERF_SEL_RB_RPTR_WRAP_VF15 = 0x76, ++ IH_PERF_SEL_BIF_RISING_VF0 = 0x77, ++ IH_PERF_SEL_BIF_RISING_VF1 = 0x78, ++ IH_PERF_SEL_BIF_RISING_VF2 = 0x79, ++ IH_PERF_SEL_BIF_RISING_VF3 = 0x7a, ++ IH_PERF_SEL_BIF_RISING_VF4 = 0x7b, ++ IH_PERF_SEL_BIF_RISING_VF5 = 0x7c, ++ IH_PERF_SEL_BIF_RISING_VF6 = 0x7d, ++ IH_PERF_SEL_BIF_RISING_VF7 = 0x7e, ++ IH_PERF_SEL_BIF_RISING_VF8 = 0x7f, ++ IH_PERF_SEL_BIF_RISING_VF9 = 0x80, ++ IH_PERF_SEL_BIF_RISING_VF10 = 0x81, ++ IH_PERF_SEL_BIF_RISING_VF11 = 0x82, ++ IH_PERF_SEL_BIF_RISING_VF12 = 0x83, ++ IH_PERF_SEL_BIF_RISING_VF13 = 0x84, ++ IH_PERF_SEL_BIF_RISING_VF14 = 0x85, ++ IH_PERF_SEL_BIF_RISING_VF15 = 0x86, ++ IH_PERF_SEL_BIF_FALLING_VF0 = 0x87, ++ IH_PERF_SEL_BIF_FALLING_VF1 = 0x88, ++ IH_PERF_SEL_BIF_FALLING_VF2 = 0x89, ++ IH_PERF_SEL_BIF_FALLING_VF3 = 0x8a, ++ IH_PERF_SEL_BIF_FALLING_VF4 = 0x8b, ++ IH_PERF_SEL_BIF_FALLING_VF5 = 0x8c, ++ IH_PERF_SEL_BIF_FALLING_VF6 = 0x8d, ++ IH_PERF_SEL_BIF_FALLING_VF7 = 0x8e, ++ IH_PERF_SEL_BIF_FALLING_VF8 = 0x8f, ++ IH_PERF_SEL_BIF_FALLING_VF9 = 0x90, ++ IH_PERF_SEL_BIF_FALLING_VF10 = 0x91, ++ IH_PERF_SEL_BIF_FALLING_VF11 = 0x92, ++ IH_PERF_SEL_BIF_FALLING_VF12 = 0x93, ++ IH_PERF_SEL_BIF_FALLING_VF13 = 0x94, ++ IH_PERF_SEL_BIF_FALLING_VF14 = 0x95, ++ IH_PERF_SEL_BIF_FALLING_VF15 = 0x96, ++} IH_PERF_SEL; ++typedef enum SRBM_PERFCOUNT1_SEL { ++ SRBM_PERF_SEL_COUNT = 0x0, ++ SRBM_PERF_SEL_BIF_BUSY = 0x1, ++ SRBM_PERF_SEL_SDMA0_BUSY = 0x3, ++ SRBM_PERF_SEL_IH_BUSY = 0x4, ++ SRBM_PERF_SEL_MCB_BUSY = 0x5, ++ SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x6, ++ SRBM_PERF_SEL_MCC_BUSY = 0x7, ++ SRBM_PERF_SEL_MCD_BUSY = 0x8, ++ SRBM_PERF_SEL_CHUB_BUSY = 0x9, ++ SRBM_PERF_SEL_SEM_BUSY = 0xa, ++ SRBM_PERF_SEL_UVD_BUSY = 0xb, ++ SRBM_PERF_SEL_VMC_BUSY = 0xc, ++ SRBM_PERF_SEL_ODE_BUSY = 0xd, ++ SRBM_PERF_SEL_SDMA1_BUSY = 0xe, ++ SRBM_PERF_SEL_SAMMSP_BUSY = 0xf, ++ SRBM_PERF_SEL_VCE0_BUSY = 0x10, ++ SRBM_PERF_SEL_XDMA_BUSY = 0x11, ++ SRBM_PERF_SEL_ACP_BUSY = 0x12, ++ SRBM_PERF_SEL_SDMA2_BUSY = 0x13, ++ SRBM_PERF_SEL_SDMA3_BUSY = 0x14, ++ SRBM_PERF_SEL_SAMSCP_BUSY = 0x15, ++ SRBM_PERF_SEL_VMC1_BUSY = 0x16, ++ SRBM_PERF_SEL_ISP_BUSY = 0x17, ++ SRBM_PERF_SEL_VCE1_BUSY = 0x18, ++ SRBM_PERF_SEL_GCATCL2_BUSY = 0x19, ++ SRBM_PERF_SEL_OSATCL2_BUSY = 0x1a, ++ SRBM_PERF_SEL_VP8_BUSY = 0x1b, ++} SRBM_PERFCOUNT1_SEL; ++typedef enum SYS_GRBM_GFX_INDEX_SEL { ++ GRBM_GFX_INDEX_BIF = 0x0, ++ GRBM_GFX_INDEX_SDMA0 = 0x1, ++ GRBM_GFX_INDEX_SDMA1 = 0x2, ++ RESEVERED0 = 0x3, ++ GRBM_GFX_INDEX_UVD = 0x4, ++ GRBM_GFX_INDEX_VCE0 = 0x5, ++ GRBM_GFX_INDEX_VCE1 = 0x6, ++ GRBM_GFX_INDEX_ACP = 0x7, ++ GRBM_GFX_INDEX_SMU = 0x8, ++ GRBM_GFX_INDEX_SAMMSP = 0x9, ++ GRBM_GFX_INDEX_SAMSCP = 0xa, ++ GRBM_GFX_INDEX_ISP = 0xb, ++ GRBM_GFX_INDEX_TST = 0xc, ++ GRBM_GFX_INDEX_SDMA2 = 0xd, ++ GRBM_GFX_INDEX_SDMA3 = 0xe, ++} SYS_GRBM_GFX_INDEX_SEL; ++typedef enum SRBM_GFX_CNTL_SEL { ++ SRBM_GFX_CNTL_BIF = 0x0, ++ SRBM_GFX_CNTL_SDMA0 = 0x1, ++ SRBM_GFX_CNTL_SDMA1 = 0x2, ++ SRBM_GFX_CNTL_GRBM = 0x3, ++ SRBM_GFX_CNTL_UVD = 0x4, ++ SRBM_GFX_CNTL_VCE0 = 0x5, ++ SRBM_GFX_CNTL_VCE1 = 0x6, ++ SRBM_GFX_CNTL_ACP = 0x7, ++ SRBM_GFX_CNTL_SMU = 0x8, ++ SRBM_GFX_CNTL_SAMMSP = 0x9, ++ SRBM_GFX_CNTL_SAMSCP = 0xa, ++ SRBM_GFX_CNTL_ISP = 0xb, ++ SRBM_GFX_CNTL_TST = 0xc, ++ SRBM_GFX_CNTL_SDMA2 = 0xd, ++ SRBM_GFX_CNTL_SDMA3 = 0xe, ++} SRBM_GFX_CNTL_SEL; ++typedef enum SDMA_PERF_SEL { ++ SDMA_PERF_SEL_CYCLE = 0x0, ++ SDMA_PERF_SEL_IDLE = 0x1, ++ SDMA_PERF_SEL_REG_IDLE = 0x2, ++ SDMA_PERF_SEL_RB_EMPTY = 0x3, ++ SDMA_PERF_SEL_RB_FULL = 0x4, ++ SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5, ++ SDMA_PERF_SEL_RB_RPTR_WRAP = 0x6, ++ SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x7, ++ SDMA_PERF_SEL_RB_RPTR_WB = 0x8, ++ SDMA_PERF_SEL_RB_CMD_IDLE = 0x9, ++ SDMA_PERF_SEL_RB_CMD_FULL = 0xa, ++ SDMA_PERF_SEL_IB_CMD_IDLE = 0xb, ++ SDMA_PERF_SEL_IB_CMD_FULL = 0xc, ++ SDMA_PERF_SEL_EX_IDLE = 0xd, ++ SDMA_PERF_SEL_SRBM_REG_SEND = 0xe, ++ SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0xf, ++ SDMA_PERF_SEL_MC_WR_IDLE = 0x10, ++ SDMA_PERF_SEL_MC_WR_COUNT = 0x11, ++ SDMA_PERF_SEL_MC_RD_IDLE = 0x12, ++ SDMA_PERF_SEL_MC_RD_COUNT = 0x13, ++ SDMA_PERF_SEL_MC_RD_RET_STALL = 0x14, ++ SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x15, ++ SDMA_PERF_SEL_SEM_IDLE = 0x18, ++ SDMA_PERF_SEL_SEM_REQ_STALL = 0x19, ++ SDMA_PERF_SEL_SEM_REQ_COUNT = 0x1a, ++ SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x1b, ++ SDMA_PERF_SEL_SEM_RESP_FAIL = 0x1c, ++ SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d, ++ SDMA_PERF_SEL_INT_IDLE = 0x1e, ++ SDMA_PERF_SEL_INT_REQ_STALL = 0x1f, ++ SDMA_PERF_SEL_INT_REQ_COUNT = 0x20, ++ SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x21, ++ SDMA_PERF_SEL_INT_RESP_RETRY = 0x22, ++ SDMA_PERF_SEL_NUM_PACKET = 0x23, ++ SDMA_PERF_SEL_CE_WREQ_IDLE = 0x25, ++ SDMA_PERF_SEL_CE_WR_IDLE = 0x26, ++ SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x27, ++ SDMA_PERF_SEL_CE_RREQ_IDLE = 0x28, ++ SDMA_PERF_SEL_CE_OUT_IDLE = 0x29, ++ SDMA_PERF_SEL_CE_IN_IDLE = 0x2a, ++ SDMA_PERF_SEL_CE_DST_IDLE = 0x2b, ++ SDMA_PERF_SEL_CE_AFIFO_FULL = 0x2e, ++ SDMA_PERF_SEL_CE_INFO_FULL = 0x31, ++ SDMA_PERF_SEL_CE_INFO1_FULL = 0x32, ++ SDMA_PERF_SEL_CE_RD_STALL = 0x33, ++ SDMA_PERF_SEL_CE_WR_STALL = 0x34, ++ SDMA_PERF_SEL_GFX_SELECT = 0x35, ++ SDMA_PERF_SEL_RLC0_SELECT = 0x36, ++ SDMA_PERF_SEL_RLC1_SELECT = 0x37, ++ SDMA_PERF_SEL_CTX_CHANGE = 0x38, ++ SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x39, ++ SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x3a, ++ SDMA_PERF_SEL_DOORBELL = 0x3b, ++ SDMA_PERF_SEL_RD_BA_RTR = 0x3c, ++ SDMA_PERF_SEL_WR_BA_RTR = 0x3d, ++} SDMA_PERF_SEL; ++typedef enum SurfaceEndian { ++ ENDIAN_NONE = 0x0, ++ ENDIAN_8IN16 = 0x1, ++ ENDIAN_8IN32 = 0x2, ++ ENDIAN_8IN64 = 0x3, ++} SurfaceEndian; ++typedef enum ArrayMode { ++ ARRAY_LINEAR_GENERAL = 0x0, ++ ARRAY_LINEAR_ALIGNED = 0x1, ++ ARRAY_1D_TILED_THIN1 = 0x2, ++ ARRAY_1D_TILED_THICK = 0x3, ++ ARRAY_2D_TILED_THIN1 = 0x4, ++ ARRAY_PRT_TILED_THIN1 = 0x5, ++ ARRAY_PRT_2D_TILED_THIN1 = 0x6, ++ ARRAY_2D_TILED_THICK = 0x7, ++ ARRAY_2D_TILED_XTHICK = 0x8, ++ ARRAY_PRT_TILED_THICK = 0x9, ++ ARRAY_PRT_2D_TILED_THICK = 0xa, ++ ARRAY_PRT_3D_TILED_THIN1 = 0xb, ++ ARRAY_3D_TILED_THIN1 = 0xc, ++ ARRAY_3D_TILED_THICK = 0xd, ++ ARRAY_3D_TILED_XTHICK = 0xe, ++ ARRAY_PRT_3D_TILED_THICK = 0xf, ++} ArrayMode; ++typedef enum PipeTiling { ++ CONFIG_1_PIPE = 0x0, ++ CONFIG_2_PIPE = 0x1, ++ CONFIG_4_PIPE = 0x2, ++ CONFIG_8_PIPE = 0x3, ++} PipeTiling; ++typedef enum BankTiling { ++ CONFIG_4_BANK = 0x0, ++ CONFIG_8_BANK = 0x1, ++} BankTiling; ++typedef enum GroupInterleave { ++ CONFIG_256B_GROUP = 0x0, ++ CONFIG_512B_GROUP = 0x1, ++} GroupInterleave; ++typedef enum RowTiling { ++ CONFIG_1KB_ROW = 0x0, ++ CONFIG_2KB_ROW = 0x1, ++ CONFIG_4KB_ROW = 0x2, ++ CONFIG_8KB_ROW = 0x3, ++ CONFIG_1KB_ROW_OPT = 0x4, ++ CONFIG_2KB_ROW_OPT = 0x5, ++ CONFIG_4KB_ROW_OPT = 0x6, ++ CONFIG_8KB_ROW_OPT = 0x7, ++} RowTiling; ++typedef enum BankSwapBytes { ++ CONFIG_128B_SWAPS = 0x0, ++ CONFIG_256B_SWAPS = 0x1, ++ CONFIG_512B_SWAPS = 0x2, ++ CONFIG_1KB_SWAPS = 0x3, ++} BankSwapBytes; ++typedef enum SampleSplitBytes { ++ CONFIG_1KB_SPLIT = 0x0, ++ CONFIG_2KB_SPLIT = 0x1, ++ CONFIG_4KB_SPLIT = 0x2, ++ CONFIG_8KB_SPLIT = 0x3, ++} SampleSplitBytes; ++typedef enum NumPipes { ++ ADDR_CONFIG_1_PIPE = 0x0, ++ ADDR_CONFIG_2_PIPE = 0x1, ++ ADDR_CONFIG_4_PIPE = 0x2, ++ ADDR_CONFIG_8_PIPE = 0x3, ++} NumPipes; ++typedef enum PipeInterleaveSize { ++ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, ++ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, ++} PipeInterleaveSize; ++typedef enum BankInterleaveSize { ++ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, ++ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, ++ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, ++ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, ++} BankInterleaveSize; ++typedef enum NumShaderEngines { ++ ADDR_CONFIG_1_SHADER_ENGINE = 0x0, ++ ADDR_CONFIG_2_SHADER_ENGINE = 0x1, ++} NumShaderEngines; ++typedef enum ShaderEngineTileSize { ++ ADDR_CONFIG_SE_TILE_16 = 0x0, ++ ADDR_CONFIG_SE_TILE_32 = 0x1, ++} ShaderEngineTileSize; ++typedef enum NumGPUs { ++ ADDR_CONFIG_1_GPU = 0x0, ++ ADDR_CONFIG_2_GPU = 0x1, ++ ADDR_CONFIG_4_GPU = 0x2, ++} NumGPUs; ++typedef enum MultiGPUTileSize { ++ ADDR_CONFIG_GPU_TILE_16 = 0x0, ++ ADDR_CONFIG_GPU_TILE_32 = 0x1, ++ ADDR_CONFIG_GPU_TILE_64 = 0x2, ++ ADDR_CONFIG_GPU_TILE_128 = 0x3, ++} MultiGPUTileSize; ++typedef enum RowSize { ++ ADDR_CONFIG_1KB_ROW = 0x0, ++ ADDR_CONFIG_2KB_ROW = 0x1, ++ ADDR_CONFIG_4KB_ROW = 0x2, ++} RowSize; ++typedef enum NumLowerPipes { ++ ADDR_CONFIG_1_LOWER_PIPES = 0x0, ++ ADDR_CONFIG_2_LOWER_PIPES = 0x1, ++} NumLowerPipes; ++typedef enum DebugBlockId { ++ DBG_CLIENT_BLKID_RESERVED = 0x0, ++ DBG_CLIENT_BLKID_dbg = 0x1, ++ DBG_CLIENT_BLKID_scf2 = 0x2, ++ DBG_CLIENT_BLKID_mcd5 = 0x3, ++ DBG_CLIENT_BLKID_vmc = 0x4, ++ DBG_CLIENT_BLKID_sx30 = 0x5, ++ DBG_CLIENT_BLKID_mcd2 = 0x6, ++ DBG_CLIENT_BLKID_bci1 = 0x7, ++ DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, ++ DBG_CLIENT_BLKID_mcc0 = 0x9, ++ DBG_CLIENT_BLKID_uvdf_0 = 0xa, ++ DBG_CLIENT_BLKID_uvdf_1 = 0xb, ++ DBG_CLIENT_BLKID_uvdf_2 = 0xc, ++ DBG_CLIENT_BLKID_uvdi_0 = 0xd, ++ DBG_CLIENT_BLKID_bci0 = 0xe, ++ DBG_CLIENT_BLKID_vcec0_0 = 0xf, ++ DBG_CLIENT_BLKID_cb100 = 0x10, ++ DBG_CLIENT_BLKID_cb001 = 0x11, ++ DBG_CLIENT_BLKID_mcd4 = 0x12, ++ DBG_CLIENT_BLKID_tmonw00 = 0x13, ++ DBG_CLIENT_BLKID_cb101 = 0x14, ++ DBG_CLIENT_BLKID_sx10 = 0x15, ++ DBG_CLIENT_BLKID_cb301 = 0x16, ++ DBG_CLIENT_BLKID_tmonw01 = 0x17, ++ DBG_CLIENT_BLKID_vcea0_0 = 0x18, ++ DBG_CLIENT_BLKID_vcea0_1 = 0x19, ++ DBG_CLIENT_BLKID_vcea0_2 = 0x1a, ++ DBG_CLIENT_BLKID_vcea0_3 = 0x1b, ++ DBG_CLIENT_BLKID_scf1 = 0x1c, ++ DBG_CLIENT_BLKID_sx20 = 0x1d, ++ DBG_CLIENT_BLKID_spim1 = 0x1e, ++ DBG_CLIENT_BLKID_pa10 = 0x1f, ++ DBG_CLIENT_BLKID_pa00 = 0x20, ++ DBG_CLIENT_BLKID_gmcon = 0x21, ++ DBG_CLIENT_BLKID_mcb = 0x22, ++ DBG_CLIENT_BLKID_vgt0 = 0x23, ++ DBG_CLIENT_BLKID_pc0 = 0x24, ++ DBG_CLIENT_BLKID_bci2 = 0x25, ++ DBG_CLIENT_BLKID_uvdb_0 = 0x26, ++ DBG_CLIENT_BLKID_spim3 = 0x27, ++ DBG_CLIENT_BLKID_cpc_0 = 0x28, ++ DBG_CLIENT_BLKID_cpc_1 = 0x29, ++ DBG_CLIENT_BLKID_uvdm_0 = 0x2a, ++ DBG_CLIENT_BLKID_uvdm_1 = 0x2b, ++ DBG_CLIENT_BLKID_uvdm_2 = 0x2c, ++ DBG_CLIENT_BLKID_uvdm_3 = 0x2d, ++ DBG_CLIENT_BLKID_cb000 = 0x2e, ++ DBG_CLIENT_BLKID_spim0 = 0x2f, ++ DBG_CLIENT_BLKID_mcc2 = 0x30, ++ DBG_CLIENT_BLKID_ds0 = 0x31, ++ DBG_CLIENT_BLKID_srbm = 0x32, ++ DBG_CLIENT_BLKID_ih = 0x33, ++ DBG_CLIENT_BLKID_sem = 0x34, ++ DBG_CLIENT_BLKID_sdma_0 = 0x35, ++ DBG_CLIENT_BLKID_sdma_1 = 0x36, ++ DBG_CLIENT_BLKID_hdp = 0x37, ++ DBG_CLIENT_BLKID_acp_0 = 0x38, ++ DBG_CLIENT_BLKID_acp_1 = 0x39, ++ DBG_CLIENT_BLKID_cb200 = 0x3a, ++ DBG_CLIENT_BLKID_scf3 = 0x3b, ++ DBG_CLIENT_BLKID_vceb1_0 = 0x3c, ++ DBG_CLIENT_BLKID_vcea1_0 = 0x3d, ++ DBG_CLIENT_BLKID_vcea1_1 = 0x3e, ++ DBG_CLIENT_BLKID_vcea1_2 = 0x3f, ++ DBG_CLIENT_BLKID_vcea1_3 = 0x40, ++ DBG_CLIENT_BLKID_bci3 = 0x41, ++ DBG_CLIENT_BLKID_mcd0 = 0x42, ++ DBG_CLIENT_BLKID_pa11 = 0x43, ++ DBG_CLIENT_BLKID_pa01 = 0x44, ++ DBG_CLIENT_BLKID_cb201 = 0x45, ++ DBG_CLIENT_BLKID_spim2 = 0x46, ++ DBG_CLIENT_BLKID_vgt2 = 0x47, ++ DBG_CLIENT_BLKID_pc2 = 0x48, ++ DBG_CLIENT_BLKID_smu_0 = 0x49, ++ DBG_CLIENT_BLKID_smu_1 = 0x4a, ++ DBG_CLIENT_BLKID_smu_2 = 0x4b, ++ DBG_CLIENT_BLKID_cb1 = 0x4c, ++ DBG_CLIENT_BLKID_ia0 = 0x4d, ++ DBG_CLIENT_BLKID_wd = 0x4e, ++ DBG_CLIENT_BLKID_ia1 = 0x4f, ++ DBG_CLIENT_BLKID_vcec1_0 = 0x50, ++ DBG_CLIENT_BLKID_scf0 = 0x51, ++ DBG_CLIENT_BLKID_vgt1 = 0x52, ++ DBG_CLIENT_BLKID_pc1 = 0x53, ++ DBG_CLIENT_BLKID_cb0 = 0x54, ++ DBG_CLIENT_BLKID_gdc_one_0 = 0x55, ++ DBG_CLIENT_BLKID_gdc_one_1 = 0x56, ++ DBG_CLIENT_BLKID_gdc_one_2 = 0x57, ++ DBG_CLIENT_BLKID_gdc_one_3 = 0x58, ++ DBG_CLIENT_BLKID_gdc_one_4 = 0x59, ++ DBG_CLIENT_BLKID_gdc_one_5 = 0x5a, ++ DBG_CLIENT_BLKID_gdc_one_6 = 0x5b, ++ DBG_CLIENT_BLKID_gdc_one_7 = 0x5c, ++ DBG_CLIENT_BLKID_gdc_one_8 = 0x5d, ++ DBG_CLIENT_BLKID_gdc_one_9 = 0x5e, ++ DBG_CLIENT_BLKID_gdc_one_10 = 0x5f, ++ DBG_CLIENT_BLKID_gdc_one_11 = 0x60, ++ DBG_CLIENT_BLKID_gdc_one_12 = 0x61, ++ DBG_CLIENT_BLKID_gdc_one_13 = 0x62, ++ DBG_CLIENT_BLKID_gdc_one_14 = 0x63, ++ DBG_CLIENT_BLKID_gdc_one_15 = 0x64, ++ DBG_CLIENT_BLKID_gdc_one_16 = 0x65, ++ DBG_CLIENT_BLKID_gdc_one_17 = 0x66, ++ DBG_CLIENT_BLKID_gdc_one_18 = 0x67, ++ DBG_CLIENT_BLKID_gdc_one_19 = 0x68, ++ DBG_CLIENT_BLKID_gdc_one_20 = 0x69, ++ DBG_CLIENT_BLKID_gdc_one_21 = 0x6a, ++ DBG_CLIENT_BLKID_gdc_one_22 = 0x6b, ++ DBG_CLIENT_BLKID_gdc_one_23 = 0x6c, ++ DBG_CLIENT_BLKID_gdc_one_24 = 0x6d, ++ DBG_CLIENT_BLKID_gdc_one_25 = 0x6e, ++ DBG_CLIENT_BLKID_gdc_one_26 = 0x6f, ++ DBG_CLIENT_BLKID_gdc_one_27 = 0x70, ++ DBG_CLIENT_BLKID_gdc_one_28 = 0x71, ++ DBG_CLIENT_BLKID_gdc_one_29 = 0x72, ++ DBG_CLIENT_BLKID_gdc_one_30 = 0x73, ++ DBG_CLIENT_BLKID_gdc_one_31 = 0x74, ++ DBG_CLIENT_BLKID_gdc_one_32 = 0x75, ++ DBG_CLIENT_BLKID_gdc_one_33 = 0x76, ++ DBG_CLIENT_BLKID_gdc_one_34 = 0x77, ++ DBG_CLIENT_BLKID_gdc_one_35 = 0x78, ++ DBG_CLIENT_BLKID_vceb0_0 = 0x79, ++ DBG_CLIENT_BLKID_vgt3 = 0x7a, ++ DBG_CLIENT_BLKID_pc3 = 0x7b, ++ DBG_CLIENT_BLKID_mcd3 = 0x7c, ++ DBG_CLIENT_BLKID_uvdu_0 = 0x7d, ++ DBG_CLIENT_BLKID_uvdu_1 = 0x7e, ++ DBG_CLIENT_BLKID_uvdu_2 = 0x7f, ++ DBG_CLIENT_BLKID_uvdu_3 = 0x80, ++ DBG_CLIENT_BLKID_uvdu_4 = 0x81, ++ DBG_CLIENT_BLKID_uvdu_5 = 0x82, ++ DBG_CLIENT_BLKID_uvdu_6 = 0x83, ++ DBG_CLIENT_BLKID_cb300 = 0x84, ++ DBG_CLIENT_BLKID_mcd1 = 0x85, ++ DBG_CLIENT_BLKID_sx00 = 0x86, ++ DBG_CLIENT_BLKID_uvdc_0 = 0x87, ++ DBG_CLIENT_BLKID_uvdc_1 = 0x88, ++ DBG_CLIENT_BLKID_mcc3 = 0x89, ++ DBG_CLIENT_BLKID_cpg_0 = 0x8a, ++ DBG_CLIENT_BLKID_cpg_1 = 0x8b, ++ DBG_CLIENT_BLKID_gck = 0x8c, ++ DBG_CLIENT_BLKID_mcc1 = 0x8d, ++ DBG_CLIENT_BLKID_cpf_0 = 0x8e, ++ DBG_CLIENT_BLKID_cpf_1 = 0x8f, ++ DBG_CLIENT_BLKID_rlc = 0x90, ++ DBG_CLIENT_BLKID_grbm = 0x91, ++ DBG_CLIENT_BLKID_sammsp = 0x92, ++ DBG_CLIENT_BLKID_dci_pg = 0x93, ++ DBG_CLIENT_BLKID_dci_0 = 0x94, ++ DBG_CLIENT_BLKID_dccg0_0 = 0x95, ++ DBG_CLIENT_BLKID_dccg0_1 = 0x96, ++ DBG_CLIENT_BLKID_dcfe01_0 = 0x97, ++ DBG_CLIENT_BLKID_dcfe02_0 = 0x98, ++ DBG_CLIENT_BLKID_dcfe03_0 = 0x99, ++ DBG_CLIENT_BLKID_dcfe04_0 = 0x9a, ++ DBG_CLIENT_BLKID_dcfe05_0 = 0x9b, ++ DBG_CLIENT_BLKID_dcfe06_0 = 0x9c, ++ DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d, ++} DebugBlockId; ++typedef enum DebugBlockId_OLD { ++ DBG_BLOCK_ID_RESERVED = 0x0, ++ DBG_BLOCK_ID_DBG = 0x1, ++ DBG_BLOCK_ID_VMC = 0x2, ++ DBG_BLOCK_ID_PDMA = 0x3, ++ DBG_BLOCK_ID_CG = 0x4, ++ DBG_BLOCK_ID_SRBM = 0x5, ++ DBG_BLOCK_ID_GRBM = 0x6, ++ DBG_BLOCK_ID_RLC = 0x7, ++ DBG_BLOCK_ID_CSC = 0x8, ++ DBG_BLOCK_ID_SEM = 0x9, ++ DBG_BLOCK_ID_IH = 0xa, ++ DBG_BLOCK_ID_SC = 0xb, ++ DBG_BLOCK_ID_SQ = 0xc, ++ DBG_BLOCK_ID_AVP = 0xd, ++ DBG_BLOCK_ID_GMCON = 0xe, ++ DBG_BLOCK_ID_SMU = 0xf, ++ DBG_BLOCK_ID_DMA0 = 0x10, ++ DBG_BLOCK_ID_DMA1 = 0x11, ++ DBG_BLOCK_ID_SPIM = 0x12, ++ DBG_BLOCK_ID_GDS = 0x13, ++ DBG_BLOCK_ID_SPIS = 0x14, ++ DBG_BLOCK_ID_UNUSED0 = 0x15, ++ DBG_BLOCK_ID_PA0 = 0x16, ++ DBG_BLOCK_ID_PA1 = 0x17, ++ DBG_BLOCK_ID_CP0 = 0x18, ++ DBG_BLOCK_ID_CP1 = 0x19, ++ DBG_BLOCK_ID_CP2 = 0x1a, ++ DBG_BLOCK_ID_UNUSED1 = 0x1b, ++ DBG_BLOCK_ID_UVDU = 0x1c, ++ DBG_BLOCK_ID_UVDM = 0x1d, ++ DBG_BLOCK_ID_VCE = 0x1e, ++ DBG_BLOCK_ID_UNUSED2 = 0x1f, ++ DBG_BLOCK_ID_VGT0 = 0x20, ++ DBG_BLOCK_ID_VGT1 = 0x21, ++ DBG_BLOCK_ID_IA = 0x22, ++ DBG_BLOCK_ID_UNUSED3 = 0x23, ++ DBG_BLOCK_ID_SCT0 = 0x24, ++ DBG_BLOCK_ID_SCT1 = 0x25, ++ DBG_BLOCK_ID_SPM0 = 0x26, ++ DBG_BLOCK_ID_SPM1 = 0x27, ++ DBG_BLOCK_ID_TCAA = 0x28, ++ DBG_BLOCK_ID_TCAB = 0x29, ++ DBG_BLOCK_ID_TCCA = 0x2a, ++ DBG_BLOCK_ID_TCCB = 0x2b, ++ DBG_BLOCK_ID_MCC0 = 0x2c, ++ DBG_BLOCK_ID_MCC1 = 0x2d, ++ DBG_BLOCK_ID_MCC2 = 0x2e, ++ DBG_BLOCK_ID_MCC3 = 0x2f, ++ DBG_BLOCK_ID_SX0 = 0x30, ++ DBG_BLOCK_ID_SX1 = 0x31, ++ DBG_BLOCK_ID_SX2 = 0x32, ++ DBG_BLOCK_ID_SX3 = 0x33, ++ DBG_BLOCK_ID_UNUSED4 = 0x34, ++ DBG_BLOCK_ID_UNUSED5 = 0x35, ++ DBG_BLOCK_ID_UNUSED6 = 0x36, ++ DBG_BLOCK_ID_UNUSED7 = 0x37, ++ DBG_BLOCK_ID_PC0 = 0x38, ++ DBG_BLOCK_ID_PC1 = 0x39, ++ DBG_BLOCK_ID_UNUSED8 = 0x3a, ++ DBG_BLOCK_ID_UNUSED9 = 0x3b, ++ DBG_BLOCK_ID_UNUSED10 = 0x3c, ++ DBG_BLOCK_ID_UNUSED11 = 0x3d, ++ DBG_BLOCK_ID_MCB = 0x3e, ++ DBG_BLOCK_ID_UNUSED12 = 0x3f, ++ DBG_BLOCK_ID_SCB0 = 0x40, ++ DBG_BLOCK_ID_SCB1 = 0x41, ++ DBG_BLOCK_ID_UNUSED13 = 0x42, ++ DBG_BLOCK_ID_UNUSED14 = 0x43, ++ DBG_BLOCK_ID_SCF0 = 0x44, ++ DBG_BLOCK_ID_SCF1 = 0x45, ++ DBG_BLOCK_ID_UNUSED15 = 0x46, ++ DBG_BLOCK_ID_UNUSED16 = 0x47, ++ DBG_BLOCK_ID_BCI0 = 0x48, ++ DBG_BLOCK_ID_BCI1 = 0x49, ++ DBG_BLOCK_ID_BCI2 = 0x4a, ++ DBG_BLOCK_ID_BCI3 = 0x4b, ++ DBG_BLOCK_ID_UNUSED17 = 0x4c, ++ DBG_BLOCK_ID_UNUSED18 = 0x4d, ++ DBG_BLOCK_ID_UNUSED19 = 0x4e, ++ DBG_BLOCK_ID_UNUSED20 = 0x4f, ++ DBG_BLOCK_ID_CB00 = 0x50, ++ DBG_BLOCK_ID_CB01 = 0x51, ++ DBG_BLOCK_ID_CB02 = 0x52, ++ DBG_BLOCK_ID_CB03 = 0x53, ++ DBG_BLOCK_ID_CB04 = 0x54, ++ DBG_BLOCK_ID_UNUSED21 = 0x55, ++ DBG_BLOCK_ID_UNUSED22 = 0x56, ++ DBG_BLOCK_ID_UNUSED23 = 0x57, ++ DBG_BLOCK_ID_CB10 = 0x58, ++ DBG_BLOCK_ID_CB11 = 0x59, ++ DBG_BLOCK_ID_CB12 = 0x5a, ++ DBG_BLOCK_ID_CB13 = 0x5b, ++ DBG_BLOCK_ID_CB14 = 0x5c, ++ DBG_BLOCK_ID_UNUSED24 = 0x5d, ++ DBG_BLOCK_ID_UNUSED25 = 0x5e, ++ DBG_BLOCK_ID_UNUSED26 = 0x5f, ++ DBG_BLOCK_ID_TCP0 = 0x60, ++ DBG_BLOCK_ID_TCP1 = 0x61, ++ DBG_BLOCK_ID_TCP2 = 0x62, ++ DBG_BLOCK_ID_TCP3 = 0x63, ++ DBG_BLOCK_ID_TCP4 = 0x64, ++ DBG_BLOCK_ID_TCP5 = 0x65, ++ DBG_BLOCK_ID_TCP6 = 0x66, ++ DBG_BLOCK_ID_TCP7 = 0x67, ++ DBG_BLOCK_ID_TCP8 = 0x68, ++ DBG_BLOCK_ID_TCP9 = 0x69, ++ DBG_BLOCK_ID_TCP10 = 0x6a, ++ DBG_BLOCK_ID_TCP11 = 0x6b, ++ DBG_BLOCK_ID_TCP12 = 0x6c, ++ DBG_BLOCK_ID_TCP13 = 0x6d, ++ DBG_BLOCK_ID_TCP14 = 0x6e, ++ DBG_BLOCK_ID_TCP15 = 0x6f, ++ DBG_BLOCK_ID_TCP16 = 0x70, ++ DBG_BLOCK_ID_TCP17 = 0x71, ++ DBG_BLOCK_ID_TCP18 = 0x72, ++ DBG_BLOCK_ID_TCP19 = 0x73, ++ DBG_BLOCK_ID_TCP20 = 0x74, ++ DBG_BLOCK_ID_TCP21 = 0x75, ++ DBG_BLOCK_ID_TCP22 = 0x76, ++ DBG_BLOCK_ID_TCP23 = 0x77, ++ DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, ++ DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, ++ DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, ++ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, ++ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, ++ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, ++ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, ++ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, ++ DBG_BLOCK_ID_DB00 = 0x80, ++ DBG_BLOCK_ID_DB01 = 0x81, ++ DBG_BLOCK_ID_DB02 = 0x82, ++ DBG_BLOCK_ID_DB03 = 0x83, ++ DBG_BLOCK_ID_DB04 = 0x84, ++ DBG_BLOCK_ID_UNUSED27 = 0x85, ++ DBG_BLOCK_ID_UNUSED28 = 0x86, ++ DBG_BLOCK_ID_UNUSED29 = 0x87, ++ DBG_BLOCK_ID_DB10 = 0x88, ++ DBG_BLOCK_ID_DB11 = 0x89, ++ DBG_BLOCK_ID_DB12 = 0x8a, ++ DBG_BLOCK_ID_DB13 = 0x8b, ++ DBG_BLOCK_ID_DB14 = 0x8c, ++ DBG_BLOCK_ID_UNUSED30 = 0x8d, ++ DBG_BLOCK_ID_UNUSED31 = 0x8e, ++ DBG_BLOCK_ID_UNUSED32 = 0x8f, ++ DBG_BLOCK_ID_TCC0 = 0x90, ++ DBG_BLOCK_ID_TCC1 = 0x91, ++ DBG_BLOCK_ID_TCC2 = 0x92, ++ DBG_BLOCK_ID_TCC3 = 0x93, ++ DBG_BLOCK_ID_TCC4 = 0x94, ++ DBG_BLOCK_ID_TCC5 = 0x95, ++ DBG_BLOCK_ID_TCC6 = 0x96, ++ DBG_BLOCK_ID_TCC7 = 0x97, ++ DBG_BLOCK_ID_SPS00 = 0x98, ++ DBG_BLOCK_ID_SPS01 = 0x99, ++ DBG_BLOCK_ID_SPS02 = 0x9a, ++ DBG_BLOCK_ID_SPS10 = 0x9b, ++ DBG_BLOCK_ID_SPS11 = 0x9c, ++ DBG_BLOCK_ID_SPS12 = 0x9d, ++ DBG_BLOCK_ID_UNUSED33 = 0x9e, ++ DBG_BLOCK_ID_UNUSED34 = 0x9f, ++ DBG_BLOCK_ID_TA00 = 0xa0, ++ DBG_BLOCK_ID_TA01 = 0xa1, ++ DBG_BLOCK_ID_TA02 = 0xa2, ++ DBG_BLOCK_ID_TA03 = 0xa3, ++ DBG_BLOCK_ID_TA04 = 0xa4, ++ DBG_BLOCK_ID_TA05 = 0xa5, ++ DBG_BLOCK_ID_TA06 = 0xa6, ++ DBG_BLOCK_ID_TA07 = 0xa7, ++ DBG_BLOCK_ID_TA08 = 0xa8, ++ DBG_BLOCK_ID_TA09 = 0xa9, ++ DBG_BLOCK_ID_TA0A = 0xaa, ++ DBG_BLOCK_ID_TA0B = 0xab, ++ DBG_BLOCK_ID_UNUSED35 = 0xac, ++ DBG_BLOCK_ID_UNUSED36 = 0xad, ++ DBG_BLOCK_ID_UNUSED37 = 0xae, ++ DBG_BLOCK_ID_UNUSED38 = 0xaf, ++ DBG_BLOCK_ID_TA10 = 0xb0, ++ DBG_BLOCK_ID_TA11 = 0xb1, ++ DBG_BLOCK_ID_TA12 = 0xb2, ++ DBG_BLOCK_ID_TA13 = 0xb3, ++ DBG_BLOCK_ID_TA14 = 0xb4, ++ DBG_BLOCK_ID_TA15 = 0xb5, ++ DBG_BLOCK_ID_TA16 = 0xb6, ++ DBG_BLOCK_ID_TA17 = 0xb7, ++ DBG_BLOCK_ID_TA18 = 0xb8, ++ DBG_BLOCK_ID_TA19 = 0xb9, ++ DBG_BLOCK_ID_TA1A = 0xba, ++ DBG_BLOCK_ID_TA1B = 0xbb, ++ DBG_BLOCK_ID_UNUSED39 = 0xbc, ++ DBG_BLOCK_ID_UNUSED40 = 0xbd, ++ DBG_BLOCK_ID_UNUSED41 = 0xbe, ++ DBG_BLOCK_ID_UNUSED42 = 0xbf, ++ DBG_BLOCK_ID_TD00 = 0xc0, ++ DBG_BLOCK_ID_TD01 = 0xc1, ++ DBG_BLOCK_ID_TD02 = 0xc2, ++ DBG_BLOCK_ID_TD03 = 0xc3, ++ DBG_BLOCK_ID_TD04 = 0xc4, ++ DBG_BLOCK_ID_TD05 = 0xc5, ++ DBG_BLOCK_ID_TD06 = 0xc6, ++ DBG_BLOCK_ID_TD07 = 0xc7, ++ DBG_BLOCK_ID_TD08 = 0xc8, ++ DBG_BLOCK_ID_TD09 = 0xc9, ++ DBG_BLOCK_ID_TD0A = 0xca, ++ DBG_BLOCK_ID_TD0B = 0xcb, ++ DBG_BLOCK_ID_UNUSED43 = 0xcc, ++ DBG_BLOCK_ID_UNUSED44 = 0xcd, ++ DBG_BLOCK_ID_UNUSED45 = 0xce, ++ DBG_BLOCK_ID_UNUSED46 = 0xcf, ++ DBG_BLOCK_ID_TD10 = 0xd0, ++ DBG_BLOCK_ID_TD11 = 0xd1, ++ DBG_BLOCK_ID_TD12 = 0xd2, ++ DBG_BLOCK_ID_TD13 = 0xd3, ++ DBG_BLOCK_ID_TD14 = 0xd4, ++ DBG_BLOCK_ID_TD15 = 0xd5, ++ DBG_BLOCK_ID_TD16 = 0xd6, ++ DBG_BLOCK_ID_TD17 = 0xd7, ++ DBG_BLOCK_ID_TD18 = 0xd8, ++ DBG_BLOCK_ID_TD19 = 0xd9, ++ DBG_BLOCK_ID_TD1A = 0xda, ++ DBG_BLOCK_ID_TD1B = 0xdb, ++ DBG_BLOCK_ID_UNUSED47 = 0xdc, ++ DBG_BLOCK_ID_UNUSED48 = 0xdd, ++ DBG_BLOCK_ID_UNUSED49 = 0xde, ++ DBG_BLOCK_ID_UNUSED50 = 0xdf, ++ DBG_BLOCK_ID_MCD0 = 0xe0, ++ DBG_BLOCK_ID_MCD1 = 0xe1, ++ DBG_BLOCK_ID_MCD2 = 0xe2, ++ DBG_BLOCK_ID_MCD3 = 0xe3, ++ DBG_BLOCK_ID_MCD4 = 0xe4, ++ DBG_BLOCK_ID_MCD5 = 0xe5, ++ DBG_BLOCK_ID_UNUSED51 = 0xe6, ++ DBG_BLOCK_ID_UNUSED52 = 0xe7, ++} DebugBlockId_OLD; ++typedef enum DebugBlockId_BY2 { ++ DBG_BLOCK_ID_RESERVED_BY2 = 0x0, ++ DBG_BLOCK_ID_VMC_BY2 = 0x1, ++ DBG_BLOCK_ID_CG_BY2 = 0x2, ++ DBG_BLOCK_ID_GRBM_BY2 = 0x3, ++ DBG_BLOCK_ID_CSC_BY2 = 0x4, ++ DBG_BLOCK_ID_IH_BY2 = 0x5, ++ DBG_BLOCK_ID_SQ_BY2 = 0x6, ++ DBG_BLOCK_ID_GMCON_BY2 = 0x7, ++ DBG_BLOCK_ID_DMA0_BY2 = 0x8, ++ DBG_BLOCK_ID_SPIM_BY2 = 0x9, ++ DBG_BLOCK_ID_SPIS_BY2 = 0xa, ++ DBG_BLOCK_ID_PA0_BY2 = 0xb, ++ DBG_BLOCK_ID_CP0_BY2 = 0xc, ++ DBG_BLOCK_ID_CP2_BY2 = 0xd, ++ DBG_BLOCK_ID_UVDU_BY2 = 0xe, ++ DBG_BLOCK_ID_VCE_BY2 = 0xf, ++ DBG_BLOCK_ID_VGT0_BY2 = 0x10, ++ DBG_BLOCK_ID_IA_BY2 = 0x11, ++ DBG_BLOCK_ID_SCT0_BY2 = 0x12, ++ DBG_BLOCK_ID_SPM0_BY2 = 0x13, ++ DBG_BLOCK_ID_TCAA_BY2 = 0x14, ++ DBG_BLOCK_ID_TCCA_BY2 = 0x15, ++ DBG_BLOCK_ID_MCC0_BY2 = 0x16, ++ DBG_BLOCK_ID_MCC2_BY2 = 0x17, ++ DBG_BLOCK_ID_SX0_BY2 = 0x18, ++ DBG_BLOCK_ID_SX2_BY2 = 0x19, ++ DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, ++ DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, ++ DBG_BLOCK_ID_PC0_BY2 = 0x1c, ++ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, ++ DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, ++ DBG_BLOCK_ID_MCB_BY2 = 0x1f, ++ DBG_BLOCK_ID_SCB0_BY2 = 0x20, ++ DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, ++ DBG_BLOCK_ID_SCF0_BY2 = 0x22, ++ DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, ++ DBG_BLOCK_ID_BCI0_BY2 = 0x24, ++ DBG_BLOCK_ID_BCI2_BY2 = 0x25, ++ DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, ++ DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, ++ DBG_BLOCK_ID_CB00_BY2 = 0x28, ++ DBG_BLOCK_ID_CB02_BY2 = 0x29, ++ DBG_BLOCK_ID_CB04_BY2 = 0x2a, ++ DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, ++ DBG_BLOCK_ID_CB10_BY2 = 0x2c, ++ DBG_BLOCK_ID_CB12_BY2 = 0x2d, ++ DBG_BLOCK_ID_CB14_BY2 = 0x2e, ++ DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, ++ DBG_BLOCK_ID_TCP0_BY2 = 0x30, ++ DBG_BLOCK_ID_TCP2_BY2 = 0x31, ++ DBG_BLOCK_ID_TCP4_BY2 = 0x32, ++ DBG_BLOCK_ID_TCP6_BY2 = 0x33, ++ DBG_BLOCK_ID_TCP8_BY2 = 0x34, ++ DBG_BLOCK_ID_TCP10_BY2 = 0x35, ++ DBG_BLOCK_ID_TCP12_BY2 = 0x36, ++ DBG_BLOCK_ID_TCP14_BY2 = 0x37, ++ DBG_BLOCK_ID_TCP16_BY2 = 0x38, ++ DBG_BLOCK_ID_TCP18_BY2 = 0x39, ++ DBG_BLOCK_ID_TCP20_BY2 = 0x3a, ++ DBG_BLOCK_ID_TCP22_BY2 = 0x3b, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, ++ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, ++ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, ++ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, ++ DBG_BLOCK_ID_DB00_BY2 = 0x40, ++ DBG_BLOCK_ID_DB02_BY2 = 0x41, ++ DBG_BLOCK_ID_DB04_BY2 = 0x42, ++ DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, ++ DBG_BLOCK_ID_DB10_BY2 = 0x44, ++ DBG_BLOCK_ID_DB12_BY2 = 0x45, ++ DBG_BLOCK_ID_DB14_BY2 = 0x46, ++ DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, ++ DBG_BLOCK_ID_TCC0_BY2 = 0x48, ++ DBG_BLOCK_ID_TCC2_BY2 = 0x49, ++ DBG_BLOCK_ID_TCC4_BY2 = 0x4a, ++ DBG_BLOCK_ID_TCC6_BY2 = 0x4b, ++ DBG_BLOCK_ID_SPS00_BY2 = 0x4c, ++ DBG_BLOCK_ID_SPS02_BY2 = 0x4d, ++ DBG_BLOCK_ID_SPS11_BY2 = 0x4e, ++ DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, ++ DBG_BLOCK_ID_TA00_BY2 = 0x50, ++ DBG_BLOCK_ID_TA02_BY2 = 0x51, ++ DBG_BLOCK_ID_TA04_BY2 = 0x52, ++ DBG_BLOCK_ID_TA06_BY2 = 0x53, ++ DBG_BLOCK_ID_TA08_BY2 = 0x54, ++ DBG_BLOCK_ID_TA0A_BY2 = 0x55, ++ DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, ++ DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, ++ DBG_BLOCK_ID_TA10_BY2 = 0x58, ++ DBG_BLOCK_ID_TA12_BY2 = 0x59, ++ DBG_BLOCK_ID_TA14_BY2 = 0x5a, ++ DBG_BLOCK_ID_TA16_BY2 = 0x5b, ++ DBG_BLOCK_ID_TA18_BY2 = 0x5c, ++ DBG_BLOCK_ID_TA1A_BY2 = 0x5d, ++ DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, ++ DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, ++ DBG_BLOCK_ID_TD00_BY2 = 0x60, ++ DBG_BLOCK_ID_TD02_BY2 = 0x61, ++ DBG_BLOCK_ID_TD04_BY2 = 0x62, ++ DBG_BLOCK_ID_TD06_BY2 = 0x63, ++ DBG_BLOCK_ID_TD08_BY2 = 0x64, ++ DBG_BLOCK_ID_TD0A_BY2 = 0x65, ++ DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, ++ DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, ++ DBG_BLOCK_ID_TD10_BY2 = 0x68, ++ DBG_BLOCK_ID_TD12_BY2 = 0x69, ++ DBG_BLOCK_ID_TD14_BY2 = 0x6a, ++ DBG_BLOCK_ID_TD16_BY2 = 0x6b, ++ DBG_BLOCK_ID_TD18_BY2 = 0x6c, ++ DBG_BLOCK_ID_TD1A_BY2 = 0x6d, ++ DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, ++ DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, ++ DBG_BLOCK_ID_MCD0_BY2 = 0x70, ++ DBG_BLOCK_ID_MCD2_BY2 = 0x71, ++ DBG_BLOCK_ID_MCD4_BY2 = 0x72, ++ DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, ++} DebugBlockId_BY2; ++typedef enum DebugBlockId_BY4 { ++ DBG_BLOCK_ID_RESERVED_BY4 = 0x0, ++ DBG_BLOCK_ID_CG_BY4 = 0x1, ++ DBG_BLOCK_ID_CSC_BY4 = 0x2, ++ DBG_BLOCK_ID_SQ_BY4 = 0x3, ++ DBG_BLOCK_ID_DMA0_BY4 = 0x4, ++ DBG_BLOCK_ID_SPIS_BY4 = 0x5, ++ DBG_BLOCK_ID_CP0_BY4 = 0x6, ++ DBG_BLOCK_ID_UVDU_BY4 = 0x7, ++ DBG_BLOCK_ID_VGT0_BY4 = 0x8, ++ DBG_BLOCK_ID_SCT0_BY4 = 0x9, ++ DBG_BLOCK_ID_TCAA_BY4 = 0xa, ++ DBG_BLOCK_ID_MCC0_BY4 = 0xb, ++ DBG_BLOCK_ID_SX0_BY4 = 0xc, ++ DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, ++ DBG_BLOCK_ID_PC0_BY4 = 0xe, ++ DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, ++ DBG_BLOCK_ID_SCB0_BY4 = 0x10, ++ DBG_BLOCK_ID_SCF0_BY4 = 0x11, ++ DBG_BLOCK_ID_BCI0_BY4 = 0x12, ++ DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, ++ DBG_BLOCK_ID_CB00_BY4 = 0x14, ++ DBG_BLOCK_ID_CB04_BY4 = 0x15, ++ DBG_BLOCK_ID_CB10_BY4 = 0x16, ++ DBG_BLOCK_ID_CB14_BY4 = 0x17, ++ DBG_BLOCK_ID_TCP0_BY4 = 0x18, ++ DBG_BLOCK_ID_TCP4_BY4 = 0x19, ++ DBG_BLOCK_ID_TCP8_BY4 = 0x1a, ++ DBG_BLOCK_ID_TCP12_BY4 = 0x1b, ++ DBG_BLOCK_ID_TCP16_BY4 = 0x1c, ++ DBG_BLOCK_ID_TCP20_BY4 = 0x1d, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, ++ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, ++ DBG_BLOCK_ID_DB_BY4 = 0x20, ++ DBG_BLOCK_ID_DB04_BY4 = 0x21, ++ DBG_BLOCK_ID_DB10_BY4 = 0x22, ++ DBG_BLOCK_ID_DB14_BY4 = 0x23, ++ DBG_BLOCK_ID_TCC0_BY4 = 0x24, ++ DBG_BLOCK_ID_TCC4_BY4 = 0x25, ++ DBG_BLOCK_ID_SPS00_BY4 = 0x26, ++ DBG_BLOCK_ID_SPS11_BY4 = 0x27, ++ DBG_BLOCK_ID_TA00_BY4 = 0x28, ++ DBG_BLOCK_ID_TA04_BY4 = 0x29, ++ DBG_BLOCK_ID_TA08_BY4 = 0x2a, ++ DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, ++ DBG_BLOCK_ID_TA10_BY4 = 0x2c, ++ DBG_BLOCK_ID_TA14_BY4 = 0x2d, ++ DBG_BLOCK_ID_TA18_BY4 = 0x2e, ++ DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, ++ DBG_BLOCK_ID_TD00_BY4 = 0x30, ++ DBG_BLOCK_ID_TD04_BY4 = 0x31, ++ DBG_BLOCK_ID_TD08_BY4 = 0x32, ++ DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, ++ DBG_BLOCK_ID_TD10_BY4 = 0x34, ++ DBG_BLOCK_ID_TD14_BY4 = 0x35, ++ DBG_BLOCK_ID_TD18_BY4 = 0x36, ++ DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, ++ DBG_BLOCK_ID_MCD0_BY4 = 0x38, ++ DBG_BLOCK_ID_MCD4_BY4 = 0x39, ++} DebugBlockId_BY4; ++typedef enum DebugBlockId_BY8 { ++ DBG_BLOCK_ID_RESERVED_BY8 = 0x0, ++ DBG_BLOCK_ID_CSC_BY8 = 0x1, ++ DBG_BLOCK_ID_DMA0_BY8 = 0x2, ++ DBG_BLOCK_ID_CP0_BY8 = 0x3, ++ DBG_BLOCK_ID_VGT0_BY8 = 0x4, ++ DBG_BLOCK_ID_TCAA_BY8 = 0x5, ++ DBG_BLOCK_ID_SX0_BY8 = 0x6, ++ DBG_BLOCK_ID_PC0_BY8 = 0x7, ++ DBG_BLOCK_ID_SCB0_BY8 = 0x8, ++ DBG_BLOCK_ID_BCI0_BY8 = 0x9, ++ DBG_BLOCK_ID_CB00_BY8 = 0xa, ++ DBG_BLOCK_ID_CB10_BY8 = 0xb, ++ DBG_BLOCK_ID_TCP0_BY8 = 0xc, ++ DBG_BLOCK_ID_TCP8_BY8 = 0xd, ++ DBG_BLOCK_ID_TCP16_BY8 = 0xe, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, ++ DBG_BLOCK_ID_DB00_BY8 = 0x10, ++ DBG_BLOCK_ID_DB10_BY8 = 0x11, ++ DBG_BLOCK_ID_TCC0_BY8 = 0x12, ++ DBG_BLOCK_ID_SPS00_BY8 = 0x13, ++ DBG_BLOCK_ID_TA00_BY8 = 0x14, ++ DBG_BLOCK_ID_TA08_BY8 = 0x15, ++ DBG_BLOCK_ID_TA10_BY8 = 0x16, ++ DBG_BLOCK_ID_TA18_BY8 = 0x17, ++ DBG_BLOCK_ID_TD00_BY8 = 0x18, ++ DBG_BLOCK_ID_TD08_BY8 = 0x19, ++ DBG_BLOCK_ID_TD10_BY8 = 0x1a, ++ DBG_BLOCK_ID_TD18_BY8 = 0x1b, ++ DBG_BLOCK_ID_MCD0_BY8 = 0x1c, ++} DebugBlockId_BY8; ++typedef enum DebugBlockId_BY16 { ++ DBG_BLOCK_ID_RESERVED_BY16 = 0x0, ++ DBG_BLOCK_ID_DMA0_BY16 = 0x1, ++ DBG_BLOCK_ID_VGT0_BY16 = 0x2, ++ DBG_BLOCK_ID_SX0_BY16 = 0x3, ++ DBG_BLOCK_ID_SCB0_BY16 = 0x4, ++ DBG_BLOCK_ID_CB00_BY16 = 0x5, ++ DBG_BLOCK_ID_TCP0_BY16 = 0x6, ++ DBG_BLOCK_ID_TCP16_BY16 = 0x7, ++ DBG_BLOCK_ID_DB00_BY16 = 0x8, ++ DBG_BLOCK_ID_TCC0_BY16 = 0x9, ++ DBG_BLOCK_ID_TA00_BY16 = 0xa, ++ DBG_BLOCK_ID_TA10_BY16 = 0xb, ++ DBG_BLOCK_ID_TD00_BY16 = 0xc, ++ DBG_BLOCK_ID_TD10_BY16 = 0xd, ++ DBG_BLOCK_ID_MCD0_BY16 = 0xe, ++} DebugBlockId_BY16; ++typedef enum ColorTransform { ++ DCC_CT_AUTO = 0x0, ++ DCC_CT_NONE = 0x1, ++ ABGR_TO_A_BG_G_RB = 0x2, ++ BGRA_TO_BG_G_RB_A = 0x3, ++} ColorTransform; ++typedef enum CompareRef { ++ REF_NEVER = 0x0, ++ REF_LESS = 0x1, ++ REF_EQUAL = 0x2, ++ REF_LEQUAL = 0x3, ++ REF_GREATER = 0x4, ++ REF_NOTEQUAL = 0x5, ++ REF_GEQUAL = 0x6, ++ REF_ALWAYS = 0x7, ++} CompareRef; ++typedef enum ReadSize { ++ READ_256_BITS = 0x0, ++ READ_512_BITS = 0x1, ++} ReadSize; ++typedef enum DepthFormat { ++ DEPTH_INVALID = 0x0, ++ DEPTH_16 = 0x1, ++ DEPTH_X8_24 = 0x2, ++ DEPTH_8_24 = 0x3, ++ DEPTH_X8_24_FLOAT = 0x4, ++ DEPTH_8_24_FLOAT = 0x5, ++ DEPTH_32_FLOAT = 0x6, ++ DEPTH_X24_8_32_FLOAT = 0x7, ++} DepthFormat; ++typedef enum ZFormat { ++ Z_INVALID = 0x0, ++ Z_16 = 0x1, ++ Z_24 = 0x2, ++ Z_32_FLOAT = 0x3, ++} ZFormat; ++typedef enum StencilFormat { ++ STENCIL_INVALID = 0x0, ++ STENCIL_8 = 0x1, ++} StencilFormat; ++typedef enum CmaskMode { ++ CMASK_CLEAR_NONE = 0x0, ++ CMASK_CLEAR_ONE = 0x1, ++ CMASK_CLEAR_ALL = 0x2, ++ CMASK_ANY_EXPANDED = 0x3, ++ CMASK_ALPHA0_FRAG1 = 0x4, ++ CMASK_ALPHA0_FRAG2 = 0x5, ++ CMASK_ALPHA0_FRAG4 = 0x6, ++ CMASK_ALPHA0_FRAGS = 0x7, ++ CMASK_ALPHA1_FRAG1 = 0x8, ++ CMASK_ALPHA1_FRAG2 = 0x9, ++ CMASK_ALPHA1_FRAG4 = 0xa, ++ CMASK_ALPHA1_FRAGS = 0xb, ++ CMASK_ALPHAX_FRAG1 = 0xc, ++ CMASK_ALPHAX_FRAG2 = 0xd, ++ CMASK_ALPHAX_FRAG4 = 0xe, ++ CMASK_ALPHAX_FRAGS = 0xf, ++} CmaskMode; ++typedef enum QuadExportFormat { ++ EXPORT_UNUSED = 0x0, ++ EXPORT_32_R = 0x1, ++ EXPORT_32_GR = 0x2, ++ EXPORT_32_AR = 0x3, ++ EXPORT_FP16_ABGR = 0x4, ++ EXPORT_UNSIGNED16_ABGR = 0x5, ++ EXPORT_SIGNED16_ABGR = 0x6, ++ EXPORT_32_ABGR = 0x7, ++} QuadExportFormat; ++typedef enum QuadExportFormatOld { ++ EXPORT_4P_32BPC_ABGR = 0x0, ++ EXPORT_4P_16BPC_ABGR = 0x1, ++ EXPORT_4P_32BPC_GR = 0x2, ++ EXPORT_4P_32BPC_AR = 0x3, ++ EXPORT_2P_32BPC_ABGR = 0x4, ++ EXPORT_8P_32BPC_R = 0x5, ++} QuadExportFormatOld; ++typedef enum ColorFormat { ++ COLOR_INVALID = 0x0, ++ COLOR_8 = 0x1, ++ COLOR_16 = 0x2, ++ COLOR_8_8 = 0x3, ++ COLOR_32 = 0x4, ++ COLOR_16_16 = 0x5, ++ COLOR_10_11_11 = 0x6, ++ COLOR_11_11_10 = 0x7, ++ COLOR_10_10_10_2 = 0x8, ++ COLOR_2_10_10_10 = 0x9, ++ COLOR_8_8_8_8 = 0xa, ++ COLOR_32_32 = 0xb, ++ COLOR_16_16_16_16 = 0xc, ++ COLOR_RESERVED_13 = 0xd, ++ COLOR_32_32_32_32 = 0xe, ++ COLOR_RESERVED_15 = 0xf, ++ COLOR_5_6_5 = 0x10, ++ COLOR_1_5_5_5 = 0x11, ++ COLOR_5_5_5_1 = 0x12, ++ COLOR_4_4_4_4 = 0x13, ++ COLOR_8_24 = 0x14, ++ COLOR_24_8 = 0x15, ++ COLOR_X24_8_32_FLOAT = 0x16, ++ COLOR_RESERVED_23 = 0x17, ++} ColorFormat; ++typedef enum SurfaceFormat { ++ FMT_INVALID = 0x0, ++ FMT_8 = 0x1, ++ FMT_16 = 0x2, ++ FMT_8_8 = 0x3, ++ FMT_32 = 0x4, ++ FMT_16_16 = 0x5, ++ FMT_10_11_11 = 0x6, ++ FMT_11_11_10 = 0x7, ++ FMT_10_10_10_2 = 0x8, ++ FMT_2_10_10_10 = 0x9, ++ FMT_8_8_8_8 = 0xa, ++ FMT_32_32 = 0xb, ++ FMT_16_16_16_16 = 0xc, ++ FMT_32_32_32 = 0xd, ++ FMT_32_32_32_32 = 0xe, ++ FMT_RESERVED_4 = 0xf, ++ FMT_5_6_5 = 0x10, ++ FMT_1_5_5_5 = 0x11, ++ FMT_5_5_5_1 = 0x12, ++ FMT_4_4_4_4 = 0x13, ++ FMT_8_24 = 0x14, ++ FMT_24_8 = 0x15, ++ FMT_X24_8_32_FLOAT = 0x16, ++ FMT_RESERVED_33 = 0x17, ++ FMT_11_11_10_FLOAT = 0x18, ++ FMT_16_FLOAT = 0x19, ++ FMT_32_FLOAT = 0x1a, ++ FMT_16_16_FLOAT = 0x1b, ++ FMT_8_24_FLOAT = 0x1c, ++ FMT_24_8_FLOAT = 0x1d, ++ FMT_32_32_FLOAT = 0x1e, ++ FMT_10_11_11_FLOAT = 0x1f, ++ FMT_16_16_16_16_FLOAT = 0x20, ++ FMT_3_3_2 = 0x21, ++ FMT_6_5_5 = 0x22, ++ FMT_32_32_32_32_FLOAT = 0x23, ++ FMT_RESERVED_36 = 0x24, ++ FMT_1 = 0x25, ++ FMT_1_REVERSED = 0x26, ++ FMT_GB_GR = 0x27, ++ FMT_BG_RG = 0x28, ++ FMT_32_AS_8 = 0x29, ++ FMT_32_AS_8_8 = 0x2a, ++ FMT_5_9_9_9_SHAREDEXP = 0x2b, ++ FMT_8_8_8 = 0x2c, ++ FMT_16_16_16 = 0x2d, ++ FMT_16_16_16_FLOAT = 0x2e, ++ FMT_4_4 = 0x2f, ++ FMT_32_32_32_FLOAT = 0x30, ++ FMT_BC1 = 0x31, ++ FMT_BC2 = 0x32, ++ FMT_BC3 = 0x33, ++ FMT_BC4 = 0x34, ++ FMT_BC5 = 0x35, ++ FMT_BC6 = 0x36, ++ FMT_BC7 = 0x37, ++ FMT_32_AS_32_32_32_32 = 0x38, ++ FMT_APC3 = 0x39, ++ FMT_APC4 = 0x3a, ++ FMT_APC5 = 0x3b, ++ FMT_APC6 = 0x3c, ++ FMT_APC7 = 0x3d, ++ FMT_CTX1 = 0x3e, ++ FMT_RESERVED_63 = 0x3f, ++} SurfaceFormat; ++typedef enum BUF_DATA_FORMAT { ++ BUF_DATA_FORMAT_INVALID = 0x0, ++ BUF_DATA_FORMAT_8 = 0x1, ++ BUF_DATA_FORMAT_16 = 0x2, ++ BUF_DATA_FORMAT_8_8 = 0x3, ++ BUF_DATA_FORMAT_32 = 0x4, ++ BUF_DATA_FORMAT_16_16 = 0x5, ++ BUF_DATA_FORMAT_10_11_11 = 0x6, ++ BUF_DATA_FORMAT_11_11_10 = 0x7, ++ BUF_DATA_FORMAT_10_10_10_2 = 0x8, ++ BUF_DATA_FORMAT_2_10_10_10 = 0x9, ++ BUF_DATA_FORMAT_8_8_8_8 = 0xa, ++ BUF_DATA_FORMAT_32_32 = 0xb, ++ BUF_DATA_FORMAT_16_16_16_16 = 0xc, ++ BUF_DATA_FORMAT_32_32_32 = 0xd, ++ BUF_DATA_FORMAT_32_32_32_32 = 0xe, ++ BUF_DATA_FORMAT_RESERVED_15 = 0xf, ++} BUF_DATA_FORMAT; ++typedef enum IMG_DATA_FORMAT { ++ IMG_DATA_FORMAT_INVALID = 0x0, ++ IMG_DATA_FORMAT_8 = 0x1, ++ IMG_DATA_FORMAT_16 = 0x2, ++ IMG_DATA_FORMAT_8_8 = 0x3, ++ IMG_DATA_FORMAT_32 = 0x4, ++ IMG_DATA_FORMAT_16_16 = 0x5, ++ IMG_DATA_FORMAT_10_11_11 = 0x6, ++ IMG_DATA_FORMAT_11_11_10 = 0x7, ++ IMG_DATA_FORMAT_10_10_10_2 = 0x8, ++ IMG_DATA_FORMAT_2_10_10_10 = 0x9, ++ IMG_DATA_FORMAT_8_8_8_8 = 0xa, ++ IMG_DATA_FORMAT_32_32 = 0xb, ++ IMG_DATA_FORMAT_16_16_16_16 = 0xc, ++ IMG_DATA_FORMAT_32_32_32 = 0xd, ++ IMG_DATA_FORMAT_32_32_32_32 = 0xe, ++ IMG_DATA_FORMAT_RESERVED_15 = 0xf, ++ IMG_DATA_FORMAT_5_6_5 = 0x10, ++ IMG_DATA_FORMAT_1_5_5_5 = 0x11, ++ IMG_DATA_FORMAT_5_5_5_1 = 0x12, ++ IMG_DATA_FORMAT_4_4_4_4 = 0x13, ++ IMG_DATA_FORMAT_8_24 = 0x14, ++ IMG_DATA_FORMAT_24_8 = 0x15, ++ IMG_DATA_FORMAT_X24_8_32 = 0x16, ++ IMG_DATA_FORMAT_RESERVED_23 = 0x17, ++ IMG_DATA_FORMAT_RESERVED_24 = 0x18, ++ IMG_DATA_FORMAT_RESERVED_25 = 0x19, ++ IMG_DATA_FORMAT_RESERVED_26 = 0x1a, ++ IMG_DATA_FORMAT_RESERVED_27 = 0x1b, ++ IMG_DATA_FORMAT_RESERVED_28 = 0x1c, ++ IMG_DATA_FORMAT_RESERVED_29 = 0x1d, ++ IMG_DATA_FORMAT_RESERVED_30 = 0x1e, ++ IMG_DATA_FORMAT_RESERVED_31 = 0x1f, ++ IMG_DATA_FORMAT_GB_GR = 0x20, ++ IMG_DATA_FORMAT_BG_RG = 0x21, ++ IMG_DATA_FORMAT_5_9_9_9 = 0x22, ++ IMG_DATA_FORMAT_BC1 = 0x23, ++ IMG_DATA_FORMAT_BC2 = 0x24, ++ IMG_DATA_FORMAT_BC3 = 0x25, ++ IMG_DATA_FORMAT_BC4 = 0x26, ++ IMG_DATA_FORMAT_BC5 = 0x27, ++ IMG_DATA_FORMAT_BC6 = 0x28, ++ IMG_DATA_FORMAT_BC7 = 0x29, ++ IMG_DATA_FORMAT_RESERVED_42 = 0x2a, ++ IMG_DATA_FORMAT_RESERVED_43 = 0x2b, ++ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, ++ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, ++ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, ++ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, ++ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, ++ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, ++ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, ++ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, ++ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, ++ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, ++ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, ++ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, ++ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, ++ IMG_DATA_FORMAT_4_4 = 0x39, ++ IMG_DATA_FORMAT_6_5_5 = 0x3a, ++ IMG_DATA_FORMAT_1 = 0x3b, ++ IMG_DATA_FORMAT_1_REVERSED = 0x3c, ++ IMG_DATA_FORMAT_32_AS_8 = 0x3d, ++ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, ++ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, ++} IMG_DATA_FORMAT; ++typedef enum BUF_NUM_FORMAT { ++ BUF_NUM_FORMAT_UNORM = 0x0, ++ BUF_NUM_FORMAT_SNORM = 0x1, ++ BUF_NUM_FORMAT_USCALED = 0x2, ++ BUF_NUM_FORMAT_SSCALED = 0x3, ++ BUF_NUM_FORMAT_UINT = 0x4, ++ BUF_NUM_FORMAT_SINT = 0x5, ++ BUF_NUM_FORMAT_RESERVED_6 = 0x6, ++ BUF_NUM_FORMAT_FLOAT = 0x7, ++} BUF_NUM_FORMAT; ++typedef enum IMG_NUM_FORMAT { ++ IMG_NUM_FORMAT_UNORM = 0x0, ++ IMG_NUM_FORMAT_SNORM = 0x1, ++ IMG_NUM_FORMAT_USCALED = 0x2, ++ IMG_NUM_FORMAT_SSCALED = 0x3, ++ IMG_NUM_FORMAT_UINT = 0x4, ++ IMG_NUM_FORMAT_SINT = 0x5, ++ IMG_NUM_FORMAT_RESERVED_6 = 0x6, ++ IMG_NUM_FORMAT_FLOAT = 0x7, ++ IMG_NUM_FORMAT_RESERVED_8 = 0x8, ++ IMG_NUM_FORMAT_SRGB = 0x9, ++ IMG_NUM_FORMAT_RESERVED_10 = 0xa, ++ IMG_NUM_FORMAT_RESERVED_11 = 0xb, ++ IMG_NUM_FORMAT_RESERVED_12 = 0xc, ++ IMG_NUM_FORMAT_RESERVED_13 = 0xd, ++ IMG_NUM_FORMAT_RESERVED_14 = 0xe, ++ IMG_NUM_FORMAT_RESERVED_15 = 0xf, ++} IMG_NUM_FORMAT; ++typedef enum TileType { ++ ARRAY_COLOR_TILE = 0x0, ++ ARRAY_DEPTH_TILE = 0x1, ++} TileType; ++typedef enum NonDispTilingOrder { ++ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, ++ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, ++} NonDispTilingOrder; ++typedef enum MicroTileMode { ++ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, ++ ADDR_SURF_THIN_MICRO_TILING = 0x1, ++ ADDR_SURF_DEPTH_MICRO_TILING = 0x2, ++ ADDR_SURF_ROTATED_MICRO_TILING = 0x3, ++ ADDR_SURF_THICK_MICRO_TILING = 0x4, ++} MicroTileMode; ++typedef enum TileSplit { ++ ADDR_SURF_TILE_SPLIT_64B = 0x0, ++ ADDR_SURF_TILE_SPLIT_128B = 0x1, ++ ADDR_SURF_TILE_SPLIT_256B = 0x2, ++ ADDR_SURF_TILE_SPLIT_512B = 0x3, ++ ADDR_SURF_TILE_SPLIT_1KB = 0x4, ++ ADDR_SURF_TILE_SPLIT_2KB = 0x5, ++ ADDR_SURF_TILE_SPLIT_4KB = 0x6, ++} TileSplit; ++typedef enum SampleSplit { ++ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, ++ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, ++ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, ++ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, ++} SampleSplit; ++typedef enum PipeConfig { ++ ADDR_SURF_P2 = 0x0, ++ ADDR_SURF_P2_RESERVED0 = 0x1, ++ ADDR_SURF_P2_RESERVED1 = 0x2, ++ ADDR_SURF_P2_RESERVED2 = 0x3, ++ ADDR_SURF_P4_8x16 = 0x4, ++ ADDR_SURF_P4_16x16 = 0x5, ++ ADDR_SURF_P4_16x32 = 0x6, ++ ADDR_SURF_P4_32x32 = 0x7, ++ ADDR_SURF_P8_16x16_8x16 = 0x8, ++ ADDR_SURF_P8_16x32_8x16 = 0x9, ++ ADDR_SURF_P8_32x32_8x16 = 0xa, ++ ADDR_SURF_P8_16x32_16x16 = 0xb, ++ ADDR_SURF_P8_32x32_16x16 = 0xc, ++ ADDR_SURF_P8_32x32_16x32 = 0xd, ++ ADDR_SURF_P8_32x64_32x32 = 0xe, ++ ADDR_SURF_P8_RESERVED0 = 0xf, ++ ADDR_SURF_P16_32x32_8x16 = 0x10, ++ ADDR_SURF_P16_32x32_16x16 = 0x11, ++} PipeConfig; ++typedef enum NumBanks { ++ ADDR_SURF_2_BANK = 0x0, ++ ADDR_SURF_4_BANK = 0x1, ++ ADDR_SURF_8_BANK = 0x2, ++ ADDR_SURF_16_BANK = 0x3, ++} NumBanks; ++typedef enum BankWidth { ++ ADDR_SURF_BANK_WIDTH_1 = 0x0, ++ ADDR_SURF_BANK_WIDTH_2 = 0x1, ++ ADDR_SURF_BANK_WIDTH_4 = 0x2, ++ ADDR_SURF_BANK_WIDTH_8 = 0x3, ++} BankWidth; ++typedef enum BankHeight { ++ ADDR_SURF_BANK_HEIGHT_1 = 0x0, ++ ADDR_SURF_BANK_HEIGHT_2 = 0x1, ++ ADDR_SURF_BANK_HEIGHT_4 = 0x2, ++ ADDR_SURF_BANK_HEIGHT_8 = 0x3, ++} BankHeight; ++typedef enum BankWidthHeight { ++ ADDR_SURF_BANK_WH_1 = 0x0, ++ ADDR_SURF_BANK_WH_2 = 0x1, ++ ADDR_SURF_BANK_WH_4 = 0x2, ++ ADDR_SURF_BANK_WH_8 = 0x3, ++} BankWidthHeight; ++typedef enum MacroTileAspect { ++ ADDR_SURF_MACRO_ASPECT_1 = 0x0, ++ ADDR_SURF_MACRO_ASPECT_2 = 0x1, ++ ADDR_SURF_MACRO_ASPECT_4 = 0x2, ++ ADDR_SURF_MACRO_ASPECT_8 = 0x3, ++} MacroTileAspect; ++typedef enum GATCL1RequestType { ++ GATCL1_TYPE_NORMAL = 0x0, ++ GATCL1_TYPE_SHOOTDOWN = 0x1, ++ GATCL1_TYPE_BYPASS = 0x2, ++} GATCL1RequestType; ++typedef enum TCC_CACHE_POLICIES { ++ TCC_CACHE_POLICY_LRU = 0x0, ++ TCC_CACHE_POLICY_STREAM = 0x1, ++} TCC_CACHE_POLICIES; ++typedef enum MTYPE { ++ MTYPE_NC_NV = 0x0, ++ MTYPE_NC = 0x1, ++ MTYPE_CC = 0x2, ++ MTYPE_UC = 0x3, ++} MTYPE; ++typedef enum PERFMON_COUNTER_MODE { ++ PERFMON_COUNTER_MODE_ACCUM = 0x0, ++ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, ++ PERFMON_COUNTER_MODE_MAX = 0x2, ++ PERFMON_COUNTER_MODE_DIRTY = 0x3, ++ PERFMON_COUNTER_MODE_SAMPLE = 0x4, ++ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, ++ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, ++ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, ++ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, ++ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, ++ PERFMON_COUNTER_MODE_RESERVED = 0xf, ++} PERFMON_COUNTER_MODE; ++typedef enum PERFMON_SPM_MODE { ++ PERFMON_SPM_MODE_OFF = 0x0, ++ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, ++ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, ++ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, ++ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, ++ PERFMON_SPM_MODE_RESERVED_5 = 0x5, ++ PERFMON_SPM_MODE_RESERVED_6 = 0x6, ++ PERFMON_SPM_MODE_RESERVED_7 = 0x7, ++ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, ++ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, ++ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, ++} PERFMON_SPM_MODE; ++typedef enum SurfaceTiling { ++ ARRAY_LINEAR = 0x0, ++ ARRAY_TILED = 0x1, ++} SurfaceTiling; ++typedef enum SurfaceArray { ++ ARRAY_1D = 0x0, ++ ARRAY_2D = 0x1, ++ ARRAY_3D = 0x2, ++ ARRAY_3D_SLICE = 0x3, ++} SurfaceArray; ++typedef enum ColorArray { ++ ARRAY_2D_ALT_COLOR = 0x0, ++ ARRAY_2D_COLOR = 0x1, ++ ARRAY_3D_SLICE_COLOR = 0x3, ++} ColorArray; ++typedef enum DepthArray { ++ ARRAY_2D_ALT_DEPTH = 0x0, ++ ARRAY_2D_DEPTH = 0x1, ++} DepthArray; ++typedef enum ENUM_NUM_SIMD_PER_CU { ++ NUM_SIMD_PER_CU = 0x4, ++} ENUM_NUM_SIMD_PER_CU; ++typedef enum MEM_PWR_FORCE_CTRL { ++ NO_FORCE_REQUEST = 0x0, ++ FORCE_LIGHT_SLEEP_REQUEST = 0x1, ++ FORCE_DEEP_SLEEP_REQUEST = 0x2, ++ FORCE_SHUT_DOWN_REQUEST = 0x3, ++} MEM_PWR_FORCE_CTRL; ++typedef enum MEM_PWR_FORCE_CTRL2 { ++ NO_FORCE_REQ = 0x0, ++ FORCE_LIGHT_SLEEP_REQ = 0x1, ++} MEM_PWR_FORCE_CTRL2; ++typedef enum MEM_PWR_DIS_CTRL { ++ ENABLE_MEM_PWR_CTRL = 0x0, ++ DISABLE_MEM_PWR_CTRL = 0x1, ++} MEM_PWR_DIS_CTRL; ++typedef enum MEM_PWR_SEL_CTRL { ++ DYNAMIC_SHUT_DOWN_ENABLE = 0x0, ++ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, ++ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, ++} MEM_PWR_SEL_CTRL; ++typedef enum MEM_PWR_SEL_CTRL2 { ++ DYNAMIC_DEEP_SLEEP_EN = 0x0, ++ DYNAMIC_LIGHT_SLEEP_EN = 0x1, ++} MEM_PWR_SEL_CTRL2; ++ ++#endif /* OSS_3_0_ENUM_H */ +diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h +new file mode 100644 +index 0000000..7e2cca5 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h +@@ -0,0 +1,3660 @@ ++/* ++ * OSS_3_0 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef OSS_3_0_SH_MASK_H ++#define OSS_3_0_SH_MASK_H ++ ++#define IH_VMID_0_LUT__PASID_MASK 0xffff ++#define IH_VMID_0_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_1_LUT__PASID_MASK 0xffff ++#define IH_VMID_1_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_2_LUT__PASID_MASK 0xffff ++#define IH_VMID_2_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_3_LUT__PASID_MASK 0xffff ++#define IH_VMID_3_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_4_LUT__PASID_MASK 0xffff ++#define IH_VMID_4_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_5_LUT__PASID_MASK 0xffff ++#define IH_VMID_5_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_6_LUT__PASID_MASK 0xffff ++#define IH_VMID_6_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_7_LUT__PASID_MASK 0xffff ++#define IH_VMID_7_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_8_LUT__PASID_MASK 0xffff ++#define IH_VMID_8_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_9_LUT__PASID_MASK 0xffff ++#define IH_VMID_9_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_10_LUT__PASID_MASK 0xffff ++#define IH_VMID_10_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_11_LUT__PASID_MASK 0xffff ++#define IH_VMID_11_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_12_LUT__PASID_MASK 0xffff ++#define IH_VMID_12_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_13_LUT__PASID_MASK 0xffff ++#define IH_VMID_13_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_14_LUT__PASID_MASK 0xffff ++#define IH_VMID_14_LUT__PASID__SHIFT 0x0 ++#define IH_VMID_15_LUT__PASID_MASK 0xffff ++#define IH_VMID_15_LUT__PASID__SHIFT 0x0 ++#define IH_RB_CNTL__RB_ENABLE_MASK 0x1 ++#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define IH_RB_CNTL__RB_SIZE_MASK 0x3e ++#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80 ++#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 ++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 ++#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 ++#define IH_RB_CNTL__ENABLE_INTR_MASK 0x20000 ++#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 ++#define IH_RB_CNTL__MC_SWAP_MASK 0xc0000 ++#define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 ++#define IH_RB_CNTL__RPTR_REARM_MASK 0x200000 ++#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 ++#define IH_RB_CNTL__MC_VMID_MASK 0xf000000 ++#define IH_RB_CNTL__MC_VMID__SHIFT 0x18 ++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 ++#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f ++#define IH_RB_BASE__ADDR_MASK 0xffffffff ++#define IH_RB_BASE__ADDR__SHIFT 0x0 ++#define IH_RB_RPTR__OFFSET_MASK 0x3fffc ++#define IH_RB_RPTR__OFFSET__SHIFT 0x2 ++#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1 ++#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 ++#define IH_RB_WPTR__OFFSET_MASK 0x3fffc ++#define IH_RB_WPTR__OFFSET__SHIFT 0x2 ++#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000 ++#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 ++#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000 ++#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 ++#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff ++#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc ++#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x1f ++#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 ++#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300 ++#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8 ++#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00 ++#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa ++#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000 ++#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf ++#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000 ++#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 ++#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1 ++#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0 ++#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4 ++#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2 ++#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8 ++#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3 ++#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10 ++#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4 ++#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20 ++#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5 ++#define IH_STATUS__IDLE_MASK 0x1 ++#define IH_STATUS__IDLE__SHIFT 0x0 ++#define IH_STATUS__INPUT_IDLE_MASK 0x2 ++#define IH_STATUS__INPUT_IDLE__SHIFT 0x1 ++#define IH_STATUS__RB_IDLE_MASK 0x4 ++#define IH_STATUS__RB_IDLE__SHIFT 0x2 ++#define IH_STATUS__RB_FULL_MASK 0x8 ++#define IH_STATUS__RB_FULL__SHIFT 0x3 ++#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10 ++#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 ++#define IH_STATUS__RB_OVERFLOW_MASK 0x20 ++#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 ++#define IH_STATUS__MC_WR_IDLE_MASK 0x40 ++#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 ++#define IH_STATUS__MC_WR_STALL_MASK 0x80 ++#define IH_STATUS__MC_WR_STALL__SHIFT 0x7 ++#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100 ++#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 ++#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200 ++#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 ++#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400 ++#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa ++#define IH_STATUS__SWITCH_READY_MASK 0x800 ++#define IH_STATUS__SWITCH_READY__SHIFT 0xb ++#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1 ++#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 ++#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2 ++#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 ++#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x3fc ++#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 ++#define IH_PERFMON_CNTL__ENABLE1_MASK 0x400 ++#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0xa ++#define IH_PERFMON_CNTL__CLEAR1_MASK 0x800 ++#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0xb ++#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xff000 ++#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc ++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff ++#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 ++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff ++#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 ++#define IH_DEBUG__RB_FULL_DRAIN_ENABLE_MASK 0x1 ++#define IH_DEBUG__RB_FULL_DRAIN_ENABLE__SHIFT 0x0 ++#define IH_DEBUG__WPTR_OVERFLOW_ENABLE_MASK 0x2 ++#define IH_DEBUG__WPTR_OVERFLOW_ENABLE__SHIFT 0x1 ++#define IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE_MASK 0x4 ++#define IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE__SHIFT 0x2 ++#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff ++#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 ++#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff ++#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 ++#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff ++#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 ++#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1 ++#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 ++#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x2 ++#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 ++#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4 ++#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 ++#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8 ++#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 ++#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10 ++#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 ++#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20 ++#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 ++#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff ++#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 ++#define IH_DOORBELL_RPTR__OFFSET_MASK 0x1fffff ++#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 ++#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000 ++#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c ++#define IH_DOORBELL_RPTR__CAPTURED_MASK 0x40000000 ++#define IH_DOORBELL_RPTR__CAPTURED__SHIFT 0x1e ++#define IH_ACTIVE_FCN_ID__VF_ID_MASK 0xf ++#define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 ++#define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0 ++#define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 ++#define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000 ++#define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f ++#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0xffff ++#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 ++#define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0xffff0000 ++#define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 ++#define IH_VF_ENABLE__VALUE_MASK 0x1 ++#define IH_VF_ENABLE__VALUE__SHIFT 0x0 ++#define IH_VIRT_RESET_REQ__VF_MASK 0xffff ++#define IH_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define IH_VIRT_RESET_REQ__PF_MASK 0x80000000 ++#define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define IH_VF_RB_BIF_STATUS__RB_FULL_VF_MASK 0xffff ++#define IH_VF_RB_BIF_STATUS__RB_FULL_VF__SHIFT 0x0 ++#define IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF_MASK 0xffff0000 ++#define IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF__SHIFT 0x10 ++#define IH_VERSION__VALUE_MASK 0xfff ++#define IH_VERSION__VALUE__SHIFT 0x0 ++#define IH_LEVEL_INTR_MASK__MASK_MASK 0x1 ++#define IH_LEVEL_INTR_MASK__MASK__SHIFT 0x0 ++#define IH_RESET_INCOMPLETE_INT_CNTL__CG_MASK 0x1 ++#define IH_RESET_INCOMPLETE_INT_CNTL__CG__SHIFT 0x0 ++#define IH_RESET_INCOMPLETE_INT_CNTL__DC_MASK 0x2 ++#define IH_RESET_INCOMPLETE_INT_CNTL__DC__SHIFT 0x1 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP_MASK 0x8 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP__SHIFT 0x3 ++#define IH_RESET_INCOMPLETE_INT_CNTL__RLC_MASK 0x10 ++#define IH_RESET_INCOMPLETE_INT_CNTL__RLC__SHIFT 0x4 ++#define IH_RESET_INCOMPLETE_INT_CNTL__ROM_MASK 0x20 ++#define IH_RESET_INCOMPLETE_INT_CNTL__ROM__SHIFT 0x5 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SRBM_MASK 0x40 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SRBM__SHIFT 0x6 ++#define IH_RESET_INCOMPLETE_INT_CNTL__VMC_MASK 0x80 ++#define IH_RESET_INCOMPLETE_INT_CNTL__VMC__SHIFT 0x7 ++#define IH_RESET_INCOMPLETE_INT_CNTL__UVD_MASK 0x100 ++#define IH_RESET_INCOMPLETE_INT_CNTL__UVD__SHIFT 0x8 ++#define IH_RESET_INCOMPLETE_INT_CNTL__BIF_MASK 0x200 ++#define IH_RESET_INCOMPLETE_INT_CNTL__BIF__SHIFT 0x9 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA0_MASK 0x400 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA0__SHIFT 0xa ++#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA1_MASK 0x800 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SDMA1__SHIFT 0xb ++#define IH_RESET_INCOMPLETE_INT_CNTL__ISP_MASK 0x1000 ++#define IH_RESET_INCOMPLETE_INT_CNTL__ISP__SHIFT 0xc ++#define IH_RESET_INCOMPLETE_INT_CNTL__VCE0_MASK 0x2000 ++#define IH_RESET_INCOMPLETE_INT_CNTL__VCE0__SHIFT 0xd ++#define IH_RESET_INCOMPLETE_INT_CNTL__VCE1_MASK 0x4000 ++#define IH_RESET_INCOMPLETE_INT_CNTL__VCE1__SHIFT 0xe ++#define IH_RESET_INCOMPLETE_INT_CNTL__ATC_MASK 0x8000 ++#define IH_RESET_INCOMPLETE_INT_CNTL__ATC__SHIFT 0xf ++#define IH_RESET_INCOMPLETE_INT_CNTL__XDMA_MASK 0x10000 ++#define IH_RESET_INCOMPLETE_INT_CNTL__XDMA__SHIFT 0x10 ++#define IH_RESET_INCOMPLETE_INT_CNTL__ACP_MASK 0x20000 ++#define IH_RESET_INCOMPLETE_INT_CNTL__ACP__SHIFT 0x11 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SH_MASK 0x40000 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SH__SHIFT 0x12 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SH1_MASK 0x80000 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SH1__SHIFT 0x13 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SH2_MASK 0x100000 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SH2__SHIFT 0x14 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SH3_MASK 0x200000 ++#define IH_RESET_INCOMPLETE_INT_CNTL__SH3__SHIFT 0x15 ++#define IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE_MASK 0x400000 ++#define IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE__SHIFT 0x16 ++#define IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT_MASK 0xf000000 ++#define IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT__SHIFT 0x18 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG_MASK 0x1 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG__SHIFT 0x0 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC_MASK 0x2 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC__SHIFT 0x1 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP_MASK 0x8 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP__SHIFT 0x3 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC_MASK 0x10 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC__SHIFT 0x4 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM_MASK 0x20 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM__SHIFT 0x5 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM_MASK 0x40 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM__SHIFT 0x6 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC_MASK 0x80 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC__SHIFT 0x7 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD_MASK 0x100 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD__SHIFT 0x8 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF_MASK 0x200 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF__SHIFT 0x9 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0_MASK 0x400 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0__SHIFT 0xa ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1_MASK 0x800 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1__SHIFT 0xb ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP_MASK 0x1000 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP__SHIFT 0xc ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0_MASK 0x2000 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0__SHIFT 0xd ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1_MASK 0x4000 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1__SHIFT 0xe ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC_MASK 0x8000 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC__SHIFT 0xf ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA_MASK 0x10000 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA__SHIFT 0x10 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP_MASK 0x20000 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP__SHIFT 0x11 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH_MASK 0x40000 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH__SHIFT 0x12 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1_MASK 0x80000 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1__SHIFT 0x13 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2_MASK 0x100000 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2__SHIFT 0x14 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3_MASK 0x200000 ++#define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3__SHIFT 0x15 ++#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3 ++#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 ++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc ++#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 ++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00 ++#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 ++#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 ++#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 ++#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 ++#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 ++#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 ++#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 ++#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 ++#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 ++#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00 ++#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8 ++#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000 ++#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10 ++#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00 ++#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8 ++#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000 ++#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10 ++#define SEM_VF_ENABLE__VALUE_MASK 0x1 ++#define SEM_VF_ENABLE__VALUE__SHIFT 0x0 ++#define CP_CONFIG__CP_RDREQ_URG_MASK 0xf00 ++#define CP_CONFIG__CP_RDREQ_URG__SHIFT 0x8 ++#define CP_CONFIG__CP_REQ_TRAN_MASK 0x10000 ++#define CP_CONFIG__CP_REQ_TRAN__SHIFT 0x10 ++#define SEM_ACTIVE_FCN_ID__VFID_MASK 0xf ++#define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000 ++#define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define SEM_VIRT_RESET_REQ__VF_MASK 0xffff ++#define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000 ++#define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define SEM_STATUS__SEM_IDLE_MASK 0x1 ++#define SEM_STATUS__SEM_IDLE__SHIFT 0x0 ++#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2 ++#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 ++#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4 ++#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 ++#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8 ++#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 ++#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10 ++#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 ++#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20 ++#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 ++#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40 ++#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 ++#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80 ++#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 ++#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100 ++#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 ++#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200 ++#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 ++#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400 ++#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa ++#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800 ++#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb ++#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000 ++#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc ++#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000 ++#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd ++#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000 ++#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe ++#define SEM_STATUS__SWITCH_READY_MASK 0x80000000 ++#define SEM_STATUS__SWITCH_READY__SHIFT 0x1f ++#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2 ++#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00 ++#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 ++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000 ++#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc ++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000 ++#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf ++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000 ++#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 ++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000 ++#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 ++#define SEM_MAILBOX__SIDEPORT_MASK 0xff ++#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0 ++#define SEM_MAILBOX__HOSTPORT_MASK 0xff00 ++#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8 ++#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000 ++#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10 ++#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000 ++#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18 ++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff ++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0 ++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00 ++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8 ++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000 ++#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10 ++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000 ++#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18 ++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1 ++#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 ++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2 ++#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 ++#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4 ++#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2 ++#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18 ++#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3 ++#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00 ++#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8 ++#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f ++#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0 ++#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000 ++#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10 ++#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000 ++#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11 ++#define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000 ++#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12 ++#define SRBM_GFX_CNTL__PIPEID_MASK 0x3 ++#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0 ++#define SRBM_GFX_CNTL__MEID_MASK 0xc ++#define SRBM_GFX_CNTL__MEID__SHIFT 0x2 ++#define SRBM_GFX_CNTL__VMID_MASK 0xf0 ++#define SRBM_GFX_CNTL__VMID__SHIFT 0x4 ++#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700 ++#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 ++#define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff ++#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0 ++#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1 ++#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0 ++#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2 ++#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1 ++#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4 ++#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2 ++#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8 ++#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3 ++#define SRBM_STATUS2__VP8_BUSY_MASK 0x10 ++#define SRBM_STATUS2__VP8_BUSY__SHIFT 0x4 ++#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20 ++#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5 ++#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40 ++#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6 ++#define SRBM_STATUS2__VCE0_BUSY_MASK 0x80 ++#define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7 ++#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100 ++#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8 ++#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200 ++#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9 ++#define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400 ++#define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa ++#define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800 ++#define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb ++#define SRBM_STATUS2__SAMSCP_BUSY_MASK 0x1000 ++#define SRBM_STATUS2__SAMSCP_BUSY__SHIFT 0xc ++#define SRBM_STATUS2__ISP_BUSY_MASK 0x2000 ++#define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd ++#define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000 ++#define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe ++#define SRBM_STATUS2__ODE_BUSY_MASK 0x8000 ++#define SRBM_STATUS2__ODE_BUSY__SHIFT 0xf ++#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000 ++#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10 ++#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000 ++#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11 ++#define SRBM_STATUS2__SAMSCP_RQ_PENDING_MASK 0x40000 ++#define SRBM_STATUS2__SAMSCP_RQ_PENDING__SHIFT 0x12 ++#define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000 ++#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13 ++#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000 ++#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14 ++#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2 ++#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1 ++#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4 ++#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2 ++#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8 ++#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3 ++#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10 ++#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4 ++#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20 ++#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5 ++#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40 ++#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6 ++#define SRBM_STATUS__VMC_BUSY_MASK 0x100 ++#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8 ++#define SRBM_STATUS__MCB_BUSY_MASK 0x200 ++#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9 ++#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400 ++#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa ++#define SRBM_STATUS__MCC_BUSY_MASK 0x800 ++#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb ++#define SRBM_STATUS__MCD_BUSY_MASK 0x1000 ++#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc ++#define SRBM_STATUS__VMC1_BUSY_MASK 0x2000 ++#define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd ++#define SRBM_STATUS__SEM_BUSY_MASK 0x4000 ++#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe ++#define SRBM_STATUS__ACP_BUSY_MASK 0x10000 ++#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10 ++#define SRBM_STATUS__IH_BUSY_MASK 0x20000 ++#define SRBM_STATUS__IH_BUSY__SHIFT 0x11 ++#define SRBM_STATUS__UVD_BUSY_MASK 0x80000 ++#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13 ++#define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000 ++#define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14 ++#define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000 ++#define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15 ++#define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000 ++#define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16 ++#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000 ++#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d ++#define SRBM_STATUS3__MCC0_BUSY_MASK 0x1 ++#define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0 ++#define SRBM_STATUS3__MCC1_BUSY_MASK 0x2 ++#define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1 ++#define SRBM_STATUS3__MCC2_BUSY_MASK 0x4 ++#define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2 ++#define SRBM_STATUS3__MCC3_BUSY_MASK 0x8 ++#define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3 ++#define SRBM_STATUS3__MCC4_BUSY_MASK 0x10 ++#define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4 ++#define SRBM_STATUS3__MCC5_BUSY_MASK 0x20 ++#define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5 ++#define SRBM_STATUS3__MCC6_BUSY_MASK 0x40 ++#define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6 ++#define SRBM_STATUS3__MCC7_BUSY_MASK 0x80 ++#define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7 ++#define SRBM_STATUS3__MCD0_BUSY_MASK 0x100 ++#define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8 ++#define SRBM_STATUS3__MCD1_BUSY_MASK 0x200 ++#define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9 ++#define SRBM_STATUS3__MCD2_BUSY_MASK 0x400 ++#define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa ++#define SRBM_STATUS3__MCD3_BUSY_MASK 0x800 ++#define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb ++#define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000 ++#define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc ++#define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000 ++#define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd ++#define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000 ++#define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe ++#define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000 ++#define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf ++#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1 ++#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0 ++#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2 ++#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1 ++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4 ++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2 ++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8 ++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3 ++#define SRBM_SOFT_RESET__SOFT_RESET_GIONB_MASK 0x10 ++#define SRBM_SOFT_RESET__SOFT_RESET_GIONB__SHIFT 0x4 ++#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20 ++#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5 ++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40 ++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6 ++#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100 ++#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8 ++#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200 ++#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9 ++#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400 ++#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa ++#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800 ++#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb ++#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000 ++#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc ++#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000 ++#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd ++#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000 ++#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe ++#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000 ++#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf ++#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000 ++#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10 ++#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000 ++#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11 ++#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000 ++#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12 ++#define SRBM_SOFT_RESET__SOFT_RESET_VP8_MASK 0x80000 ++#define SRBM_SOFT_RESET__SOFT_RESET_VP8__SHIFT 0x13 ++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000 ++#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14 ++#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000 ++#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15 ++#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000 ++#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16 ++#define SRBM_SOFT_RESET__SOFT_RESET_ODE_MASK 0x800000 ++#define SRBM_SOFT_RESET__SOFT_RESET_ODE__SHIFT 0x17 ++#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000 ++#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18 ++#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000 ++#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19 ++#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000 ++#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a ++#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000 ++#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b ++#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP_MASK 0x10000000 ++#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP__SHIFT 0x1c ++#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000 ++#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d ++#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000 ++#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e ++#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000 ++#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f ++#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f ++#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0 ++#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff ++#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0 ++#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff ++#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 ++#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_TIME_MASK 0xfff ++#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_TIME__SHIFT 0x0 ++#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_ENABLE_MASK 0x80000000 ++#define SRBM_CREDIT_RECOVER_CNTL__CREDIT_RECOVER_ENABLE__SHIFT 0x1f ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_BIF_MASK 0x1 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_BIF__SHIFT 0x0 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU_MASK 0x2 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU__SHIFT 0x1 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_DC_MASK 0x4 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_DC__SHIFT 0x2 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GIONB_MASK 0x8 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GIONB__SHIFT 0x3 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ACP_MASK 0x10 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ACP__SHIFT 0x4 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_XDMA_MASK 0x20 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_XDMA__SHIFT 0x5 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ODE_MASK 0x40 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ODE__SHIFT 0x6 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_REGBB_MASK 0x80 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_REGBB__SHIFT 0x7 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VP8_MASK 0x100 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VP8__SHIFT 0x8 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GRBM_MASK 0x200 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_GRBM__SHIFT 0x9 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_UVD_MASK 0x400 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_UVD__SHIFT 0xa ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE0_MASK 0x800 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE0__SHIFT 0xb ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE1_MASK 0x1000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_VCE1__SHIFT 0xc ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ISP_MASK 0x2000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_ISP__SHIFT 0xd ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SAM_MASK 0x4000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SAM__SHIFT 0xe ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCB_MASK 0x8000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCB__SHIFT 0xf ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC0_MASK 0x10000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC0__SHIFT 0x10 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC1_MASK 0x20000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC1__SHIFT 0x11 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC2_MASK 0x40000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC2__SHIFT 0x12 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC3_MASK 0x80000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC3__SHIFT 0x13 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC4_MASK 0x100000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC4__SHIFT 0x14 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC5_MASK 0x200000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC5__SHIFT 0x15 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC6_MASK 0x400000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC6__SHIFT 0x16 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC7_MASK 0x800000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCC7__SHIFT 0x17 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD0_MASK 0x1000000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD0__SHIFT 0x18 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD1_MASK 0x2000000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD1__SHIFT 0x19 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD2_MASK 0x4000000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD2__SHIFT 0x1a ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD3_MASK 0x8000000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD3__SHIFT 0x1b ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD4_MASK 0x10000000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD4__SHIFT 0x1c ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD5_MASK 0x20000000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD5__SHIFT 0x1d ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD6_MASK 0x40000000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD6__SHIFT 0x1e ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD7_MASK 0x80000000 ++#define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_MCD7__SHIFT 0x1f ++#define SRBM_CREDIT_RESET__CREDIT_RESET_BIF_MASK 0x1 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_BIF__SHIFT 0x0 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_SMU_MASK 0x2 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_SMU__SHIFT 0x1 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_DC_MASK 0x4 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_DC__SHIFT 0x2 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_GIONB_MASK 0x8 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_GIONB__SHIFT 0x3 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_ACP_MASK 0x10 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_ACP__SHIFT 0x4 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_XDMA_MASK 0x20 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_XDMA__SHIFT 0x5 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_ODE_MASK 0x40 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_ODE__SHIFT 0x6 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_REGBB_MASK 0x80 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_REGBB__SHIFT 0x7 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_VP8_MASK 0x100 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_VP8__SHIFT 0x8 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_GRBM_MASK 0x200 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_GRBM__SHIFT 0x9 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_UVD_MASK 0x400 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_UVD__SHIFT 0xa ++#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE0_MASK 0x800 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE0__SHIFT 0xb ++#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE1_MASK 0x1000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_VCE1__SHIFT 0xc ++#define SRBM_CREDIT_RESET__CREDIT_RESET_ISP_MASK 0x2000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_ISP__SHIFT 0xd ++#define SRBM_CREDIT_RESET__CREDIT_RESET_SAM_MASK 0x4000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_SAM__SHIFT 0xe ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCB_MASK 0x8000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCB__SHIFT 0xf ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC0_MASK 0x10000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC0__SHIFT 0x10 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC1_MASK 0x20000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC1__SHIFT 0x11 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC2_MASK 0x40000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC2__SHIFT 0x12 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC3_MASK 0x80000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC3__SHIFT 0x13 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC4_MASK 0x100000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC4__SHIFT 0x14 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC5_MASK 0x200000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC5__SHIFT 0x15 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC6_MASK 0x400000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC6__SHIFT 0x16 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC7_MASK 0x800000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCC7__SHIFT 0x17 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD0_MASK 0x1000000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD0__SHIFT 0x18 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD1_MASK 0x2000000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD1__SHIFT 0x19 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD2_MASK 0x4000000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD2__SHIFT 0x1a ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD3_MASK 0x8000000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD3__SHIFT 0x1b ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD4_MASK 0x10000000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD4__SHIFT 0x1c ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD5_MASK 0x20000000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD5__SHIFT 0x1d ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD6_MASK 0x40000000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD6__SHIFT 0x1e ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD7_MASK 0x80000000 ++#define SRBM_CREDIT_RESET__CREDIT_RESET_MCD7__SHIFT 0x1f ++#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 ++#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 ++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 ++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc ++#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 ++#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 ++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 ++#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 ++#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 ++#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 ++#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 ++#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 ++#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf ++#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 ++#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 ++#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 ++#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf ++#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 ++#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 ++#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 ++#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf ++#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 ++#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 ++#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 ++#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf ++#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 ++#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 ++#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 ++#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf ++#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 ++#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 ++#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 ++#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf ++#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 ++#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 ++#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 ++#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf ++#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 ++#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 ++#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 ++#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf ++#define SRBM_VP8_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 ++#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 ++#define SRBM_VP8_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 ++#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1 ++#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0 ++#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2 ++#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1 ++#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4 ++#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2 ++#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10 ++#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4 ++#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20 ++#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5 ++#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40 ++#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6 ++#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80 ++#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7 ++#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100 ++#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8 ++#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200 ++#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9 ++#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400 ++#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa ++#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE_MASK 0x800 ++#define SRBM_DEBUG__VP8_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xb ++#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1 ++#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0 ++#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY_MASK 0x2 ++#define SRBM_DEBUG_SNAPSHOT__GIONB_RDY__SHIFT 0x1 ++#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4 ++#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2 ++#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8 ++#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3 ++#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10 ++#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4 ++#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20 ++#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5 ++#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40 ++#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6 ++#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80 ++#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7 ++#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100 ++#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8 ++#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200 ++#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9 ++#define SRBM_DEBUG_SNAPSHOT__VP8_RDY_MASK 0x400 ++#define SRBM_DEBUG_SNAPSHOT__VP8_RDY__SHIFT 0xa ++#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800 ++#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb ++#define SRBM_DEBUG_SNAPSHOT__ODE_RDY_MASK 0x1000 ++#define SRBM_DEBUG_SNAPSHOT__ODE_RDY__SHIFT 0xc ++#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000 ++#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd ++#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000 ++#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe ++#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000 ++#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf ++#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000 ++#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10 ++#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000 ++#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11 ++#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000 ++#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12 ++#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000 ++#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13 ++#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000 ++#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14 ++#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000 ++#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15 ++#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000 ++#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16 ++#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000 ++#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17 ++#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000 ++#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18 ++#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000 ++#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19 ++#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000 ++#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a ++#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000 ++#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b ++#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000 ++#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c ++#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000 ++#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d ++#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY_MASK 0x40000000 ++#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY__SHIFT 0x1e ++#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000 ++#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f ++#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1 ++#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0 ++#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc ++#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 ++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000 ++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12 ++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000 ++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13 ++#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000 ++#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14 ++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000 ++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15 ++#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000 ++#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16 ++#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000 ++#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17 ++#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000 ++#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18 ++#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000 ++#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19 ++#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000 ++#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a ++#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP_MASK 0x8000000 ++#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP__SHIFT 0x1b ++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000 ++#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c ++#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000 ++#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d ++#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 ++#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f ++#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1 ++#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0 ++#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2 ++#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1 ++#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4 ++#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2 ++#define SRBM_READ_ERROR2__READ_VF_MASK 0x800000 ++#define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17 ++#define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000 ++#define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18 ++#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1 ++#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0 ++#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2 ++#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1 ++#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1 ++#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0 ++#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2 ++#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1 ++#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1 ++#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0 ++#define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2 ++#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP_MASK 0x4 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT 0x2 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000 ++#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14 ++#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000 ++#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18 ++#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000 ++#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19 ++#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000 ++#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a ++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000 ++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b ++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000 ++#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c ++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc ++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2 ++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000 ++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13 ++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000 ++#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14 ++#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000 ++#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f ++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff ++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0 ++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000 ++#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10 ++#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff ++#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0 ++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff ++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0 ++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000 ++#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10 ++#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff ++#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0 ++#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf ++#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 ++#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 ++#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 ++#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 ++#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa ++#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f ++#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 ++#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f ++#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 ++#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff ++#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0 ++#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff ++#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0 ++#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff ++#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0 ++#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff ++#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0 ++#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3 ++#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 ++#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff ++#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 ++#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 ++#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 ++#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff ++#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 ++#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 ++#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 ++#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff ++#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 ++#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 ++#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 ++#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff ++#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 ++#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 ++#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 ++#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff ++#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 ++#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 ++#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 ++#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff ++#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 ++#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 ++#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 ++#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff ++#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 ++#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 ++#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 ++#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff ++#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 ++#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 ++#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 ++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff ++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 ++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 ++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff ++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 ++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 ++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff ++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 ++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 ++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff ++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 ++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 ++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff ++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 ++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 ++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff ++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 ++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 ++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff ++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 ++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 ++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff ++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 ++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 ++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff ++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 ++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 ++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff ++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 ++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 ++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff ++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 ++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 ++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff ++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 ++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 ++#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 ++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff ++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 ++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 ++#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 ++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff ++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 ++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 ++#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 ++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff ++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 ++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 ++#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 ++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff ++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 ++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 ++#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 ++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff ++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 ++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 ++#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 ++#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff ++#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 ++#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 ++#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff ++#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 ++#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 ++#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff ++#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 ++#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 ++#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 ++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff ++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 ++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 ++#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 ++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff ++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 ++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 ++#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 ++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff ++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 ++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 ++#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 ++#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff ++#define SRBM_VP8_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 ++#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 ++#define SRBM_VP8_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 ++#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf ++#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0 ++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff ++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0 ++#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00 ++#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8 ++#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000 ++#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10 ++#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000 ++#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d ++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 ++#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e ++#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000 ++#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f ++#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf ++#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0 ++#define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3 ++#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0 ++#define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc ++#define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2 ++#define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0 ++#define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4 ++#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700 ++#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8 ++#define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1 ++#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0 ++#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1 ++#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0 ++#define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff ++#define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000 ++#define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0xffff0 ++#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x4 ++#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 ++#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 ++#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 ++#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 ++#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 ++#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c ++#define DH_TEST__DH_TEST_MASK 0x1 ++#define DH_TEST__DH_TEST__SHIFT 0x0 ++#define KHFS0__RESERVED_MASK 0xffffffff ++#define KHFS0__RESERVED__SHIFT 0x0 ++#define KHFS1__RESERVED_MASK 0xffffffff ++#define KHFS1__RESERVED__SHIFT 0x0 ++#define KHFS2__RESERVED_MASK 0xffffffff ++#define KHFS2__RESERVED__SHIFT 0x0 ++#define KHFS3__RESERVED_MASK 0xffffffff ++#define KHFS3__RESERVED__SHIFT 0x0 ++#define KSESSION0__RESERVED_MASK 0xffffffff ++#define KSESSION0__RESERVED__SHIFT 0x0 ++#define KSESSION1__RESERVED_MASK 0xffffffff ++#define KSESSION1__RESERVED__SHIFT 0x0 ++#define KSESSION2__RESERVED_MASK 0xffffffff ++#define KSESSION2__RESERVED__SHIFT 0x0 ++#define KSESSION3__RESERVED_MASK 0xffffffff ++#define KSESSION3__RESERVED__SHIFT 0x0 ++#define KSIG0__RESERVED_MASK 0xffffffff ++#define KSIG0__RESERVED__SHIFT 0x0 ++#define KSIG1__RESERVED_MASK 0xffffffff ++#define KSIG1__RESERVED__SHIFT 0x0 ++#define KSIG2__RESERVED_MASK 0xffffffff ++#define KSIG2__RESERVED__SHIFT 0x0 ++#define KSIG3__RESERVED_MASK 0xffffffff ++#define KSIG3__RESERVED__SHIFT 0x0 ++#define EXP0__RESERVED_MASK 0xffffffff ++#define EXP0__RESERVED__SHIFT 0x0 ++#define EXP1__RESERVED_MASK 0xffffffff ++#define EXP1__RESERVED__SHIFT 0x0 ++#define EXP2__RESERVED_MASK 0xffffffff ++#define EXP2__RESERVED__SHIFT 0x0 ++#define EXP3__RESERVED_MASK 0xffffffff ++#define EXP3__RESERVED__SHIFT 0x0 ++#define EXP4__RESERVED_MASK 0xffffffff ++#define EXP4__RESERVED__SHIFT 0x0 ++#define EXP5__RESERVED_MASK 0xffffffff ++#define EXP5__RESERVED__SHIFT 0x0 ++#define EXP6__RESERVED_MASK 0xffffffff ++#define EXP6__RESERVED__SHIFT 0x0 ++#define EXP7__RESERVED_MASK 0xffffffff ++#define EXP7__RESERVED__SHIFT 0x0 ++#define LX0__RESERVED_MASK 0xffffffff ++#define LX0__RESERVED__SHIFT 0x0 ++#define LX1__RESERVED_MASK 0xffffffff ++#define LX1__RESERVED__SHIFT 0x0 ++#define LX2__RESERVED_MASK 0xffffffff ++#define LX2__RESERVED__SHIFT 0x0 ++#define LX3__RESERVED_MASK 0xffffffff ++#define LX3__RESERVED__SHIFT 0x0 ++#define CLIENT2_K0__RESERVED_MASK 0xffffffff ++#define CLIENT2_K0__RESERVED__SHIFT 0x0 ++#define CLIENT2_K1__RESERVED_MASK 0xffffffff ++#define CLIENT2_K1__RESERVED__SHIFT 0x0 ++#define CLIENT2_K2__RESERVED_MASK 0xffffffff ++#define CLIENT2_K2__RESERVED__SHIFT 0x0 ++#define CLIENT2_K3__RESERVED_MASK 0xffffffff ++#define CLIENT2_K3__RESERVED__SHIFT 0x0 ++#define CLIENT2_CK0__RESERVED_MASK 0xffffffff ++#define CLIENT2_CK0__RESERVED__SHIFT 0x0 ++#define CLIENT2_CK1__RESERVED_MASK 0xffffffff ++#define CLIENT2_CK1__RESERVED__SHIFT 0x0 ++#define CLIENT2_CK2__RESERVED_MASK 0xffffffff ++#define CLIENT2_CK2__RESERVED__SHIFT 0x0 ++#define CLIENT2_CK3__RESERVED_MASK 0xffffffff ++#define CLIENT2_CK3__RESERVED__SHIFT 0x0 ++#define CLIENT2_CD0__RESERVED_MASK 0xffffffff ++#define CLIENT2_CD0__RESERVED__SHIFT 0x0 ++#define CLIENT2_CD1__RESERVED_MASK 0xffffffff ++#define CLIENT2_CD1__RESERVED__SHIFT 0x0 ++#define CLIENT2_CD2__RESERVED_MASK 0xffffffff ++#define CLIENT2_CD2__RESERVED__SHIFT 0x0 ++#define CLIENT2_CD3__RESERVED_MASK 0xffffffff ++#define CLIENT2_CD3__RESERVED__SHIFT 0x0 ++#define CLIENT2_BM__RESERVED_MASK 0xffffffff ++#define CLIENT2_BM__RESERVED__SHIFT 0x0 ++#define CLIENT2_OFFSET__RESERVED_MASK 0xffffffff ++#define CLIENT2_OFFSET__RESERVED__SHIFT 0x0 ++#define CLIENT2_STATUS__RESERVED_MASK 0xffffffff ++#define CLIENT2_STATUS__RESERVED__SHIFT 0x0 ++#define CLIENT0_K0__RESERVED_MASK 0xffffffff ++#define CLIENT0_K0__RESERVED__SHIFT 0x0 ++#define CLIENT0_K1__RESERVED_MASK 0xffffffff ++#define CLIENT0_K1__RESERVED__SHIFT 0x0 ++#define CLIENT0_K2__RESERVED_MASK 0xffffffff ++#define CLIENT0_K2__RESERVED__SHIFT 0x0 ++#define CLIENT0_K3__RESERVED_MASK 0xffffffff ++#define CLIENT0_K3__RESERVED__SHIFT 0x0 ++#define CLIENT0_CK0__RESERVED_MASK 0xffffffff ++#define CLIENT0_CK0__RESERVED__SHIFT 0x0 ++#define CLIENT0_CK1__RESERVED_MASK 0xffffffff ++#define CLIENT0_CK1__RESERVED__SHIFT 0x0 ++#define CLIENT0_CK2__RESERVED_MASK 0xffffffff ++#define CLIENT0_CK2__RESERVED__SHIFT 0x0 ++#define CLIENT0_CK3__RESERVED_MASK 0xffffffff ++#define CLIENT0_CK3__RESERVED__SHIFT 0x0 ++#define CLIENT0_CD0__RESERVED_MASK 0xffffffff ++#define CLIENT0_CD0__RESERVED__SHIFT 0x0 ++#define CLIENT0_CD1__RESERVED_MASK 0xffffffff ++#define CLIENT0_CD1__RESERVED__SHIFT 0x0 ++#define CLIENT0_CD2__RESERVED_MASK 0xffffffff ++#define CLIENT0_CD2__RESERVED__SHIFT 0x0 ++#define CLIENT0_CD3__RESERVED_MASK 0xffffffff ++#define CLIENT0_CD3__RESERVED__SHIFT 0x0 ++#define CLIENT0_BM__RESERVED_MASK 0xffffffff ++#define CLIENT0_BM__RESERVED__SHIFT 0x0 ++#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffff ++#define CLIENT0_OFFSET__RESERVED__SHIFT 0x0 ++#define CLIENT0_STATUS__RESERVED_MASK 0xffffffff ++#define CLIENT0_STATUS__RESERVED__SHIFT 0x0 ++#define CLIENT1_K0__RESERVED_MASK 0xffffffff ++#define CLIENT1_K0__RESERVED__SHIFT 0x0 ++#define CLIENT1_K1__RESERVED_MASK 0xffffffff ++#define CLIENT1_K1__RESERVED__SHIFT 0x0 ++#define CLIENT1_K2__RESERVED_MASK 0xffffffff ++#define CLIENT1_K2__RESERVED__SHIFT 0x0 ++#define CLIENT1_K3__RESERVED_MASK 0xffffffff ++#define CLIENT1_K3__RESERVED__SHIFT 0x0 ++#define CLIENT1_CK0__RESERVED_MASK 0xffffffff ++#define CLIENT1_CK0__RESERVED__SHIFT 0x0 ++#define CLIENT1_CK1__RESERVED_MASK 0xffffffff ++#define CLIENT1_CK1__RESERVED__SHIFT 0x0 ++#define CLIENT1_CK2__RESERVED_MASK 0xffffffff ++#define CLIENT1_CK2__RESERVED__SHIFT 0x0 ++#define CLIENT1_CK3__RESERVED_MASK 0xffffffff ++#define CLIENT1_CK3__RESERVED__SHIFT 0x0 ++#define CLIENT1_CD0__RESERVED_MASK 0xffffffff ++#define CLIENT1_CD0__RESERVED__SHIFT 0x0 ++#define CLIENT1_CD1__RESERVED_MASK 0xffffffff ++#define CLIENT1_CD1__RESERVED__SHIFT 0x0 ++#define CLIENT1_CD2__RESERVED_MASK 0xffffffff ++#define CLIENT1_CD2__RESERVED__SHIFT 0x0 ++#define CLIENT1_CD3__RESERVED_MASK 0xffffffff ++#define CLIENT1_CD3__RESERVED__SHIFT 0x0 ++#define CLIENT1_BM__RESERVED_MASK 0xffffffff ++#define CLIENT1_BM__RESERVED__SHIFT 0x0 ++#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffff ++#define CLIENT1_OFFSET__RESERVED__SHIFT 0x0 ++#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffff ++#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x0 ++#define KEFUSE0__RESERVED_MASK 0xffffffff ++#define KEFUSE0__RESERVED__SHIFT 0x0 ++#define KEFUSE1__RESERVED_MASK 0xffffffff ++#define KEFUSE1__RESERVED__SHIFT 0x0 ++#define KEFUSE2__RESERVED_MASK 0xffffffff ++#define KEFUSE2__RESERVED__SHIFT 0x0 ++#define KEFUSE3__RESERVED_MASK 0xffffffff ++#define KEFUSE3__RESERVED__SHIFT 0x0 ++#define HFS_SEED0__RESERVED_MASK 0xffffffff ++#define HFS_SEED0__RESERVED__SHIFT 0x0 ++#define HFS_SEED1__RESERVED_MASK 0xffffffff ++#define HFS_SEED1__RESERVED__SHIFT 0x0 ++#define HFS_SEED2__RESERVED_MASK 0xffffffff ++#define HFS_SEED2__RESERVED__SHIFT 0x0 ++#define HFS_SEED3__RESERVED_MASK 0xffffffff ++#define HFS_SEED3__RESERVED__SHIFT 0x0 ++#define RINGOSC_MASK__MASK_MASK 0xffff ++#define RINGOSC_MASK__MASK__SHIFT 0x0 ++#define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffff ++#define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x0 ++#define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffff ++#define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x0 ++#define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffff ++#define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x0 ++#define SPU_PORT_STATUS__RESERVED_MASK 0xffffffff ++#define SPU_PORT_STATUS__RESERVED__SHIFT 0x0 ++#define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffff ++#define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x0 ++#define CLIENT3_K0__RESERVED_MASK 0xffffffff ++#define CLIENT3_K0__RESERVED__SHIFT 0x0 ++#define CLIENT3_K1__RESERVED_MASK 0xffffffff ++#define CLIENT3_K1__RESERVED__SHIFT 0x0 ++#define CLIENT3_K2__RESERVED_MASK 0xffffffff ++#define CLIENT3_K2__RESERVED__SHIFT 0x0 ++#define CLIENT3_K3__RESERVED_MASK 0xffffffff ++#define CLIENT3_K3__RESERVED__SHIFT 0x0 ++#define CLIENT3_CK0__RESERVED_MASK 0xffffffff ++#define CLIENT3_CK0__RESERVED__SHIFT 0x0 ++#define CLIENT3_CK1__RESERVED_MASK 0xffffffff ++#define CLIENT3_CK1__RESERVED__SHIFT 0x0 ++#define CLIENT3_CK2__RESERVED_MASK 0xffffffff ++#define CLIENT3_CK2__RESERVED__SHIFT 0x0 ++#define CLIENT3_CK3__RESERVED_MASK 0xffffffff ++#define CLIENT3_CK3__RESERVED__SHIFT 0x0 ++#define CLIENT3_CD0__RESERVED_MASK 0xffffffff ++#define CLIENT3_CD0__RESERVED__SHIFT 0x0 ++#define CLIENT3_CD1__RESERVED_MASK 0xffffffff ++#define CLIENT3_CD1__RESERVED__SHIFT 0x0 ++#define CLIENT3_CD2__RESERVED_MASK 0xffffffff ++#define CLIENT3_CD2__RESERVED__SHIFT 0x0 ++#define CLIENT3_CD3__RESERVED_MASK 0xffffffff ++#define CLIENT3_CD3__RESERVED__SHIFT 0x0 ++#define CLIENT3_BM__RESERVED_MASK 0xffffffff ++#define CLIENT3_BM__RESERVED__SHIFT 0x0 ++#define CLIENT3_OFFSET__RESERVED_MASK 0xffffffff ++#define CLIENT3_OFFSET__RESERVED__SHIFT 0x0 ++#define CLIENT3_STATUS__RESERVED_MASK 0xffffffff ++#define CLIENT3_STATUS__RESERVED__SHIFT 0x0 ++#define CLIENT4_OFFSET_HI__RESERVED_MASK 0xffffffff ++#define CLIENT4_OFFSET_HI__RESERVED__SHIFT 0x0 ++#define CLIENT4_K0__RESERVED_MASK 0xffffffff ++#define CLIENT4_K0__RESERVED__SHIFT 0x0 ++#define CLIENT4_K1__RESERVED_MASK 0xffffffff ++#define CLIENT4_K1__RESERVED__SHIFT 0x0 ++#define CLIENT4_K2__RESERVED_MASK 0xffffffff ++#define CLIENT4_K2__RESERVED__SHIFT 0x0 ++#define CLIENT4_K3__RESERVED_MASK 0xffffffff ++#define CLIENT4_K3__RESERVED__SHIFT 0x0 ++#define CLIENT4_CK0__RESERVED_MASK 0xffffffff ++#define CLIENT4_CK0__RESERVED__SHIFT 0x0 ++#define CLIENT4_CK1__RESERVED_MASK 0xffffffff ++#define CLIENT4_CK1__RESERVED__SHIFT 0x0 ++#define CLIENT4_CK2__RESERVED_MASK 0xffffffff ++#define CLIENT4_CK2__RESERVED__SHIFT 0x0 ++#define CLIENT4_CK3__RESERVED_MASK 0xffffffff ++#define CLIENT4_CK3__RESERVED__SHIFT 0x0 ++#define CLIENT4_CD0__RESERVED_MASK 0xffffffff ++#define CLIENT4_CD0__RESERVED__SHIFT 0x0 ++#define CLIENT4_CD1__RESERVED_MASK 0xffffffff ++#define CLIENT4_CD1__RESERVED__SHIFT 0x0 ++#define CLIENT4_CD2__RESERVED_MASK 0xffffffff ++#define CLIENT4_CD2__RESERVED__SHIFT 0x0 ++#define CLIENT4_CD3__RESERVED_MASK 0xffffffff ++#define CLIENT4_CD3__RESERVED__SHIFT 0x0 ++#define CLIENT4_BM__RESERVED_MASK 0xffffffff ++#define CLIENT4_BM__RESERVED__SHIFT 0x0 ++#define CLIENT4_OFFSET__RESERVED_MASK 0xffffffff ++#define CLIENT4_OFFSET__RESERVED__SHIFT 0x0 ++#define CLIENT4_STATUS__RESERVED_MASK 0xffffffff ++#define CLIENT4_STATUS__RESERVED__SHIFT 0x0 ++#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0xff ++#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x0 ++#define SDMA0_UCODE_ADDR__VALUE_MASK 0x1fff ++#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 ++#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff ++#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 ++#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 ++#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 ++#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200 ++#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 ++#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400 ++#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa ++#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800 ++#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb ++#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000 ++#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc ++#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf ++#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 ++#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1 ++#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 ++#define SDMA0_CNTL__ATC_L1_ENABLE_MASK 0x2 ++#define SDMA0_CNTL__ATC_L1_ENABLE__SHIFT 0x1 ++#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 ++#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 ++#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8 ++#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 ++#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 ++#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20 ++#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 ++#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 ++#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb ++#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000 ++#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 ++#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 ++#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 ++#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 ++#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 ++#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 ++#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c ++#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 ++#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d ++#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 ++#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e ++#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 ++#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 ++#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 ++#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 ++#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 ++#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 ++#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 ++#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 ++#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 ++#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 ++#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 ++#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 ++#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 ++#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a ++#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 ++#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c ++#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 ++#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e ++#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 ++#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 ++#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7 ++#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0 ++#define SDMA0_HASH__BANK_BITS_MASK 0x70 ++#define SDMA0_HASH__BANK_BITS__SHIFT 0x4 ++#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700 ++#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 ++#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000 ++#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc ++#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff ++#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 ++#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc ++#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 ++#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc ++#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 ++#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff ++#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 ++#define SDMA0_STATUS_REG__IDLE_MASK 0x1 ++#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 ++#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2 ++#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 ++#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4 ++#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 ++#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8 ++#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 ++#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10 ++#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 ++#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20 ++#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 ++#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40 ++#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 ++#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80 ++#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 ++#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100 ++#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 ++#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200 ++#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 ++#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400 ++#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa ++#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 ++#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb ++#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000 ++#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc ++#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000 ++#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd ++#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000 ++#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe ++#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 ++#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf ++#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 ++#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 ++#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 ++#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 ++#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 ++#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 ++#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000 ++#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 ++#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 ++#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 ++#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 ++#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 ++#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 ++#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 ++#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 ++#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 ++#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000 ++#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a ++#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 ++#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b ++#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 ++#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c ++#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000 ++#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e ++#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 ++#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f ++#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 ++#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 ++#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2 ++#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 ++#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 ++#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 ++#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 ++#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 ++#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 ++#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 ++#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20 ++#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 ++#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40 ++#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 ++#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 ++#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 ++#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 ++#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa ++#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 ++#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd ++#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 ++#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe ++#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000 ++#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 ++#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000 ++#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 ++#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x3 ++#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 ++#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 ++#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 ++#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 ++#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 ++#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc ++#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 ++#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 ++#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 ++#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 ++#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 ++#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 ++#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa ++#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff ++#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 ++#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff ++#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 ++#define SDMA0_F32_CNTL__HALT_MASK 0x1 ++#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 ++#define SDMA0_F32_CNTL__STEP_MASK 0x2 ++#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 ++#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc ++#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 ++#define SDMA0_FREEZE__FREEZE_MASK 0x10 ++#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 ++#define SDMA0_FREEZE__FROZEN_MASK 0x20 ++#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 ++#define SDMA0_FREEZE__F32_FREEZE_MASK 0x40 ++#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 ++#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf ++#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 ++#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 ++#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 ++#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000 ++#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e ++#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf ++#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 ++#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00 ++#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 ++#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000 ++#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e ++#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1 ++#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0 ++#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2 ++#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1 ++#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4 ++#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2 ++#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30 ++#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 ++#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40 ++#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6 ++#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80 ++#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7 ++#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00 ++#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8 ++#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000 ++#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14 ++#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff ++#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 ++#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 ++#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 ++#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200 ++#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 ++#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400 ++#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa ++#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800 ++#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb ++#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000 ++#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc ++#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000 ++#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd ++#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 ++#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b ++#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 ++#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c ++#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff ++#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 ++#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff ++#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 ++#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2 ++#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 ++#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 ++#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 ++#define SDMA0_VM_CNTL__CMD_MASK 0xf ++#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 ++#define SDMA0_VM_CTX_LO__ADDR_MASK 0xfffffffc ++#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 ++#define SDMA0_VM_CTX_HI__ADDR_MASK 0xffffffff ++#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 ++#define SDMA0_STATUS2_REG__ID_MASK 0x3 ++#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 ++#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xffc ++#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 ++#define SDMA0_STATUS2_REG__CURRENT_FCN_IDLE_MASK 0xc000 ++#define SDMA0_STATUS2_REG__CURRENT_FCN_IDLE__SHIFT 0xe ++#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000 ++#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 ++#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0xf ++#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000 ++#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x1 ++#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 ++#define SDMA0_VM_CTX_CNTL__VMID_MASK 0xf0 ++#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 ++#define SDMA0_VIRT_RESET_REQ__VF_MASK 0xffff ++#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000 ++#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x1 ++#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 ++#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff ++#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 ++#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 ++#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 ++#define SDMA0_ID__DEVICE_ID_MASK 0xff ++#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 ++#define SDMA0_VERSION__VALUE_MASK 0xffff ++#define SDMA0_VERSION__VALUE__SHIFT 0x0 ++#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff ++#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 ++#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000 ++#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f ++#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff ++#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 ++#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff ++#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 ++#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0xffff ++#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x0 ++#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xffff0000 ++#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x10 ++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL_MASK 0x1 ++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL__SHIFT 0x0 ++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT_MASK 0x2 ++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x1 ++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT_MASK 0x4 ++#define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x2 ++#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8 ++#define SDMA0_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x1 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x2 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x4 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x8 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x10 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x4 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x20 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x100 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x200 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x400 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x800 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x1000 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x2000 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x4000 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x8000 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x10000 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x20000 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x40000 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x80000 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR_MASK 0x80 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_VIRTUAL_ADDR__SHIFT 0x7 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL_MASK 0x100 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_APE1_CNTL__SHIFT 0x8 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x200 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x400 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa ++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1_MASK 0x800 ++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG1__SHIFT 0xb ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x1000 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x2000 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd ++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x4000 ++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x8000 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x10000 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x20000 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 ++#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000 ++#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x1 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x2 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x4 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x8 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x10 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x20 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x40 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x6 ++#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xffffff80 ++#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x1 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x2 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x4 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x8 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x3 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x4 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x5 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG_MASK 0x40 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_TILING_CONFIG__SHIFT 0x6 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH_MASK 0x80 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_HASH__SHIFT 0x7 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH_MASK 0x400 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_RB_RPTR_FETCH__SHIFT 0xa ++#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH_MASK 0x800 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_IB_OFFSET_FETCH__SHIFT 0xb ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM_MASK 0x1000 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PROGRAM__SHIFT 0xc ++#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG_MASK 0x2000 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS_REG__SHIFT 0xd ++#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG_MASK 0x4000 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_STATUS1_REG__SHIFT 0xe ++#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL_MASK 0x8000 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_RD_BURST_CNTL__SHIFT 0xf ++#define SDMA0_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000 ++#define SDMA0_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10 ++#define SDMA0_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000 ++#define SDMA0_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL_MASK 0x40000 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_F32_CNTL__SHIFT 0x12 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE_MASK 0x80000 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_FREEZE__SHIFT 0x13 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM_MASK 0x100000 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE0_QUANTUM__SHIFT 0x14 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM_MASK 0x200000 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PHASE1_QUANTUM__SHIFT 0x15 ++#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING_MASK 0x400000 ++#define SDMA0_PUB_REG_TYPE0__SDMA_POWER_GATING__SHIFT 0x16 ++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG_MASK 0x800000 ++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_CONFIG__SHIFT 0x17 ++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE_MASK 0x1000000 ++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_WRITE__SHIFT 0x18 ++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ_MASK 0x2000000 ++#define SDMA0_PUB_REG_TYPE0__SDMA_PGFSM_READ__SHIFT 0x19 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG_MASK 0x4000000 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_EDC_CONFIG__SHIFT 0x1a ++#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD_MASK 0x8000000 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_BA_THRESHOLD__SHIFT 0x1b ++#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID_MASK 0x10000000 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_DEVICE_ID__SHIFT 0x1c ++#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION_MASK 0x20000000 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_VERSION__SHIFT 0x1d ++#define SDMA0_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000 ++#define SDMA0_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL_MASK 0x1 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL__SHIFT 0x0 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO_MASK 0x2 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO__SHIFT 0x1 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI_MASK 0x4 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_HI__SHIFT 0x2 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x8 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x3 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID_MASK 0x10 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ACTIVE_FCN_ID__SHIFT 0x4 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL_MASK 0x20 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_CNTL__SHIFT 0x5 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ_MASK 0x40 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VIRT_RESET_REQ__SHIFT 0x6 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE_MASK 0x80 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VF_ENABLE__SHIFT 0x7 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x100 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x8 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x200 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x9 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x400 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0xa ++#define SDMA0_PUB_REG_TYPE1__RESERVED_MASK 0xfffff800 ++#define SDMA0_PUB_REG_TYPE1__RESERVED__SHIFT 0xb ++#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 ++#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e ++#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 ++#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 ++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 ++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 ++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 ++#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 ++#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff ++#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff ++#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc ++#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc ++#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 ++#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 ++#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 ++#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 ++#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc ++#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc ++#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 ++#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff ++#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff ++#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff ++#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 ++#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 ++#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 ++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 ++#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 ++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 ++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 ++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 ++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA0_GFX_DOORBELL__OFFSET_MASK 0x1fffff ++#define SDMA0_GFX_DOORBELL__OFFSET__SHIFT 0x0 ++#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000 ++#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000 ++#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 ++#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 ++#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 ++#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 ++#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 ++#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 ++#define SDMA0_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2 ++#define SDMA0_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1 ++#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 ++#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 ++#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 ++#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 ++#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 ++#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e ++#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff ++#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0 ++#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 ++#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 ++#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1 ++#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc ++#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff ++#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 ++#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff ++#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 ++#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff ++#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff ++#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff ++#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff ++#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff ++#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff ++#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff ++#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1 ++#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2 ++#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 ++#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 ++#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 ++#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e ++#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 ++#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 ++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 ++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 ++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 ++#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 ++#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff ++#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff ++#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc ++#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc ++#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 ++#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 ++#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 ++#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 ++#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc ++#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc ++#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 ++#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff ++#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff ++#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff ++#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 ++#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 ++#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 ++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 ++#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 ++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 ++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 ++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 ++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff ++#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000 ++#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 ++#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 ++#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 ++#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2 ++#define SDMA0_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1 ++#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 ++#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 ++#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 ++#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 ++#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 ++#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e ++#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff ++#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0 ++#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 ++#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 ++#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 ++#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc ++#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff ++#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 ++#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff ++#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 ++#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff ++#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff ++#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff ++#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff ++#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff ++#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff ++#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff ++#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1 ++#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2 ++#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 ++#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 ++#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 ++#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e ++#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 ++#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 ++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 ++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 ++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 ++#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 ++#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff ++#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff ++#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc ++#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc ++#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 ++#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 ++#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 ++#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 ++#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc ++#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc ++#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 ++#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff ++#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff ++#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff ++#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 ++#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 ++#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 ++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 ++#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 ++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 ++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 ++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 ++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff ++#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000 ++#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 ++#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 ++#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 ++#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2 ++#define SDMA0_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1 ++#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 ++#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 ++#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 ++#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 ++#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 ++#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e ++#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff ++#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0 ++#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 ++#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 ++#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 ++#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc ++#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff ++#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 ++#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff ++#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 ++#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff ++#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff ++#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff ++#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff ++#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff ++#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff ++#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff ++#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1 ++#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2 ++#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 ++#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 ++#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA1_UCODE_ADDR__VALUE_MASK 0x1fff ++#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 ++#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff ++#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 ++#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 ++#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 ++#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x200 ++#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 ++#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x400 ++#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa ++#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x800 ++#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb ++#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x3ff000 ++#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc ++#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf ++#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 ++#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1 ++#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 ++#define SDMA1_CNTL__ATC_L1_ENABLE_MASK 0x2 ++#define SDMA1_CNTL__ATC_L1_ENABLE__SHIFT 0x1 ++#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 ++#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 ++#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8 ++#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 ++#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 ++#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x20 ++#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 ++#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 ++#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb ++#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x20000 ++#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 ++#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 ++#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 ++#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 ++#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 ++#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 ++#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c ++#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 ++#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d ++#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 ++#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e ++#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 ++#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 ++#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 ++#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 ++#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 ++#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 ++#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 ++#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 ++#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 ++#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 ++#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 ++#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 ++#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 ++#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a ++#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 ++#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c ++#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 ++#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e ++#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 ++#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 ++#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7 ++#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0 ++#define SDMA1_HASH__BANK_BITS_MASK 0x70 ++#define SDMA1_HASH__BANK_BITS__SHIFT 0x4 ++#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700 ++#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 ++#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000 ++#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc ++#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff ++#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 ++#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc ++#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 ++#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc ++#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 ++#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff ++#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 ++#define SDMA1_STATUS_REG__IDLE_MASK 0x1 ++#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 ++#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2 ++#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 ++#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4 ++#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 ++#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8 ++#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 ++#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10 ++#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 ++#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20 ++#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 ++#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40 ++#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 ++#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80 ++#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 ++#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100 ++#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 ++#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200 ++#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 ++#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400 ++#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa ++#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 ++#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb ++#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000 ++#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc ++#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000 ++#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd ++#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000 ++#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe ++#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 ++#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf ++#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 ++#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 ++#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 ++#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 ++#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 ++#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 ++#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000 ++#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 ++#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 ++#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 ++#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 ++#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 ++#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 ++#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 ++#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 ++#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 ++#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000 ++#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a ++#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 ++#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b ++#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 ++#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c ++#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000 ++#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e ++#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 ++#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f ++#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 ++#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 ++#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2 ++#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 ++#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 ++#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 ++#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 ++#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 ++#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 ++#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 ++#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20 ++#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 ++#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40 ++#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 ++#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 ++#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 ++#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 ++#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa ++#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 ++#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd ++#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 ++#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe ++#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000 ++#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 ++#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000 ++#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 ++#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x3 ++#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 ++#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 ++#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 ++#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 ++#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 ++#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc ++#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 ++#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 ++#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 ++#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 ++#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 ++#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 ++#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa ++#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff ++#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 ++#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff ++#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 ++#define SDMA1_F32_CNTL__HALT_MASK 0x1 ++#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 ++#define SDMA1_F32_CNTL__STEP_MASK 0x2 ++#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 ++#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc ++#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 ++#define SDMA1_FREEZE__FREEZE_MASK 0x10 ++#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 ++#define SDMA1_FREEZE__FROZEN_MASK 0x20 ++#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 ++#define SDMA1_FREEZE__F32_FREEZE_MASK 0x40 ++#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 ++#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf ++#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 ++#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00 ++#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 ++#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000 ++#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e ++#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf ++#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 ++#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00 ++#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 ++#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000 ++#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e ++#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2 ++#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 ++#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 ++#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 ++#define SDMA1_VM_CNTL__CMD_MASK 0xf ++#define SDMA1_VM_CNTL__CMD__SHIFT 0x0 ++#define SDMA1_VM_CTX_LO__ADDR_MASK 0xfffffffc ++#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 ++#define SDMA1_VM_CTX_HI__ADDR_MASK 0xffffffff ++#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 ++#define SDMA1_STATUS2_REG__ID_MASK 0x3 ++#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 ++#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xffc ++#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 ++#define SDMA1_STATUS2_REG__CURRENT_FCN_IDLE_MASK 0xc000 ++#define SDMA1_STATUS2_REG__CURRENT_FCN_IDLE__SHIFT 0xe ++#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000 ++#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 ++#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0xf ++#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000 ++#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x1 ++#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 ++#define SDMA1_VM_CTX_CNTL__VMID_MASK 0xf0 ++#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 ++#define SDMA1_VIRT_RESET_REQ__VF_MASK 0xffff ++#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000 ++#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x1 ++#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 ++#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff ++#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 ++#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 ++#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 ++#define SDMA1_ID__DEVICE_ID_MASK 0xff ++#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 ++#define SDMA1_VERSION__VALUE_MASK 0xffff ++#define SDMA1_VERSION__VALUE__SHIFT 0x0 ++#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7fffffff ++#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 ++#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000 ++#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f ++#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xffffffff ++#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 ++#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xffffffff ++#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 ++#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0xffff ++#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x0 ++#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xffff0000 ++#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x10 ++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL_MASK 0x1 ++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL__SHIFT 0x0 ++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT_MASK 0x2 ++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x1 ++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT_MASK 0x4 ++#define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x2 ++#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3_MASK 0xfffffff8 ++#define SDMA1_PERF_REG_TYPE0__RESERVED_31_3__SHIFT 0x3 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x1 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x2 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x4 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x8 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x10 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x4 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x20 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x5 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x40 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x6 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x80 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x7 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x100 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x200 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x400 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x800 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x1000 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x2000 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x4000 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x8000 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x10000 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x20000 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x40000 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x80000 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 ++#define SDMA1_CONTEXT_REG_TYPE0__RESERVED_MASK 0xfff00000 ++#define SDMA1_CONTEXT_REG_TYPE0__RESERVED__SHIFT 0x14 ++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0_MASK 0x7f ++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG0__SHIFT 0x0 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR_MASK 0x80 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_VIRTUAL_ADDR__SHIFT 0x7 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL_MASK 0x100 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_APE1_CNTL__SHIFT 0x8 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x200 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x400 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa ++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x800 ++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xb ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x1000 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x2000 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd ++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3_MASK 0x4000 ++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG3__SHIFT 0xe ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x8000 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x10000 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x20000 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 ++#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xfffc0000 ++#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x1 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x2 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x4 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x8 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x10 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x20 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x40 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x6 ++#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xffffff80 ++#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x1 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x2 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x4 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x2 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x8 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x3 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x4 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x5 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG_MASK 0x40 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_TILING_CONFIG__SHIFT 0x6 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH_MASK 0x80 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_HASH__SHIFT 0x7 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x200 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x9 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH_MASK 0x400 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_RB_RPTR_FETCH__SHIFT 0xa ++#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH_MASK 0x800 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_IB_OFFSET_FETCH__SHIFT 0xb ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM_MASK 0x1000 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PROGRAM__SHIFT 0xc ++#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG_MASK 0x2000 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS_REG__SHIFT 0xd ++#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG_MASK 0x4000 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_STATUS1_REG__SHIFT 0xe ++#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL_MASK 0x8000 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_RD_BURST_CNTL__SHIFT 0xf ++#define SDMA1_PUB_REG_TYPE0__RESERVED_16_MASK 0x10000 ++#define SDMA1_PUB_REG_TYPE0__RESERVED_16__SHIFT 0x10 ++#define SDMA1_PUB_REG_TYPE0__RESERVED_17_MASK 0x20000 ++#define SDMA1_PUB_REG_TYPE0__RESERVED_17__SHIFT 0x11 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL_MASK 0x40000 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_F32_CNTL__SHIFT 0x12 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE_MASK 0x80000 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_FREEZE__SHIFT 0x13 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM_MASK 0x100000 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE0_QUANTUM__SHIFT 0x14 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM_MASK 0x200000 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PHASE1_QUANTUM__SHIFT 0x15 ++#define SDMA1_PUB_REG_TYPE0__VOID_REG0_MASK 0x3c00000 ++#define SDMA1_PUB_REG_TYPE0__VOID_REG0__SHIFT 0x16 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG_MASK 0x4000000 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_EDC_CONFIG__SHIFT 0x1a ++#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD_MASK 0x8000000 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_BA_THRESHOLD__SHIFT 0x1b ++#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID_MASK 0x10000000 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_DEVICE_ID__SHIFT 0x1c ++#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION_MASK 0x20000000 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_VERSION__SHIFT 0x1d ++#define SDMA1_PUB_REG_TYPE0__RESERVED_MASK 0xc0000000 ++#define SDMA1_PUB_REG_TYPE0__RESERVED__SHIFT 0x1e ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL_MASK 0x1 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL__SHIFT 0x0 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO_MASK 0x2 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO__SHIFT 0x1 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI_MASK 0x4 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_HI__SHIFT 0x2 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x8 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x3 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID_MASK 0x10 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ACTIVE_FCN_ID__SHIFT 0x4 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL_MASK 0x20 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_CNTL__SHIFT 0x5 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ_MASK 0x40 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VIRT_RESET_REQ__SHIFT 0x6 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE_MASK 0x80 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VF_ENABLE__SHIFT 0x7 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x100 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x8 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x200 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x9 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x400 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0xa ++#define SDMA1_PUB_REG_TYPE1__RESERVED_MASK 0xfffff800 ++#define SDMA1_PUB_REG_TYPE1__RESERVED__SHIFT 0xb ++#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 ++#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e ++#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 ++#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 ++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 ++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 ++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 ++#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 ++#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff ++#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff ++#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc ++#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc ++#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 ++#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 ++#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 ++#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 ++#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc ++#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc ++#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 ++#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff ++#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff ++#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff ++#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 ++#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 ++#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 ++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 ++#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 ++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 ++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 ++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 ++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA1_GFX_DOORBELL__OFFSET_MASK 0x1fffff ++#define SDMA1_GFX_DOORBELL__OFFSET__SHIFT 0x0 ++#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000 ++#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000 ++#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 ++#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 ++#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 ++#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 ++#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 ++#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 ++#define SDMA1_GFX_VIRTUAL_ADDR__INVAL_MASK 0x2 ++#define SDMA1_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1 ++#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 ++#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 ++#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 ++#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 ++#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 ++#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e ++#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff ++#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0 ++#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 ++#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 ++#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1 ++#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xfffffffc ++#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff ++#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 ++#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff ++#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 ++#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff ++#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xffffffff ++#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xffffffff ++#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xffffffff ++#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xffffffff ++#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xffffffff ++#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xffffffff ++#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1 ++#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x2 ++#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 ++#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 ++#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 ++#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e ++#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 ++#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 ++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 ++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 ++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 ++#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 ++#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff ++#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff ++#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc ++#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc ++#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 ++#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 ++#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 ++#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 ++#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc ++#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc ++#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 ++#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff ++#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff ++#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff ++#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 ++#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 ++#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 ++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 ++#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 ++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 ++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 ++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 ++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff ++#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000 ++#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 ++#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 ++#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 ++#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL_MASK 0x2 ++#define SDMA1_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1 ++#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 ++#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 ++#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 ++#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 ++#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 ++#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e ++#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff ++#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0 ++#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 ++#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 ++#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 ++#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc ++#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff ++#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 ++#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff ++#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 ++#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff ++#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xffffffff ++#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xffffffff ++#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xffffffff ++#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xffffffff ++#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xffffffff ++#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xffffffff ++#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1 ++#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x2 ++#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 ++#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 ++#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 ++#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e ++#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 ++#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 ++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 ++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 ++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 ++#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 ++#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff ++#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff ++#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc ++#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc ++#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 ++#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 ++#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 ++#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 ++#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc ++#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc ++#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 ++#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff ++#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff ++#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff ++#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 ++#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 ++#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 ++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 ++#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 ++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 ++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 ++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 ++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff ++#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000 ++#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 ++#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 ++#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 ++#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL_MASK 0x2 ++#define SDMA1_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1 ++#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 ++#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 ++#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 ++#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 ++#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 ++#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e ++#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff ++#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0 ++#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 ++#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 ++#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 ++#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc ++#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff ++#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 ++#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc ++#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff ++#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff ++#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 ++#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff ++#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xffffffff ++#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xffffffff ++#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xffffffff ++#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xffffffff ++#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xffffffff ++#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xffffffff ++#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1 ++#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x2 ++#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 ++#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x100 ++#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7 ++#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0 ++#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8 ++#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3 ++#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600 ++#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 ++#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800 ++#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb ++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000 ++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 ++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000 ++#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 ++#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000 ++#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16 ++#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000 ++#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17 ++#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000 ++#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18 ++#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000 ++#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d ++#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000 ++#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e ++#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000 ++#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f ++#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff ++#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0 ++#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1 ++#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0 ++#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e ++#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1 ++#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60 ++#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5 ++#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380 ++#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7 ++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00 ++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa ++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000 ++#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd ++#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000 ++#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf ++#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000 ++#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10 ++#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000 ++#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11 ++#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000 ++#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14 ++#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000 ++#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16 ++#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000 ++#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18 ++#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000 ++#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a ++#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000 ++#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c ++#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000 ++#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f ++#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff ++#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0 ++#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800 ++#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb ++#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1 ++#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 ++#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2 ++#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 ++#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1 ++#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 ++#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2 ++#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 ++#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff ++#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 ++#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 ++#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0 ++#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f ++#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 ++#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe ++#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1 ++#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30 ++#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4 ++#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0 ++#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6 ++#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700 ++#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8 ++#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800 ++#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb ++#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000 ++#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe ++#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7 ++#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0 ++#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18 ++#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3 ++#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff ++#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 ++#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00 ++#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 ++#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7 ++#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 ++#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 ++#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 ++#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 ++#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 ++#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 ++#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc ++#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 ++#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 ++#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 ++#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 ++#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 ++#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 ++#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 ++#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c ++#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 ++#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e ++#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1 ++#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 ++#define HDP_MISC_CNTL__VM_ID_MASK 0x1e ++#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1 ++#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20 ++#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 ++#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40 ++#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 ++#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780 ++#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7 ++#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800 ++#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb ++#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000 ++#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc ++#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000 ++#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd ++#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000 ++#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13 ++#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000 ++#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14 ++#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000 ++#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 ++#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE_MASK 0x400000 ++#define HDP_MISC_CNTL__LEGACY_TILING_ENABLE__SHIFT 0x16 ++#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE_MASK 0x800000 ++#define HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE__SHIFT 0x17 ++#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1 ++#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 ++#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e ++#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1 ++#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80 ++#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 ++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7 ++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0 ++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38 ++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3 ++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0 ++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6 ++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00 ++#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9 ++#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000 ++#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b ++#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1 ++#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 ++#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2 ++#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 ++#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c ++#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 ++#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40 ++#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 ++#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80 ++#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 ++#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00 ++#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 ++#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000 ++#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe ++#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000 ++#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf ++#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x10000 ++#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 ++#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x1e0000 ++#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 ++#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff ++#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 ++#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1 ++#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 ++#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2 ++#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 ++#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4 ++#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 ++#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8 ++#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 ++#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff ++#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 ++#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff ++#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 ++#define HDP_VF_ENABLE__VF_EN_MASK 0x1 ++#define HDP_VF_ENABLE__VF_EN__SHIFT 0x0 ++#define HDP_VF_ENABLE__VF_NUM_MASK 0xffff0000 ++#define HDP_VF_ENABLE__VF_NUM__SHIFT 0x10 ++#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff ++#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000 ++#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 ++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff ++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 ++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000 ++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 ++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000 ++#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 ++#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 ++#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff ++#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 ++#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff ++#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 ++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf ++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 ++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30 ++#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 ++#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff ++#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 ++#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1 ++#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 ++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe ++#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1 ++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000 ++#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15 ++#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1 ++#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 ++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe ++#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1 ++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000 ++#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15 ++#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1 ++#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 ++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe ++#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1 ++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000 ++#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15 ++#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1 ++#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 ++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe ++#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1 ++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000 ++#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15 ++#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1 ++#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 ++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe ++#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1 ++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000 ++#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15 ++#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1 ++#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 ++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe ++#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1 ++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000 ++#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15 ++#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1 ++#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 ++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe ++#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1 ++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000 ++#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15 ++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1 ++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0 ++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6 ++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1 ++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8 ++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3 ++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0 ++#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000 ++#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b ++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1 ++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 ++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6 ++#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 ++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1 ++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0 ++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6 ++#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1 ++#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18 ++#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3 ++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f ++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 ++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0 ++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 ++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000 ++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc ++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000 ++#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd ++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f ++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0 ++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40 ++#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6 ++#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80 ++#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7 ++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf ++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0 ++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0 ++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4 ++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000 ++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc ++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000 ++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e ++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000 ++#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f ++#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff ++#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 ++#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000 ++#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 ++#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000 ++#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 ++#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff ++#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 ++#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000 ++#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 ++#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000 ++#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 ++#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff ++#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 ++#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000 ++#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 ++#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000 ++#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 ++#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff ++#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 ++#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000 ++#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 ++#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000 ++#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 ++#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff ++#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 ++#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000 ++#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 ++#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000 ++#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 ++#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff ++#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 ++#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000 ++#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 ++#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000 ++#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 ++#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff ++#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 ++#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000 ++#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 ++#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000 ++#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 ++#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff ++#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 ++#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000 ++#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 ++#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000 ++#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 ++#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff ++#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 ++#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff ++#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 ++#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff ++#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 ++#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff ++#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 ++#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000 ++#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 ++#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff ++#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 ++#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00 ++#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 ++#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000 ++#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 ++#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000 ++#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 ++#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff ++#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0 ++#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000 ++#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10 ++#define HDP_XDP_DBG_DATA__STS_MASK 0xffff ++#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0 ++#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000 ++#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10 ++#define HDP_XDP_DBG_MASK__STS_MASK 0xffff ++#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0 ++#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000 ++#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10 ++#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf ++#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 ++#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0 ++#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 ++#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00 ++#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 ++#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000 ++#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc ++#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000 ++#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 ++#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000 ++#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 ++#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000 ++#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 ++#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000 ++#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c ++ ++#endif /* OSS_3_0_SH_MASK_H */ +-- +cgit v0.10.2 + |