diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/0013-yocto-amd-drm-amdgpu-add-amdgpu-uapi-header.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/0013-yocto-amd-drm-amdgpu-add-amdgpu-uapi-header.patch | 9860 |
1 files changed, 9860 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0013-yocto-amd-drm-amdgpu-add-amdgpu-uapi-header.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0013-yocto-amd-drm-amdgpu-add-amdgpu-uapi-header.patch new file mode 100644 index 00000000..7909ea24 --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/0013-yocto-amd-drm-amdgpu-add-amdgpu-uapi-header.patch @@ -0,0 +1,9860 @@ +From 3d1676c0d334981b60e7ae14a1d968e64ae73711 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 16 Apr 2015 15:24:40 -0400 +Subject: drm/amdgpu: add GMC 8.2 register headers + +These are register headers for the GMC (Graphics Memory Controller) +block on the GPU. + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com> + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h +new file mode 100644 +index 0000000..06ef7d9 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_d.h +@@ -0,0 +1,910 @@ ++/* ++ * GMC_8_2 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef GMC_8_2_D_H ++#define GMC_8_2_D_H ++ ++#define mmMC_CONFIG 0x800 ++#define mmMC_ARB_ATOMIC 0x9be ++#define mmMC_ARB_AGE_CNTL 0x9bf ++#define mmMC_ARB_RET_CREDITS2 0x9c0 ++#define mmMC_ARB_FED_CNTL 0x9c1 ++#define mmMC_ARB_GECC2_STATUS 0x9c2 ++#define mmMC_ARB_GECC2_MISC 0x9c3 ++#define mmMC_ARB_GECC2_DEBUG 0x9c4 ++#define mmMC_ARB_GECC2_DEBUG2 0x9c5 ++#define mmMC_ARB_PERF_CID 0x9c6 ++#define mmMC_ARB_SNOOP 0x9c7 ++#define mmMC_ARB_GRUB 0x9c8 ++#define mmMC_ARB_GECC2 0x9c9 ++#define mmMC_ARB_GECC2_CLI 0x9ca ++#define mmMC_ARB_ADDR_SWIZ0 0x9cb ++#define mmMC_ARB_ADDR_SWIZ1 0x9cc ++#define mmMC_ARB_MISC3 0x9cd ++#define mmMC_ARB_GRUB_PROMOTE 0x9ce ++#define mmMC_ARB_RTT_DATA 0x9cf ++#define mmMC_ARB_RTT_CNTL0 0x9d0 ++#define mmMC_ARB_RTT_CNTL1 0x9d1 ++#define mmMC_ARB_RTT_CNTL2 0x9d2 ++#define mmMC_ARB_RTT_DEBUG 0x9d3 ++#define mmMC_ARB_CAC_CNTL 0x9d4 ++#define mmMC_ARB_MISC2 0x9d5 ++#define mmMC_ARB_MISC 0x9d6 ++#define mmMC_ARB_BANKMAP 0x9d7 ++#define mmMC_ARB_RAMCFG 0x9d8 ++#define mmMC_ARB_POP 0x9d9 ++#define mmMC_ARB_MINCLKS 0x9da ++#define mmMC_ARB_SQM_CNTL 0x9db ++#define mmMC_ARB_ADDR_HASH 0x9dc ++#define mmMC_ARB_DRAM_TIMING 0x9dd ++#define mmMC_ARB_DRAM_TIMING2 0x9de ++#define mmMC_ARB_WTM_CNTL_RD 0x9df ++#define mmMC_ARB_WTM_CNTL_WR 0x9e0 ++#define mmMC_ARB_WTM_GRPWT_RD 0x9e1 ++#define mmMC_ARB_WTM_GRPWT_WR 0x9e2 ++#define mmMC_ARB_TM_CNTL_RD 0x9e3 ++#define mmMC_ARB_TM_CNTL_WR 0x9e4 ++#define mmMC_ARB_LAZY0_RD 0x9e5 ++#define mmMC_ARB_LAZY0_WR 0x9e6 ++#define mmMC_ARB_LAZY1_RD 0x9e7 ++#define mmMC_ARB_LAZY1_WR 0x9e8 ++#define mmMC_ARB_AGE_RD 0x9e9 ++#define mmMC_ARB_AGE_WR 0x9ea ++#define mmMC_ARB_RFSH_CNTL 0x9eb ++#define mmMC_ARB_RFSH_RATE 0x9ec ++#define mmMC_ARB_PM_CNTL 0x9ed ++#define mmMC_ARB_GDEC_RD_CNTL 0x9ee ++#define mmMC_ARB_GDEC_WR_CNTL 0x9ef ++#define mmMC_ARB_LM_RD 0x9f0 ++#define mmMC_ARB_LM_WR 0x9f1 ++#define mmMC_ARB_REMREQ 0x9f2 ++#define mmMC_ARB_REPLAY 0x9f3 ++#define mmMC_ARB_RET_CREDITS_RD 0x9f4 ++#define mmMC_ARB_RET_CREDITS_WR 0x9f5 ++#define mmMC_ARB_MAX_LAT_CID 0x9f6 ++#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7 ++#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8 ++#define mmMC_ARB_GRUB_REALTIME_RD 0x9f9 ++#define mmMC_ARB_CG 0x9fa ++#define mmMC_ARB_GRUB_REALTIME_WR 0x9fb ++#define mmMC_ARB_DRAM_TIMING_1 0x9fc ++#define mmMC_ARB_BUSY_STATUS 0x9fd ++#define mmMC_ARB_DRAM_TIMING2_1 0x9ff ++#define mmMC_ARB_GRUB2 0xa01 ++#define mmMC_ARB_BURST_TIME 0xa02 ++#define mmMC_CITF_XTRA_ENABLE 0x96d ++#define mmCC_MC_MAX_CHANNEL 0x96e ++#define mmMC_CG_CONFIG 0x96f ++#define mmMC_CITF_CNTL 0x970 ++#define mmMC_CITF_CREDITS_VM 0x971 ++#define mmMC_CITF_CREDITS_ARB_RD 0x972 ++#define mmMC_CITF_CREDITS_ARB_WR 0x973 ++#define mmMC_CITF_DAGB_CNTL 0x974 ++#define mmMC_CITF_INT_CREDITS 0x975 ++#define mmMC_CITF_RET_MODE 0x976 ++#define mmMC_CITF_DAGB_DLY 0x977 ++#define mmMC_RD_GRP_EXT 0x978 ++#define mmMC_WR_GRP_EXT 0x979 ++#define mmMC_CITF_REMREQ 0x97a ++#define mmMC_WR_TC0 0x97b ++#define mmMC_WR_TC1 0x97c ++#define mmMC_CITF_INT_CREDITS_WR 0x97d ++#define mmMC_CITF_CREDITS_ARB_RD2 0x97e ++#define mmMC_CITF_WTM_RD_CNTL 0x97f ++#define mmMC_CITF_WTM_WR_CNTL 0x980 ++#define mmMC_RD_CB 0x981 ++#define mmMC_RD_DB 0x982 ++#define mmMC_RD_TC0 0x983 ++#define mmMC_RD_TC1 0x984 ++#define mmMC_RD_HUB 0x985 ++#define mmMC_WR_CB 0x986 ++#define mmMC_WR_DB 0x987 ++#define mmMC_WR_HUB 0x988 ++#define mmMC_CITF_CREDITS_XBAR 0x989 ++#define mmMC_RD_GRP_LCL 0x98a ++#define mmMC_WR_GRP_LCL 0x98b ++#define mmMC_CITF_PERF_MON_CNTL2 0x98e ++#define mmMC_CITF_PERF_MON_RSLT2 0x991 ++#define mmMC_CITF_MISC_RD_CG 0x992 ++#define mmMC_CITF_MISC_WR_CG 0x993 ++#define mmMC_CITF_MISC_VM_CG 0x994 ++#define mmMC_HUB_MISC_POWER 0x82d ++#define mmMC_HUB_MISC_HUB_CG 0x82e ++#define mmMC_HUB_MISC_VM_CG 0x82f ++#define mmMC_HUB_MISC_SIP_CG 0x830 ++#define mmMC_HUB_MISC_STATUS 0x832 ++#define mmMC_HUB_MISC_OVERRIDE 0x833 ++#define mmMC_HUB_MISC_FRAMING 0x834 ++#define mmMC_HUB_WDP_CNTL 0x835 ++#define mmMC_HUB_WDP_ERR 0x836 ++#define mmMC_HUB_WDP_BP 0x837 ++#define mmMC_HUB_WDP_STATUS 0x838 ++#define mmMC_HUB_RDREQ_STATUS 0x839 ++#define mmMC_HUB_WRRET_STATUS 0x83a ++#define mmMC_HUB_RDREQ_CNTL 0x83b ++#define mmMC_HUB_WRRET_CNTL 0x83c ++#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d ++#define mmMC_HUB_WDP_WTM_CNTL 0x83e ++#define mmMC_HUB_WDP_CREDITS 0x83f ++#define mmMC_HUB_WDP_CREDITS2 0x840 ++#define mmMC_HUB_WDP_GBL0 0x841 ++#define mmMC_HUB_WDP_GBL1 0x842 ++#define mmMC_HUB_RDREQ_CREDITS 0x844 ++#define mmMC_HUB_RDREQ_CREDITS2 0x845 ++#define mmMC_HUB_SHARED_DAGB_DLY 0x846 ++#define mmMC_HUB_MISC_IDLE_STATUS 0x847 ++#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848 ++#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849 ++#define mmMC_HUB_WDP_BYPASS_GBL0 0x84a ++#define mmMC_HUB_WDP_BYPASS_GBL1 0x84b ++#define mmMC_HUB_RDREQ_BYPASS_GBL0 0x84c ++#define mmMC_HUB_WDP_SH2 0x84d ++#define mmMC_HUB_WDP_SH3 0x84e ++#define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS 0x84f ++#define mmMC_HUB_RDREQ_MCDW 0x851 ++#define mmMC_HUB_RDREQ_MCDX 0x852 ++#define mmMC_HUB_RDREQ_MCDY 0x853 ++#define mmMC_HUB_RDREQ_MCDZ 0x854 ++#define mmMC_HUB_RDREQ_SIP 0x855 ++#define mmMC_HUB_RDREQ_GBL0 0x856 ++#define mmMC_HUB_RDREQ_GBL1 0x857 ++#define mmMC_HUB_RDREQ_SMU 0x858 ++#define mmMC_HUB_RDREQ_SDMA0 0x859 ++#define mmMC_HUB_RDREQ_HDP 0x85a ++#define mmMC_HUB_RDREQ_SDMA1 0x85b ++#define mmMC_HUB_RDREQ_RLC 0x85c ++#define mmMC_HUB_RDREQ_SEM 0x85d ++#define mmMC_HUB_RDREQ_VCE0 0x85e ++#define mmMC_HUB_RDREQ_UMC 0x85f ++#define mmMC_HUB_RDREQ_UVD 0x860 ++#define mmMC_HUB_RDREQ_DMIF 0x862 ++#define mmMC_HUB_RDREQ_MCIF 0x863 ++#define mmMC_HUB_RDREQ_VMC 0x864 ++#define mmMC_HUB_RDREQ_VCEU0 0x865 ++#define mmMC_HUB_WDP_MCDW 0x866 ++#define mmMC_HUB_WDP_MCDX 0x867 ++#define mmMC_HUB_WDP_MCDY 0x868 ++#define mmMC_HUB_WDP_MCDZ 0x869 ++#define mmMC_HUB_WDP_SIP 0x86a ++#define mmMC_HUB_WDP_SDMA1 0x86b ++#define mmMC_HUB_WDP_SH0 0x86c ++#define mmMC_HUB_WDP_MCIF 0x86d ++#define mmMC_HUB_WDP_VCE0 0x86e ++#define mmMC_HUB_WDP_XDP 0x86f ++#define mmMC_HUB_WDP_IH 0x870 ++#define mmMC_HUB_WDP_RLC 0x871 ++#define mmMC_HUB_WDP_SEM 0x872 ++#define mmMC_HUB_WDP_SMU 0x873 ++#define mmMC_HUB_WDP_SH1 0x874 ++#define mmMC_HUB_WDP_UMC 0x875 ++#define mmMC_HUB_WDP_UVD 0x876 ++#define mmMC_HUB_WDP_HDP 0x877 ++#define mmMC_HUB_WDP_SDMA0 0x878 ++#define mmMC_HUB_WRRET_MCDW 0x879 ++#define mmMC_HUB_WRRET_MCDX 0x87a ++#define mmMC_HUB_WRRET_MCDY 0x87b ++#define mmMC_HUB_WRRET_MCDZ 0x87c ++#define mmMC_HUB_WDP_VCEU0 0x87d ++#define mmMC_HUB_WDP_XDMAM 0x87e ++#define mmMC_HUB_WDP_XDMA 0x87f ++#define mmMC_HUB_RDREQ_XDMAM 0x880 ++#define mmMC_HUB_RDREQ_ACPG 0x881 ++#define mmMC_HUB_RDREQ_ACPO 0x882 ++#define mmMC_HUB_RDREQ_SAMMSP 0x883 ++#define mmMC_HUB_RDREQ_VP8 0x884 ++#define mmMC_HUB_RDREQ_VP8U 0x885 ++#define mmMC_HUB_WDP_ACPG 0x886 ++#define mmMC_HUB_WDP_ACPO 0x887 ++#define mmMC_HUB_WDP_SAMMSP 0x888 ++#define mmMC_HUB_WDP_VP8 0x889 ++#define mmMC_HUB_WDP_VP8U 0x88a ++#define mmMC_HUB_RDREQ_ISP_SPM 0xde0 ++#define mmMC_HUB_RDREQ_ISP_MPM 0xde1 ++#define mmMC_HUB_RDREQ_ISP_CCPU 0xde2 ++#define mmMC_HUB_WDP_ISP_SPM 0xde3 ++#define mmMC_HUB_WDP_ISP_MPS 0xde4 ++#define mmMC_HUB_WDP_ISP_MPM 0xde5 ++#define mmMC_HUB_WDP_ISP_CCPU 0xde6 ++#define mmMC_HUB_RDREQ_MCDS 0xde7 ++#define mmMC_HUB_RDREQ_MCDT 0xde8 ++#define mmMC_HUB_RDREQ_MCDU 0xde9 ++#define mmMC_HUB_RDREQ_MCDV 0xdea ++#define mmMC_HUB_WDP_MCDS 0xdeb ++#define mmMC_HUB_WDP_MCDT 0xdec ++#define mmMC_HUB_WDP_MCDU 0xded ++#define mmMC_HUB_WDP_MCDV 0xdee ++#define mmMC_HUB_WRRET_MCDS 0xdef ++#define mmMC_HUB_WRRET_MCDT 0xdf0 ++#define mmMC_HUB_WRRET_MCDU 0xdf1 ++#define mmMC_HUB_WRRET_MCDV 0xdf2 ++#define mmMC_HUB_WDP_CREDITS_MCDW 0xdf3 ++#define mmMC_HUB_WDP_CREDITS_MCDX 0xdf4 ++#define mmMC_HUB_WDP_CREDITS_MCDY 0xdf5 ++#define mmMC_HUB_WDP_CREDITS_MCDZ 0xdf6 ++#define mmMC_HUB_WDP_CREDITS_MCDS 0xdf7 ++#define mmMC_HUB_WDP_CREDITS_MCDT 0xdf8 ++#define mmMC_HUB_WDP_CREDITS_MCDU 0xdf9 ++#define mmMC_HUB_WDP_CREDITS_MCDV 0xdfa ++#define mmMC_HUB_WDP_BP2 0xdfb ++#define mmMC_HUB_RDREQ_VCE1 0xdfc ++#define mmMC_HUB_RDREQ_VCEU1 0xdfd ++#define mmMC_HUB_WDP_VCE1 0xdfe ++#define mmMC_HUB_WDP_VCEU1 0xdff ++#define mmMC_RPB_CONF 0x94d ++#define mmMC_RPB_IF_CONF 0x94e ++#define mmMC_RPB_DBG1 0x94f ++#define mmMC_RPB_EFF_CNTL 0x950 ++#define mmMC_RPB_ARB_CNTL 0x951 ++#define mmMC_RPB_BIF_CNTL 0x952 ++#define mmMC_RPB_WR_SWITCH_CNTL 0x953 ++#define mmMC_RPB_WR_COMBINE_CNTL 0x954 ++#define mmMC_RPB_RD_SWITCH_CNTL 0x955 ++#define mmMC_RPB_CID_QUEUE_WR 0x956 ++#define mmMC_RPB_CID_QUEUE_RD 0x957 ++#define mmMC_RPB_PERF_COUNTER_CNTL 0x958 ++#define mmMC_RPB_PERF_COUNTER_STATUS 0x959 ++#define mmMC_RPB_CID_QUEUE_EX 0x95a ++#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b ++#define mmMC_RPB_TCI_CNTL 0x95c ++#define mmMC_RPB_TCI_CNTL2 0x95d ++#define mmMC_SHARED_CHMAP 0x801 ++#define mmMC_SHARED_CHREMAP 0x802 ++#define mmMC_RD_GRP_GFX 0x803 ++#define mmMC_WR_GRP_GFX 0x804 ++#define mmMC_RD_GRP_SYS 0x805 ++#define mmMC_WR_GRP_SYS 0x806 ++#define mmMC_RD_GRP_OTH 0x807 ++#define mmMC_WR_GRP_OTH 0x808 ++#define mmMC_VM_FB_LOCATION 0x809 ++#define mmMC_VM_AGP_TOP 0x80a ++#define mmMC_VM_AGP_BOT 0x80b ++#define mmMC_VM_AGP_BASE 0x80c ++#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d ++#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e ++#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f ++#define mmMC_VM_DC_WRITE_CNTL 0x810 ++#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811 ++#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812 ++#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813 ++#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814 ++#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815 ++#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816 ++#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817 ++#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818 ++#define mmMC_VM_MX_L1_TLB_CNTL 0x819 ++#define mmMC_VM_FB_OFFSET 0x81a ++#define mmMC_VM_STEERING 0x81b ++#define mmMC_SHARED_CHREMAP2 0x81c ++#define mmMC_SHARED_VF_ENABLE 0x81d ++#define mmMC_SHARED_VIRT_RESET_REQ 0x81e ++#define mmMC_SHARED_ACTIVE_FCN_ID 0x81f ++#define mmMC_CONFIG_MCD 0x828 ++#define mmMC_CG_CONFIG_MCD 0x829 ++#define mmMC_MEM_POWER_LS 0x82a ++#define mmMC_SHARED_BLACKOUT_CNTL 0x82b ++#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891 ++#define mmMC_VM_MB_L1_TLB1_DEBUG 0x892 ++#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893 ++#define mmMC_VM_MB_L1_TLB0_STATUS 0x895 ++#define mmMC_VM_MB_L1_TLB1_STATUS 0x896 ++#define mmMC_VM_MB_L1_TLB2_STATUS 0x897 ++#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1 ++#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5 ++#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6 ++#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998 ++#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999 ++#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a ++#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b ++#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c ++#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d ++#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4 ++#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7 ++#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8 ++#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd ++#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce ++#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf ++#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0 ++#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1 ++#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2 ++#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3 ++#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4 ++#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5 ++#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6 ++#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7 ++#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8 ++#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9 ++#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da ++#define mmMC_XPB_RTR_DEST_MAP0 0x8db ++#define mmMC_XPB_RTR_DEST_MAP1 0x8dc ++#define mmMC_XPB_RTR_DEST_MAP2 0x8dd ++#define mmMC_XPB_RTR_DEST_MAP3 0x8de ++#define mmMC_XPB_RTR_DEST_MAP4 0x8df ++#define mmMC_XPB_RTR_DEST_MAP5 0x8e0 ++#define mmMC_XPB_RTR_DEST_MAP6 0x8e1 ++#define mmMC_XPB_RTR_DEST_MAP7 0x8e2 ++#define mmMC_XPB_RTR_DEST_MAP8 0x8e3 ++#define mmMC_XPB_RTR_DEST_MAP9 0x8e4 ++#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5 ++#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6 ++#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7 ++#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8 ++#define mmMC_XPB_CLG_CFG0 0x8e9 ++#define mmMC_XPB_CLG_CFG1 0x8ea ++#define mmMC_XPB_CLG_CFG2 0x8eb ++#define mmMC_XPB_CLG_CFG3 0x8ec ++#define mmMC_XPB_CLG_CFG4 0x8ed ++#define mmMC_XPB_CLG_CFG5 0x8ee ++#define mmMC_XPB_CLG_CFG6 0x8ef ++#define mmMC_XPB_CLG_CFG7 0x8f0 ++#define mmMC_XPB_CLG_CFG8 0x8f1 ++#define mmMC_XPB_CLG_CFG9 0x8f2 ++#define mmMC_XPB_CLG_CFG10 0x8f3 ++#define mmMC_XPB_CLG_CFG11 0x8f4 ++#define mmMC_XPB_CLG_CFG12 0x8f5 ++#define mmMC_XPB_CLG_CFG13 0x8f6 ++#define mmMC_XPB_CLG_CFG14 0x8f7 ++#define mmMC_XPB_CLG_CFG15 0x8f8 ++#define mmMC_XPB_CLG_CFG16 0x8f9 ++#define mmMC_XPB_CLG_CFG17 0x8fa ++#define mmMC_XPB_CLG_CFG18 0x8fb ++#define mmMC_XPB_CLG_CFG19 0x8fc ++#define mmMC_XPB_CLG_EXTRA 0x8fd ++#define mmMC_XPB_LB_ADDR 0x8fe ++#define mmMC_XPB_UNC_THRESH_HST 0x8ff ++#define mmMC_XPB_UNC_THRESH_SID 0x900 ++#define mmMC_XPB_WCB_STS 0x901 ++#define mmMC_XPB_WCB_CFG 0x902 ++#define mmMC_XPB_P2P_BAR_CFG 0x903 ++#define mmMC_XPB_P2P_BAR0 0x904 ++#define mmMC_XPB_P2P_BAR1 0x905 ++#define mmMC_XPB_P2P_BAR2 0x906 ++#define mmMC_XPB_P2P_BAR3 0x907 ++#define mmMC_XPB_P2P_BAR4 0x908 ++#define mmMC_XPB_P2P_BAR5 0x909 ++#define mmMC_XPB_P2P_BAR6 0x90a ++#define mmMC_XPB_P2P_BAR7 0x90b ++#define mmMC_XPB_P2P_BAR_SETUP 0x90c ++#define mmMC_XPB_P2P_BAR_DEBUG 0x90d ++#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e ++#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f ++#define mmMC_XPB_PEER_SYS_BAR0 0x910 ++#define mmMC_XPB_PEER_SYS_BAR1 0x911 ++#define mmMC_XPB_PEER_SYS_BAR2 0x912 ++#define mmMC_XPB_PEER_SYS_BAR3 0x913 ++#define mmMC_XPB_PEER_SYS_BAR4 0x914 ++#define mmMC_XPB_PEER_SYS_BAR5 0x915 ++#define mmMC_XPB_PEER_SYS_BAR6 0x916 ++#define mmMC_XPB_PEER_SYS_BAR7 0x917 ++#define mmMC_XPB_PEER_SYS_BAR8 0x918 ++#define mmMC_XPB_PEER_SYS_BAR9 0x919 ++#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a ++#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b ++#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c ++#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d ++#define mmMC_XPB_CLK_GAT 0x91e ++#define mmMC_XPB_INTF_CFG 0x91f ++#define mmMC_XPB_INTF_STS 0x920 ++#define mmMC_XPB_PIPE_STS 0x921 ++#define mmMC_XPB_SUB_CTRL 0x922 ++#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923 ++#define mmMC_XPB_PERF_KNOBS 0x924 ++#define mmMC_XPB_STICKY 0x925 ++#define mmMC_XPB_STICKY_W1C 0x926 ++#define mmMC_XPB_MISC_CFG 0x927 ++#define mmMC_XPB_CLG_CFG20 0x928 ++#define mmMC_XPB_CLG_CFG21 0x929 ++#define mmMC_XPB_CLG_CFG22 0x92a ++#define mmMC_XPB_CLG_CFG23 0x92b ++#define mmMC_XPB_CLG_CFG24 0x92c ++#define mmMC_XPB_CLG_CFG25 0x92d ++#define mmMC_XPB_CLG_CFG26 0x92e ++#define mmMC_XPB_CLG_CFG27 0x92f ++#define mmMC_XPB_CLG_CFG28 0x930 ++#define mmMC_XPB_CLG_CFG29 0x931 ++#define mmMC_XPB_CLG_CFG30 0x932 ++#define mmMC_XPB_CLG_CFG31 0x933 ++#define mmMC_XPB_INTF_CFG2 0x934 ++#define mmMC_XPB_CLG_EXTRA_RD 0x935 ++#define mmMC_XPB_CLG_CFG32 0x936 ++#define mmMC_XPB_CLG_CFG33 0x937 ++#define mmMC_XPB_CLG_CFG34 0x938 ++#define mmMC_XPB_CLG_CFG35 0x939 ++#define mmMC_XPB_CLG_CFG36 0x93a ++#define mmMC_XBAR_ADDR_DEC 0xc80 ++#define mmMC_XBAR_REMOTE 0xc81 ++#define mmMC_XBAR_WRREQ_CREDIT 0xc82 ++#define mmMC_XBAR_RDREQ_CREDIT 0xc83 ++#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84 ++#define mmMC_XBAR_WRRET_CREDIT1 0xc85 ++#define mmMC_XBAR_WRRET_CREDIT2 0xc86 ++#define mmMC_XBAR_RDRET_CREDIT1 0xc87 ++#define mmMC_XBAR_RDRET_CREDIT2 0xc88 ++#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89 ++#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a ++#define mmMC_XBAR_CHTRIREMAP 0xc8b ++#define mmMC_XBAR_TWOCHAN 0xc8c ++#define mmMC_XBAR_ARB 0xc8d ++#define mmMC_XBAR_ARB_MAX_BURST 0xc8e ++#define mmMC_XBAR_FIFO_MON_CNTL0 0xc8f ++#define mmMC_XBAR_FIFO_MON_CNTL1 0xc90 ++#define mmMC_XBAR_FIFO_MON_CNTL2 0xc91 ++#define mmMC_XBAR_FIFO_MON_RSLT0 0xc92 ++#define mmMC_XBAR_FIFO_MON_RSLT1 0xc93 ++#define mmMC_XBAR_FIFO_MON_RSLT2 0xc94 ++#define mmMC_XBAR_FIFO_MON_RSLT3 0xc95 ++#define mmMC_XBAR_FIFO_MON_MAX_THSH 0xc96 ++#define mmMC_XBAR_SPARE0 0xc97 ++#define mmMC_XBAR_SPARE1 0xc98 ++#define mmMC_CITF_PERFCOUNTER_LO 0x7a0 ++#define mmMC_HUB_PERFCOUNTER_LO 0x7a1 ++#define mmMC_RPB_PERFCOUNTER_LO 0x7a2 ++#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3 ++#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4 ++#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5 ++#define mmMC_ARB_PERFCOUNTER_LO 0x7a6 ++#define mmATC_PERFCOUNTER_LO 0x7a7 ++#define mmMC_CITF_PERFCOUNTER_HI 0x7a8 ++#define mmMC_HUB_PERFCOUNTER_HI 0x7a9 ++#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa ++#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab ++#define mmMC_RPB_PERFCOUNTER_HI 0x7ac ++#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad ++#define mmMC_ARB_PERFCOUNTER_HI 0x7ae ++#define mmATC_PERFCOUNTER_HI 0x7af ++#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0 ++#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1 ++#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2 ++#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3 ++#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4 ++#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5 ++#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6 ++#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7 ++#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8 ++#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9 ++#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba ++#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb ++#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc ++#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd ++#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be ++#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf ++#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0 ++#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1 ++#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2 ++#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3 ++#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4 ++#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5 ++#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6 ++#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7 ++#define mmATC_PERFCOUNTER0_CFG 0x7c8 ++#define mmATC_PERFCOUNTER1_CFG 0x7c9 ++#define mmATC_PERFCOUNTER2_CFG 0x7ca ++#define mmATC_PERFCOUNTER3_CFG 0x7cb ++#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc ++#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd ++#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce ++#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf ++#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0 ++#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1 ++#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2 ++#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3 ++#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4 ++#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5 ++#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6 ++#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7 ++#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8 ++#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9 ++#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da ++#define mmMC_GRUB_PERFCOUNTER_LO 0x7e4 ++#define mmMC_GRUB_PERFCOUNTER_HI 0x7e5 ++#define mmMC_GRUB_PERFCOUNTER0_CFG 0x7e6 ++#define mmMC_GRUB_PERFCOUNTER1_CFG 0x7e7 ++#define mmMC_GRUB_PERFCOUNTER_RSLT_CNTL 0x7e8 ++#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0 ++#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1 ++#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2 ++#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3 ++#define mmATC_VM_APERTURE0_CNTL 0xcc4 ++#define mmATC_VM_APERTURE1_CNTL 0xcc5 ++#define mmATC_VM_APERTURE0_CNTL2 0xcc6 ++#define mmATC_VM_APERTURE1_CNTL2 0xcc7 ++#define mmATC_ATS_CNTL 0xcc9 ++#define mmATC_ATS_DEBUG 0xcca ++#define mmATC_ATS_FAULT_DEBUG 0xccb ++#define mmATC_ATS_STATUS 0xccc ++#define mmATC_ATS_FAULT_CNTL 0xccd ++#define mmATC_ATS_FAULT_STATUS_INFO 0xcce ++#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf ++#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0 ++#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1 ++#define mmATC_ATS_FAULT_STATUS_INFO2 0xcd2 ++#define mmATC_MISC_CG 0xcd4 ++#define mmATC_L2_CNTL 0xcd5 ++#define mmATC_L2_CNTL2 0xcd6 ++#define mmATC_L2_DEBUG 0xcd7 ++#define mmATC_L2_DEBUG2 0xcd8 ++#define mmATC_L2_CACHE_DATA0 0xcd9 ++#define mmATC_L2_CACHE_DATA1 0xcda ++#define mmATC_L2_CACHE_DATA2 0xcdb ++#define mmATC_L1_CNTL 0xcdc ++#define mmATC_L1_ADDRESS_OFFSET 0xcdd ++#define mmATC_L1RD_DEBUG_TLB 0xcde ++#define mmATC_L1WR_DEBUG_TLB 0xcdf ++#define mmATC_L1RD_STATUS 0xce0 ++#define mmATC_L1WR_STATUS 0xce1 ++#define mmATC_L1RD_DEBUG2_TLB 0xce2 ++#define mmATC_L1WR_DEBUG2_TLB 0xce3 ++#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6 ++#define mmATC_VMID0_PASID_MAPPING 0xce7 ++#define mmATC_VMID1_PASID_MAPPING 0xce8 ++#define mmATC_VMID2_PASID_MAPPING 0xce9 ++#define mmATC_VMID3_PASID_MAPPING 0xcea ++#define mmATC_VMID4_PASID_MAPPING 0xceb ++#define mmATC_VMID5_PASID_MAPPING 0xcec ++#define mmATC_VMID6_PASID_MAPPING 0xced ++#define mmATC_VMID7_PASID_MAPPING 0xcee ++#define mmATC_VMID8_PASID_MAPPING 0xcef ++#define mmATC_VMID9_PASID_MAPPING 0xcf0 ++#define mmATC_VMID10_PASID_MAPPING 0xcf1 ++#define mmATC_VMID11_PASID_MAPPING 0xcf2 ++#define mmATC_VMID12_PASID_MAPPING 0xcf3 ++#define mmATC_VMID13_PASID_MAPPING 0xcf4 ++#define mmATC_VMID14_PASID_MAPPING 0xcf5 ++#define mmATC_VMID15_PASID_MAPPING 0xcf6 ++#define mmATC_ATS_VMID_STATUS 0xd07 ++#define mmATC_ATS_SMU_STATUS 0xd08 ++#define mmATC_L2_CNTL3 0xd09 ++#define mmATC_L2_STATUS 0xd0a ++#define mmATC_L2_STATUS2 0xd0b ++#define mmGMCON_RENG_RAM_INDEX 0xd40 ++#define mmGMCON_RENG_RAM_DATA 0xd41 ++#define mmGMCON_RENG_EXECUTE 0xd42 ++#define mmGMCON_MISC 0xd43 ++#define mmGMCON_MISC2 0xd44 ++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45 ++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46 ++#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47 ++#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48 ++#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49 ++#define mmGMCON_PERF_MON_CNTL0 0xd4a ++#define mmGMCON_PERF_MON_CNTL1 0xd4b ++#define mmGMCON_PERF_MON_RSLT0 0xd4c ++#define mmGMCON_PERF_MON_RSLT1 0xd4d ++#define mmGMCON_PGFSM_CONFIG 0xd4e ++#define mmGMCON_PGFSM_WRITE 0xd4f ++#define mmGMCON_PGFSM_READ 0xd50 ++#define mmGMCON_MISC3 0xd51 ++#define mmGMCON_MASK 0xd52 ++#define mmGMCON_LPT_TARGET 0xd53 ++#define mmGMCON_DEBUG 0xd5f ++#define mmVM_L2_CNTL 0x500 ++#define mmVM_L2_CNTL2 0x501 ++#define mmVM_L2_CNTL3 0x502 ++#define mmVM_L2_STATUS 0x503 ++#define mmVM_CONTEXT0_CNTL 0x504 ++#define mmVM_CONTEXT1_CNTL 0x505 ++#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506 ++#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507 ++#define mmVM_CONTEXT0_CNTL2 0x50c ++#define mmVM_CONTEXT1_CNTL2 0x50d ++#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e ++#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f ++#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510 ++#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511 ++#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512 ++#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513 ++#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514 ++#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515 ++#define mmVM_INVALIDATE_REQUEST 0x51e ++#define mmVM_INVALIDATE_RESPONSE 0x51f ++#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c ++#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d ++#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e ++#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f ++#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530 ++#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531 ++#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532 ++#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533 ++#define mmVM_PRT_CNTL 0x534 ++#define mmVM_CONTEXTS_DISABLE 0x535 ++#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536 ++#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537 ++#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538 ++#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539 ++#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e ++#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f ++#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546 ++#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547 ++#define mmVM_FAULT_CLIENT_ID 0x54e ++#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f ++#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550 ++#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551 ++#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552 ++#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553 ++#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554 ++#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555 ++#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556 ++#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557 ++#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558 ++#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f ++#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560 ++#define mmVM_DEBUG 0x56f ++#define mmVM_L2_CG 0x570 ++#define mmVM_L2_BANK_SELECT_MASKA 0x572 ++#define mmVM_L2_BANK_SELECT_MASKB 0x573 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575 ++#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576 ++#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577 ++#define mmVM_L2_CNTL4 0x578 ++#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x579 ++#define mmMC_VM_FB_SIZE_OFFSET_VF0 0xf980 ++#define mmMC_VM_FB_SIZE_OFFSET_VF1 0xf981 ++#define mmMC_VM_FB_SIZE_OFFSET_VF2 0xf982 ++#define mmMC_VM_FB_SIZE_OFFSET_VF3 0xf983 ++#define mmMC_VM_FB_SIZE_OFFSET_VF4 0xf984 ++#define mmMC_VM_FB_SIZE_OFFSET_VF5 0xf985 ++#define mmMC_VM_FB_SIZE_OFFSET_VF6 0xf986 ++#define mmMC_VM_FB_SIZE_OFFSET_VF7 0xf987 ++#define mmMC_VM_FB_SIZE_OFFSET_VF8 0xf988 ++#define mmMC_VM_FB_SIZE_OFFSET_VF9 0xf989 ++#define mmMC_VM_FB_SIZE_OFFSET_VF10 0xf98a ++#define mmMC_VM_FB_SIZE_OFFSET_VF11 0xf98b ++#define mmMC_VM_FB_SIZE_OFFSET_VF12 0xf98c ++#define mmMC_VM_FB_SIZE_OFFSET_VF13 0xf98d ++#define mmMC_VM_FB_SIZE_OFFSET_VF14 0xf98e ++#define mmMC_VM_FB_SIZE_OFFSET_VF15 0xf98f ++#define mmMC_VM_NB_MMIOBASE 0xf990 ++#define mmMC_VM_NB_MMIOLIMIT 0xf991 ++#define mmMC_VM_NB_PCI_CTRL 0xf992 ++#define mmMC_VM_NB_PCI_ARB 0xf993 ++#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0xf994 ++#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0xf995 ++#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0xf996 ++#define mmMC_VM_NB_TOP_OF_DRAM3 0xf997 ++#define mmMC_VM_MARC_BASE_LO_0 0xf998 ++#define mmMC_VM_MARC_BASE_LO_1 0xf99e ++#define mmMC_VM_MARC_BASE_LO_2 0xf9a4 ++#define mmMC_VM_MARC_BASE_LO_3 0xf9aa ++#define mmMC_VM_MARC_BASE_HI_0 0xf999 ++#define mmMC_VM_MARC_BASE_HI_1 0xf99f ++#define mmMC_VM_MARC_BASE_HI_2 0xf9a5 ++#define mmMC_VM_MARC_BASE_HI_3 0xf9ab ++#define mmMC_VM_MARC_RELOC_LO_0 0xf99a ++#define mmMC_VM_MARC_RELOC_LO_1 0xf9a0 ++#define mmMC_VM_MARC_RELOC_LO_2 0xf9a6 ++#define mmMC_VM_MARC_RELOC_LO_3 0xf9ac ++#define mmMC_VM_MARC_RELOC_HI_0 0xf99b ++#define mmMC_VM_MARC_RELOC_HI_1 0xf9a1 ++#define mmMC_VM_MARC_RELOC_HI_2 0xf9a7 ++#define mmMC_VM_MARC_RELOC_HI_3 0xf9ad ++#define mmMC_VM_MARC_LEN_LO_0 0xf99c ++#define mmMC_VM_MARC_LEN_LO_1 0xf9a2 ++#define mmMC_VM_MARC_LEN_LO_2 0xf9a8 ++#define mmMC_VM_MARC_LEN_LO_3 0xf9ae ++#define mmMC_VM_MARC_LEN_HI_0 0xf99d ++#define mmMC_VM_MARC_LEN_HI_1 0xf9a3 ++#define mmMC_VM_MARC_LEN_HI_2 0xf9a9 ++#define mmMC_VM_MARC_LEN_HI_3 0xf9af ++#define mmMC_VM_MARC_CNTL 0xf9b0 ++#define mmMC_ARB_HARSH_EN_RD 0xdc0 ++#define mmMC_ARB_HARSH_EN_WR 0xdc1 ++#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2 ++#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3 ++#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4 ++#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5 ++#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6 ++#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7 ++#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8 ++#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9 ++#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca ++#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb ++#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc ++#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd ++#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce ++#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf ++#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0 ++#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1 ++#define mmMC_ARB_HARSH_SAT0_RD 0xdd2 ++#define mmMC_ARB_HARSH_SAT0_WR 0xdd3 ++#define mmMC_ARB_HARSH_SAT1_RD 0xdd4 ++#define mmMC_ARB_HARSH_SAT1_WR 0xdd5 ++#define mmMC_ARB_HARSH_CTL_RD 0xdd6 ++#define mmMC_ARB_HARSH_CTL_WR 0xdd7 ++#define mmMC_ARB_GRUB_PRIORITY1_RD 0xdd8 ++#define mmMC_ARB_GRUB_PRIORITY1_WR 0xdd9 ++#define mmMC_ARB_GRUB_PRIORITY2_RD 0xdda ++#define mmMC_ARB_GRUB_PRIORITY2_WR 0xddb ++#define mmMC_FUS_DRAM0_CS0_BASE 0xa05 ++#define mmMC_FUS_DRAM1_CS0_BASE 0xa06 ++#define mmMC_FUS_DRAM0_CS1_BASE 0xa07 ++#define mmMC_FUS_DRAM1_CS1_BASE 0xa08 ++#define mmMC_FUS_DRAM0_CS2_BASE 0xa09 ++#define mmMC_FUS_DRAM1_CS2_BASE 0xa0a ++#define mmMC_FUS_DRAM0_CS3_BASE 0xa0b ++#define mmMC_FUS_DRAM1_CS3_BASE 0xa0c ++#define mmMC_FUS_DRAM0_CS01_MASK 0xa0d ++#define mmMC_FUS_DRAM1_CS01_MASK 0xa0e ++#define mmMC_FUS_DRAM0_CS23_MASK 0xa0f ++#define mmMC_FUS_DRAM1_CS23_MASK 0xa10 ++#define mmMC_FUS_DRAM0_BANK_ADDR_MAPPING 0xa11 ++#define mmMC_FUS_DRAM1_BANK_ADDR_MAPPING 0xa12 ++#define mmMC_FUS_DRAM0_CTL_BASE 0xa13 ++#define mmMC_FUS_DRAM1_CTL_BASE 0xa14 ++#define mmMC_FUS_DRAM0_CTL_LIMIT 0xa15 ++#define mmMC_FUS_DRAM1_CTL_LIMIT 0xa16 ++#define mmMC_FUS_DRAM_CTL_HIGH_01 0xa17 ++#define mmMC_FUS_DRAM_CTL_HIGH_23 0xa18 ++#define mmMC_FUS_DRAM_MODE 0xa19 ++#define mmMC_FUS_DRAM_APER_BASE 0xa1a ++#define mmMC_FUS_DRAM_APER_TOP 0xa1b ++#define mmMC_FUS_DRAM_APER_DEF 0xa1e ++#define mmMC_FUS_ARB_GARLIC_ISOC_PRI 0xa1f ++#define mmMC_FUS_ARB_GARLIC_CNTL 0xa20 ++#define mmMC_FUS_ARB_GARLIC_WR_PRI 0xa21 ++#define mmMC_FUS_ARB_GARLIC_WR_PRI2 0xa22 ++#define mmMC_CG_DATAPORT 0xa32 ++#define mmMC_GRUB_PROBE_MAP 0xa33 ++#define mmMC_GRUB_POST_PROBE_DELAY 0xa34 ++#define mmMC_GRUB_PROBE_CREDITS 0xa35 ++#define mmMC_GRUB_FEATURES 0xa36 ++#define mmMC_GRUB_TX_CREDITS 0xa37 ++#define mmMC_GRUB_TCB_INDEX 0xa38 ++#define mmMC_GRUB_TCB_DATA_LO 0xa39 ++#define mmMC_GRUB_TCB_DATA_HI 0xa3a ++#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x5e78 ++#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x5e78 ++#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x5eb8 ++#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x5ef8 ++#define mmMCIF_WB_BUFMGR_CUR_LINE_R 0x5e79 ++#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x5e79 ++#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x5eb9 ++#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x5ef9 ++#define mmMCIF_WB_BUFMGR_STATUS 0x5e7a ++#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x5e7a ++#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x5eba ++#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x5efa ++#define mmMCIF_WB_BUF_PITCH 0x5e7b ++#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x5e7b ++#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x5ebb ++#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x5efb ++#define mmMCIF_WB_BUF_1_STATUS 0x5e7c ++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x5e7c ++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x5ebc ++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x5efc ++#define mmMCIF_WB_BUF_1_STATUS2 0x5e7d ++#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x5e7d ++#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x5ebd ++#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x5efd ++#define mmMCIF_WB_BUF_2_STATUS 0x5e7e ++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x5e7e ++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x5ebe ++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x5efe ++#define mmMCIF_WB_BUF_2_STATUS2 0x5e7f ++#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x5e7f ++#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x5ebf ++#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x5eff ++#define mmMCIF_WB_BUF_3_STATUS 0x5e80 ++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x5e80 ++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x5ec0 ++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x5f00 ++#define mmMCIF_WB_BUF_3_STATUS2 0x5e81 ++#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x5e81 ++#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x5ec1 ++#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x5f01 ++#define mmMCIF_WB_BUF_4_STATUS 0x5e82 ++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x5e82 ++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x5ec2 ++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x5f02 ++#define mmMCIF_WB_BUF_4_STATUS2 0x5e83 ++#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x5e83 ++#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x5ec3 ++#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x5f03 ++#define mmMCIF_WB_ARBITRATION_CONTROL 0x5e84 ++#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x5e84 ++#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x5ec4 ++#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x5f04 ++#define mmMCIF_WB_URGENCY_WATERMARK 0x5e85 ++#define mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK 0x5e85 ++#define mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK 0x5ec5 ++#define mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK 0x5f05 ++#define mmMCIF_WB_TEST_DEBUG_INDEX 0x5e86 ++#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x5e86 ++#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x5ec6 ++#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x5f06 ++#define mmMCIF_WB_TEST_DEBUG_DATA 0x5e87 ++#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x5e87 ++#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x5ec7 ++#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x5f07 ++#define mmMCIF_WB_BUF_1_ADDR_Y 0x5e88 ++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x5e88 ++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x5ec8 ++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x5f08 ++#define mmMCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89 ++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89 ++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5ec9 ++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5f09 ++#define mmMCIF_WB_BUF_1_ADDR_C 0x5e8a ++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x5e8a ++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x5eca ++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x5f0a ++#define mmMCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b ++#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b ++#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5ecb ++#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5f0b ++#define mmMCIF_WB_BUF_2_ADDR_Y 0x5e8c ++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x5e8c ++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x5ecc ++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x5f0c ++#define mmMCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d ++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d ++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5ecd ++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5f0d ++#define mmMCIF_WB_BUF_2_ADDR_C 0x5e8e ++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x5e8e ++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x5ece ++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x5f0e ++#define mmMCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f ++#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f ++#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5ecf ++#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5f0f ++#define mmMCIF_WB_BUF_3_ADDR_Y 0x5e90 ++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x5e90 ++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x5ed0 ++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x5f10 ++#define mmMCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91 ++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91 ++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5ed1 ++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5f11 ++#define mmMCIF_WB_BUF_3_ADDR_C 0x5e92 ++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x5e92 ++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x5ed2 ++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x5f12 ++#define mmMCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93 ++#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93 ++#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5ed3 ++#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5f13 ++#define mmMCIF_WB_BUF_4_ADDR_Y 0x5e94 ++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x5e94 ++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x5ed4 ++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x5f14 ++#define mmMCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95 ++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95 ++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5ed5 ++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5f15 ++#define mmMCIF_WB_BUF_4_ADDR_C 0x5e96 ++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x5e96 ++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x5ed6 ++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x5f16 ++#define mmMCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97 ++#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97 ++#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5ed7 ++#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5f17 ++#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x5e98 ++#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x5e98 ++#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x5ed8 ++#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x5f18 ++#define mmMCIF_WB_HVVMID_CONTROL 0x5e99 ++#define mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL 0x5e99 ++#define mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL 0x5ed9 ++#define mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL 0x5f19 ++ ++#endif /* GMC_8_2_D_H */ +diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h +new file mode 100644 +index 0000000..bc18e4d +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h +@@ -0,0 +1,1068 @@ ++/* ++ * GMC_8_2 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef GMC_8_2_ENUM_H ++#define GMC_8_2_ENUM_H ++ ++typedef enum DebugBlockId { ++ DBG_BLOCK_ID_RESERVED = 0x0, ++ DBG_BLOCK_ID_DBG = 0x1, ++ DBG_BLOCK_ID_VMC = 0x2, ++ DBG_BLOCK_ID_PDMA = 0x3, ++ DBG_BLOCK_ID_CG = 0x4, ++ DBG_BLOCK_ID_SRBM = 0x5, ++ DBG_BLOCK_ID_GRBM = 0x6, ++ DBG_BLOCK_ID_RLC = 0x7, ++ DBG_BLOCK_ID_CSC = 0x8, ++ DBG_BLOCK_ID_SEM = 0x9, ++ DBG_BLOCK_ID_IH = 0xa, ++ DBG_BLOCK_ID_SC = 0xb, ++ DBG_BLOCK_ID_SQ = 0xc, ++ DBG_BLOCK_ID_UVDU = 0xd, ++ DBG_BLOCK_ID_SQA = 0xe, ++ DBG_BLOCK_ID_SDMA0 = 0xf, ++ DBG_BLOCK_ID_SDMA1 = 0x10, ++ DBG_BLOCK_ID_SPIM = 0x11, ++ DBG_BLOCK_ID_GDS = 0x12, ++ DBG_BLOCK_ID_VC0 = 0x13, ++ DBG_BLOCK_ID_VC1 = 0x14, ++ DBG_BLOCK_ID_PA0 = 0x15, ++ DBG_BLOCK_ID_PA1 = 0x16, ++ DBG_BLOCK_ID_CP0 = 0x17, ++ DBG_BLOCK_ID_CP1 = 0x18, ++ DBG_BLOCK_ID_CP2 = 0x19, ++ DBG_BLOCK_ID_XBR = 0x1a, ++ DBG_BLOCK_ID_UVDM = 0x1b, ++ DBG_BLOCK_ID_VGT0 = 0x1c, ++ DBG_BLOCK_ID_VGT1 = 0x1d, ++ DBG_BLOCK_ID_IA = 0x1e, ++ DBG_BLOCK_ID_SXM0 = 0x1f, ++ DBG_BLOCK_ID_SXM1 = 0x20, ++ DBG_BLOCK_ID_SCT0 = 0x21, ++ DBG_BLOCK_ID_SCT1 = 0x22, ++ DBG_BLOCK_ID_SPM0 = 0x23, ++ DBG_BLOCK_ID_SPM1 = 0x24, ++ DBG_BLOCK_ID_UNUSED0 = 0x25, ++ DBG_BLOCK_ID_UNUSED1 = 0x26, ++ DBG_BLOCK_ID_TCAA = 0x27, ++ DBG_BLOCK_ID_TCAB = 0x28, ++ DBG_BLOCK_ID_TCCA = 0x29, ++ DBG_BLOCK_ID_TCCB = 0x2a, ++ DBG_BLOCK_ID_MCC0 = 0x2b, ++ DBG_BLOCK_ID_MCC1 = 0x2c, ++ DBG_BLOCK_ID_MCC2 = 0x2d, ++ DBG_BLOCK_ID_MCC3 = 0x2e, ++ DBG_BLOCK_ID_SXS0 = 0x2f, ++ DBG_BLOCK_ID_SXS1 = 0x30, ++ DBG_BLOCK_ID_SXS2 = 0x31, ++ DBG_BLOCK_ID_SXS3 = 0x32, ++ DBG_BLOCK_ID_SXS4 = 0x33, ++ DBG_BLOCK_ID_SXS5 = 0x34, ++ DBG_BLOCK_ID_SXS6 = 0x35, ++ DBG_BLOCK_ID_SXS7 = 0x36, ++ DBG_BLOCK_ID_SXS8 = 0x37, ++ DBG_BLOCK_ID_SXS9 = 0x38, ++ DBG_BLOCK_ID_BCI0 = 0x39, ++ DBG_BLOCK_ID_BCI1 = 0x3a, ++ DBG_BLOCK_ID_BCI2 = 0x3b, ++ DBG_BLOCK_ID_BCI3 = 0x3c, ++ DBG_BLOCK_ID_MCB = 0x3d, ++ DBG_BLOCK_ID_UNUSED6 = 0x3e, ++ DBG_BLOCK_ID_SQA00 = 0x3f, ++ DBG_BLOCK_ID_SQA01 = 0x40, ++ DBG_BLOCK_ID_SQA02 = 0x41, ++ DBG_BLOCK_ID_SQA10 = 0x42, ++ DBG_BLOCK_ID_SQA11 = 0x43, ++ DBG_BLOCK_ID_SQA12 = 0x44, ++ DBG_BLOCK_ID_UNUSED7 = 0x45, ++ DBG_BLOCK_ID_UNUSED8 = 0x46, ++ DBG_BLOCK_ID_SQB00 = 0x47, ++ DBG_BLOCK_ID_SQB01 = 0x48, ++ DBG_BLOCK_ID_SQB10 = 0x49, ++ DBG_BLOCK_ID_SQB11 = 0x4a, ++ DBG_BLOCK_ID_SQ00 = 0x4b, ++ DBG_BLOCK_ID_SQ01 = 0x4c, ++ DBG_BLOCK_ID_SQ10 = 0x4d, ++ DBG_BLOCK_ID_SQ11 = 0x4e, ++ DBG_BLOCK_ID_CB00 = 0x4f, ++ DBG_BLOCK_ID_CB01 = 0x50, ++ DBG_BLOCK_ID_CB02 = 0x51, ++ DBG_BLOCK_ID_CB03 = 0x52, ++ DBG_BLOCK_ID_CB04 = 0x53, ++ DBG_BLOCK_ID_UNUSED9 = 0x54, ++ DBG_BLOCK_ID_UNUSED10 = 0x55, ++ DBG_BLOCK_ID_UNUSED11 = 0x56, ++ DBG_BLOCK_ID_CB10 = 0x57, ++ DBG_BLOCK_ID_CB11 = 0x58, ++ DBG_BLOCK_ID_CB12 = 0x59, ++ DBG_BLOCK_ID_CB13 = 0x5a, ++ DBG_BLOCK_ID_CB14 = 0x5b, ++ DBG_BLOCK_ID_UNUSED12 = 0x5c, ++ DBG_BLOCK_ID_UNUSED13 = 0x5d, ++ DBG_BLOCK_ID_UNUSED14 = 0x5e, ++ DBG_BLOCK_ID_TCP0 = 0x5f, ++ DBG_BLOCK_ID_TCP1 = 0x60, ++ DBG_BLOCK_ID_TCP2 = 0x61, ++ DBG_BLOCK_ID_TCP3 = 0x62, ++ DBG_BLOCK_ID_TCP4 = 0x63, ++ DBG_BLOCK_ID_TCP5 = 0x64, ++ DBG_BLOCK_ID_TCP6 = 0x65, ++ DBG_BLOCK_ID_TCP7 = 0x66, ++ DBG_BLOCK_ID_TCP8 = 0x67, ++ DBG_BLOCK_ID_TCP9 = 0x68, ++ DBG_BLOCK_ID_TCP10 = 0x69, ++ DBG_BLOCK_ID_TCP11 = 0x6a, ++ DBG_BLOCK_ID_TCP12 = 0x6b, ++ DBG_BLOCK_ID_TCP13 = 0x6c, ++ DBG_BLOCK_ID_TCP14 = 0x6d, ++ DBG_BLOCK_ID_TCP15 = 0x6e, ++ DBG_BLOCK_ID_TCP16 = 0x6f, ++ DBG_BLOCK_ID_TCP17 = 0x70, ++ DBG_BLOCK_ID_TCP18 = 0x71, ++ DBG_BLOCK_ID_TCP19 = 0x72, ++ DBG_BLOCK_ID_TCP20 = 0x73, ++ DBG_BLOCK_ID_TCP21 = 0x74, ++ DBG_BLOCK_ID_TCP22 = 0x75, ++ DBG_BLOCK_ID_TCP23 = 0x76, ++ DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, ++ DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, ++ DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, ++ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, ++ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, ++ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, ++ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, ++ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, ++ DBG_BLOCK_ID_DB00 = 0x7f, ++ DBG_BLOCK_ID_DB01 = 0x80, ++ DBG_BLOCK_ID_DB02 = 0x81, ++ DBG_BLOCK_ID_DB03 = 0x82, ++ DBG_BLOCK_ID_DB04 = 0x83, ++ DBG_BLOCK_ID_UNUSED15 = 0x84, ++ DBG_BLOCK_ID_UNUSED16 = 0x85, ++ DBG_BLOCK_ID_UNUSED17 = 0x86, ++ DBG_BLOCK_ID_DB10 = 0x87, ++ DBG_BLOCK_ID_DB11 = 0x88, ++ DBG_BLOCK_ID_DB12 = 0x89, ++ DBG_BLOCK_ID_DB13 = 0x8a, ++ DBG_BLOCK_ID_DB14 = 0x8b, ++ DBG_BLOCK_ID_UNUSED18 = 0x8c, ++ DBG_BLOCK_ID_UNUSED19 = 0x8d, ++ DBG_BLOCK_ID_UNUSED20 = 0x8e, ++ DBG_BLOCK_ID_TCC0 = 0x8f, ++ DBG_BLOCK_ID_TCC1 = 0x90, ++ DBG_BLOCK_ID_TCC2 = 0x91, ++ DBG_BLOCK_ID_TCC3 = 0x92, ++ DBG_BLOCK_ID_TCC4 = 0x93, ++ DBG_BLOCK_ID_TCC5 = 0x94, ++ DBG_BLOCK_ID_TCC6 = 0x95, ++ DBG_BLOCK_ID_TCC7 = 0x96, ++ DBG_BLOCK_ID_SPS00 = 0x97, ++ DBG_BLOCK_ID_SPS01 = 0x98, ++ DBG_BLOCK_ID_SPS02 = 0x99, ++ DBG_BLOCK_ID_SPS10 = 0x9a, ++ DBG_BLOCK_ID_SPS11 = 0x9b, ++ DBG_BLOCK_ID_SPS12 = 0x9c, ++ DBG_BLOCK_ID_UNUSED21 = 0x9d, ++ DBG_BLOCK_ID_UNUSED22 = 0x9e, ++ DBG_BLOCK_ID_TA00 = 0x9f, ++ DBG_BLOCK_ID_TA01 = 0xa0, ++ DBG_BLOCK_ID_TA02 = 0xa1, ++ DBG_BLOCK_ID_TA03 = 0xa2, ++ DBG_BLOCK_ID_TA04 = 0xa3, ++ DBG_BLOCK_ID_TA05 = 0xa4, ++ DBG_BLOCK_ID_TA06 = 0xa5, ++ DBG_BLOCK_ID_TA07 = 0xa6, ++ DBG_BLOCK_ID_TA08 = 0xa7, ++ DBG_BLOCK_ID_TA09 = 0xa8, ++ DBG_BLOCK_ID_TA0A = 0xa9, ++ DBG_BLOCK_ID_TA0B = 0xaa, ++ DBG_BLOCK_ID_UNUSED23 = 0xab, ++ DBG_BLOCK_ID_UNUSED24 = 0xac, ++ DBG_BLOCK_ID_UNUSED25 = 0xad, ++ DBG_BLOCK_ID_UNUSED26 = 0xae, ++ DBG_BLOCK_ID_TA10 = 0xaf, ++ DBG_BLOCK_ID_TA11 = 0xb0, ++ DBG_BLOCK_ID_TA12 = 0xb1, ++ DBG_BLOCK_ID_TA13 = 0xb2, ++ DBG_BLOCK_ID_TA14 = 0xb3, ++ DBG_BLOCK_ID_TA15 = 0xb4, ++ DBG_BLOCK_ID_TA16 = 0xb5, ++ DBG_BLOCK_ID_TA17 = 0xb6, ++ DBG_BLOCK_ID_TA18 = 0xb7, ++ DBG_BLOCK_ID_TA19 = 0xb8, ++ DBG_BLOCK_ID_TA1A = 0xb9, ++ DBG_BLOCK_ID_TA1B = 0xba, ++ DBG_BLOCK_ID_UNUSED27 = 0xbb, ++ DBG_BLOCK_ID_UNUSED28 = 0xbc, ++ DBG_BLOCK_ID_UNUSED29 = 0xbd, ++ DBG_BLOCK_ID_UNUSED30 = 0xbe, ++ DBG_BLOCK_ID_TD00 = 0xbf, ++ DBG_BLOCK_ID_TD01 = 0xc0, ++ DBG_BLOCK_ID_TD02 = 0xc1, ++ DBG_BLOCK_ID_TD03 = 0xc2, ++ DBG_BLOCK_ID_TD04 = 0xc3, ++ DBG_BLOCK_ID_TD05 = 0xc4, ++ DBG_BLOCK_ID_TD06 = 0xc5, ++ DBG_BLOCK_ID_TD07 = 0xc6, ++ DBG_BLOCK_ID_TD08 = 0xc7, ++ DBG_BLOCK_ID_TD09 = 0xc8, ++ DBG_BLOCK_ID_TD0A = 0xc9, ++ DBG_BLOCK_ID_TD0B = 0xca, ++ DBG_BLOCK_ID_UNUSED31 = 0xcb, ++ DBG_BLOCK_ID_UNUSED32 = 0xcc, ++ DBG_BLOCK_ID_UNUSED33 = 0xcd, ++ DBG_BLOCK_ID_UNUSED34 = 0xce, ++ DBG_BLOCK_ID_TD10 = 0xcf, ++ DBG_BLOCK_ID_TD11 = 0xd0, ++ DBG_BLOCK_ID_TD12 = 0xd1, ++ DBG_BLOCK_ID_TD13 = 0xd2, ++ DBG_BLOCK_ID_TD14 = 0xd3, ++ DBG_BLOCK_ID_TD15 = 0xd4, ++ DBG_BLOCK_ID_TD16 = 0xd5, ++ DBG_BLOCK_ID_TD17 = 0xd6, ++ DBG_BLOCK_ID_TD18 = 0xd7, ++ DBG_BLOCK_ID_TD19 = 0xd8, ++ DBG_BLOCK_ID_TD1A = 0xd9, ++ DBG_BLOCK_ID_TD1B = 0xda, ++ DBG_BLOCK_ID_UNUSED35 = 0xdb, ++ DBG_BLOCK_ID_UNUSED36 = 0xdc, ++ DBG_BLOCK_ID_UNUSED37 = 0xdd, ++ DBG_BLOCK_ID_UNUSED38 = 0xde, ++ DBG_BLOCK_ID_LDS00 = 0xdf, ++ DBG_BLOCK_ID_LDS01 = 0xe0, ++ DBG_BLOCK_ID_LDS02 = 0xe1, ++ DBG_BLOCK_ID_LDS03 = 0xe2, ++ DBG_BLOCK_ID_LDS04 = 0xe3, ++ DBG_BLOCK_ID_LDS05 = 0xe4, ++ DBG_BLOCK_ID_LDS06 = 0xe5, ++ DBG_BLOCK_ID_LDS07 = 0xe6, ++ DBG_BLOCK_ID_LDS08 = 0xe7, ++ DBG_BLOCK_ID_LDS09 = 0xe8, ++ DBG_BLOCK_ID_LDS0A = 0xe9, ++ DBG_BLOCK_ID_LDS0B = 0xea, ++ DBG_BLOCK_ID_UNUSED39 = 0xeb, ++ DBG_BLOCK_ID_UNUSED40 = 0xec, ++ DBG_BLOCK_ID_UNUSED41 = 0xed, ++ DBG_BLOCK_ID_UNUSED42 = 0xee, ++ DBG_BLOCK_ID_LDS10 = 0xef, ++ DBG_BLOCK_ID_LDS11 = 0xf0, ++ DBG_BLOCK_ID_LDS12 = 0xf1, ++ DBG_BLOCK_ID_LDS13 = 0xf2, ++ DBG_BLOCK_ID_LDS14 = 0xf3, ++ DBG_BLOCK_ID_LDS15 = 0xf4, ++ DBG_BLOCK_ID_LDS16 = 0xf5, ++ DBG_BLOCK_ID_LDS17 = 0xf6, ++ DBG_BLOCK_ID_LDS18 = 0xf7, ++ DBG_BLOCK_ID_LDS19 = 0xf8, ++ DBG_BLOCK_ID_LDS1A = 0xf9, ++ DBG_BLOCK_ID_LDS1B = 0xfa, ++ DBG_BLOCK_ID_UNUSED43 = 0xfb, ++ DBG_BLOCK_ID_UNUSED44 = 0xfc, ++ DBG_BLOCK_ID_UNUSED45 = 0xfd, ++ DBG_BLOCK_ID_UNUSED46 = 0xfe, ++} DebugBlockId; ++typedef enum DebugBlockId_BY2 { ++ DBG_BLOCK_ID_RESERVED_BY2 = 0x0, ++ DBG_BLOCK_ID_VMC_BY2 = 0x1, ++ DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, ++ DBG_BLOCK_ID_GRBM_BY2 = 0x3, ++ DBG_BLOCK_ID_CSC_BY2 = 0x4, ++ DBG_BLOCK_ID_IH_BY2 = 0x5, ++ DBG_BLOCK_ID_SQ_BY2 = 0x6, ++ DBG_BLOCK_ID_UVD_BY2 = 0x7, ++ DBG_BLOCK_ID_SDMA0_BY2 = 0x8, ++ DBG_BLOCK_ID_SPIM_BY2 = 0x9, ++ DBG_BLOCK_ID_VC0_BY2 = 0xa, ++ DBG_BLOCK_ID_PA_BY2 = 0xb, ++ DBG_BLOCK_ID_CP0_BY2 = 0xc, ++ DBG_BLOCK_ID_CP2_BY2 = 0xd, ++ DBG_BLOCK_ID_PC0_BY2 = 0xe, ++ DBG_BLOCK_ID_BCI0_BY2 = 0xf, ++ DBG_BLOCK_ID_SXM0_BY2 = 0x10, ++ DBG_BLOCK_ID_SCT0_BY2 = 0x11, ++ DBG_BLOCK_ID_SPM0_BY2 = 0x12, ++ DBG_BLOCK_ID_BCI2_BY2 = 0x13, ++ DBG_BLOCK_ID_TCA_BY2 = 0x14, ++ DBG_BLOCK_ID_TCCA_BY2 = 0x15, ++ DBG_BLOCK_ID_MCC_BY2 = 0x16, ++ DBG_BLOCK_ID_MCC2_BY2 = 0x17, ++ DBG_BLOCK_ID_MCD_BY2 = 0x18, ++ DBG_BLOCK_ID_MCD2_BY2 = 0x19, ++ DBG_BLOCK_ID_MCD4_BY2 = 0x1a, ++ DBG_BLOCK_ID_MCB_BY2 = 0x1b, ++ DBG_BLOCK_ID_SQA_BY2 = 0x1c, ++ DBG_BLOCK_ID_SQA02_BY2 = 0x1d, ++ DBG_BLOCK_ID_SQA11_BY2 = 0x1e, ++ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, ++ DBG_BLOCK_ID_SQB_BY2 = 0x20, ++ DBG_BLOCK_ID_SQB10_BY2 = 0x21, ++ DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, ++ DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, ++ DBG_BLOCK_ID_CB_BY2 = 0x24, ++ DBG_BLOCK_ID_CB02_BY2 = 0x25, ++ DBG_BLOCK_ID_CB10_BY2 = 0x26, ++ DBG_BLOCK_ID_CB12_BY2 = 0x27, ++ DBG_BLOCK_ID_SXS_BY2 = 0x28, ++ DBG_BLOCK_ID_SXS2_BY2 = 0x29, ++ DBG_BLOCK_ID_SXS4_BY2 = 0x2a, ++ DBG_BLOCK_ID_SXS6_BY2 = 0x2b, ++ DBG_BLOCK_ID_DB_BY2 = 0x2c, ++ DBG_BLOCK_ID_DB02_BY2 = 0x2d, ++ DBG_BLOCK_ID_DB10_BY2 = 0x2e, ++ DBG_BLOCK_ID_DB12_BY2 = 0x2f, ++ DBG_BLOCK_ID_TCP_BY2 = 0x30, ++ DBG_BLOCK_ID_TCP2_BY2 = 0x31, ++ DBG_BLOCK_ID_TCP4_BY2 = 0x32, ++ DBG_BLOCK_ID_TCP6_BY2 = 0x33, ++ DBG_BLOCK_ID_TCP8_BY2 = 0x34, ++ DBG_BLOCK_ID_TCP10_BY2 = 0x35, ++ DBG_BLOCK_ID_TCP12_BY2 = 0x36, ++ DBG_BLOCK_ID_TCP14_BY2 = 0x37, ++ DBG_BLOCK_ID_TCP16_BY2 = 0x38, ++ DBG_BLOCK_ID_TCP18_BY2 = 0x39, ++ DBG_BLOCK_ID_TCP20_BY2 = 0x3a, ++ DBG_BLOCK_ID_TCP22_BY2 = 0x3b, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, ++ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, ++ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, ++ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, ++ DBG_BLOCK_ID_TCC_BY2 = 0x40, ++ DBG_BLOCK_ID_TCC2_BY2 = 0x41, ++ DBG_BLOCK_ID_TCC4_BY2 = 0x42, ++ DBG_BLOCK_ID_TCC6_BY2 = 0x43, ++ DBG_BLOCK_ID_SPS_BY2 = 0x44, ++ DBG_BLOCK_ID_SPS02_BY2 = 0x45, ++ DBG_BLOCK_ID_SPS11_BY2 = 0x46, ++ DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, ++ DBG_BLOCK_ID_TA_BY2 = 0x48, ++ DBG_BLOCK_ID_TA02_BY2 = 0x49, ++ DBG_BLOCK_ID_TA04_BY2 = 0x4a, ++ DBG_BLOCK_ID_TA06_BY2 = 0x4b, ++ DBG_BLOCK_ID_TA08_BY2 = 0x4c, ++ DBG_BLOCK_ID_TA0A_BY2 = 0x4d, ++ DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, ++ DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, ++ DBG_BLOCK_ID_TA10_BY2 = 0x50, ++ DBG_BLOCK_ID_TA12_BY2 = 0x51, ++ DBG_BLOCK_ID_TA14_BY2 = 0x52, ++ DBG_BLOCK_ID_TA16_BY2 = 0x53, ++ DBG_BLOCK_ID_TA18_BY2 = 0x54, ++ DBG_BLOCK_ID_TA1A_BY2 = 0x55, ++ DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, ++ DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, ++ DBG_BLOCK_ID_TD_BY2 = 0x58, ++ DBG_BLOCK_ID_TD02_BY2 = 0x59, ++ DBG_BLOCK_ID_TD04_BY2 = 0x5a, ++ DBG_BLOCK_ID_TD06_BY2 = 0x5b, ++ DBG_BLOCK_ID_TD08_BY2 = 0x5c, ++ DBG_BLOCK_ID_TD0A_BY2 = 0x5d, ++ DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, ++ DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, ++ DBG_BLOCK_ID_TD10_BY2 = 0x60, ++ DBG_BLOCK_ID_TD12_BY2 = 0x61, ++ DBG_BLOCK_ID_TD14_BY2 = 0x62, ++ DBG_BLOCK_ID_TD16_BY2 = 0x63, ++ DBG_BLOCK_ID_TD18_BY2 = 0x64, ++ DBG_BLOCK_ID_TD1A_BY2 = 0x65, ++ DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, ++ DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, ++ DBG_BLOCK_ID_LDS_BY2 = 0x68, ++ DBG_BLOCK_ID_LDS02_BY2 = 0x69, ++ DBG_BLOCK_ID_LDS04_BY2 = 0x6a, ++ DBG_BLOCK_ID_LDS06_BY2 = 0x6b, ++ DBG_BLOCK_ID_LDS08_BY2 = 0x6c, ++ DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, ++ DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, ++ DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, ++ DBG_BLOCK_ID_LDS10_BY2 = 0x70, ++ DBG_BLOCK_ID_LDS12_BY2 = 0x71, ++ DBG_BLOCK_ID_LDS14_BY2 = 0x72, ++ DBG_BLOCK_ID_LDS16_BY2 = 0x73, ++ DBG_BLOCK_ID_LDS18_BY2 = 0x74, ++ DBG_BLOCK_ID_LDS1A_BY2 = 0x75, ++ DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, ++ DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, ++} DebugBlockId_BY2; ++typedef enum DebugBlockId_BY4 { ++ DBG_BLOCK_ID_RESERVED_BY4 = 0x0, ++ DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, ++ DBG_BLOCK_ID_CSC_BY4 = 0x2, ++ DBG_BLOCK_ID_SQ_BY4 = 0x3, ++ DBG_BLOCK_ID_SDMA0_BY4 = 0x4, ++ DBG_BLOCK_ID_VC0_BY4 = 0x5, ++ DBG_BLOCK_ID_CP0_BY4 = 0x6, ++ DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, ++ DBG_BLOCK_ID_SXM0_BY4 = 0x8, ++ DBG_BLOCK_ID_SPM0_BY4 = 0x9, ++ DBG_BLOCK_ID_TCAA_BY4 = 0xa, ++ DBG_BLOCK_ID_MCC_BY4 = 0xb, ++ DBG_BLOCK_ID_MCD_BY4 = 0xc, ++ DBG_BLOCK_ID_MCD4_BY4 = 0xd, ++ DBG_BLOCK_ID_SQA_BY4 = 0xe, ++ DBG_BLOCK_ID_SQA11_BY4 = 0xf, ++ DBG_BLOCK_ID_SQB_BY4 = 0x10, ++ DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, ++ DBG_BLOCK_ID_CB_BY4 = 0x12, ++ DBG_BLOCK_ID_CB10_BY4 = 0x13, ++ DBG_BLOCK_ID_SXS_BY4 = 0x14, ++ DBG_BLOCK_ID_SXS4_BY4 = 0x15, ++ DBG_BLOCK_ID_DB_BY4 = 0x16, ++ DBG_BLOCK_ID_DB10_BY4 = 0x17, ++ DBG_BLOCK_ID_TCP_BY4 = 0x18, ++ DBG_BLOCK_ID_TCP4_BY4 = 0x19, ++ DBG_BLOCK_ID_TCP8_BY4 = 0x1a, ++ DBG_BLOCK_ID_TCP12_BY4 = 0x1b, ++ DBG_BLOCK_ID_TCP16_BY4 = 0x1c, ++ DBG_BLOCK_ID_TCP20_BY4 = 0x1d, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, ++ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, ++ DBG_BLOCK_ID_TCC_BY4 = 0x20, ++ DBG_BLOCK_ID_TCC4_BY4 = 0x21, ++ DBG_BLOCK_ID_SPS_BY4 = 0x22, ++ DBG_BLOCK_ID_SPS11_BY4 = 0x23, ++ DBG_BLOCK_ID_TA_BY4 = 0x24, ++ DBG_BLOCK_ID_TA04_BY4 = 0x25, ++ DBG_BLOCK_ID_TA08_BY4 = 0x26, ++ DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, ++ DBG_BLOCK_ID_TA10_BY4 = 0x28, ++ DBG_BLOCK_ID_TA14_BY4 = 0x29, ++ DBG_BLOCK_ID_TA18_BY4 = 0x2a, ++ DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, ++ DBG_BLOCK_ID_TD_BY4 = 0x2c, ++ DBG_BLOCK_ID_TD04_BY4 = 0x2d, ++ DBG_BLOCK_ID_TD08_BY4 = 0x2e, ++ DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, ++ DBG_BLOCK_ID_TD10_BY4 = 0x30, ++ DBG_BLOCK_ID_TD14_BY4 = 0x31, ++ DBG_BLOCK_ID_TD18_BY4 = 0x32, ++ DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, ++ DBG_BLOCK_ID_LDS_BY4 = 0x34, ++ DBG_BLOCK_ID_LDS04_BY4 = 0x35, ++ DBG_BLOCK_ID_LDS08_BY4 = 0x36, ++ DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, ++ DBG_BLOCK_ID_LDS10_BY4 = 0x38, ++ DBG_BLOCK_ID_LDS14_BY4 = 0x39, ++ DBG_BLOCK_ID_LDS18_BY4 = 0x3a, ++ DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, ++} DebugBlockId_BY4; ++typedef enum DebugBlockId_BY8 { ++ DBG_BLOCK_ID_RESERVED_BY8 = 0x0, ++ DBG_BLOCK_ID_CSC_BY8 = 0x1, ++ DBG_BLOCK_ID_SDMA0_BY8 = 0x2, ++ DBG_BLOCK_ID_CP0_BY8 = 0x3, ++ DBG_BLOCK_ID_SXM0_BY8 = 0x4, ++ DBG_BLOCK_ID_TCA_BY8 = 0x5, ++ DBG_BLOCK_ID_MCD_BY8 = 0x6, ++ DBG_BLOCK_ID_SQA_BY8 = 0x7, ++ DBG_BLOCK_ID_SQB_BY8 = 0x8, ++ DBG_BLOCK_ID_CB_BY8 = 0x9, ++ DBG_BLOCK_ID_SXS_BY8 = 0xa, ++ DBG_BLOCK_ID_DB_BY8 = 0xb, ++ DBG_BLOCK_ID_TCP_BY8 = 0xc, ++ DBG_BLOCK_ID_TCP8_BY8 = 0xd, ++ DBG_BLOCK_ID_TCP16_BY8 = 0xe, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, ++ DBG_BLOCK_ID_TCC_BY8 = 0x10, ++ DBG_BLOCK_ID_SPS_BY8 = 0x11, ++ DBG_BLOCK_ID_TA_BY8 = 0x12, ++ DBG_BLOCK_ID_TA08_BY8 = 0x13, ++ DBG_BLOCK_ID_TA10_BY8 = 0x14, ++ DBG_BLOCK_ID_TA18_BY8 = 0x15, ++ DBG_BLOCK_ID_TD_BY8 = 0x16, ++ DBG_BLOCK_ID_TD08_BY8 = 0x17, ++ DBG_BLOCK_ID_TD10_BY8 = 0x18, ++ DBG_BLOCK_ID_TD18_BY8 = 0x19, ++ DBG_BLOCK_ID_LDS_BY8 = 0x1a, ++ DBG_BLOCK_ID_LDS08_BY8 = 0x1b, ++ DBG_BLOCK_ID_LDS10_BY8 = 0x1c, ++ DBG_BLOCK_ID_LDS18_BY8 = 0x1d, ++} DebugBlockId_BY8; ++typedef enum DebugBlockId_BY16 { ++ DBG_BLOCK_ID_RESERVED_BY16 = 0x0, ++ DBG_BLOCK_ID_SDMA0_BY16 = 0x1, ++ DBG_BLOCK_ID_SXM_BY16 = 0x2, ++ DBG_BLOCK_ID_MCD_BY16 = 0x3, ++ DBG_BLOCK_ID_SQB_BY16 = 0x4, ++ DBG_BLOCK_ID_SXS_BY16 = 0x5, ++ DBG_BLOCK_ID_TCP_BY16 = 0x6, ++ DBG_BLOCK_ID_TCP16_BY16 = 0x7, ++ DBG_BLOCK_ID_TCC_BY16 = 0x8, ++ DBG_BLOCK_ID_TA_BY16 = 0x9, ++ DBG_BLOCK_ID_TA10_BY16 = 0xa, ++ DBG_BLOCK_ID_TD_BY16 = 0xb, ++ DBG_BLOCK_ID_TD10_BY16 = 0xc, ++ DBG_BLOCK_ID_LDS_BY16 = 0xd, ++ DBG_BLOCK_ID_LDS10_BY16 = 0xe, ++} DebugBlockId_BY16; ++typedef enum SurfaceEndian { ++ ENDIAN_NONE = 0x0, ++ ENDIAN_8IN16 = 0x1, ++ ENDIAN_8IN32 = 0x2, ++ ENDIAN_8IN64 = 0x3, ++} SurfaceEndian; ++typedef enum ArrayMode { ++ ARRAY_LINEAR_GENERAL = 0x0, ++ ARRAY_LINEAR_ALIGNED = 0x1, ++ ARRAY_1D_TILED_THIN1 = 0x2, ++ ARRAY_1D_TILED_THICK = 0x3, ++ ARRAY_2D_TILED_THIN1 = 0x4, ++ ARRAY_PRT_TILED_THIN1 = 0x5, ++ ARRAY_PRT_2D_TILED_THIN1 = 0x6, ++ ARRAY_2D_TILED_THICK = 0x7, ++ ARRAY_2D_TILED_XTHICK = 0x8, ++ ARRAY_PRT_TILED_THICK = 0x9, ++ ARRAY_PRT_2D_TILED_THICK = 0xa, ++ ARRAY_PRT_3D_TILED_THIN1 = 0xb, ++ ARRAY_3D_TILED_THIN1 = 0xc, ++ ARRAY_3D_TILED_THICK = 0xd, ++ ARRAY_3D_TILED_XTHICK = 0xe, ++ ARRAY_PRT_3D_TILED_THICK = 0xf, ++} ArrayMode; ++typedef enum PipeTiling { ++ CONFIG_1_PIPE = 0x0, ++ CONFIG_2_PIPE = 0x1, ++ CONFIG_4_PIPE = 0x2, ++ CONFIG_8_PIPE = 0x3, ++} PipeTiling; ++typedef enum BankTiling { ++ CONFIG_4_BANK = 0x0, ++ CONFIG_8_BANK = 0x1, ++} BankTiling; ++typedef enum GroupInterleave { ++ CONFIG_256B_GROUP = 0x0, ++ CONFIG_512B_GROUP = 0x1, ++} GroupInterleave; ++typedef enum RowTiling { ++ CONFIG_1KB_ROW = 0x0, ++ CONFIG_2KB_ROW = 0x1, ++ CONFIG_4KB_ROW = 0x2, ++ CONFIG_8KB_ROW = 0x3, ++ CONFIG_1KB_ROW_OPT = 0x4, ++ CONFIG_2KB_ROW_OPT = 0x5, ++ CONFIG_4KB_ROW_OPT = 0x6, ++ CONFIG_8KB_ROW_OPT = 0x7, ++} RowTiling; ++typedef enum BankSwapBytes { ++ CONFIG_128B_SWAPS = 0x0, ++ CONFIG_256B_SWAPS = 0x1, ++ CONFIG_512B_SWAPS = 0x2, ++ CONFIG_1KB_SWAPS = 0x3, ++} BankSwapBytes; ++typedef enum SampleSplitBytes { ++ CONFIG_1KB_SPLIT = 0x0, ++ CONFIG_2KB_SPLIT = 0x1, ++ CONFIG_4KB_SPLIT = 0x2, ++ CONFIG_8KB_SPLIT = 0x3, ++} SampleSplitBytes; ++typedef enum NumPipes { ++ ADDR_CONFIG_1_PIPE = 0x0, ++ ADDR_CONFIG_2_PIPE = 0x1, ++ ADDR_CONFIG_4_PIPE = 0x2, ++ ADDR_CONFIG_8_PIPE = 0x3, ++} NumPipes; ++typedef enum PipeInterleaveSize { ++ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, ++ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, ++} PipeInterleaveSize; ++typedef enum BankInterleaveSize { ++ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, ++ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, ++ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, ++ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, ++} BankInterleaveSize; ++typedef enum NumShaderEngines { ++ ADDR_CONFIG_1_SHADER_ENGINE = 0x0, ++ ADDR_CONFIG_2_SHADER_ENGINE = 0x1, ++} NumShaderEngines; ++typedef enum ShaderEngineTileSize { ++ ADDR_CONFIG_SE_TILE_16 = 0x0, ++ ADDR_CONFIG_SE_TILE_32 = 0x1, ++} ShaderEngineTileSize; ++typedef enum NumGPUs { ++ ADDR_CONFIG_1_GPU = 0x0, ++ ADDR_CONFIG_2_GPU = 0x1, ++ ADDR_CONFIG_4_GPU = 0x2, ++} NumGPUs; ++typedef enum MultiGPUTileSize { ++ ADDR_CONFIG_GPU_TILE_16 = 0x0, ++ ADDR_CONFIG_GPU_TILE_32 = 0x1, ++ ADDR_CONFIG_GPU_TILE_64 = 0x2, ++ ADDR_CONFIG_GPU_TILE_128 = 0x3, ++} MultiGPUTileSize; ++typedef enum RowSize { ++ ADDR_CONFIG_1KB_ROW = 0x0, ++ ADDR_CONFIG_2KB_ROW = 0x1, ++ ADDR_CONFIG_4KB_ROW = 0x2, ++} RowSize; ++typedef enum NumLowerPipes { ++ ADDR_CONFIG_1_LOWER_PIPES = 0x0, ++ ADDR_CONFIG_2_LOWER_PIPES = 0x1, ++} NumLowerPipes; ++typedef enum ColorTransform { ++ DCC_CT_AUTO = 0x0, ++ DCC_CT_NONE = 0x1, ++ ABGR_TO_A_BG_G_RB = 0x2, ++ BGRA_TO_BG_G_RB_A = 0x3, ++} ColorTransform; ++typedef enum CompareRef { ++ REF_NEVER = 0x0, ++ REF_LESS = 0x1, ++ REF_EQUAL = 0x2, ++ REF_LEQUAL = 0x3, ++ REF_GREATER = 0x4, ++ REF_NOTEQUAL = 0x5, ++ REF_GEQUAL = 0x6, ++ REF_ALWAYS = 0x7, ++} CompareRef; ++typedef enum ReadSize { ++ READ_256_BITS = 0x0, ++ READ_512_BITS = 0x1, ++} ReadSize; ++typedef enum DepthFormat { ++ DEPTH_INVALID = 0x0, ++ DEPTH_16 = 0x1, ++ DEPTH_X8_24 = 0x2, ++ DEPTH_8_24 = 0x3, ++ DEPTH_X8_24_FLOAT = 0x4, ++ DEPTH_8_24_FLOAT = 0x5, ++ DEPTH_32_FLOAT = 0x6, ++ DEPTH_X24_8_32_FLOAT = 0x7, ++} DepthFormat; ++typedef enum ZFormat { ++ Z_INVALID = 0x0, ++ Z_16 = 0x1, ++ Z_24 = 0x2, ++ Z_32_FLOAT = 0x3, ++} ZFormat; ++typedef enum StencilFormat { ++ STENCIL_INVALID = 0x0, ++ STENCIL_8 = 0x1, ++} StencilFormat; ++typedef enum CmaskMode { ++ CMASK_CLEAR_NONE = 0x0, ++ CMASK_CLEAR_ONE = 0x1, ++ CMASK_CLEAR_ALL = 0x2, ++ CMASK_ANY_EXPANDED = 0x3, ++ CMASK_ALPHA0_FRAG1 = 0x4, ++ CMASK_ALPHA0_FRAG2 = 0x5, ++ CMASK_ALPHA0_FRAG4 = 0x6, ++ CMASK_ALPHA0_FRAGS = 0x7, ++ CMASK_ALPHA1_FRAG1 = 0x8, ++ CMASK_ALPHA1_FRAG2 = 0x9, ++ CMASK_ALPHA1_FRAG4 = 0xa, ++ CMASK_ALPHA1_FRAGS = 0xb, ++ CMASK_ALPHAX_FRAG1 = 0xc, ++ CMASK_ALPHAX_FRAG2 = 0xd, ++ CMASK_ALPHAX_FRAG4 = 0xe, ++ CMASK_ALPHAX_FRAGS = 0xf, ++} CmaskMode; ++typedef enum QuadExportFormat { ++ EXPORT_UNUSED = 0x0, ++ EXPORT_32_R = 0x1, ++ EXPORT_32_GR = 0x2, ++ EXPORT_32_AR = 0x3, ++ EXPORT_FP16_ABGR = 0x4, ++ EXPORT_UNSIGNED16_ABGR = 0x5, ++ EXPORT_SIGNED16_ABGR = 0x6, ++ EXPORT_32_ABGR = 0x7, ++} QuadExportFormat; ++typedef enum QuadExportFormatOld { ++ EXPORT_4P_32BPC_ABGR = 0x0, ++ EXPORT_4P_16BPC_ABGR = 0x1, ++ EXPORT_4P_32BPC_GR = 0x2, ++ EXPORT_4P_32BPC_AR = 0x3, ++ EXPORT_2P_32BPC_ABGR = 0x4, ++ EXPORT_8P_32BPC_R = 0x5, ++} QuadExportFormatOld; ++typedef enum ColorFormat { ++ COLOR_INVALID = 0x0, ++ COLOR_8 = 0x1, ++ COLOR_16 = 0x2, ++ COLOR_8_8 = 0x3, ++ COLOR_32 = 0x4, ++ COLOR_16_16 = 0x5, ++ COLOR_10_11_11 = 0x6, ++ COLOR_11_11_10 = 0x7, ++ COLOR_10_10_10_2 = 0x8, ++ COLOR_2_10_10_10 = 0x9, ++ COLOR_8_8_8_8 = 0xa, ++ COLOR_32_32 = 0xb, ++ COLOR_16_16_16_16 = 0xc, ++ COLOR_RESERVED_13 = 0xd, ++ COLOR_32_32_32_32 = 0xe, ++ COLOR_RESERVED_15 = 0xf, ++ COLOR_5_6_5 = 0x10, ++ COLOR_1_5_5_5 = 0x11, ++ COLOR_5_5_5_1 = 0x12, ++ COLOR_4_4_4_4 = 0x13, ++ COLOR_8_24 = 0x14, ++ COLOR_24_8 = 0x15, ++ COLOR_X24_8_32_FLOAT = 0x16, ++ COLOR_RESERVED_23 = 0x17, ++} ColorFormat; ++typedef enum SurfaceFormat { ++ FMT_INVALID = 0x0, ++ FMT_8 = 0x1, ++ FMT_16 = 0x2, ++ FMT_8_8 = 0x3, ++ FMT_32 = 0x4, ++ FMT_16_16 = 0x5, ++ FMT_10_11_11 = 0x6, ++ FMT_11_11_10 = 0x7, ++ FMT_10_10_10_2 = 0x8, ++ FMT_2_10_10_10 = 0x9, ++ FMT_8_8_8_8 = 0xa, ++ FMT_32_32 = 0xb, ++ FMT_16_16_16_16 = 0xc, ++ FMT_32_32_32 = 0xd, ++ FMT_32_32_32_32 = 0xe, ++ FMT_RESERVED_4 = 0xf, ++ FMT_5_6_5 = 0x10, ++ FMT_1_5_5_5 = 0x11, ++ FMT_5_5_5_1 = 0x12, ++ FMT_4_4_4_4 = 0x13, ++ FMT_8_24 = 0x14, ++ FMT_24_8 = 0x15, ++ FMT_X24_8_32_FLOAT = 0x16, ++ FMT_RESERVED_33 = 0x17, ++ FMT_11_11_10_FLOAT = 0x18, ++ FMT_16_FLOAT = 0x19, ++ FMT_32_FLOAT = 0x1a, ++ FMT_16_16_FLOAT = 0x1b, ++ FMT_8_24_FLOAT = 0x1c, ++ FMT_24_8_FLOAT = 0x1d, ++ FMT_32_32_FLOAT = 0x1e, ++ FMT_10_11_11_FLOAT = 0x1f, ++ FMT_16_16_16_16_FLOAT = 0x20, ++ FMT_3_3_2 = 0x21, ++ FMT_6_5_5 = 0x22, ++ FMT_32_32_32_32_FLOAT = 0x23, ++ FMT_RESERVED_36 = 0x24, ++ FMT_1 = 0x25, ++ FMT_1_REVERSED = 0x26, ++ FMT_GB_GR = 0x27, ++ FMT_BG_RG = 0x28, ++ FMT_32_AS_8 = 0x29, ++ FMT_32_AS_8_8 = 0x2a, ++ FMT_5_9_9_9_SHAREDEXP = 0x2b, ++ FMT_8_8_8 = 0x2c, ++ FMT_16_16_16 = 0x2d, ++ FMT_16_16_16_FLOAT = 0x2e, ++ FMT_4_4 = 0x2f, ++ FMT_32_32_32_FLOAT = 0x30, ++ FMT_BC1 = 0x31, ++ FMT_BC2 = 0x32, ++ FMT_BC3 = 0x33, ++ FMT_BC4 = 0x34, ++ FMT_BC5 = 0x35, ++ FMT_BC6 = 0x36, ++ FMT_BC7 = 0x37, ++ FMT_32_AS_32_32_32_32 = 0x38, ++ FMT_APC3 = 0x39, ++ FMT_APC4 = 0x3a, ++ FMT_APC5 = 0x3b, ++ FMT_APC6 = 0x3c, ++ FMT_APC7 = 0x3d, ++ FMT_CTX1 = 0x3e, ++ FMT_RESERVED_63 = 0x3f, ++} SurfaceFormat; ++typedef enum BUF_DATA_FORMAT { ++ BUF_DATA_FORMAT_INVALID = 0x0, ++ BUF_DATA_FORMAT_8 = 0x1, ++ BUF_DATA_FORMAT_16 = 0x2, ++ BUF_DATA_FORMAT_8_8 = 0x3, ++ BUF_DATA_FORMAT_32 = 0x4, ++ BUF_DATA_FORMAT_16_16 = 0x5, ++ BUF_DATA_FORMAT_10_11_11 = 0x6, ++ BUF_DATA_FORMAT_11_11_10 = 0x7, ++ BUF_DATA_FORMAT_10_10_10_2 = 0x8, ++ BUF_DATA_FORMAT_2_10_10_10 = 0x9, ++ BUF_DATA_FORMAT_8_8_8_8 = 0xa, ++ BUF_DATA_FORMAT_32_32 = 0xb, ++ BUF_DATA_FORMAT_16_16_16_16 = 0xc, ++ BUF_DATA_FORMAT_32_32_32 = 0xd, ++ BUF_DATA_FORMAT_32_32_32_32 = 0xe, ++ BUF_DATA_FORMAT_RESERVED_15 = 0xf, ++} BUF_DATA_FORMAT; ++typedef enum IMG_DATA_FORMAT { ++ IMG_DATA_FORMAT_INVALID = 0x0, ++ IMG_DATA_FORMAT_8 = 0x1, ++ IMG_DATA_FORMAT_16 = 0x2, ++ IMG_DATA_FORMAT_8_8 = 0x3, ++ IMG_DATA_FORMAT_32 = 0x4, ++ IMG_DATA_FORMAT_16_16 = 0x5, ++ IMG_DATA_FORMAT_10_11_11 = 0x6, ++ IMG_DATA_FORMAT_11_11_10 = 0x7, ++ IMG_DATA_FORMAT_10_10_10_2 = 0x8, ++ IMG_DATA_FORMAT_2_10_10_10 = 0x9, ++ IMG_DATA_FORMAT_8_8_8_8 = 0xa, ++ IMG_DATA_FORMAT_32_32 = 0xb, ++ IMG_DATA_FORMAT_16_16_16_16 = 0xc, ++ IMG_DATA_FORMAT_32_32_32 = 0xd, ++ IMG_DATA_FORMAT_32_32_32_32 = 0xe, ++ IMG_DATA_FORMAT_RESERVED_15 = 0xf, ++ IMG_DATA_FORMAT_5_6_5 = 0x10, ++ IMG_DATA_FORMAT_1_5_5_5 = 0x11, ++ IMG_DATA_FORMAT_5_5_5_1 = 0x12, ++ IMG_DATA_FORMAT_4_4_4_4 = 0x13, ++ IMG_DATA_FORMAT_8_24 = 0x14, ++ IMG_DATA_FORMAT_24_8 = 0x15, ++ IMG_DATA_FORMAT_X24_8_32 = 0x16, ++ IMG_DATA_FORMAT_RESERVED_23 = 0x17, ++ IMG_DATA_FORMAT_RESERVED_24 = 0x18, ++ IMG_DATA_FORMAT_RESERVED_25 = 0x19, ++ IMG_DATA_FORMAT_RESERVED_26 = 0x1a, ++ IMG_DATA_FORMAT_RESERVED_27 = 0x1b, ++ IMG_DATA_FORMAT_RESERVED_28 = 0x1c, ++ IMG_DATA_FORMAT_RESERVED_29 = 0x1d, ++ IMG_DATA_FORMAT_RESERVED_30 = 0x1e, ++ IMG_DATA_FORMAT_RESERVED_31 = 0x1f, ++ IMG_DATA_FORMAT_GB_GR = 0x20, ++ IMG_DATA_FORMAT_BG_RG = 0x21, ++ IMG_DATA_FORMAT_5_9_9_9 = 0x22, ++ IMG_DATA_FORMAT_BC1 = 0x23, ++ IMG_DATA_FORMAT_BC2 = 0x24, ++ IMG_DATA_FORMAT_BC3 = 0x25, ++ IMG_DATA_FORMAT_BC4 = 0x26, ++ IMG_DATA_FORMAT_BC5 = 0x27, ++ IMG_DATA_FORMAT_BC6 = 0x28, ++ IMG_DATA_FORMAT_BC7 = 0x29, ++ IMG_DATA_FORMAT_RESERVED_42 = 0x2a, ++ IMG_DATA_FORMAT_RESERVED_43 = 0x2b, ++ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, ++ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, ++ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, ++ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, ++ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, ++ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, ++ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, ++ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, ++ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, ++ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, ++ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, ++ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, ++ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, ++ IMG_DATA_FORMAT_4_4 = 0x39, ++ IMG_DATA_FORMAT_6_5_5 = 0x3a, ++ IMG_DATA_FORMAT_1 = 0x3b, ++ IMG_DATA_FORMAT_1_REVERSED = 0x3c, ++ IMG_DATA_FORMAT_32_AS_8 = 0x3d, ++ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, ++ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, ++} IMG_DATA_FORMAT; ++typedef enum BUF_NUM_FORMAT { ++ BUF_NUM_FORMAT_UNORM = 0x0, ++ BUF_NUM_FORMAT_SNORM = 0x1, ++ BUF_NUM_FORMAT_USCALED = 0x2, ++ BUF_NUM_FORMAT_SSCALED = 0x3, ++ BUF_NUM_FORMAT_UINT = 0x4, ++ BUF_NUM_FORMAT_SINT = 0x5, ++ BUF_NUM_FORMAT_RESERVED_6 = 0x6, ++ BUF_NUM_FORMAT_FLOAT = 0x7, ++} BUF_NUM_FORMAT; ++typedef enum IMG_NUM_FORMAT { ++ IMG_NUM_FORMAT_UNORM = 0x0, ++ IMG_NUM_FORMAT_SNORM = 0x1, ++ IMG_NUM_FORMAT_USCALED = 0x2, ++ IMG_NUM_FORMAT_SSCALED = 0x3, ++ IMG_NUM_FORMAT_UINT = 0x4, ++ IMG_NUM_FORMAT_SINT = 0x5, ++ IMG_NUM_FORMAT_RESERVED_6 = 0x6, ++ IMG_NUM_FORMAT_FLOAT = 0x7, ++ IMG_NUM_FORMAT_RESERVED_8 = 0x8, ++ IMG_NUM_FORMAT_SRGB = 0x9, ++ IMG_NUM_FORMAT_RESERVED_10 = 0xa, ++ IMG_NUM_FORMAT_RESERVED_11 = 0xb, ++ IMG_NUM_FORMAT_RESERVED_12 = 0xc, ++ IMG_NUM_FORMAT_RESERVED_13 = 0xd, ++ IMG_NUM_FORMAT_RESERVED_14 = 0xe, ++ IMG_NUM_FORMAT_RESERVED_15 = 0xf, ++} IMG_NUM_FORMAT; ++typedef enum TileType { ++ ARRAY_COLOR_TILE = 0x0, ++ ARRAY_DEPTH_TILE = 0x1, ++} TileType; ++typedef enum NonDispTilingOrder { ++ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, ++ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, ++} NonDispTilingOrder; ++typedef enum MicroTileMode { ++ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, ++ ADDR_SURF_THIN_MICRO_TILING = 0x1, ++ ADDR_SURF_DEPTH_MICRO_TILING = 0x2, ++ ADDR_SURF_ROTATED_MICRO_TILING = 0x3, ++ ADDR_SURF_THICK_MICRO_TILING = 0x4, ++} MicroTileMode; ++typedef enum TileSplit { ++ ADDR_SURF_TILE_SPLIT_64B = 0x0, ++ ADDR_SURF_TILE_SPLIT_128B = 0x1, ++ ADDR_SURF_TILE_SPLIT_256B = 0x2, ++ ADDR_SURF_TILE_SPLIT_512B = 0x3, ++ ADDR_SURF_TILE_SPLIT_1KB = 0x4, ++ ADDR_SURF_TILE_SPLIT_2KB = 0x5, ++ ADDR_SURF_TILE_SPLIT_4KB = 0x6, ++} TileSplit; ++typedef enum SampleSplit { ++ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, ++ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, ++ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, ++ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, ++} SampleSplit; ++typedef enum PipeConfig { ++ ADDR_SURF_P2 = 0x0, ++ ADDR_SURF_P2_RESERVED0 = 0x1, ++ ADDR_SURF_P2_RESERVED1 = 0x2, ++ ADDR_SURF_P2_RESERVED2 = 0x3, ++ ADDR_SURF_P4_8x16 = 0x4, ++ ADDR_SURF_P4_16x16 = 0x5, ++ ADDR_SURF_P4_16x32 = 0x6, ++ ADDR_SURF_P4_32x32 = 0x7, ++ ADDR_SURF_P8_16x16_8x16 = 0x8, ++ ADDR_SURF_P8_16x32_8x16 = 0x9, ++ ADDR_SURF_P8_32x32_8x16 = 0xa, ++ ADDR_SURF_P8_16x32_16x16 = 0xb, ++ ADDR_SURF_P8_32x32_16x16 = 0xc, ++ ADDR_SURF_P8_32x32_16x32 = 0xd, ++ ADDR_SURF_P8_32x64_32x32 = 0xe, ++ ADDR_SURF_P8_RESERVED0 = 0xf, ++ ADDR_SURF_P16_32x32_8x16 = 0x10, ++ ADDR_SURF_P16_32x32_16x16 = 0x11, ++} PipeConfig; ++typedef enum NumBanks { ++ ADDR_SURF_2_BANK = 0x0, ++ ADDR_SURF_4_BANK = 0x1, ++ ADDR_SURF_8_BANK = 0x2, ++ ADDR_SURF_16_BANK = 0x3, ++} NumBanks; ++typedef enum BankWidth { ++ ADDR_SURF_BANK_WIDTH_1 = 0x0, ++ ADDR_SURF_BANK_WIDTH_2 = 0x1, ++ ADDR_SURF_BANK_WIDTH_4 = 0x2, ++ ADDR_SURF_BANK_WIDTH_8 = 0x3, ++} BankWidth; ++typedef enum BankHeight { ++ ADDR_SURF_BANK_HEIGHT_1 = 0x0, ++ ADDR_SURF_BANK_HEIGHT_2 = 0x1, ++ ADDR_SURF_BANK_HEIGHT_4 = 0x2, ++ ADDR_SURF_BANK_HEIGHT_8 = 0x3, ++} BankHeight; ++typedef enum BankWidthHeight { ++ ADDR_SURF_BANK_WH_1 = 0x0, ++ ADDR_SURF_BANK_WH_2 = 0x1, ++ ADDR_SURF_BANK_WH_4 = 0x2, ++ ADDR_SURF_BANK_WH_8 = 0x3, ++} BankWidthHeight; ++typedef enum MacroTileAspect { ++ ADDR_SURF_MACRO_ASPECT_1 = 0x0, ++ ADDR_SURF_MACRO_ASPECT_2 = 0x1, ++ ADDR_SURF_MACRO_ASPECT_4 = 0x2, ++ ADDR_SURF_MACRO_ASPECT_8 = 0x3, ++} MacroTileAspect; ++typedef enum GATCL1RequestType { ++ GATCL1_TYPE_NORMAL = 0x0, ++ GATCL1_TYPE_SHOOTDOWN = 0x1, ++ GATCL1_TYPE_BYPASS = 0x2, ++} GATCL1RequestType; ++typedef enum TCC_CACHE_POLICIES { ++ TCC_CACHE_POLICY_LRU = 0x0, ++ TCC_CACHE_POLICY_STREAM = 0x1, ++} TCC_CACHE_POLICIES; ++typedef enum MTYPE { ++ MTYPE_NC_NV = 0x0, ++ MTYPE_NC = 0x1, ++ MTYPE_CC = 0x2, ++ MTYPE_UC = 0x3, ++} MTYPE; ++typedef enum PERFMON_COUNTER_MODE { ++ PERFMON_COUNTER_MODE_ACCUM = 0x0, ++ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, ++ PERFMON_COUNTER_MODE_MAX = 0x2, ++ PERFMON_COUNTER_MODE_DIRTY = 0x3, ++ PERFMON_COUNTER_MODE_SAMPLE = 0x4, ++ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, ++ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, ++ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, ++ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, ++ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, ++ PERFMON_COUNTER_MODE_RESERVED = 0xf, ++} PERFMON_COUNTER_MODE; ++typedef enum PERFMON_SPM_MODE { ++ PERFMON_SPM_MODE_OFF = 0x0, ++ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, ++ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, ++ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, ++ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, ++ PERFMON_SPM_MODE_RESERVED_5 = 0x5, ++ PERFMON_SPM_MODE_RESERVED_6 = 0x6, ++ PERFMON_SPM_MODE_RESERVED_7 = 0x7, ++ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, ++ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, ++ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, ++} PERFMON_SPM_MODE; ++typedef enum SurfaceTiling { ++ ARRAY_LINEAR = 0x0, ++ ARRAY_TILED = 0x1, ++} SurfaceTiling; ++typedef enum SurfaceArray { ++ ARRAY_1D = 0x0, ++ ARRAY_2D = 0x1, ++ ARRAY_3D = 0x2, ++ ARRAY_3D_SLICE = 0x3, ++} SurfaceArray; ++typedef enum ColorArray { ++ ARRAY_2D_ALT_COLOR = 0x0, ++ ARRAY_2D_COLOR = 0x1, ++ ARRAY_3D_SLICE_COLOR = 0x3, ++} ColorArray; ++typedef enum DepthArray { ++ ARRAY_2D_ALT_DEPTH = 0x0, ++ ARRAY_2D_DEPTH = 0x1, ++} DepthArray; ++typedef enum ENUM_NUM_SIMD_PER_CU { ++ NUM_SIMD_PER_CU = 0x4, ++} ENUM_NUM_SIMD_PER_CU; ++typedef enum MEM_PWR_FORCE_CTRL { ++ NO_FORCE_REQUEST = 0x0, ++ FORCE_LIGHT_SLEEP_REQUEST = 0x1, ++ FORCE_DEEP_SLEEP_REQUEST = 0x2, ++ FORCE_SHUT_DOWN_REQUEST = 0x3, ++} MEM_PWR_FORCE_CTRL; ++typedef enum MEM_PWR_FORCE_CTRL2 { ++ NO_FORCE_REQ = 0x0, ++ FORCE_LIGHT_SLEEP_REQ = 0x1, ++} MEM_PWR_FORCE_CTRL2; ++typedef enum MEM_PWR_DIS_CTRL { ++ ENABLE_MEM_PWR_CTRL = 0x0, ++ DISABLE_MEM_PWR_CTRL = 0x1, ++} MEM_PWR_DIS_CTRL; ++typedef enum MEM_PWR_SEL_CTRL { ++ DYNAMIC_SHUT_DOWN_ENABLE = 0x0, ++ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, ++ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, ++} MEM_PWR_SEL_CTRL; ++typedef enum MEM_PWR_SEL_CTRL2 { ++ DYNAMIC_DEEP_SLEEP_EN = 0x0, ++ DYNAMIC_LIGHT_SLEEP_EN = 0x1, ++} MEM_PWR_SEL_CTRL2; ++ ++#endif /* GMC_8_2_ENUM_H */ +diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h +new file mode 100644 +index 0000000..c5dd8ec +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h +@@ -0,0 +1,7850 @@ ++/* ++ * GMC_8_2 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef GMC_8_2_SH_MASK_H ++#define GMC_8_2_SH_MASK_H ++ ++#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 ++#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 ++#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 ++#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 ++#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 ++#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 ++#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 ++#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 ++#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 ++#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 ++#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20 ++#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5 ++#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40 ++#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6 ++#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80 ++#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7 ++#define MC_CONFIG__MC_RD_ENABLE_MASK 0x700 ++#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8 ++#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000 ++#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f ++#define MC_ARB_ATOMIC__TC_GRP_MASK 0x7 ++#define MC_ARB_ATOMIC__TC_GRP__SHIFT 0x0 ++#define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8 ++#define MC_ARB_ATOMIC__TC_GRP_EN__SHIFT 0x3 ++#define MC_ARB_ATOMIC__SDMA_GRP_MASK 0x70 ++#define MC_ARB_ATOMIC__SDMA_GRP__SHIFT 0x4 ++#define MC_ARB_ATOMIC__SDMA_GRP_EN_MASK 0x80 ++#define MC_ARB_ATOMIC__SDMA_GRP_EN__SHIFT 0x7 ++#define MC_ARB_ATOMIC__OUTSTANDING_MASK 0xff00 ++#define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8 ++#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP_MASK 0xff0000 ++#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP__SHIFT 0x10 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80 ++#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7 ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100 ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8 ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200 ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9 ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400 ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800 ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000 ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000 ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000 ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000 ++#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf ++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000 ++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10 ++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000 ++#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13 ++#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000 ++#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16 ++#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000 ++#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17 ++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000 ++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18 ++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000 ++#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19 ++#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff ++#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0 ++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100 ++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8 ++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200 ++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9 ++#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400 ++#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa ++#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800 ++#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb ++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000 ++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc ++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000 ++#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd ++#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD_MASK 0x4000 ++#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD__SHIFT 0xe ++#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR_MASK 0x8000 ++#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR__SHIFT 0xf ++#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED_MASK 0xff0000 ++#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT 0x10 ++#define MC_ARB_FED_CNTL__MODE_MASK 0x3 ++#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0 ++#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc ++#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2 ++#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10 ++#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4 ++#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20 ++#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5 ++#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40 ++#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6 ++#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80 ++#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7 ++#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1 ++#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0 ++#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2 ++#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1 ++#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4 ++#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2 ++#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8 ++#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3 ++#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10 ++#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4 ++#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20 ++#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5 ++#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40 ++#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6 ++#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80 ++#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7 ++#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100 ++#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8 ++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200 ++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9 ++#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400 ++#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa ++#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800 ++#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb ++#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000 ++#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc ++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000 ++#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd ++#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000 ++#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe ++#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000 ++#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf ++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000 ++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10 ++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000 ++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11 ++#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000 ++#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12 ++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000 ++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14 ++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000 ++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15 ++#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000 ++#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16 ++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000 ++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18 ++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000 ++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19 ++#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000 ++#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a ++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000 ++#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c ++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000 ++#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d ++#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf ++#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0 ++#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10 ++#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4 ++#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20 ++#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5 ++#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40 ++#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6 ++#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80 ++#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7 ++#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100 ++#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8 ++#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200 ++#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9 ++#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400 ++#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa ++#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800 ++#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb ++#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000 ++#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc ++#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000 ++#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd ++#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3 ++#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0 ++#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4 ++#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2 ++#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18 ++#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3 ++#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20 ++#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5 ++#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff ++#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0 ++#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00 ++#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8 ++#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000 ++#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10 ++#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000 ++#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18 ++#define MC_ARB_PERF_CID__CH0_MASK 0xff ++#define MC_ARB_PERF_CID__CH0__SHIFT 0x0 ++#define MC_ARB_PERF_CID__CH1_MASK 0xff00 ++#define MC_ARB_PERF_CID__CH1__SHIFT 0x8 ++#define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000 ++#define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10 ++#define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000 ++#define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11 ++#define MC_ARB_SNOOP__TC_GRP_RD_MASK 0x7 ++#define MC_ARB_SNOOP__TC_GRP_RD__SHIFT 0x0 ++#define MC_ARB_SNOOP__TC_GRP_RD_EN_MASK 0x8 ++#define MC_ARB_SNOOP__TC_GRP_RD_EN__SHIFT 0x3 ++#define MC_ARB_SNOOP__TC_GRP_WR_MASK 0x70 ++#define MC_ARB_SNOOP__TC_GRP_WR__SHIFT 0x4 ++#define MC_ARB_SNOOP__TC_GRP_WR_EN_MASK 0x80 ++#define MC_ARB_SNOOP__TC_GRP_WR_EN__SHIFT 0x7 ++#define MC_ARB_SNOOP__SDMA_GRP_RD_MASK 0x700 ++#define MC_ARB_SNOOP__SDMA_GRP_RD__SHIFT 0x8 ++#define MC_ARB_SNOOP__SDMA_GRP_RD_EN_MASK 0x800 ++#define MC_ARB_SNOOP__SDMA_GRP_RD_EN__SHIFT 0xb ++#define MC_ARB_SNOOP__SDMA_GRP_WR_MASK 0x7000 ++#define MC_ARB_SNOOP__SDMA_GRP_WR__SHIFT 0xc ++#define MC_ARB_SNOOP__SDMA_GRP_WR_EN_MASK 0x8000 ++#define MC_ARB_SNOOP__SDMA_GRP_WR_EN__SHIFT 0xf ++#define MC_ARB_SNOOP__OUTSTANDING_RD_MASK 0xff0000 ++#define MC_ARB_SNOOP__OUTSTANDING_RD__SHIFT 0x10 ++#define MC_ARB_SNOOP__OUTSTANDING_WR_MASK 0xff000000 ++#define MC_ARB_SNOOP__OUTSTANDING_WR__SHIFT 0x18 ++#define MC_ARB_GRUB__GRUB_WATERMARK_MASK 0xff ++#define MC_ARB_GRUB__GRUB_WATERMARK__SHIFT 0x0 ++#define MC_ARB_GRUB__GRUB_WATERMARK_PRI_MASK 0xff00 ++#define MC_ARB_GRUB__GRUB_WATERMARK_PRI__SHIFT 0x8 ++#define MC_ARB_GRUB__GRUB_WATERMARK_MED_MASK 0xff0000 ++#define MC_ARB_GRUB__GRUB_WATERMARK_MED__SHIFT 0x10 ++#define MC_ARB_GRUB__REG_WR_EN_MASK 0x3000000 ++#define MC_ARB_GRUB__REG_WR_EN__SHIFT 0x18 ++#define MC_ARB_GRUB__REG_RD_SEL_MASK 0x4000000 ++#define MC_ARB_GRUB__REG_RD_SEL__SHIFT 0x1a ++#define MC_ARB_GECC2__ENABLE_MASK 0x1 ++#define MC_ARB_GECC2__ENABLE__SHIFT 0x0 ++#define MC_ARB_GECC2__ECC_MODE_MASK 0x6 ++#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1 ++#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18 ++#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3 ++#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60 ++#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5 ++#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780 ++#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7 ++#define MC_ARB_GECC2__READ_ERR_MASK 0x3800 ++#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb ++#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000 ++#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe ++#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000 ++#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf ++#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000 ++#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15 ++#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000 ++#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16 ++#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff ++#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0 ++#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00 ++#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8 ++#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000 ++#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10 ++#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000 ++#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18 ++#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf ++#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0 ++#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0 ++#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4 ++#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00 ++#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8 ++#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000 ++#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc ++#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000 ++#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10 ++#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000 ++#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14 ++#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000 ++#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18 ++#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000 ++#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c ++#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf ++#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0 ++#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0 ++#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4 ++#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00 ++#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8 ++#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000 ++#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc ++#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1 ++#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0 ++#define MC_ARB_MISC3__CHAN4_EN_MASK 0x2 ++#define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1 ++#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4 ++#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2 ++#define MC_ARB_MISC3__UVD_URG_MODE_MASK 0x8 ++#define MC_ARB_MISC3__UVD_URG_MODE__SHIFT 0x3 ++#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN_MASK 0x10 ++#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN__SHIFT 0x4 ++#define MC_ARB_MISC3__TBD_FIELD_MASK 0xffffffe0 ++#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x5 ++#define MC_ARB_GRUB_PROMOTE__URGENT_RD_MASK 0xff ++#define MC_ARB_GRUB_PROMOTE__URGENT_RD__SHIFT 0x0 ++#define MC_ARB_GRUB_PROMOTE__URGENT_WR_MASK 0xff00 ++#define MC_ARB_GRUB_PROMOTE__URGENT_WR__SHIFT 0x8 ++#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD_MASK 0xff0000 ++#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD__SHIFT 0x10 ++#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR_MASK 0xff000000 ++#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR__SHIFT 0x18 ++#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff ++#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0 ++#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1 ++#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0 ++#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2 ++#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1 ++#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc ++#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2 ++#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10 ++#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4 ++#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20 ++#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5 ++#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40 ++#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6 ++#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80 ++#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7 ++#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100 ++#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8 ++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200 ++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9 ++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400 ++#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa ++#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800 ++#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb ++#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000 ++#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000 ++#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17 ++#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000 ++#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18 ++#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000 ++#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19 ++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f ++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0 ++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20 ++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5 ++#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0 ++#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6 ++#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000 ++#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd ++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000 ++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14 ++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000 ++#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19 ++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000 ++#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e ++#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f ++#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0 ++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0 ++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6 ++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000 ++#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc ++#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000 ++#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd ++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3 ++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0 ++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc ++#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2 ++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0 ++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4 ++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000 ++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc ++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000 ++#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11 ++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000 ++#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19 ++#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1 ++#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0 ++#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e ++#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1 ++#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80 ++#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7 ++#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000 ++#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd ++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20 ++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5 ++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40 ++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6 ++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80 ++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7 ++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100 ++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8 ++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200 ++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9 ++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400 ++#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa ++#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800 ++#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb ++#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000 ++#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc ++#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000 ++#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd ++#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000 ++#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe ++#define MC_ARB_MISC2__GECC_MASK 0x40000 ++#define MC_ARB_MISC2__GECC__SHIFT 0x12 ++#define MC_ARB_MISC2__GECC_RST_MASK 0x80000 ++#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13 ++#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000 ++#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14 ++#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000 ++#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15 ++#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000 ++#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19 ++#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000 ++#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c ++#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000 ++#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d ++#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000 ++#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e ++#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000 ++#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f ++#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1 ++#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0 ++#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2 ++#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1 ++#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4 ++#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2 ++#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8 ++#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3 ++#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800 ++#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb ++#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000 ++#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13 ++#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000 ++#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14 ++#define MC_ARB_MISC__CALI_RATES_MASK 0x600000 ++#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15 ++#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000 ++#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17 ++#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000 ++#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18 ++#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000 ++#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19 ++#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000 ++#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a ++#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000 ++#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e ++#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000 ++#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f ++#define MC_ARB_BANKMAP__BANK0_MASK 0xf ++#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0 ++#define MC_ARB_BANKMAP__BANK1_MASK 0xf0 ++#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4 ++#define MC_ARB_BANKMAP__BANK2_MASK 0xf00 ++#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8 ++#define MC_ARB_BANKMAP__BANK3_MASK 0xf000 ++#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc ++#define MC_ARB_BANKMAP__RANK_MASK 0xf0000 ++#define MC_ARB_BANKMAP__RANK__SHIFT 0x10 ++#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3 ++#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0 ++#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4 ++#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2 ++#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38 ++#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3 ++#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0 ++#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6 ++#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100 ++#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8 ++#define MC_ARB_RAMCFG__RSV_1_MASK 0x200 ++#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9 ++#define MC_ARB_RAMCFG__RSV_2_MASK 0x400 ++#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa ++#define MC_ARB_RAMCFG__RSV_3_MASK 0x800 ++#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb ++#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000 ++#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc ++#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000 ++#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd ++#define MC_ARB_POP__ENABLE_ARB_MASK 0x1 ++#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0 ++#define MC_ARB_POP__SPEC_OPEN_MASK 0x2 ++#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1 ++#define MC_ARB_POP__POP_DEPTH_MASK 0x3c ++#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2 ++#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0 ++#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6 ++#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000 ++#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc ++#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000 ++#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf ++#define MC_ARB_POP__QUICK_STOP_MASK 0x20000 ++#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11 ++#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000 ++#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12 ++#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000 ++#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13 ++#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff ++#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0 ++#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00 ++#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8 ++#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000 ++#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10 ++#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000 ++#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11 ++#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff ++#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0 ++#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100 ++#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8 ++#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200 ++#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9 ++#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00 ++#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa ++#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000 ++#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10 ++#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000 ++#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18 ++#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf ++#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0 ++#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0 ++#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4 ++#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000 ++#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc ++#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff ++#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0 ++#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00 ++#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8 ++#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000 ++#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10 ++#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000 ++#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18 ++#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff ++#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0 ++#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00 ++#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8 ++#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000 ++#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10 ++#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000 ++#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18 ++#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3 ++#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0 ++#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4 ++#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400 ++#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa ++#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800 ++#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb ++#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000 ++#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc ++#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000 ++#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd ++#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3 ++#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0 ++#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4 ++#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400 ++#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa ++#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800 ++#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb ++#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000 ++#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc ++#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000 ++#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd ++#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3 ++#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0 ++#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc ++#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2 ++#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30 ++#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4 ++#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0 ++#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6 ++#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300 ++#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8 ++#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00 ++#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa ++#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000 ++#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc ++#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000 ++#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe ++#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000 ++#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10 ++#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3 ++#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0 ++#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc ++#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2 ++#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30 ++#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4 ++#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0 ++#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6 ++#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300 ++#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8 ++#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00 ++#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa ++#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000 ++#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc ++#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000 ++#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe ++#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000 ++#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10 ++#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1 ++#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0 ++#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6 ++#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1 ++#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8 ++#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3 ++#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10 ++#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4 ++#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1 ++#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0 ++#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6 ++#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1 ++#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8 ++#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3 ++#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10 ++#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4 ++#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff ++#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0 ++#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00 ++#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8 ++#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000 ++#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10 ++#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000 ++#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18 ++#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff ++#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0 ++#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00 ++#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8 ++#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000 ++#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10 ++#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000 ++#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18 ++#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff ++#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0 ++#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00 ++#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8 ++#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000 ++#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10 ++#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000 ++#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18 ++#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff ++#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0 ++#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00 ++#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8 ++#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000 ++#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10 ++#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000 ++#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18 ++#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3 ++#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0 ++#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc ++#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2 ++#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30 ++#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4 ++#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0 ++#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6 ++#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300 ++#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8 ++#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00 ++#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa ++#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000 ++#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc ++#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000 ++#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe ++#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000 ++#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10 ++#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000 ++#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11 ++#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000 ++#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12 ++#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000 ++#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13 ++#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000 ++#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14 ++#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000 ++#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15 ++#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000 ++#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16 ++#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000 ++#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17 ++#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000 ++#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18 ++#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000 ++#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19 ++#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000 ++#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a ++#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000 ++#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b ++#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000 ++#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c ++#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000 ++#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d ++#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000 ++#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e ++#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000 ++#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f ++#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3 ++#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0 ++#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc ++#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2 ++#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30 ++#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4 ++#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0 ++#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6 ++#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300 ++#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8 ++#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00 ++#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa ++#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000 ++#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc ++#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000 ++#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe ++#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000 ++#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10 ++#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000 ++#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11 ++#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000 ++#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12 ++#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000 ++#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13 ++#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000 ++#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14 ++#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000 ++#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15 ++#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000 ++#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16 ++#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000 ++#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17 ++#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000 ++#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18 ++#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000 ++#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19 ++#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000 ++#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a ++#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000 ++#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b ++#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000 ++#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c ++#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000 ++#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d ++#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000 ++#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e ++#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000 ++#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f ++#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1 ++#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0 ++#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e ++#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1 ++#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0 ++#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6 ++#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800 ++#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb ++#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000 ++#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc ++#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000 ++#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd ++#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000 ++#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe ++#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff ++#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0 ++#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3 ++#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0 ++#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4 ++#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2 ++#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8 ++#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3 ++#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10 ++#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4 ++#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20 ++#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5 ++#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40 ++#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6 ++#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80 ++#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7 ++#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300 ++#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8 ++#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400 ++#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa ++#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800 ++#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb ++#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000 ++#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc ++#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000 ++#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd ++#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000 ++#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe ++#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000 ++#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf ++#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY_MASK 0x10000 ++#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY__SHIFT 0x10 ++#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY_MASK 0x20000 ++#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY__SHIFT 0x11 ++#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000 ++#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12 ++#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000 ++#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13 ++#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000 ++#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14 ++#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY_MASK 0x1000000 ++#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY__SHIFT 0x18 ++#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY_MASK 0x2000000 ++#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY__SHIFT 0x19 ++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf ++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0 ++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0 ++#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4 ++#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100 ++#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8 ++#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200 ++#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9 ++#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 ++#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa ++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf ++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0 ++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0 ++#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4 ++#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100 ++#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8 ++#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200 ++#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9 ++#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00 ++#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa ++#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff ++#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0 ++#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00 ++#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8 ++#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000 ++#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10 ++#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000 ++#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11 ++#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000 ++#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12 ++#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000 ++#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13 ++#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000 ++#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14 ++#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000 ++#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15 ++#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff ++#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0 ++#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00 ++#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8 ++#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000 ++#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10 ++#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000 ++#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11 ++#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000 ++#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12 ++#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000 ++#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13 ++#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000 ++#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14 ++#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000 ++#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15 ++#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000 ++#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18 ++#define MC_ARB_LM_WR__ATOMIC_LM_EOB_MASK 0x2000000 ++#define MC_ARB_LM_WR__ATOMIC_LM_EOB__SHIFT 0x19 ++#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB_MASK 0x4000000 ++#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB__SHIFT 0x1a ++#define MC_ARB_REMREQ__RD_WATER_MASK 0xff ++#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0 ++#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00 ++#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8 ++#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000 ++#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10 ++#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000 ++#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14 ++#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000 ++#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18 ++#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1 ++#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0 ++#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2 ++#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1 ++#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4 ++#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2 ++#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8 ++#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3 ++#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10 ++#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4 ++#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20 ++#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5 ++#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40 ++#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6 ++#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80 ++#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7 ++#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00 ++#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8 ++#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000 ++#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf ++#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff ++#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0 ++#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00 ++#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8 ++#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000 ++#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10 ++#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000 ++#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18 ++#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff ++#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0 ++#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00 ++#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8 ++#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000 ++#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10 ++#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000 ++#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18 ++#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000 ++#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c ++#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff ++#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0 ++#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00 ++#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8 ++#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000 ++#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10 ++#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000 ++#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11 ++#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000 ++#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12 ++#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000 ++#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13 ++#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff ++#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0 ++#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff ++#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0 ++#define MC_ARB_GRUB_REALTIME_RD__CB0_MASK 0x1 ++#define MC_ARB_GRUB_REALTIME_RD__CB0__SHIFT 0x0 ++#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0_MASK 0x2 ++#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0__SHIFT 0x1 ++#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0_MASK 0x4 ++#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0__SHIFT 0x2 ++#define MC_ARB_GRUB_REALTIME_RD__DB0_MASK 0x8 ++#define MC_ARB_GRUB_REALTIME_RD__DB0__SHIFT 0x3 ++#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0_MASK 0x10 ++#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0__SHIFT 0x4 ++#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0_MASK 0x20 ++#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0__SHIFT 0x5 ++#define MC_ARB_GRUB_REALTIME_RD__TC0_MASK 0x40 ++#define MC_ARB_GRUB_REALTIME_RD__TC0__SHIFT 0x6 ++#define MC_ARB_GRUB_REALTIME_RD__IA_MASK 0x80 ++#define MC_ARB_GRUB_REALTIME_RD__IA__SHIFT 0x7 ++#define MC_ARB_GRUB_REALTIME_RD__ACPG_MASK 0x100 ++#define MC_ARB_GRUB_REALTIME_RD__ACPG__SHIFT 0x8 ++#define MC_ARB_GRUB_REALTIME_RD__ACPO_MASK 0x200 ++#define MC_ARB_GRUB_REALTIME_RD__ACPO__SHIFT 0x9 ++#define MC_ARB_GRUB_REALTIME_RD__DMIF_MASK 0x400 ++#define MC_ARB_GRUB_REALTIME_RD__DMIF__SHIFT 0xa ++#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0_MASK 0x800 ++#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0__SHIFT 0xb ++#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1_MASK 0x1000 ++#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1__SHIFT 0xc ++#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW_MASK 0x2000 ++#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW__SHIFT 0xd ++#define MC_ARB_GRUB_REALTIME_RD__MCIF_MASK 0x4000 ++#define MC_ARB_GRUB_REALTIME_RD__MCIF__SHIFT 0xe ++#define MC_ARB_GRUB_REALTIME_RD__RLC_MASK 0x8000 ++#define MC_ARB_GRUB_REALTIME_RD__RLC__SHIFT 0xf ++#define MC_ARB_GRUB_REALTIME_RD__VMC_MASK 0x10000 ++#define MC_ARB_GRUB_REALTIME_RD__VMC__SHIFT 0x10 ++#define MC_ARB_GRUB_REALTIME_RD__SDMA1_MASK 0x20000 ++#define MC_ARB_GRUB_REALTIME_RD__SDMA1__SHIFT 0x11 ++#define MC_ARB_GRUB_REALTIME_RD__SMU_MASK 0x40000 ++#define MC_ARB_GRUB_REALTIME_RD__SMU__SHIFT 0x12 ++#define MC_ARB_GRUB_REALTIME_RD__VCE0_MASK 0x80000 ++#define MC_ARB_GRUB_REALTIME_RD__VCE0__SHIFT 0x13 ++#define MC_ARB_GRUB_REALTIME_RD__VCE1_MASK 0x100000 ++#define MC_ARB_GRUB_REALTIME_RD__VCE1__SHIFT 0x14 ++#define MC_ARB_GRUB_REALTIME_RD__XDMAM_MASK 0x200000 ++#define MC_ARB_GRUB_REALTIME_RD__XDMAM__SHIFT 0x15 ++#define MC_ARB_GRUB_REALTIME_RD__SDMA0_MASK 0x400000 ++#define MC_ARB_GRUB_REALTIME_RD__SDMA0__SHIFT 0x16 ++#define MC_ARB_GRUB_REALTIME_RD__HDP_MASK 0x800000 ++#define MC_ARB_GRUB_REALTIME_RD__HDP__SHIFT 0x17 ++#define MC_ARB_GRUB_REALTIME_RD__UMC_MASK 0x1000000 ++#define MC_ARB_GRUB_REALTIME_RD__UMC__SHIFT 0x18 ++#define MC_ARB_GRUB_REALTIME_RD__UVD_MASK 0x2000000 ++#define MC_ARB_GRUB_REALTIME_RD__UVD__SHIFT 0x19 ++#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0_MASK 0x4000000 ++#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0__SHIFT 0x1a ++#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1_MASK 0x8000000 ++#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1__SHIFT 0x1b ++#define MC_ARB_GRUB_REALTIME_RD__SEM_MASK 0x10000000 ++#define MC_ARB_GRUB_REALTIME_RD__SEM__SHIFT 0x1c ++#define MC_ARB_GRUB_REALTIME_RD__SAMMSP_MASK 0x20000000 ++#define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d ++#define MC_ARB_GRUB_REALTIME_RD__VP8_MASK 0x40000000 ++#define MC_ARB_GRUB_REALTIME_RD__VP8__SHIFT 0x1e ++#define MC_ARB_GRUB_REALTIME_RD__ISP_MASK 0x80000000 ++#define MC_ARB_GRUB_REALTIME_RD__ISP__SHIFT 0x1f ++#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff ++#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0 ++#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00 ++#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8 ++#define MC_ARB_CG__RSV_0_MASK 0xff0000 ++#define MC_ARB_CG__RSV_0__SHIFT 0x10 ++#define MC_ARB_CG__RSV_1_MASK 0xff000000 ++#define MC_ARB_CG__RSV_1__SHIFT 0x18 ++#define MC_ARB_GRUB_REALTIME_WR__CB0_MASK 0x1 ++#define MC_ARB_GRUB_REALTIME_WR__CB0__SHIFT 0x0 ++#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0_MASK 0x2 ++#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0__SHIFT 0x1 ++#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0_MASK 0x4 ++#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0__SHIFT 0x2 ++#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0_MASK 0x8 ++#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0__SHIFT 0x3 ++#define MC_ARB_GRUB_REALTIME_WR__DB0_MASK 0x10 ++#define MC_ARB_GRUB_REALTIME_WR__DB0__SHIFT 0x4 ++#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0_MASK 0x20 ++#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0__SHIFT 0x5 ++#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0_MASK 0x40 ++#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0__SHIFT 0x6 ++#define MC_ARB_GRUB_REALTIME_WR__TC0_MASK 0x80 ++#define MC_ARB_GRUB_REALTIME_WR__TC0__SHIFT 0x7 ++#define MC_ARB_GRUB_REALTIME_WR__SH_MASK 0x100 ++#define MC_ARB_GRUB_REALTIME_WR__SH__SHIFT 0x8 ++#define MC_ARB_GRUB_REALTIME_WR__ACPG_MASK 0x200 ++#define MC_ARB_GRUB_REALTIME_WR__ACPG__SHIFT 0x9 ++#define MC_ARB_GRUB_REALTIME_WR__ACPO_MASK 0x400 ++#define MC_ARB_GRUB_REALTIME_WR__ACPO__SHIFT 0xa ++#define MC_ARB_GRUB_REALTIME_WR__MCIF_MASK 0x800 ++#define MC_ARB_GRUB_REALTIME_WR__MCIF__SHIFT 0xb ++#define MC_ARB_GRUB_REALTIME_WR__RLC_MASK 0x1000 ++#define MC_ARB_GRUB_REALTIME_WR__RLC__SHIFT 0xc ++#define MC_ARB_GRUB_REALTIME_WR__SDMA1_MASK 0x2000 ++#define MC_ARB_GRUB_REALTIME_WR__SDMA1__SHIFT 0xd ++#define MC_ARB_GRUB_REALTIME_WR__SMU_MASK 0x4000 ++#define MC_ARB_GRUB_REALTIME_WR__SMU__SHIFT 0xe ++#define MC_ARB_GRUB_REALTIME_WR__VCE0_MASK 0x8000 ++#define MC_ARB_GRUB_REALTIME_WR__VCE0__SHIFT 0xf ++#define MC_ARB_GRUB_REALTIME_WR__VCE1_MASK 0x10000 ++#define MC_ARB_GRUB_REALTIME_WR__VCE1__SHIFT 0x10 ++#define MC_ARB_GRUB_REALTIME_WR__SAMMSP_MASK 0x20000 ++#define MC_ARB_GRUB_REALTIME_WR__SAMMSP__SHIFT 0x11 ++#define MC_ARB_GRUB_REALTIME_WR__XDMA_MASK 0x40000 ++#define MC_ARB_GRUB_REALTIME_WR__XDMA__SHIFT 0x12 ++#define MC_ARB_GRUB_REALTIME_WR__XDMAM_MASK 0x80000 ++#define MC_ARB_GRUB_REALTIME_WR__XDMAM__SHIFT 0x13 ++#define MC_ARB_GRUB_REALTIME_WR__SDMA0_MASK 0x100000 ++#define MC_ARB_GRUB_REALTIME_WR__SDMA0__SHIFT 0x14 ++#define MC_ARB_GRUB_REALTIME_WR__HDP_MASK 0x200000 ++#define MC_ARB_GRUB_REALTIME_WR__HDP__SHIFT 0x15 ++#define MC_ARB_GRUB_REALTIME_WR__UMC_MASK 0x400000 ++#define MC_ARB_GRUB_REALTIME_WR__UMC__SHIFT 0x16 ++#define MC_ARB_GRUB_REALTIME_WR__UVD_MASK 0x800000 ++#define MC_ARB_GRUB_REALTIME_WR__UVD__SHIFT 0x17 ++#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0_MASK 0x1000000 ++#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0__SHIFT 0x18 ++#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1_MASK 0x2000000 ++#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1__SHIFT 0x19 ++#define MC_ARB_GRUB_REALTIME_WR__XDP_MASK 0x4000000 ++#define MC_ARB_GRUB_REALTIME_WR__XDP__SHIFT 0x1a ++#define MC_ARB_GRUB_REALTIME_WR__SEM_MASK 0x8000000 ++#define MC_ARB_GRUB_REALTIME_WR__SEM__SHIFT 0x1b ++#define MC_ARB_GRUB_REALTIME_WR__IH_MASK 0x10000000 ++#define MC_ARB_GRUB_REALTIME_WR__IH__SHIFT 0x1c ++#define MC_ARB_GRUB_REALTIME_WR__VP8_MASK 0x20000000 ++#define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d ++#define MC_ARB_GRUB_REALTIME_WR__ISP_MASK 0x40000000 ++#define MC_ARB_GRUB_REALTIME_WR__ISP__SHIFT 0x1e ++#define MC_ARB_GRUB_REALTIME_WR__VIN0_MASK 0x80000000 ++#define MC_ARB_GRUB_REALTIME_WR__VIN0__SHIFT 0x1f ++#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff ++#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0 ++#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00 ++#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8 ++#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000 ++#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10 ++#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000 ++#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18 ++#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1 ++#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0 ++#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2 ++#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1 ++#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4 ++#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2 ++#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8 ++#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3 ++#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10 ++#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4 ++#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20 ++#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5 ++#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40 ++#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6 ++#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80 ++#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7 ++#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100 ++#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8 ++#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200 ++#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9 ++#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400 ++#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa ++#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800 ++#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb ++#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000 ++#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc ++#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000 ++#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd ++#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000 ++#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe ++#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000 ++#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf ++#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000 ++#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10 ++#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000 ++#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11 ++#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000 ++#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12 ++#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000 ++#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13 ++#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000 ++#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14 ++#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000 ++#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15 ++#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000 ++#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16 ++#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000 ++#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17 ++#define MC_ARB_BUSY_STATUS__WRRET0_MASK 0x1000000 ++#define MC_ARB_BUSY_STATUS__WRRET0__SHIFT 0x18 ++#define MC_ARB_BUSY_STATUS__WRRET1_MASK 0x2000000 ++#define MC_ARB_BUSY_STATUS__WRRET1__SHIFT 0x19 ++#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000 ++#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a ++#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000 ++#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b ++#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000 ++#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c ++#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000 ++#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d ++#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000 ++#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e ++#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000 ++#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f ++#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff ++#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0 ++#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00 ++#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8 ++#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000 ++#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10 ++#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000 ++#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18 ++#define MC_ARB_GRUB2__REALTIME_GRP_RD_MASK 0xff ++#define MC_ARB_GRUB2__REALTIME_GRP_RD__SHIFT 0x0 ++#define MC_ARB_GRUB2__REALTIME_GRP_WR_MASK 0xff00 ++#define MC_ARB_GRUB2__REALTIME_GRP_WR__SHIFT 0x8 ++#define MC_ARB_GRUB2__DISP_RD_STALL_EN_MASK 0x10000 ++#define MC_ARB_GRUB2__DISP_RD_STALL_EN__SHIFT 0x10 ++#define MC_ARB_GRUB2__ACP_RD_STALL_EN_MASK 0x20000 ++#define MC_ARB_GRUB2__ACP_RD_STALL_EN__SHIFT 0x11 ++#define MC_ARB_GRUB2__UVD_RD_STALL_EN_MASK 0x40000 ++#define MC_ARB_GRUB2__UVD_RD_STALL_EN__SHIFT 0x12 ++#define MC_ARB_GRUB2__VCE0_RD_STALL_EN_MASK 0x80000 ++#define MC_ARB_GRUB2__VCE0_RD_STALL_EN__SHIFT 0x13 ++#define MC_ARB_GRUB2__VCE1_RD_STALL_EN_MASK 0x100000 ++#define MC_ARB_GRUB2__VCE1_RD_STALL_EN__SHIFT 0x14 ++#define MC_ARB_GRUB2__REALTIME_RD_WTS_MASK 0x200000 ++#define MC_ARB_GRUB2__REALTIME_RD_WTS__SHIFT 0x15 ++#define MC_ARB_GRUB2__REALTIME_WR_WTS_MASK 0x400000 ++#define MC_ARB_GRUB2__REALTIME_WR_WTS__SHIFT 0x16 ++#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL_MASK 0x800000 ++#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL__SHIFT 0x17 ++#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG_MASK 0x1000000 ++#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG__SHIFT 0x18 ++#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD_MASK 0x2000000 ++#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD__SHIFT 0x19 ++#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD_MASK 0x4000000 ++#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD__SHIFT 0x1a ++#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR_MASK 0x8000000 ++#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR__SHIFT 0x1b ++#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR_MASK 0x10000000 ++#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR__SHIFT 0x1c ++#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f ++#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0 ++#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0 ++#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5 ++#define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00 ++#define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa ++#define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000 ++#define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf ++#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1 ++#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0 ++#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2 ++#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1 ++#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4 ++#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2 ++#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8 ++#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3 ++#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10 ++#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4 ++#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00 ++#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8 ++#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000 ++#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc ++#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000 ++#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd ++#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000 ++#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf ++#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000 ++#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11 ++#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000 ++#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13 ++#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000 ++#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15 ++#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000 ++#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17 ++#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000 ++#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19 ++#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000 ++#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a ++#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000 ++#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b ++#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000 ++#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c ++#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000 ++#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d ++#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e ++#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1 ++#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1 ++#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 ++#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2 ++#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 ++#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4 ++#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 ++#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 ++#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 ++#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30 ++#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4 ++#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0 ++#define MC_CG_CONFIG__INDEX__SHIFT 0x6 ++#define MC_CITF_CNTL__IGNOREPM_MASK 0x4 ++#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2 ++#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8 ++#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3 ++#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30 ++#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4 ++#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40 ++#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6 ++#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180 ++#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7 ++#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200 ++#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9 ++#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f ++#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0 ++#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0 ++#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6 ++#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff ++#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0 ++#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00 ++#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8 ++#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000 ++#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10 ++#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000 ++#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18 ++#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000 ++#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19 ++#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff ++#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0 ++#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00 ++#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8 ++#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000 ++#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10 ++#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000 ++#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18 ++#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000 ++#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19 ++#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1 ++#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0 ++#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e ++#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1 ++#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20 ++#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5 ++#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0 ++#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6 ++#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f ++#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0 ++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000 ++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc ++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000 ++#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12 ++#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000 ++#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18 ++#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1 ++#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0 ++#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2 ++#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1 ++#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4 ++#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2 ++#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8 ++#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3 ++#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10 ++#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4 ++#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20 ++#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5 ++#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40 ++#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6 ++#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80 ++#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7 ++#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f ++#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0 ++#define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000 ++#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10 ++#define MC_CITF_DAGB_DLY__POS_MASK 0x3f000000 ++#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18 ++#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf ++#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0 ++#define MC_RD_GRP_EXT__TC0_MASK 0xf0 ++#define MC_RD_GRP_EXT__TC0__SHIFT 0x4 ++#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf ++#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0 ++#define MC_WR_GRP_EXT__TC0_MASK 0xf0 ++#define MC_WR_GRP_EXT__TC0__SHIFT 0x4 ++#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f ++#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0 ++#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80 ++#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7 ++#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000 ++#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe ++#define MC_WR_TC0__ENABLE_MASK 0x1 ++#define MC_WR_TC0__ENABLE__SHIFT 0x0 ++#define MC_WR_TC0__PRESCALE_MASK 0x6 ++#define MC_WR_TC0__PRESCALE__SHIFT 0x1 ++#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_WR_TC0__STALL_MODE_MASK 0x30 ++#define MC_WR_TC0__STALL_MODE__SHIFT 0x4 ++#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40 ++#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_WR_TC0__MAX_BURST_MASK 0x780 ++#define MC_WR_TC0__MAX_BURST__SHIFT 0x7 ++#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800 ++#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb ++#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_WR_TC1__ENABLE_MASK 0x1 ++#define MC_WR_TC1__ENABLE__SHIFT 0x0 ++#define MC_WR_TC1__PRESCALE_MASK 0x6 ++#define MC_WR_TC1__PRESCALE__SHIFT 0x1 ++#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_WR_TC1__STALL_MODE_MASK 0x30 ++#define MC_WR_TC1__STALL_MODE__SHIFT 0x4 ++#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40 ++#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_WR_TC1__MAX_BURST_MASK 0x780 ++#define MC_WR_TC1__MAX_BURST__SHIFT 0x7 ++#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800 ++#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb ++#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f ++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0 ++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0 ++#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6 ++#define MC_CITF_CREDITS_ARB_RD2__READ_MED_MASK 0xff ++#define MC_CITF_CREDITS_ARB_RD2__READ_MED__SHIFT 0x0 ++#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7 ++#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0 ++#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38 ++#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3 ++#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0 ++#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6 ++#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00 ++#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9 ++#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000 ++#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc ++#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000 ++#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf ++#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 ++#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12 ++#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000 ++#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15 ++#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000 ++#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18 ++#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000 ++#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19 ++#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7 ++#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0 ++#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38 ++#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3 ++#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0 ++#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6 ++#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00 ++#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9 ++#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000 ++#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc ++#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000 ++#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf ++#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 ++#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12 ++#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000 ++#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15 ++#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000 ++#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18 ++#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000 ++#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19 ++#define MC_RD_CB__ENABLE_MASK 0x1 ++#define MC_RD_CB__ENABLE__SHIFT 0x0 ++#define MC_RD_CB__PRESCALE_MASK 0x6 ++#define MC_RD_CB__PRESCALE__SHIFT 0x1 ++#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_RD_CB__STALL_MODE_MASK 0x30 ++#define MC_RD_CB__STALL_MODE__SHIFT 0x4 ++#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40 ++#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_RD_CB__MAX_BURST_MASK 0x780 ++#define MC_RD_CB__MAX_BURST__SHIFT 0x7 ++#define MC_RD_CB__LAZY_TIMER_MASK 0x7800 ++#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb ++#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_RD_DB__ENABLE_MASK 0x1 ++#define MC_RD_DB__ENABLE__SHIFT 0x0 ++#define MC_RD_DB__PRESCALE_MASK 0x6 ++#define MC_RD_DB__PRESCALE__SHIFT 0x1 ++#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_RD_DB__STALL_MODE_MASK 0x30 ++#define MC_RD_DB__STALL_MODE__SHIFT 0x4 ++#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40 ++#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_RD_DB__MAX_BURST_MASK 0x780 ++#define MC_RD_DB__MAX_BURST__SHIFT 0x7 ++#define MC_RD_DB__LAZY_TIMER_MASK 0x7800 ++#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb ++#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_RD_TC0__ENABLE_MASK 0x1 ++#define MC_RD_TC0__ENABLE__SHIFT 0x0 ++#define MC_RD_TC0__PRESCALE_MASK 0x6 ++#define MC_RD_TC0__PRESCALE__SHIFT 0x1 ++#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_RD_TC0__STALL_MODE_MASK 0x30 ++#define MC_RD_TC0__STALL_MODE__SHIFT 0x4 ++#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40 ++#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_RD_TC0__MAX_BURST_MASK 0x780 ++#define MC_RD_TC0__MAX_BURST__SHIFT 0x7 ++#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800 ++#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb ++#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_RD_TC1__ENABLE_MASK 0x1 ++#define MC_RD_TC1__ENABLE__SHIFT 0x0 ++#define MC_RD_TC1__PRESCALE_MASK 0x6 ++#define MC_RD_TC1__PRESCALE__SHIFT 0x1 ++#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_RD_TC1__STALL_MODE_MASK 0x30 ++#define MC_RD_TC1__STALL_MODE__SHIFT 0x4 ++#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40 ++#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_RD_TC1__MAX_BURST_MASK 0x780 ++#define MC_RD_TC1__MAX_BURST__SHIFT 0x7 ++#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800 ++#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb ++#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_RD_HUB__ENABLE_MASK 0x1 ++#define MC_RD_HUB__ENABLE__SHIFT 0x0 ++#define MC_RD_HUB__PRESCALE_MASK 0x6 ++#define MC_RD_HUB__PRESCALE__SHIFT 0x1 ++#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_RD_HUB__STALL_MODE_MASK 0x30 ++#define MC_RD_HUB__STALL_MODE__SHIFT 0x4 ++#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40 ++#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_RD_HUB__MAX_BURST_MASK 0x780 ++#define MC_RD_HUB__MAX_BURST__SHIFT 0x7 ++#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800 ++#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb ++#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_WR_CB__ENABLE_MASK 0x1 ++#define MC_WR_CB__ENABLE__SHIFT 0x0 ++#define MC_WR_CB__PRESCALE_MASK 0x6 ++#define MC_WR_CB__PRESCALE__SHIFT 0x1 ++#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_WR_CB__STALL_MODE_MASK 0x30 ++#define MC_WR_CB__STALL_MODE__SHIFT 0x4 ++#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40 ++#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_WR_CB__MAX_BURST_MASK 0x780 ++#define MC_WR_CB__MAX_BURST__SHIFT 0x7 ++#define MC_WR_CB__LAZY_TIMER_MASK 0x7800 ++#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb ++#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_WR_DB__ENABLE_MASK 0x1 ++#define MC_WR_DB__ENABLE__SHIFT 0x0 ++#define MC_WR_DB__PRESCALE_MASK 0x6 ++#define MC_WR_DB__PRESCALE__SHIFT 0x1 ++#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_WR_DB__STALL_MODE_MASK 0x30 ++#define MC_WR_DB__STALL_MODE__SHIFT 0x4 ++#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40 ++#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_WR_DB__MAX_BURST_MASK 0x780 ++#define MC_WR_DB__MAX_BURST__SHIFT 0x7 ++#define MC_WR_DB__LAZY_TIMER_MASK 0x7800 ++#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb ++#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_WR_HUB__ENABLE_MASK 0x1 ++#define MC_WR_HUB__ENABLE__SHIFT 0x0 ++#define MC_WR_HUB__PRESCALE_MASK 0x6 ++#define MC_WR_HUB__PRESCALE__SHIFT 0x1 ++#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_WR_HUB__STALL_MODE_MASK 0x30 ++#define MC_WR_HUB__STALL_MODE__SHIFT 0x4 ++#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40 ++#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_WR_HUB__MAX_BURST_MASK 0x780 ++#define MC_WR_HUB__MAX_BURST__SHIFT 0x7 ++#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800 ++#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb ++#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff ++#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0 ++#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00 ++#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8 ++#define MC_RD_GRP_LCL__CB0_MASK 0xf000 ++#define MC_RD_GRP_LCL__CB0__SHIFT 0xc ++#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000 ++#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10 ++#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000 ++#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14 ++#define MC_RD_GRP_LCL__DB0_MASK 0xf000000 ++#define MC_RD_GRP_LCL__DB0__SHIFT 0x18 ++#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000 ++#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c ++#define MC_WR_GRP_LCL__CB0_MASK 0xf ++#define MC_WR_GRP_LCL__CB0__SHIFT 0x0 ++#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0 ++#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4 ++#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00 ++#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8 ++#define MC_WR_GRP_LCL__DB0_MASK 0xf000 ++#define MC_WR_GRP_LCL__DB0__SHIFT 0xc ++#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000 ++#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10 ++#define MC_WR_GRP_LCL__SX0_MASK 0xf00000 ++#define MC_WR_GRP_LCL__SX0__SHIFT 0x14 ++#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000 ++#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c ++#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff ++#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0 ++#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x2 ++#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x1 ++#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x4 ++#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x2 ++#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x8 ++#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x3 ++#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x10 ++#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x4 ++#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x20 ++#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x5 ++#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x40 ++#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x6 ++#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x80 ++#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x7 ++#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x100 ++#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x8 ++#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x200 ++#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x9 ++#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x400 ++#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xa ++#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x800 ++#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0xb ++#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x1000 ++#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0xc ++#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x2000 ++#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0xd ++#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY_MASK 0x4000 ++#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY__SHIFT 0xe ++#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY_MASK 0x8000 ++#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY__SHIFT 0xf ++#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY_MASK 0x10000 ++#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY__SHIFT 0x10 ++#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY_MASK 0x20000 ++#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY__SHIFT 0x11 ++#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY_MASK 0x40000 ++#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY__SHIFT 0x12 ++#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f ++#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0 ++#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0 ++#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6 ++#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000 ++#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc ++#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000 ++#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12 ++#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000 ++#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13 ++#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f ++#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0 ++#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0 ++#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6 ++#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000 ++#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc ++#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000 ++#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12 ++#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000 ++#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13 ++#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f ++#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0 ++#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0 ++#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6 ++#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000 ++#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc ++#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000 ++#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12 ++#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 ++#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 ++#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4 ++#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2 ++#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18 ++#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3 ++#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f ++#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0 ++#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0 ++#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6 ++#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000 ++#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc ++#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000 ++#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12 ++#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000 ++#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13 ++#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f ++#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0 ++#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0 ++#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6 ++#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000 ++#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc ++#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000 ++#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12 ++#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000 ++#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13 ++#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f ++#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0 ++#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0 ++#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6 ++#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000 ++#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc ++#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000 ++#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12 ++#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000 ++#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC_MASK 0x4 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC__SHIFT 0x2 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x8 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x3 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x10 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x4 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x20 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x5 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x40 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x6 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ_MASK 0x80 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ__SHIFT 0x7 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET_MASK 0x100 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET__SHIFT 0x8 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x200 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x9 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x400 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0xa ++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC_MASK 0x800 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC__SHIFT 0xb ++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x1000 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0xc ++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x2000 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0xd ++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC_MASK 0x4000 ++#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC__SHIFT 0xe ++#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x8000 ++#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xf ++#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x10000 ++#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x10 ++#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x20000 ++#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x11 ++#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING_MASK 0x40000 ++#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING__SHIFT 0x12 ++#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x80000 ++#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x13 ++#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3 ++#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0 ++#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff ++#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0 ++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2 ++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1 ++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4 ++#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2 ++#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8 ++#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3 ++#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 ++#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 ++#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0 ++#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5 ++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000 ++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd ++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000 ++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe ++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000 ++#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf ++#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000 ++#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10 ++#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000 ++#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11 ++#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000 ++#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12 ++#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000 ++#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13 ++#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000 ++#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14 ++#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000 ++#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15 ++#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000 ++#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16 ++#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE_MASK 0x800000 ++#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE__SHIFT 0x17 ++#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1 ++#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0 ++#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2 ++#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1 ++#define MC_HUB_WDP_BP__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe ++#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1 ++#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000 ++#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12 ++#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1 ++#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0 ++#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2 ++#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 ++#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4 ++#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 ++#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8 ++#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 ++#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10 ++#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 ++#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20 ++#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5 ++#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40 ++#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6 ++#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80 ++#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7 ++#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100 ++#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8 ++#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200 ++#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9 ++#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400 ++#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa ++#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800 ++#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb ++#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000 ++#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc ++#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000 ++#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd ++#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000 ++#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe ++#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000 ++#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf ++#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000 ++#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10 ++#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000 ++#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11 ++#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000 ++#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12 ++#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000 ++#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13 ++#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000 ++#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14 ++#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000 ++#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15 ++#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000 ++#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16 ++#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1 ++#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0 ++#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2 ++#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1 ++#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4 ++#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2 ++#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8 ++#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3 ++#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10 ++#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4 ++#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20 ++#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5 ++#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40 ++#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6 ++#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80 ++#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7 ++#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100 ++#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8 ++#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200 ++#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9 ++#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400 ++#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa ++#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800 ++#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb ++#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000 ++#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc ++#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000 ++#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd ++#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000 ++#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe ++#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000 ++#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf ++#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1 ++#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0 ++#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2 ++#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1 ++#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4 ++#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2 ++#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8 ++#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3 ++#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10 ++#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4 ++#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20 ++#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5 ++#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40 ++#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6 ++#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80 ++#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7 ++#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1 ++#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0 ++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4 ++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2 ++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8 ++#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3 ++#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10 ++#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4 ++#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20 ++#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5 ++#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40 ++#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6 ++#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80 ++#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7 ++#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100 ++#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8 ++#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200 ++#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9 ++#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400 ++#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa ++#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800 ++#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb ++#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000 ++#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc ++#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000 ++#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd ++#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000 ++#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe ++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000 ++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15 ++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000 ++#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16 ++#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000 ++#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17 ++#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000 ++#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18 ++#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000 ++#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19 ++#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE_MASK 0x4000000 ++#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE__SHIFT 0x1a ++#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD_MASK 0x78000000 ++#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD__SHIFT 0x1b ++#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1 ++#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0 ++#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe ++#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1 ++#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000 ++#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15 ++#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000 ++#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16 ++#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000 ++#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e ++#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000 ++#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 ++#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 ++#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7 ++#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0 ++#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38 ++#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3 ++#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0 ++#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6 ++#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00 ++#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9 ++#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000 ++#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc ++#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000 ++#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf ++#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000 ++#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12 ++#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000 ++#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15 ++#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff ++#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0 ++#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00 ++#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8 ++#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000 ++#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10 ++#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000 ++#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18 ++#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff ++#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0 ++#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00 ++#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8 ++#define MC_HUB_WDP_CREDITS2__VM2_MASK 0xff0000 ++#define MC_HUB_WDP_CREDITS2__VM2__SHIFT 0x10 ++#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf ++#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0 ++#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0 ++#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4 ++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00 ++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8 ++#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000 ++#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10 ++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000 ++#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11 ++#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf ++#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0 ++#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0 ++#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4 ++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00 ++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8 ++#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000 ++#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10 ++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000 ++#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11 ++#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff ++#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0 ++#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00 ++#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8 ++#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000 ++#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10 ++#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000 ++#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18 ++#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff ++#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0 ++#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00 ++#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8 ++#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f ++#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0 ++#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000 ++#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10 ++#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000 ++#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x100000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x14 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x200000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x15 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x400000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x16 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x800000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x17 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ_MASK 0x1000000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ__SHIFT 0x18 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE_MASK 0x2000000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE__SHIFT 0x19 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x4000000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1a ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x8000000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1b ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x10000000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1c ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x20000000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ_MASK 0x40000000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ__SHIFT 0x1e ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE_MASK 0x80000000 ++#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE__SHIFT 0x1f ++#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3 ++#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c ++#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2 ++#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3 ++#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c ++#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2 ++#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe ++#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1 ++#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00 ++#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9 ++#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000 ++#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11 ++#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000 ++#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18 ++#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe ++#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1 ++#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00 ++#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9 ++#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000 ++#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11 ++#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000 ++#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18 ++#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe ++#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1 ++#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00 ++#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9 ++#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC_MASK 0x1 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC__SHIFT 0x0 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC_MASK 0x2 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC__SHIFT 0x1 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC_MASK 0x4 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC__SHIFT 0x2 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC_MASK 0x8 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC__SHIFT 0x3 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC_MASK 0x10 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC__SHIFT 0x4 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC_MASK 0x20 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC__SHIFT 0x5 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC_MASK 0x40 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC__SHIFT 0x6 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC_MASK 0x80 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC__SHIFT 0x7 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC_MASK 0x100 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC__SHIFT 0x8 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC_MASK 0x200 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC__SHIFT 0x9 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC_MASK 0x400 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC__SHIFT 0xa ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC_MASK 0x800 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC__SHIFT 0xb ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC_MASK 0x1000 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC__SHIFT 0xc ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC_MASK 0x2000 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC__SHIFT 0xd ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC_MASK 0x4000 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC__SHIFT 0xe ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC_MASK 0x8000 ++#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC__SHIFT 0xf ++#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4 ++#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2 ++#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78 ++#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3 ++#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780 ++#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7 ++#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800 ++#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb ++#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000 ++#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12 ++#define MC_HUB_RDREQ_MCDW__MED_CREDITS_MASK 0xfe000000 ++#define MC_HUB_RDREQ_MCDW__MED_CREDITS__SHIFT 0x19 ++#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4 ++#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2 ++#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78 ++#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3 ++#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780 ++#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7 ++#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800 ++#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb ++#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000 ++#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12 ++#define MC_HUB_RDREQ_MCDX__MED_CREDITS_MASK 0xfe000000 ++#define MC_HUB_RDREQ_MCDX__MED_CREDITS__SHIFT 0x19 ++#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4 ++#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2 ++#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78 ++#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3 ++#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780 ++#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7 ++#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800 ++#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb ++#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000 ++#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12 ++#define MC_HUB_RDREQ_MCDY__MED_CREDITS_MASK 0xfe000000 ++#define MC_HUB_RDREQ_MCDY__MED_CREDITS__SHIFT 0x19 ++#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4 ++#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2 ++#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78 ++#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3 ++#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780 ++#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7 ++#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800 ++#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb ++#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000 ++#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12 ++#define MC_HUB_RDREQ_MCDZ__MED_CREDITS_MASK 0xfe000000 ++#define MC_HUB_RDREQ_MCDZ__MED_CREDITS__SHIFT 0x19 ++#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f ++#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0 ++#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL_MASK 0x80 ++#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL__SHIFT 0x7 ++#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00 ++#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8 ++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff ++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0 ++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00 ++#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8 ++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff ++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0 ++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00 ++#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8 ++#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_VCE0__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_VCE0__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_VCE0__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_VCE0__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_VCE0__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_VCE0__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_VCE0__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_VCE0__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_VCE0__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_VCE0__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_VCE0__VM_BYPASS_MASK 0x10000 ++#define MC_HUB_RDREQ_VCE0__VM_BYPASS__SHIFT 0x10 ++#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 ++#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 ++#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000 ++#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10 ++#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 ++#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 ++#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000 ++#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10 ++#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 ++#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 ++#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_VCEU0__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_VCEU0__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_VCEU0__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_VCEU0__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_VCEU0__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_VCEU0__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_VCEU0__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_VCEU0__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4 ++#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2 ++#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78 ++#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3 ++#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80 ++#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7 ++#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000 ++#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd ++#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000 ++#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11 ++#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000 ++#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18 ++#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4 ++#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2 ++#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78 ++#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3 ++#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80 ++#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7 ++#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000 ++#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd ++#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000 ++#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11 ++#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000 ++#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18 ++#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4 ++#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2 ++#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78 ++#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3 ++#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80 ++#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7 ++#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000 ++#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd ++#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000 ++#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11 ++#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000 ++#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18 ++#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4 ++#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2 ++#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78 ++#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3 ++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80 ++#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7 ++#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000 ++#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd ++#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000 ++#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11 ++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000 ++#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18 ++#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3 ++#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0 ++#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc ++#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2 ++#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_VCE0__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_VCE0__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_VCE0__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_VCE0__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_VCE0__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_VCE0__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_VCE0__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_VCE0__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_VCE0__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_VCE0__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_VCE0__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_VCE0__VM_BYPASS_MASK 0x10000 ++#define MC_HUB_WDP_VCE0__VM_BYPASS__SHIFT 0x10 ++#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 ++#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 ++#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_IH__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000 ++#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10 ++#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 ++#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 ++#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1 ++#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0 ++#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe ++#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1 ++#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1 ++#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0 ++#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe ++#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1 ++#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1 ++#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0 ++#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe ++#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1 ++#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1 ++#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0 ++#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe ++#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1 ++#define MC_HUB_WDP_VCEU0__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_VCEU0__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_VCEU0__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_VCEU0__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_VCEU0__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_VCEU0__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_VCEU0__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_VCEU0__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_VCEU0__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_VCEU0__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000 ++#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11 ++#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000 ++#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12 ++#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000 ++#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13 ++#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000 ++#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11 ++#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000 ++#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12 ++#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000 ++#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13 ++#define MC_HUB_RDREQ_SAMMSP__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_SAMMSP__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_SAMMSP__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_SAMMSP__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_SAMMSP__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_SAMMSP__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_SAMMSP__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_SAMMSP__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_VP8__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_VP8__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_VP8__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_VP8__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_VP8__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_VP8__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_VP8__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_VP8__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_VP8__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_VP8__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_VP8U__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_VP8U__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_VP8U__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_VP8U__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_VP8U__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_VP8U__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_VP8U__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_VP8U__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_VP8U__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_VP8U__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000 ++#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11 ++#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000 ++#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12 ++#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000 ++#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13 ++#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000 ++#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11 ++#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000 ++#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12 ++#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000 ++#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13 ++#define MC_HUB_WDP_SAMMSP__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_SAMMSP__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_SAMMSP__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_SAMMSP__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_SAMMSP__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_SAMMSP__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_SAMMSP__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_SAMMSP__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_SAMMSP__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_SAMMSP__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_VP8__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_VP8__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_VP8__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_VP8__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_VP8__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_VP8__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_VP8__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_VP8__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_VP8__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_VP8__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_VP8__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_VP8__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_VP8U__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_VP8U__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_VP8U__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_VP8U__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_VP8U__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_VP8U__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_VP8U__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_VP8U__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_VP8U__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_VP8U__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_VP8U__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000 ++#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11 ++#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000 ++#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12 ++#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000 ++#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13 ++#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000 ++#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11 ++#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000 ++#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12 ++#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000 ++#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13 ++#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000 ++#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11 ++#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000 ++#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12 ++#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000 ++#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13 ++#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000 ++#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11 ++#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000 ++#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12 ++#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000 ++#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13 ++#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x20000 ++#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x11 ++#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x40000 ++#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x12 ++#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x1f80000 ++#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x13 ++#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000 ++#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11 ++#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000 ++#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12 ++#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000 ++#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13 ++#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000 ++#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11 ++#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000 ++#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12 ++#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000 ++#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13 ++#define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4 ++#define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2 ++#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78 ++#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3 ++#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780 ++#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7 ++#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800 ++#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb ++#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000 ++#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12 ++#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD_MASK 0xfe000000 ++#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD__SHIFT 0x19 ++#define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4 ++#define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2 ++#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78 ++#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3 ++#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780 ++#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7 ++#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800 ++#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb ++#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000 ++#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12 ++#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD_MASK 0xfe000000 ++#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD__SHIFT 0x19 ++#define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4 ++#define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2 ++#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78 ++#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3 ++#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780 ++#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7 ++#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800 ++#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb ++#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000 ++#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12 ++#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD_MASK 0xfe000000 ++#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD__SHIFT 0x19 ++#define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4 ++#define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2 ++#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78 ++#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3 ++#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780 ++#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7 ++#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800 ++#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb ++#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000 ++#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12 ++#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD_MASK 0xfe000000 ++#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD__SHIFT 0x19 ++#define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4 ++#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2 ++#define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78 ++#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3 ++#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80 ++#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7 ++#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000 ++#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd ++#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000 ++#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11 ++#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000 ++#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18 ++#define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4 ++#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2 ++#define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78 ++#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3 ++#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80 ++#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7 ++#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000 ++#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd ++#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000 ++#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11 ++#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000 ++#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18 ++#define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4 ++#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2 ++#define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78 ++#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3 ++#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80 ++#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7 ++#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000 ++#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd ++#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000 ++#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11 ++#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000 ++#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18 ++#define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2 ++#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1 ++#define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4 ++#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2 ++#define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78 ++#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3 ++#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80 ++#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7 ++#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000 ++#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd ++#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000 ++#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11 ++#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000 ++#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18 ++#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1 ++#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0 ++#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe ++#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1 ++#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1 ++#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0 ++#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe ++#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1 ++#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1 ++#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0 ++#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe ++#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1 ++#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1 ++#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0 ++#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe ++#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1 ++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f ++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0 ++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 ++#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 ++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f ++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0 ++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 ++#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 ++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f ++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0 ++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 ++#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 ++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f ++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0 ++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 ++#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 ++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f ++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0 ++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 ++#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 ++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f ++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0 ++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 ++#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 ++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f ++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0 ++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 ++#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 ++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f ++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0 ++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80 ++#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7 ++#define MC_HUB_WDP_BP2__RDRET_MASK 0xffff ++#define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0 ++#define MC_HUB_RDREQ_VCE1__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_VCE1__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_VCE1__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_VCE1__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_VCE1__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_VCE1__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_VCE1__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_VCE1__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_VCE1__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_VCE1__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_VCE1__VM_BYPASS_MASK 0x10000 ++#define MC_HUB_RDREQ_VCE1__VM_BYPASS__SHIFT 0x10 ++#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 ++#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 ++#define MC_HUB_RDREQ_VCEU1__ENABLE_MASK 0x1 ++#define MC_HUB_RDREQ_VCEU1__ENABLE__SHIFT 0x0 ++#define MC_HUB_RDREQ_VCEU1__PRESCALE_MASK 0x6 ++#define MC_HUB_RDREQ_VCEU1__PRESCALE__SHIFT 0x1 ++#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_RDREQ_VCEU1__STALL_MODE_MASK 0x30 ++#define MC_HUB_RDREQ_VCEU1__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_RDREQ_VCEU1__MAXBURST_MASK 0x780 ++#define MC_HUB_RDREQ_VCEU1__MAXBURST__SHIFT 0x7 ++#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_HUB_WDP_VCE1__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_VCE1__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_VCE1__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_VCE1__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_VCE1__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_VCE1__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_VCE1__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_VCE1__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_VCE1__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_VCE1__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_VCE1__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_VCE1__VM_BYPASS_MASK 0x10000 ++#define MC_HUB_WDP_VCE1__VM_BYPASS__SHIFT 0x10 ++#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000 ++#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11 ++#define MC_HUB_WDP_VCEU1__ENABLE_MASK 0x1 ++#define MC_HUB_WDP_VCEU1__ENABLE__SHIFT 0x0 ++#define MC_HUB_WDP_VCEU1__PRESCALE_MASK 0x6 ++#define MC_HUB_WDP_VCEU1__PRESCALE__SHIFT 0x1 ++#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT_MASK 0x8 ++#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3 ++#define MC_HUB_WDP_VCEU1__STALL_MODE_MASK 0x30 ++#define MC_HUB_WDP_VCEU1__STALL_MODE__SHIFT 0x4 ++#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_MASK 0x40 ++#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE__SHIFT 0x6 ++#define MC_HUB_WDP_VCEU1__MAXBURST_MASK 0x780 ++#define MC_HUB_WDP_VCEU1__MAXBURST__SHIFT 0x7 ++#define MC_HUB_WDP_VCEU1__LAZY_TIMER_MASK 0x7800 ++#define MC_HUB_WDP_VCEU1__LAZY_TIMER__SHIFT 0xb ++#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000 ++#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf ++#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000 ++#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10 ++#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000 ++#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf ++#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000 ++#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10 ++#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000 ++#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11 ++#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff ++#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0 ++#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00 ++#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8 ++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff ++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0 ++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00 ++#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8 ++#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000 ++#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14 ++#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff ++#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 ++#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00 ++#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 ++#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff ++#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0 ++#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00 ++#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8 ++#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000 ++#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10 ++#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff ++#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0 ++#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00 ++#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8 ++#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff ++#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 ++#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00 ++#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8 ++#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000 ++#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10 ++#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000 ++#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18 ++#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1 ++#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0 ++#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6 ++#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1 ++#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78 ++#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3 ++#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80 ++#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7 ++#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff ++#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 ++#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00 ++#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8 ++#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000 ++#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10 ++#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000 ++#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18 ++#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff ++#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0 ++#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100 ++#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8 ++#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600 ++#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9 ++#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800 ++#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb ++#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000 ++#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd ++#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff ++#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0 ++#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300 ++#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8 ++#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00 ++#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa ++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3 ++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4 ++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2 ++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8 ++#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3 ++#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10 ++#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4 ++#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0 ++#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5 ++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00 ++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9 ++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000 ++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe ++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000 ++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13 ++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000 ++#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18 ++#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff ++#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0 ++#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1 ++#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0 ++#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e ++#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 ++#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff ++#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 ++#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000 ++#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 ++#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1 ++#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0 ++#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6 ++#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1 ++#define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8 ++#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3 ++#define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0 ++#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4 ++#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00 ++#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8 ++#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000 ++#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10 ++#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000 ++#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18 ++#define MC_RPB_TCI_CNTL2__TCI_POLICY_MASK 0x1 ++#define MC_RPB_TCI_CNTL2__TCI_POLICY__SHIFT 0x0 ++#define MC_RPB_TCI_CNTL2__TCI_MTYPE_MASK 0x6 ++#define MC_RPB_TCI_CNTL2__TCI_MTYPE__SHIFT 0x1 ++#define MC_RPB_TCI_CNTL2__TCI_SNOOP_MASK 0x8 ++#define MC_RPB_TCI_CNTL2__TCI_SNOOP__SHIFT 0x3 ++#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL_MASK 0x10 ++#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL__SHIFT 0x4 ++#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN_MASK 0x20 ++#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN__SHIFT 0x5 ++#define MC_RPB_TCI_CNTL2__TCI_EXE_MASK 0x40 ++#define MC_RPB_TCI_CNTL2__TCI_EXE__SHIFT 0x6 ++#define MC_SHARED_CHMAP__CHAN0_MASK 0xf ++#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0 ++#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0 ++#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4 ++#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00 ++#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8 ++#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000 ++#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc ++#define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000 ++#define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10 ++#define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000 ++#define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14 ++#define MC_SHARED_CHREMAP__CHAN0_MASK 0xf ++#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0 ++#define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0 ++#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4 ++#define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00 ++#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8 ++#define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000 ++#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc ++#define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000 ++#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10 ++#define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000 ++#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14 ++#define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000 ++#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18 ++#define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000 ++#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c ++#define MC_RD_GRP_GFX__CP_MASK 0xf ++#define MC_RD_GRP_GFX__CP__SHIFT 0x0 ++#define MC_RD_GRP_GFX__SH_MASK 0xf0 ++#define MC_RD_GRP_GFX__SH__SHIFT 0x4 ++#define MC_RD_GRP_GFX__IA_MASK 0xf00 ++#define MC_RD_GRP_GFX__IA__SHIFT 0x8 ++#define MC_RD_GRP_GFX__ACPG_MASK 0xf000 ++#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc ++#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000 ++#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10 ++#define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000 ++#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14 ++#define MC_RD_GRP_GFX__ISP_MASK 0xf000000 ++#define MC_RD_GRP_GFX__ISP__SHIFT 0x18 ++#define MC_RD_GRP_GFX__VP8_MASK 0xf0000000 ++#define MC_RD_GRP_GFX__VP8__SHIFT 0x1c ++#define MC_WR_GRP_GFX__CP_MASK 0xf ++#define MC_WR_GRP_GFX__CP__SHIFT 0x0 ++#define MC_WR_GRP_GFX__SH_MASK 0xf0 ++#define MC_WR_GRP_GFX__SH__SHIFT 0x4 ++#define MC_WR_GRP_GFX__ACPG_MASK 0xf00 ++#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8 ++#define MC_WR_GRP_GFX__ACPO_MASK 0xf000 ++#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc ++#define MC_WR_GRP_GFX__ISP_MASK 0xf0000 ++#define MC_WR_GRP_GFX__ISP__SHIFT 0x10 ++#define MC_WR_GRP_GFX__VP8_MASK 0xf00000 ++#define MC_WR_GRP_GFX__VP8__SHIFT 0x14 ++#define MC_WR_GRP_GFX__XDMA_MASK 0xf000000 ++#define MC_WR_GRP_GFX__XDMA__SHIFT 0x18 ++#define MC_WR_GRP_GFX__XDMAM_MASK 0xf0000000 ++#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x1c ++#define MC_RD_GRP_SYS__RLC_MASK 0xf ++#define MC_RD_GRP_SYS__RLC__SHIFT 0x0 ++#define MC_RD_GRP_SYS__VMC_MASK 0xf0 ++#define MC_RD_GRP_SYS__VMC__SHIFT 0x4 ++#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00 ++#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8 ++#define MC_RD_GRP_SYS__DMIF_MASK 0xf000 ++#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc ++#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000 ++#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10 ++#define MC_RD_GRP_SYS__SMU_MASK 0xf00000 ++#define MC_RD_GRP_SYS__SMU__SHIFT 0x14 ++#define MC_RD_GRP_SYS__VCE0_MASK 0xf000000 ++#define MC_RD_GRP_SYS__VCE0__SHIFT 0x18 ++#define MC_RD_GRP_SYS__VCE1_MASK 0xf0000000 ++#define MC_RD_GRP_SYS__VCE1__SHIFT 0x1c ++#define MC_WR_GRP_SYS__IH_MASK 0xf ++#define MC_WR_GRP_SYS__IH__SHIFT 0x0 ++#define MC_WR_GRP_SYS__MCIF_MASK 0xf0 ++#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4 ++#define MC_WR_GRP_SYS__RLC_MASK 0xf00 ++#define MC_WR_GRP_SYS__RLC__SHIFT 0x8 ++#define MC_WR_GRP_SYS__SAMMSP_MASK 0xf000 ++#define MC_WR_GRP_SYS__SAMMSP__SHIFT 0xc ++#define MC_WR_GRP_SYS__SMU_MASK 0xf0000 ++#define MC_WR_GRP_SYS__SMU__SHIFT 0x10 ++#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000 ++#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14 ++#define MC_WR_GRP_SYS__VCE0_MASK 0xf000000 ++#define MC_WR_GRP_SYS__VCE0__SHIFT 0x18 ++#define MC_WR_GRP_SYS__VCE1_MASK 0xf0000000 ++#define MC_WR_GRP_SYS__VCE1__SHIFT 0x1c ++#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf ++#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0 ++#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0 ++#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4 ++#define MC_RD_GRP_OTH__HDP_MASK 0xf00 ++#define MC_RD_GRP_OTH__HDP__SHIFT 0x8 ++#define MC_RD_GRP_OTH__SEM_MASK 0xf000 ++#define MC_RD_GRP_OTH__SEM__SHIFT 0xc ++#define MC_RD_GRP_OTH__UMC_MASK 0xf0000 ++#define MC_RD_GRP_OTH__UMC__SHIFT 0x10 ++#define MC_RD_GRP_OTH__UVD_MASK 0xf00000 ++#define MC_RD_GRP_OTH__UVD__SHIFT 0x14 ++#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000 ++#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18 ++#define MC_RD_GRP_OTH__SAMMSP_MASK 0xf0000000 ++#define MC_RD_GRP_OTH__SAMMSP__SHIFT 0x1c ++#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf ++#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0 ++#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0 ++#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4 ++#define MC_WR_GRP_OTH__HDP_MASK 0xf00 ++#define MC_WR_GRP_OTH__HDP__SHIFT 0x8 ++#define MC_WR_GRP_OTH__SEM_MASK 0xf000 ++#define MC_WR_GRP_OTH__SEM__SHIFT 0xc ++#define MC_WR_GRP_OTH__UMC_MASK 0xf0000 ++#define MC_WR_GRP_OTH__UMC__SHIFT 0x10 ++#define MC_WR_GRP_OTH__UVD_MASK 0xf00000 ++#define MC_WR_GRP_OTH__UVD__SHIFT 0x14 ++#define MC_WR_GRP_OTH__XDP_MASK 0xf000000 ++#define MC_WR_GRP_OTH__XDP__SHIFT 0x18 ++#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000 ++#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c ++#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff ++#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0 ++#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000 ++#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10 ++#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff ++#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 ++#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff ++#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 ++#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff ++#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 ++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3 ++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0 ++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc ++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2 ++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30 ++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4 ++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0 ++#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6 ++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100 ++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8 ++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200 ++#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9 ++#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff ++#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 ++#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff ++#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 ++#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff ++#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 ++#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff ++#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 ++#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff ++#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 ++#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff ++#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 ++#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff ++#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 ++#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff ++#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0 ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1 ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2 ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1 ++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18 ++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 ++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20 ++#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40 ++#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 ++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780 ++#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 ++#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff ++#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 ++#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3 ++#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 ++#define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf ++#define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0 ++#define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0 ++#define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4 ++#define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00 ++#define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8 ++#define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000 ++#define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc ++#define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000 ++#define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10 ++#define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000 ++#define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14 ++#define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000 ++#define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18 ++#define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000 ++#define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c ++#define MC_SHARED_VF_ENABLE__VF_ENABLE_MASK 0x1 ++#define MC_SHARED_VF_ENABLE__VF_ENABLE__SHIFT 0x0 ++#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0xffff ++#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000 ++#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0xf ++#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000 ++#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1 ++#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0 ++#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2 ++#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1 ++#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4 ++#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2 ++#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8 ++#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3 ++#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10 ++#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4 ++#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 ++#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5 ++#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40 ++#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6 ++#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80 ++#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7 ++#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700 ++#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8 ++#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800 ++#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb ++#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000 ++#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc ++#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000 ++#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd ++#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000 ++#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f ++#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1 ++#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0 ++#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2 ++#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1 ++#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4 ++#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2 ++#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8 ++#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3 ++#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10 ++#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4 ++#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 ++#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5 ++#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40 ++#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6 ++#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80 ++#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7 ++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700 ++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8 ++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800 ++#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb ++#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000 ++#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd ++#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f ++#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 ++#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0 ++#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 ++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7 ++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0 ++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE_MASK 0x8 ++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE__SHIFT 0x3 ++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM_MASK 0xff0 ++#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM__SHIFT 0x4 ++#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH_MASK 0x1000 ++#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH__SHIFT 0xc ++#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN_MASK 0x2000 ++#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN__SHIFT 0xd ++#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 ++#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 ++#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 ++#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 ++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 ++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 ++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 ++#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc ++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000 ++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf ++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 ++#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 ++#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 ++#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 ++#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 ++#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 ++#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 ++#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 ++#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 ++#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc ++#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000 ++#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf ++#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 ++#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 ++#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 ++#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 ++#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 ++#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 ++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 ++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 ++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 ++#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc ++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000 ++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf ++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 ++#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 ++#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1 ++#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1 ++#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1 ++#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f ++#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0 ++#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 ++#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 ++#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 ++#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 ++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 ++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 ++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 ++#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc ++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000 ++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf ++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 ++#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 ++#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1 ++#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 ++#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 ++#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 ++#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 ++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 ++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 ++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 ++#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc ++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000 ++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf ++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 ++#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 ++#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 ++#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 ++#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 ++#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 ++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 ++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 ++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 ++#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc ++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000 ++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf ++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 ++#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 ++#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 ++#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 ++#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 ++#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 ++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 ++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 ++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 ++#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc ++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000 ++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf ++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 ++#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 ++#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1 ++#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1 ++#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1 ++#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0 ++#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f ++#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0 ++#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1 ++#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0 ++#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100 ++#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8 ++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00 ++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9 ++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000 ++#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc ++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000 ++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf ++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000 ++#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13 ++#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1 ++#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0 ++#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff ++#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 ++#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1 ++#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 ++#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1 ++#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 ++#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1 ++#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 ++#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1 ++#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 ++#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1 ++#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 ++#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1 ++#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 ++#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1 ++#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 ++#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1 ++#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 ++#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1 ++#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 ++#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1 ++#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 ++#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1 ++#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 ++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1 ++#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 ++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1 ++#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 ++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1 ++#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 ++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe ++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 ++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000 ++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 ++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000 ++#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 ++#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000 ++#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 ++#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000 ++#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a ++#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff ++#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0 ++#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00 ++#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8 ++#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000 ++#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10 ++#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000 ++#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11 ++#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000 ++#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19 ++#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff ++#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0 ++#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00 ++#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa ++#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000 ++#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14 ++#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000 ++#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a ++#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f ++#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0 ++#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0 ++#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6 ++#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000 ++#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc ++#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f ++#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0 ++#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0 ++#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6 ++#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000 ++#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc ++#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff ++#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 ++#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000 ++#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 ++#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000 ++#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 ++#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff ++#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0 ++#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000 ++#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10 ++#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000 ++#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12 ++#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf ++#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 ++#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30 ++#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 ++#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40 ++#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 ++#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80 ++#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 ++#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100 ++#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 ++#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200 ++#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 ++#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400 ++#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa ++#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800 ++#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb ++#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000 ++#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc ++#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf ++#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 ++#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0 ++#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 ++#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00 ++#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 ++#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000 ++#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc ++#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000 ++#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd ++#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000 ++#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe ++#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000 ++#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf ++#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000 ++#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 ++#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf ++#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 ++#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0 ++#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 ++#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00 ++#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 ++#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000 ++#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc ++#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000 ++#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd ++#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000 ++#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe ++#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000 ++#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf ++#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000 ++#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 ++#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf ++#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 ++#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0 ++#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 ++#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00 ++#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 ++#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000 ++#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc ++#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000 ++#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd ++#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000 ++#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe ++#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000 ++#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf ++#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000 ++#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 ++#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf ++#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 ++#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0 ++#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 ++#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00 ++#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 ++#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000 ++#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc ++#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000 ++#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd ++#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000 ++#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe ++#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000 ++#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf ++#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000 ++#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 ++#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf ++#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 ++#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0 ++#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 ++#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00 ++#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 ++#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000 ++#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc ++#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000 ++#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd ++#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000 ++#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe ++#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000 ++#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf ++#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000 ++#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 ++#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf ++#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 ++#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0 ++#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 ++#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00 ++#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 ++#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000 ++#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc ++#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000 ++#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd ++#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000 ++#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe ++#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000 ++#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf ++#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000 ++#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 ++#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf ++#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 ++#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0 ++#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 ++#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00 ++#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 ++#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000 ++#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc ++#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000 ++#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd ++#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000 ++#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe ++#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000 ++#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf ++#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000 ++#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 ++#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf ++#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 ++#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0 ++#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 ++#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00 ++#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 ++#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000 ++#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc ++#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000 ++#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd ++#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000 ++#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe ++#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000 ++#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf ++#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000 ++#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 ++#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff ++#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 ++#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00 ++#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 ++#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000 ++#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc ++#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000 ++#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd ++#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000 ++#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe ++#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000 ++#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf ++#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000 ++#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 ++#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff ++#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0 ++#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00 ++#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8 ++#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000 ++#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc ++#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff ++#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 ++#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00 ++#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 ++#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff ++#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 ++#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00 ++#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 ++#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1 ++#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 ++#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2 ++#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc ++#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2 ++#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1 ++#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 ++#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2 ++#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc ++#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2 ++#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1 ++#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 ++#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2 ++#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc ++#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2 ++#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1 ++#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 ++#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2 ++#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc ++#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2 ++#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1 ++#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 ++#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2 ++#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc ++#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2 ++#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1 ++#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 ++#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2 ++#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc ++#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2 ++#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1 ++#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 ++#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2 ++#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc ++#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2 ++#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1 ++#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 ++#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2 ++#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc ++#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2 ++#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1 ++#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 ++#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2 ++#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc ++#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2 ++#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1 ++#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 ++#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2 ++#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc ++#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2 ++#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1 ++#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 ++#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2 ++#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc ++#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2 ++#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1 ++#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 ++#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2 ++#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc ++#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2 ++#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1 ++#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 ++#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2 ++#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc ++#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2 ++#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1 ++#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 ++#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2 ++#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1 ++#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc ++#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2 ++#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f ++#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0 ++#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0 ++#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6 ++#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000 ++#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc ++#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000 ++#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12 ++#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000 ++#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 ++#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff ++#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 ++#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00 ++#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 ++#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000 ++#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 ++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000 ++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 ++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000 ++#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 ++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000 ++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 ++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000 ++#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a ++#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000 ++#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b ++#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000 ++#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d ++#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000 ++#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e ++#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000 ++#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f ++#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff ++#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 ++#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00 ++#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 ++#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000 ++#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf ++#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000 ++#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 ++#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000 ++#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 ++#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000 ++#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 ++#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000 ++#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 ++#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1 ++#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 ++#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe ++#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 ++#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00 ++#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 ++#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000 ++#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf ++#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000 ++#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 ++#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000 ++#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 ++#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000 ++#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 ++#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000 ++#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 ++#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000 ++#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 ++#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000 ++#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 ++#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000 ++#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 ++#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000 ++#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 ++#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000 ++#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 ++#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1 ++#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 ++#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2 ++#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 ++#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4 ++#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 ++#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8 ++#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 ++#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10 ++#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 ++#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20 ++#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 ++#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40 ++#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 ++#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80 ++#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 ++#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100 ++#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 ++#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200 ++#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 ++#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400 ++#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa ++#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800 ++#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb ++#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000 ++#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc ++#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000 ++#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd ++#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000 ++#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe ++#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000 ++#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf ++#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000 ++#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 ++#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000 ++#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 ++#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000 ++#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 ++#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000 ++#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 ++#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff ++#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 ++#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f ++#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 ++#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0 ++#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 ++#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000 ++#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc ++#define MC_XPB_STICKY__BITS_MASK 0xffffffff ++#define MC_XPB_STICKY__BITS__SHIFT 0x0 ++#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff ++#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0 ++#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff ++#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 ++#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00 ++#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 ++#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000 ++#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 ++#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000 ++#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 ++#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000 ++#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f ++#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff ++#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 ++#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff ++#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0 ++#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00 ++#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8 ++#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000 ++#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10 ++#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000 ++#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11 ++#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000 ++#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19 ++#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe ++#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf ++#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0 ++#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70 ++#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4 ++#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380 ++#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7 ++#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00 ++#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa ++#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000 ++#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe ++#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1 ++#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0 ++#define MC_XBAR_ADDR_DEC__GECC_MASK 0x2 ++#define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1 ++#define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4 ++#define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2 ++#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8 ++#define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3 ++#define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1 ++#define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0 ++#define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2 ++#define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1 ++#define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff ++#define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0 ++#define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00 ++#define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8 ++#define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000 ++#define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10 ++#define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000 ++#define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18 ++#define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff ++#define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0 ++#define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00 ++#define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8 ++#define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000 ++#define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10 ++#define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000 ++#define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18 ++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff ++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0 ++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00 ++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8 ++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000 ++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10 ++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000 ++#define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18 ++#define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff ++#define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0 ++#define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00 ++#define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8 ++#define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000 ++#define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10 ++#define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000 ++#define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18 ++#define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff ++#define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0 ++#define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00 ++#define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8 ++#define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff ++#define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0 ++#define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00 ++#define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8 ++#define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000 ++#define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10 ++#define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000 ++#define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18 ++#define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff ++#define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0 ++#define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00 ++#define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8 ++#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000 ++#define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10 ++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff ++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0 ++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00 ++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8 ++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000 ++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10 ++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000 ++#define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18 ++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff ++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0 ++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00 ++#define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8 ++#define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3 ++#define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0 ++#define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc ++#define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2 ++#define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30 ++#define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4 ++#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1 ++#define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0 ++#define MC_XBAR_TWOCHAN__CH0_MASK 0x6 ++#define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1 ++#define MC_XBAR_TWOCHAN__CH1_MASK 0x18 ++#define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3 ++#define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1 ++#define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0 ++#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2 ++#define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1 ++#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4 ++#define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2 ++#define MC_XBAR_ARB__ACP_RDRET_URG_MASK 0x8 ++#define MC_XBAR_ARB__ACP_RDRET_URG__SHIFT 0x3 ++#define MC_XBAR_ARB__HDP_RDRET_URG_MASK 0x10 ++#define MC_XBAR_ARB__HDP_RDRET_URG__SHIFT 0x4 ++#define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf ++#define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0 ++#define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0 ++#define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4 ++#define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00 ++#define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8 ++#define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000 ++#define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc ++#define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000 ++#define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10 ++#define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000 ++#define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14 ++#define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000 ++#define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18 ++#define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000 ++#define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c ++#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH_MASK 0xfff ++#define MC_XBAR_FIFO_MON_CNTL0__START_THRESH__SHIFT 0x0 ++#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH_MASK 0xfff000 ++#define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH__SHIFT 0xc ++#define MC_XBAR_FIFO_MON_CNTL0__START_MODE_MASK 0x3000000 ++#define MC_XBAR_FIFO_MON_CNTL0__START_MODE__SHIFT 0x18 ++#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE_MASK 0xc000000 ++#define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE__SHIFT 0x1a ++#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000 ++#define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c ++#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff ++#define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0 ++#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID_MASK 0xff00 ++#define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID__SHIFT 0x8 ++#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000 ++#define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10 ++#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID_MASK 0xff ++#define MC_XBAR_FIFO_MON_CNTL2__MON0_ID__SHIFT 0x0 ++#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID_MASK 0xff00 ++#define MC_XBAR_FIFO_MON_CNTL2__MON1_ID__SHIFT 0x8 ++#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID_MASK 0xff0000 ++#define MC_XBAR_FIFO_MON_CNTL2__MON2_ID__SHIFT 0x10 ++#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID_MASK 0xff000000 ++#define MC_XBAR_FIFO_MON_CNTL2__MON3_ID__SHIFT 0x18 ++#define MC_XBAR_FIFO_MON_RSLT0__COUNT_MASK 0xffffffff ++#define MC_XBAR_FIFO_MON_RSLT0__COUNT__SHIFT 0x0 ++#define MC_XBAR_FIFO_MON_RSLT1__COUNT_MASK 0xffffffff ++#define MC_XBAR_FIFO_MON_RSLT1__COUNT__SHIFT 0x0 ++#define MC_XBAR_FIFO_MON_RSLT2__COUNT_MASK 0xffffffff ++#define MC_XBAR_FIFO_MON_RSLT2__COUNT__SHIFT 0x0 ++#define MC_XBAR_FIFO_MON_RSLT3__COUNT_MASK 0xffffffff ++#define MC_XBAR_FIFO_MON_RSLT3__COUNT__SHIFT 0x0 ++#define MC_XBAR_FIFO_MON_MAX_THSH__MON0_MASK 0xff ++#define MC_XBAR_FIFO_MON_MAX_THSH__MON0__SHIFT 0x0 ++#define MC_XBAR_FIFO_MON_MAX_THSH__MON1_MASK 0xff00 ++#define MC_XBAR_FIFO_MON_MAX_THSH__MON1__SHIFT 0x8 ++#define MC_XBAR_FIFO_MON_MAX_THSH__MON2_MASK 0xff0000 ++#define MC_XBAR_FIFO_MON_MAX_THSH__MON2__SHIFT 0x10 ++#define MC_XBAR_FIFO_MON_MAX_THSH__MON3_MASK 0xff000000 ++#define MC_XBAR_FIFO_MON_MAX_THSH__MON3__SHIFT 0x18 ++#define MC_XBAR_SPARE0__BIT_MASK 0xffffffff ++#define MC_XBAR_SPARE0__BIT__SHIFT 0x0 ++#define MC_XBAR_SPARE1__BIT_MASK 0xffffffff ++#define MC_XBAR_SPARE1__BIT__SHIFT 0x0 ++#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff ++#define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff ++#define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff ++#define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff ++#define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff ++#define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff ++#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff ++#define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff ++#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff ++#define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 ++#define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff ++#define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 ++#define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff ++#define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 ++#define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff ++#define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 ++#define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff ++#define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 ++#define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff ++#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 ++#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff ++#define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 ++#define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff ++#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 ++#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff ++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 ++#define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 ++#define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff ++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 ++#define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 ++#define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff ++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 ++#define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 ++#define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff ++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 ++#define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c ++#define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 ++#define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d ++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff ++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 ++#define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 ++#define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff ++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 ++#define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 ++#define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff ++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 ++#define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 ++#define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff ++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 ++#define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c ++#define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 ++#define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d ++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff ++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 ++#define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 ++#define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff ++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 ++#define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 ++#define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff ++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 ++#define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 ++#define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff ++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 ++#define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c ++#define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 ++#define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d ++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff ++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 ++#define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 ++#define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff ++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 ++#define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 ++#define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff ++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 ++#define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 ++#define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff ++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 ++#define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c ++#define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 ++#define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d ++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff ++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 ++#define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 ++#define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff ++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 ++#define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 ++#define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff ++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 ++#define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 ++#define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff ++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 ++#define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c ++#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 ++#define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d ++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff ++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 ++#define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 ++#define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff ++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 ++#define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 ++#define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff ++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 ++#define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 ++#define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff ++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 ++#define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c ++#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 ++#define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d ++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff ++#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 ++#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 ++#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 ++#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 ++#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff ++#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 ++#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 ++#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 ++#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 ++#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff ++#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 ++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00 ++#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 ++#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000 ++#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 ++#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000 ++#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c ++#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000 ++#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d ++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff ++#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 ++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00 ++#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 ++#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000 ++#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 ++#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000 ++#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c ++#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000 ++#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 ++#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 ++#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 ++#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 ++#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf ++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 ++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 ++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 ++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 ++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 ++#define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf ++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 ++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 ++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 ++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 ++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 ++#define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf ++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 ++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 ++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 ++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 ++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 ++#define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf ++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 ++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 ++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 ++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 ++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 ++#define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf ++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 ++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 ++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 ++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 ++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 ++#define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 ++#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf ++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 ++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 ++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 ++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 ++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 ++#define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf ++#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 ++#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 ++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 ++#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 ++#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 ++#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff ++#define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff ++#define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 ++#define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff ++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 ++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 ++#define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 ++#define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 ++#define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff ++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 ++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 ++#define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 ++#define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 ++#define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf ++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 ++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 ++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 ++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 ++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 ++#define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define MC_GRUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff ++#define MC_GRUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 ++#define MC_GRUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff ++#define MC_GRUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 ++#define MC_GRUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000 ++#define MC_GRUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 ++#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff ++#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_GRUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_GRUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_GRUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_GRUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000 ++#define MC_GRUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c ++#define MC_GRUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000 ++#define MC_GRUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d ++#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff ++#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 ++#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00 ++#define MC_GRUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 ++#define MC_GRUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000 ++#define MC_GRUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 ++#define MC_GRUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000 ++#define MC_GRUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c ++#define MC_GRUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000 ++#define MC_GRUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d ++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf ++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 ++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00 ++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 ++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000 ++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 ++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000 ++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 ++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000 ++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 ++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000 ++#define MC_GRUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a ++#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff ++#define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 ++#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff ++#define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 ++#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff ++#define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 ++#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff ++#define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0 ++#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3 ++#define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0 ++#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3 ++#define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0 ++#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff ++#define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0 ++#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff ++#define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0 ++#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1 ++#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 ++#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2 ++#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 ++#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4 ++#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 ++#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00 ++#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 ++#define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000 ++#define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10 ++#define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1 ++#define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0 ++#define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2 ++#define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1 ++#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4 ++#define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2 ++#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20 ++#define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5 ++#define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40 ++#define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6 ++#define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80 ++#define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7 ++#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100 ++#define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8 ++#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200 ++#define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9 ++#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00 ++#define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa ++#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000 ++#define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe ++#define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000 ++#define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf ++#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000 ++#define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10 ++#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000 ++#define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11 ++#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x40000 ++#define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x12 ++#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING_MASK 0x80000 ++#define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING__SHIFT 0x13 ++#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH_MASK 0x100000 ++#define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH__SHIFT 0x14 ++#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT_MASK 0x200000 ++#define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT__SHIFT 0x15 ++#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f ++#define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0 ++#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100 ++#define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8 ++#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000 ++#define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10 ++#define ATC_ATS_STATUS__BUSY_MASK 0x1 ++#define ATC_ATS_STATUS__BUSY__SHIFT 0x0 ++#define ATC_ATS_STATUS__CRASHED_MASK 0x2 ++#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 ++#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4 ++#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 ++#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x1ff ++#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 ++#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x7fc00 ++#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa ++#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1ff00000 ++#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 ++#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x1ff ++#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 ++#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00 ++#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa ++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000 ++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf ++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000 ++#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 ++#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000 ++#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 ++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000 ++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 ++#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000 ++#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 ++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000 ++#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 ++#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff ++#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 ++#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xfffffff ++#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 ++#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1 ++#define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0 ++#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x1 ++#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 ++#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x3e ++#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 ++#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID_MASK 0x1fe00 ++#define ATC_ATS_FAULT_STATUS_INFO2__L1_ID__SHIFT 0x9 ++#define ATC_MISC_CG__OFFDLY_MASK 0xfc0 ++#define ATC_MISC_CG__OFFDLY__SHIFT 0x6 ++#define ATC_MISC_CG__ENABLE_MASK 0x40000 ++#define ATC_MISC_CG__ENABLE__SHIFT 0x12 ++#define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000 ++#define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200 ++#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9 ++#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f ++#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 ++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0 ++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 ++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100 ++#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 ++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00 ++#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 ++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000 ++#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc ++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000 ++#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf ++#define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f ++#define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0 ++#define ATC_L2_DEBUG__L2_MEM_SELECT_MASK 0x80 ++#define ATC_L2_DEBUG__L2_MEM_SELECT__SHIFT 0x7 ++#define ATC_L2_DEBUG__CACHE_INDEX_MASK 0xfff00 ++#define ATC_L2_DEBUG__CACHE_INDEX__SHIFT 0x8 ++#define ATC_L2_DEBUG__CACHE_SELECT_MASK 0x1000000 ++#define ATC_L2_DEBUG__CACHE_SELECT__SHIFT 0x18 ++#define ATC_L2_DEBUG__CACHE_BANK_SELECT_MASK 0x2000000 ++#define ATC_L2_DEBUG__CACHE_BANK_SELECT__SHIFT 0x19 ++#define ATC_L2_DEBUG__CACHE_WAY_SELECT_MASK 0x8000000 ++#define ATC_L2_DEBUG__CACHE_WAY_SELECT__SHIFT 0x1b ++#define ATC_L2_DEBUG__CACHE_READ_MASK 0x20000000 ++#define ATC_L2_DEBUG__CACHE_READ__SHIFT 0x1d ++#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR_MASK 0x40000000 ++#define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR__SHIFT 0x1e ++#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR_MASK 0x80000000 ++#define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR__SHIFT 0x1f ++#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f ++#define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0 ++#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0 ++#define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5 ++#define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100 ++#define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8 ++#define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200 ++#define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9 ++#define ATC_L2_DEBUG2__DISABLE_2M_CACHE_MASK 0x400 ++#define ATC_L2_DEBUG2__DISABLE_2M_CACHE__SHIFT 0xa ++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS_MASK 0x800 ++#define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS__SHIFT 0xb ++#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000 ++#define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe ++#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000 ++#define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf ++#define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000 ++#define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11 ++#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE_MASK 0x780000 ++#define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE__SHIFT 0x13 ++#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD_MASK 0x7f800000 ++#define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD__SHIFT 0x17 ++#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO_MASK 0x80000000 ++#define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO__SHIFT 0x1f ++#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x1 ++#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 ++#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x2 ++#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 ++#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x1fffffc ++#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 ++#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x1e000000 ++#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x19 ++#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xffffffff ++#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 ++#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW_MASK 0xfffffff ++#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW__SHIFT 0x0 ++#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3 ++#define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0 ++#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4 ++#define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2 ++#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10 ++#define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4 ++#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff ++#define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0 ++#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1 ++#define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0 ++#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2 ++#define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1 ++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0 ++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4 ++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700 ++#define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8 ++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000 ++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc ++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000 ++#define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14 ++#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000 ++#define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c ++#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000 ++#define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e ++#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000 ++#define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f ++#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1 ++#define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0 ++#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2 ++#define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1 ++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0 ++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4 ++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700 ++#define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8 ++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000 ++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc ++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000 ++#define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14 ++#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000 ++#define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c ++#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000 ++#define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e ++#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000 ++#define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f ++#define ATC_L1RD_STATUS__BUSY_MASK 0x1 ++#define ATC_L1RD_STATUS__BUSY__SHIFT 0x0 ++#define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2 ++#define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1 ++#define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100 ++#define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8 ++#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000 ++#define ATC_L1RD_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc ++#define ATC_L1RD_STATUS__CAM_INDEX_MASK 0x3e0000 ++#define ATC_L1RD_STATUS__CAM_INDEX__SHIFT 0x11 ++#define ATC_L1WR_STATUS__BUSY_MASK 0x1 ++#define ATC_L1WR_STATUS__BUSY__SHIFT 0x0 ++#define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2 ++#define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1 ++#define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100 ++#define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8 ++#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000 ++#define ATC_L1WR_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc ++#define ATC_L1WR_STATUS__CAM_INDEX_MASK 0x3e0000 ++#define ATC_L1WR_STATUS__CAM_INDEX__SHIFT 0x11 ++#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff ++#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0 ++#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000 ++#define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe ++#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000 ++#define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10 ++#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000 ++#define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11 ++#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000 ++#define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12 ++#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000 ++#define ATC_L1RD_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13 ++#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff ++#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0 ++#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000 ++#define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe ++#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000 ++#define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10 ++#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000 ++#define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11 ++#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000 ++#define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12 ++#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000 ++#define ATC_L1WR_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000 ++#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf ++#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff ++#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 ++#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000 ++#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e ++#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000 ++#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f ++#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x1 ++#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 ++#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x2 ++#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 ++#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x4 ++#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 ++#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x8 ++#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 ++#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x10 ++#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 ++#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x20 ++#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 ++#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x40 ++#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 ++#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x80 ++#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 ++#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x100 ++#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 ++#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x200 ++#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 ++#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x400 ++#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa ++#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x800 ++#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb ++#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x1000 ++#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc ++#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x2000 ++#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd ++#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x4000 ++#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe ++#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x8000 ++#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf ++#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN_MASK 0x1 ++#define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN__SHIFT 0x0 ++#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING_MASK 0x7f ++#define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING__SHIFT 0x0 ++#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER_MASK 0x80 ++#define ATC_L2_CNTL3__ENABLE_FREE_COUNTER__SHIFT 0x7 ++#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD_MASK 0x1f00 ++#define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD__SHIFT 0x8 ++#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION_MASK 0x2000 ++#define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION__SHIFT 0xd ++#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST_MASK 0x1c000 ++#define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0xe ++#define ATC_L2_STATUS__BUSY_MASK 0x1 ++#define ATC_L2_STATUS__BUSY__SHIFT 0x0 ++#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3ffffffe ++#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 ++#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE_MASK 0x7 ++#define ATC_L2_STATUS2__CACHE_ADDRESS_MODE__SHIFT 0x0 ++#define ATC_L2_STATUS2__PARITY_ERROR_INFO_MASK 0x7f8 ++#define ATC_L2_STATUS2__PARITY_ERROR_INFO__SHIFT 0x3 ++#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff ++#define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 ++#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff ++#define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 ++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1 ++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 ++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2 ++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 ++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc ++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 ++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000 ++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc ++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000 ++#define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16 ++#define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400 ++#define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa ++#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800 ++#define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb ++#define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000 ++#define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc ++#define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000 ++#define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10 ++#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000 ++#define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11 ++#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000 ++#define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13 ++#define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000 ++#define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15 ++#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000 ++#define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16 ++#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000 ++#define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17 ++#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000 ++#define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18 ++#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000 ++#define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19 ++#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000 ++#define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a ++#define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000 ++#define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b ++#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000 ++#define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c ++#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000 ++#define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f ++#define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f ++#define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x0 ++#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0 ++#define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6 ++#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800 ++#define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb ++#define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe0000 ++#define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x11 ++#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000 ++#define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d ++#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000 ++#define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e ++#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000 ++#define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f ++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff ++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0 ++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000 ++#define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10 ++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff ++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0 ++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000 ++#define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10 ++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff ++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0 ++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000 ++#define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10 ++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff ++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 ++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000 ++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 ++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff ++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 ++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000 ++#define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 ++#define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff ++#define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0 ++#define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000 ++#define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc ++#define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000 ++#define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18 ++#define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000 ++#define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a ++#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000 ++#define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c ++#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x20000000 ++#define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d ++#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x40000000 ++#define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e ++#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x80000000 ++#define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f ++#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f ++#define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0 ++#define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0 ++#define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6 ++#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000 ++#define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc ++#define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc0000 ++#define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12 ++#define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe000000 ++#define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x19 ++#define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff ++#define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0 ++#define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff ++#define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0 ++#define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff ++#define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 ++#define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 ++#define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 ++#define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200 ++#define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 ++#define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400 ++#define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa ++#define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800 ++#define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb ++#define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000 ++#define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc ++#define GMCON_PGFSM_CONFIG__READ_MASK 0x2000 ++#define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd ++#define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000 ++#define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe ++#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 ++#define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b ++#define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 ++#define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c ++#define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff ++#define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0 ++#define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff ++#define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0 ++#define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000 ++#define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18 ++#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000 ++#define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c ++#define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff ++#define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0 ++#define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff00 ++#define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x8 ++#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff0000 ++#define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 ++#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x10000000 ++#define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c ++#define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x20000000 ++#define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d ++#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x40000000 ++#define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e ++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1 ++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0 ++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2 ++#define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1 ++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4 ++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2 ++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8 ++#define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3 ++#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff0 ++#define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4 ++#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff ++#define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x0 ++#define GMCON_DEBUG__GFX_STALL_MASK 0x1 ++#define GMCON_DEBUG__GFX_STALL__SHIFT 0x0 ++#define GMCON_DEBUG__GFX_CLEAR_MASK 0x2 ++#define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1 ++#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0_MASK 0x4 ++#define GMCON_DEBUG__GMCON_DEBUG_RESERVED0__SHIFT 0x2 ++#define GMCON_DEBUG__SR_COMMIT_STATE_MASK 0x8 ++#define GMCON_DEBUG__SR_COMMIT_STATE__SHIFT 0x3 ++#define GMCON_DEBUG__STCTRL_ST_MASK 0xf0 ++#define GMCON_DEBUG__STCTRL_ST__SHIFT 0x4 ++#define GMCON_DEBUG__MISC_FLAGS_MASK 0xffffff00 ++#define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x8 ++#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1 ++#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 ++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2 ++#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 ++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc ++#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 ++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30 ++#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 ++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100 ++#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 ++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200 ++#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 ++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400 ++#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa ++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800 ++#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb ++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000 ++#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc ++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000 ++#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf ++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000 ++#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 ++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000 ++#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 ++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000 ++#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 ++#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000 ++#define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a ++#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000 ++#define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c ++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1 ++#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 ++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2 ++#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 ++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000 ++#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 ++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000 ++#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 ++#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000 ++#define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 ++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000 ++#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a ++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000 ++#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c ++#define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f ++#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 ++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0 ++#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 ++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00 ++#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 ++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000 ++#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf ++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000 ++#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 ++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000 ++#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 ++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000 ++#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 ++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000 ++#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c ++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000 ++#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d ++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000 ++#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e ++#define VM_L2_STATUS__L2_BUSY_MASK 0x1 ++#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 ++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe ++#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 ++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1 ++#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6 ++#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 ++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 ++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 ++#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 ++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 ++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 ++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 ++#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800 ++#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000 ++#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000 ++#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000 ++#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000 ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000 ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000 ++#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 ++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000 ++#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 ++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1 ++#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 ++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6 ++#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 ++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8 ++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 ++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10 ++#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 ++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40 ++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 ++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80 ++#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200 ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400 ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800 ++#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000 ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000 ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000 ++#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000 ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000 ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000 ++#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000 ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000 ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000 ++#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000 ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000 ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000 ++#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 ++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000 ++#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1 ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2 ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc ++#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2 ++#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff ++#define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0 ++#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1 ++#define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 ++#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2 ++#define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 ++#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4 ++#define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 ++#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8 ++#define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 ++#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10 ++#define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 ++#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1 ++#define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 ++#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2 ++#define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 ++#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4 ++#define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 ++#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8 ++#define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 ++#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10 ++#define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 ++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000 ++#define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000 ++#define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf ++#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1 ++#define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0 ++#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2 ++#define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1 ++#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4 ++#define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2 ++#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8 ++#define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3 ++#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10 ++#define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4 ++#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20 ++#define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5 ++#define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40 ++#define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000 ++#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf ++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff ++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 ++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000 ++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc ++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000 ++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 ++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000 ++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 ++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000 ++#define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d ++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff ++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0 ++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000 ++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc ++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000 ++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18 ++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000 ++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19 ++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000 ++#define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d ++#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff ++#define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0 ++#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff ++#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0 ++#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff ++#define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0 ++#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff ++#define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0 ++#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff ++#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0 ++#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff ++#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0 ++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff ++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0 ++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00 ++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9 ++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB_MASK 0x40000 ++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB__SHIFT 0x12 ++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB_MASK 0x80000 ++#define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB__SHIFT 0x13 ++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_DEBUG__FLAGS_MASK 0xffffffff ++#define VM_DEBUG__FLAGS__SHIFT 0x0 ++#define VM_L2_CG__OFFDLY_MASK 0xfc0 ++#define VM_L2_CG__OFFDLY__SHIFT 0x6 ++#define VM_L2_CG__ENABLE_MASK 0x40000 ++#define VM_L2_CG__ENABLE__SHIFT 0x12 ++#define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000 ++#define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13 ++#define VM_L2_CG__OVERRIDE_MASK 0x100000 ++#define VM_L2_CG__OVERRIDE__SHIFT 0x14 ++#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff ++#define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0 ++#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x7f ++#define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff ++#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0 ++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff ++#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0 ++#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x3f ++#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x40 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x80 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x100 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x200 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x400 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x800 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x1000 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x2000 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x4000 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x8000 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x10000 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x20000 ++#define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x1ff ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x7fc00 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa ++#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x100000 ++#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x1000000 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x2000000 ++#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 ++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0xffff ++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 ++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xffff0000 ++#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 ++#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xffffffff ++#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 ++#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xffffffff ++#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 ++#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x800000 ++#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 ++#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x8 ++#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 ++#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xff800000 ++#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 ++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x1 ++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 ++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xff800000 ++#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 ++#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0xff ++#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 ++#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3fffffff ++#define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0 ++#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000 ++#define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f ++#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xfffff000 ++#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc ++#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xfffff000 ++#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc ++#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xfffff000 ++#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc ++#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xfffff000 ++#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc ++#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0xfffff ++#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 ++#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0xfffff ++#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 ++#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0xfffff ++#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 ++#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0xfffff ++#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x1 ++#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x2 ++#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 ++#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xfffff000 ++#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc ++#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x1 ++#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x2 ++#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 ++#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xfffff000 ++#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc ++#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x1 ++#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x2 ++#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 ++#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xfffff000 ++#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc ++#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x1 ++#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x2 ++#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 ++#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xfffff000 ++#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc ++#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0xfffff ++#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0xfffff ++#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0xfffff ++#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 ++#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0xfffff ++#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 ++#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xfffff000 ++#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc ++#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xfffff000 ++#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc ++#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xfffff000 ++#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc ++#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xfffff000 ++#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc ++#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0xfffff ++#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 ++#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0xfffff ++#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 ++#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0xfffff ++#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 ++#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0xfffff ++#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 ++#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS_MASK 0x1 ++#define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS__SHIFT 0x0 ++#define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff ++#define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0 ++#define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00 ++#define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8 ++#define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000 ++#define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10 ++#define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000 ++#define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18 ++#define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff ++#define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0 ++#define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00 ++#define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8 ++#define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000 ++#define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10 ++#define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000 ++#define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18 ++#define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff ++#define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0 ++#define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00 ++#define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8 ++#define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000 ++#define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10 ++#define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000 ++#define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18 ++#define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff ++#define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0 ++#define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00 ++#define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8 ++#define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000 ++#define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10 ++#define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000 ++#define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18 ++#define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff ++#define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0 ++#define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00 ++#define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8 ++#define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000 ++#define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10 ++#define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000 ++#define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18 ++#define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff ++#define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0 ++#define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00 ++#define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8 ++#define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000 ++#define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10 ++#define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000 ++#define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18 ++#define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff ++#define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0 ++#define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00 ++#define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8 ++#define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000 ++#define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10 ++#define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000 ++#define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18 ++#define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff ++#define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0 ++#define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00 ++#define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8 ++#define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000 ++#define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10 ++#define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000 ++#define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18 ++#define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff ++#define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0 ++#define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00 ++#define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8 ++#define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000 ++#define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10 ++#define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000 ++#define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18 ++#define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff ++#define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0 ++#define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00 ++#define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8 ++#define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000 ++#define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10 ++#define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000 ++#define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18 ++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff ++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0 ++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00 ++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8 ++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000 ++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10 ++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000 ++#define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18 ++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff ++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0 ++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00 ++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8 ++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000 ++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10 ++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000 ++#define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18 ++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff ++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0 ++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00 ++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8 ++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000 ++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10 ++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000 ++#define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18 ++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff ++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0 ++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00 ++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8 ++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000 ++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10 ++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000 ++#define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18 ++#define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff ++#define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0 ++#define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00 ++#define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8 ++#define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000 ++#define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10 ++#define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000 ++#define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18 ++#define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff ++#define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0 ++#define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00 ++#define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8 ++#define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000 ++#define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10 ++#define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000 ++#define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18 ++#define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff ++#define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0 ++#define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00 ++#define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8 ++#define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000 ++#define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10 ++#define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000 ++#define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18 ++#define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff ++#define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0 ++#define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00 ++#define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8 ++#define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000 ++#define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10 ++#define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000 ++#define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18 ++#define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff ++#define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0 ++#define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00 ++#define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8 ++#define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000 ++#define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10 ++#define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000 ++#define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18 ++#define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff ++#define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0 ++#define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00 ++#define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8 ++#define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000 ++#define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10 ++#define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000 ++#define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18 ++#define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff ++#define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0 ++#define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00 ++#define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8 ++#define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000 ++#define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10 ++#define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000 ++#define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18 ++#define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff ++#define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0 ++#define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00 ++#define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8 ++#define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000 ++#define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10 ++#define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000 ++#define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18 ++#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff ++#define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0 ++#define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100 ++#define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8 ++#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200 ++#define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9 ++#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400 ++#define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa ++#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800 ++#define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb ++#define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000 ++#define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc ++#define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000 ++#define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe ++#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000 ++#define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16 ++#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff ++#define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0 ++#define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100 ++#define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8 ++#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200 ++#define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9 ++#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400 ++#define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa ++#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800 ++#define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb ++#define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000 ++#define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc ++#define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000 ++#define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe ++#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000 ++#define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16 ++#define MC_ARB_GRUB_PRIORITY1_RD__CB0_MASK 0x3 ++#define MC_ARB_GRUB_PRIORITY1_RD__CB0__SHIFT 0x0 ++#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0_MASK 0xc ++#define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0__SHIFT 0x2 ++#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0_MASK 0x30 ++#define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0__SHIFT 0x4 ++#define MC_ARB_GRUB_PRIORITY1_RD__DB0_MASK 0xc0 ++#define MC_ARB_GRUB_PRIORITY1_RD__DB0__SHIFT 0x6 ++#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0_MASK 0x300 ++#define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0__SHIFT 0x8 ++#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0_MASK 0xc00 ++#define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0__SHIFT 0xa ++#define MC_ARB_GRUB_PRIORITY1_RD__TC0_MASK 0x3000 ++#define MC_ARB_GRUB_PRIORITY1_RD__TC0__SHIFT 0xc ++#define MC_ARB_GRUB_PRIORITY1_RD__ACPG_MASK 0xc000 ++#define MC_ARB_GRUB_PRIORITY1_RD__ACPG__SHIFT 0xe ++#define MC_ARB_GRUB_PRIORITY1_RD__ACPO_MASK 0x30000 ++#define MC_ARB_GRUB_PRIORITY1_RD__ACPO__SHIFT 0x10 ++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_MASK 0xc0000 ++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF__SHIFT 0x12 ++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0_MASK 0x300000 ++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0__SHIFT 0x14 ++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1_MASK 0xc00000 ++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1__SHIFT 0x16 ++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW_MASK 0x3000000 ++#define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW__SHIFT 0x18 ++#define MC_ARB_GRUB_PRIORITY1_RD__MCIF_MASK 0xc000000 ++#define MC_ARB_GRUB_PRIORITY1_RD__MCIF__SHIFT 0x1a ++#define MC_ARB_GRUB_PRIORITY1_RD__RLC_MASK 0x30000000 ++#define MC_ARB_GRUB_PRIORITY1_RD__RLC__SHIFT 0x1c ++#define MC_ARB_GRUB_PRIORITY1_RD__VMC_MASK 0xc0000000 ++#define MC_ARB_GRUB_PRIORITY1_RD__VMC__SHIFT 0x1e ++#define MC_ARB_GRUB_PRIORITY1_WR__CB0_MASK 0x3 ++#define MC_ARB_GRUB_PRIORITY1_WR__CB0__SHIFT 0x0 ++#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0_MASK 0xc ++#define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0__SHIFT 0x2 ++#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0_MASK 0x30 ++#define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0__SHIFT 0x4 ++#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0_MASK 0xc0 ++#define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0__SHIFT 0x6 ++#define MC_ARB_GRUB_PRIORITY1_WR__DB0_MASK 0x300 ++#define MC_ARB_GRUB_PRIORITY1_WR__DB0__SHIFT 0x8 ++#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0_MASK 0xc00 ++#define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0__SHIFT 0xa ++#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0_MASK 0x3000 ++#define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0__SHIFT 0xc ++#define MC_ARB_GRUB_PRIORITY1_WR__TC0_MASK 0xc000 ++#define MC_ARB_GRUB_PRIORITY1_WR__TC0__SHIFT 0xe ++#define MC_ARB_GRUB_PRIORITY1_WR__SH_MASK 0x30000 ++#define MC_ARB_GRUB_PRIORITY1_WR__SH__SHIFT 0x10 ++#define MC_ARB_GRUB_PRIORITY1_WR__ACPG_MASK 0xc0000 ++#define MC_ARB_GRUB_PRIORITY1_WR__ACPG__SHIFT 0x12 ++#define MC_ARB_GRUB_PRIORITY1_WR__ACPO_MASK 0x300000 ++#define MC_ARB_GRUB_PRIORITY1_WR__ACPO__SHIFT 0x14 ++#define MC_ARB_GRUB_PRIORITY1_WR__MCIF_MASK 0xc00000 ++#define MC_ARB_GRUB_PRIORITY1_WR__MCIF__SHIFT 0x16 ++#define MC_ARB_GRUB_PRIORITY1_WR__RLC_MASK 0x3000000 ++#define MC_ARB_GRUB_PRIORITY1_WR__RLC__SHIFT 0x18 ++#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1_MASK 0xc000000 ++#define MC_ARB_GRUB_PRIORITY1_WR__SDMA1__SHIFT 0x1a ++#define MC_ARB_GRUB_PRIORITY1_WR__SMU_MASK 0x30000000 ++#define MC_ARB_GRUB_PRIORITY1_WR__SMU__SHIFT 0x1c ++#define MC_ARB_GRUB_PRIORITY1_WR__VCE0_MASK 0xc0000000 ++#define MC_ARB_GRUB_PRIORITY1_WR__VCE0__SHIFT 0x1e ++#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1_MASK 0x3 ++#define MC_ARB_GRUB_PRIORITY2_RD__SDMA1__SHIFT 0x0 ++#define MC_ARB_GRUB_PRIORITY2_RD__SMU_MASK 0xc ++#define MC_ARB_GRUB_PRIORITY2_RD__SMU__SHIFT 0x2 ++#define MC_ARB_GRUB_PRIORITY2_RD__VCE0_MASK 0x30 ++#define MC_ARB_GRUB_PRIORITY2_RD__VCE0__SHIFT 0x4 ++#define MC_ARB_GRUB_PRIORITY2_RD__VCE1_MASK 0xc0 ++#define MC_ARB_GRUB_PRIORITY2_RD__VCE1__SHIFT 0x6 ++#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM_MASK 0x300 ++#define MC_ARB_GRUB_PRIORITY2_RD__XDMAM__SHIFT 0x8 ++#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0_MASK 0xc00 ++#define MC_ARB_GRUB_PRIORITY2_RD__SDMA0__SHIFT 0xa ++#define MC_ARB_GRUB_PRIORITY2_RD__HDP_MASK 0x3000 ++#define MC_ARB_GRUB_PRIORITY2_RD__HDP__SHIFT 0xc ++#define MC_ARB_GRUB_PRIORITY2_RD__UMC_MASK 0xc000 ++#define MC_ARB_GRUB_PRIORITY2_RD__UMC__SHIFT 0xe ++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_MASK 0x30000 ++#define MC_ARB_GRUB_PRIORITY2_RD__UVD__SHIFT 0x10 ++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0_MASK 0xc0000 ++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0__SHIFT 0x12 ++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1_MASK 0x300000 ++#define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1__SHIFT 0x14 ++#define MC_ARB_GRUB_PRIORITY2_RD__SEM_MASK 0xc00000 ++#define MC_ARB_GRUB_PRIORITY2_RD__SEM__SHIFT 0x16 ++#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP_MASK 0x3000000 ++#define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP__SHIFT 0x18 ++#define MC_ARB_GRUB_PRIORITY2_RD__VP8_MASK 0xc000000 ++#define MC_ARB_GRUB_PRIORITY2_RD__VP8__SHIFT 0x1a ++#define MC_ARB_GRUB_PRIORITY2_RD__ISP_MASK 0x30000000 ++#define MC_ARB_GRUB_PRIORITY2_RD__ISP__SHIFT 0x1c ++#define MC_ARB_GRUB_PRIORITY2_RD__RSV2_MASK 0xc0000000 ++#define MC_ARB_GRUB_PRIORITY2_RD__RSV2__SHIFT 0x1e ++#define MC_ARB_GRUB_PRIORITY2_WR__VCE1_MASK 0x3 ++#define MC_ARB_GRUB_PRIORITY2_WR__VCE1__SHIFT 0x0 ++#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP_MASK 0xc ++#define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP__SHIFT 0x2 ++#define MC_ARB_GRUB_PRIORITY2_WR__XDMA_MASK 0x30 ++#define MC_ARB_GRUB_PRIORITY2_WR__XDMA__SHIFT 0x4 ++#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM_MASK 0xc0 ++#define MC_ARB_GRUB_PRIORITY2_WR__XDMAM__SHIFT 0x6 ++#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0_MASK 0x300 ++#define MC_ARB_GRUB_PRIORITY2_WR__SDMA0__SHIFT 0x8 ++#define MC_ARB_GRUB_PRIORITY2_WR__HDP_MASK 0xc00 ++#define MC_ARB_GRUB_PRIORITY2_WR__HDP__SHIFT 0xa ++#define MC_ARB_GRUB_PRIORITY2_WR__UMC_MASK 0x3000 ++#define MC_ARB_GRUB_PRIORITY2_WR__UMC__SHIFT 0xc ++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_MASK 0xc000 ++#define MC_ARB_GRUB_PRIORITY2_WR__UVD__SHIFT 0xe ++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0_MASK 0x30000 ++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0__SHIFT 0x10 ++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1_MASK 0xc0000 ++#define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1__SHIFT 0x12 ++#define MC_ARB_GRUB_PRIORITY2_WR__XDP_MASK 0x300000 ++#define MC_ARB_GRUB_PRIORITY2_WR__XDP__SHIFT 0x14 ++#define MC_ARB_GRUB_PRIORITY2_WR__SEM_MASK 0xc00000 ++#define MC_ARB_GRUB_PRIORITY2_WR__SEM__SHIFT 0x16 ++#define MC_ARB_GRUB_PRIORITY2_WR__IH_MASK 0x3000000 ++#define MC_ARB_GRUB_PRIORITY2_WR__IH__SHIFT 0x18 ++#define MC_ARB_GRUB_PRIORITY2_WR__VP8_MASK 0xc000000 ++#define MC_ARB_GRUB_PRIORITY2_WR__VP8__SHIFT 0x1a ++#define MC_ARB_GRUB_PRIORITY2_WR__ISP_MASK 0x30000000 ++#define MC_ARB_GRUB_PRIORITY2_WR__ISP__SHIFT 0x1c ++#define MC_ARB_GRUB_PRIORITY2_WR__VIN0_MASK 0xc0000000 ++#define MC_ARB_GRUB_PRIORITY2_WR__VIN0__SHIFT 0x1e ++#define MC_FUS_DRAM0_CS0_BASE__CSENABLE_MASK 0x1 ++#define MC_FUS_DRAM0_CS0_BASE__CSENABLE__SHIFT 0x0 ++#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11_MASK 0xffe0 ++#define MC_FUS_DRAM0_CS0_BASE__BASEADDR21_11__SHIFT 0x5 ++#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000 ++#define MC_FUS_DRAM0_CS0_BASE__BASEADDR38_27__SHIFT 0x13 ++#define MC_FUS_DRAM1_CS0_BASE__CSENABLE_MASK 0x1 ++#define MC_FUS_DRAM1_CS0_BASE__CSENABLE__SHIFT 0x0 ++#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11_MASK 0xffe0 ++#define MC_FUS_DRAM1_CS0_BASE__BASEADDR21_11__SHIFT 0x5 ++#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27_MASK 0x7ff80000 ++#define MC_FUS_DRAM1_CS0_BASE__BASEADDR38_27__SHIFT 0x13 ++#define MC_FUS_DRAM0_CS1_BASE__CSENABLE_MASK 0x1 ++#define MC_FUS_DRAM0_CS1_BASE__CSENABLE__SHIFT 0x0 ++#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11_MASK 0xffe0 ++#define MC_FUS_DRAM0_CS1_BASE__BASEADDR21_11__SHIFT 0x5 ++#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000 ++#define MC_FUS_DRAM0_CS1_BASE__BASEADDR38_27__SHIFT 0x13 ++#define MC_FUS_DRAM1_CS1_BASE__CSENABLE_MASK 0x1 ++#define MC_FUS_DRAM1_CS1_BASE__CSENABLE__SHIFT 0x0 ++#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11_MASK 0xffe0 ++#define MC_FUS_DRAM1_CS1_BASE__BASEADDR21_11__SHIFT 0x5 ++#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27_MASK 0x7ff80000 ++#define MC_FUS_DRAM1_CS1_BASE__BASEADDR38_27__SHIFT 0x13 ++#define MC_FUS_DRAM0_CS2_BASE__CSENABLE_MASK 0x1 ++#define MC_FUS_DRAM0_CS2_BASE__CSENABLE__SHIFT 0x0 ++#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11_MASK 0xffe0 ++#define MC_FUS_DRAM0_CS2_BASE__BASEADDR21_11__SHIFT 0x5 ++#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000 ++#define MC_FUS_DRAM0_CS2_BASE__BASEADDR38_27__SHIFT 0x13 ++#define MC_FUS_DRAM1_CS2_BASE__CSENABLE_MASK 0x1 ++#define MC_FUS_DRAM1_CS2_BASE__CSENABLE__SHIFT 0x0 ++#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11_MASK 0xffe0 ++#define MC_FUS_DRAM1_CS2_BASE__BASEADDR21_11__SHIFT 0x5 ++#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27_MASK 0x7ff80000 ++#define MC_FUS_DRAM1_CS2_BASE__BASEADDR38_27__SHIFT 0x13 ++#define MC_FUS_DRAM0_CS3_BASE__CSENABLE_MASK 0x1 ++#define MC_FUS_DRAM0_CS3_BASE__CSENABLE__SHIFT 0x0 ++#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11_MASK 0xffe0 ++#define MC_FUS_DRAM0_CS3_BASE__BASEADDR21_11__SHIFT 0x5 ++#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000 ++#define MC_FUS_DRAM0_CS3_BASE__BASEADDR38_27__SHIFT 0x13 ++#define MC_FUS_DRAM1_CS3_BASE__CSENABLE_MASK 0x1 ++#define MC_FUS_DRAM1_CS3_BASE__CSENABLE__SHIFT 0x0 ++#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11_MASK 0xffe0 ++#define MC_FUS_DRAM1_CS3_BASE__BASEADDR21_11__SHIFT 0x5 ++#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27_MASK 0x7ff80000 ++#define MC_FUS_DRAM1_CS3_BASE__BASEADDR38_27__SHIFT 0x13 ++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf ++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0 ++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0 ++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4 ++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100 ++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8 ++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200 ++#define MC_FUS_DRAM0_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9 ++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP_MASK 0xf ++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM0ADDRMAP__SHIFT 0x0 ++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP_MASK 0xf0 ++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__DIMM1ADDRMAP__SHIFT 0x4 ++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE_MASK 0x100 ++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWIZZLEMODE__SHIFT 0x8 ++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP_MASK 0x200 ++#define MC_FUS_DRAM1_BANK_ADDR_MAPPING__BANKSWAP__SHIFT 0x9 ++#define MC_FUS_DRAM0_CTL_BASE__DCTSEL_MASK 0x7 ++#define MC_FUS_DRAM0_CTL_BASE__DCTSEL__SHIFT 0x0 ++#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN_MASK 0x78 ++#define MC_FUS_DRAM0_CTL_BASE__DCTINTLVEN__SHIFT 0x3 ++#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR_MASK 0xfffff80 ++#define MC_FUS_DRAM0_CTL_BASE__DCTBASEADDR__SHIFT 0x7 ++#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN_MASK 0x10000000 ++#define MC_FUS_DRAM0_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c ++#define MC_FUS_DRAM1_CTL_BASE__DCTSEL_MASK 0x7 ++#define MC_FUS_DRAM1_CTL_BASE__DCTSEL__SHIFT 0x0 ++#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN_MASK 0x78 ++#define MC_FUS_DRAM1_CTL_BASE__DCTINTLVEN__SHIFT 0x3 ++#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR_MASK 0xfffff80 ++#define MC_FUS_DRAM1_CTL_BASE__DCTBASEADDR__SHIFT 0x7 ++#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN_MASK 0x10000000 ++#define MC_FUS_DRAM1_CTL_BASE__DCTOFFSETEN__SHIFT 0x1c ++#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff ++#define MC_FUS_DRAM0_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0 ++#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000 ++#define MC_FUS_DRAM0_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15 ++#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR_MASK 0x1fffff ++#define MC_FUS_DRAM1_CTL_LIMIT__DCTLIMITADDR__SHIFT 0x0 ++#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID_MASK 0x200000 ++#define MC_FUS_DRAM1_CTL_LIMIT__DRAMHOLEVALID__SHIFT 0x15 ++#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0_MASK 0xfff ++#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF0__SHIFT 0x0 ++#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1_MASK 0xfff000 ++#define MC_FUS_DRAM_CTL_HIGH_01__DCTHIGHADDROFF1__SHIFT 0xc ++#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2_MASK 0xfff ++#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF2__SHIFT 0x0 ++#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3_MASK 0xfff000 ++#define MC_FUS_DRAM_CTL_HIGH_23__DCTHIGHADDROFF3__SHIFT 0xc ++#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR_MASK 0x7 ++#define MC_FUS_DRAM_MODE__DCTSELINTLVADDR__SHIFT 0x0 ++#define MC_FUS_DRAM_MODE__DRAMTYPE_MASK 0x38 ++#define MC_FUS_DRAM_MODE__DRAMTYPE__SHIFT 0x3 ++#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET_MASK 0x7fc0 ++#define MC_FUS_DRAM_MODE__DRAMHOLEOFFSET__SHIFT 0x6 ++#define MC_FUS_DRAM_MODE__DDR3LPX32_MASK 0x8000 ++#define MC_FUS_DRAM_MODE__DDR3LPX32__SHIFT 0xf ++#define MC_FUS_DRAM_MODE__BANKGROUPSWAP_MASK 0x10000 ++#define MC_FUS_DRAM_MODE__BANKGROUPSWAP__SHIFT 0x10 ++#define MC_FUS_DRAM_APER_BASE__BASE_MASK 0xfffff ++#define MC_FUS_DRAM_APER_BASE__BASE__SHIFT 0x0 ++#define MC_FUS_DRAM_APER_TOP__TOP_MASK 0xfffff ++#define MC_FUS_DRAM_APER_TOP__TOP__SHIFT 0x0 ++#define MC_FUS_DRAM_APER_DEF__DEF_MASK 0xfffffff ++#define MC_FUS_DRAM_APER_DEF__DEF__SHIFT 0x0 ++#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS_MASK 0x10000000 ++#define MC_FUS_DRAM_APER_DEF__LOCK_MC_FUS_DRAM_REGS__SHIFT 0x1c ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN_MASK 0x1 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_TOKURG_EN__SHIFT 0x0 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN_MASK 0x2 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_TOKURG_EN__SHIFT 0x1 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN_MASK 0x4 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_TOKURG_EN__SHIFT 0x2 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN_MASK 0x8 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_TOKURG_EN__SHIFT 0x3 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN_MASK 0x10 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_PRIURG_EN__SHIFT 0x4 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN_MASK 0x20 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_PRIURG_EN__SHIFT 0x5 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN_MASK 0x40 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_PRIURG_EN__SHIFT 0x6 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN_MASK 0x80 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_PRIURG_EN__SHIFT 0x7 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN_MASK 0x100 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__DMIF_RD_ISOC_EN__SHIFT 0x8 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN_MASK 0x200 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UVD_RD_ISOC_EN__SHIFT 0x9 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN_MASK 0x400 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCE_RD_ISOC_EN__SHIFT 0xa ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN_MASK 0x800 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__MCIF_RD_ISOC_EN__SHIFT 0xb ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN_MASK 0x1000 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__UMC_RD_ISOC_EN__SHIFT 0xc ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN_MASK 0x2000 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__VCEU_RD_ISOC_EN__SHIFT 0xd ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN_MASK 0x4000 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__ACP_RD_ISOC_EN__SHIFT 0xe ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN_MASK 0x8000 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_EN__SHIFT 0xf ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL_MASK 0x30000 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__REQPRI_OVERRIDE_VAL__SHIFT 0x10 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN_MASK 0x40000 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_EN__SHIFT 0x12 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN_MASK 0x80000 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_EN__SHIFT 0x13 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN_MASK 0x100000 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_EN__SHIFT 0x14 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL_MASK 0x200000 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIPRMTE_OVERRIDE_VAL__SHIFT 0x15 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL_MASK 0x400000 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__TOKURG_OVERRIDE_VAL__SHIFT 0x16 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL_MASK 0x800000 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__PRIURG_OVERRIDE_VAL__SHIFT 0x17 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS_MASK 0x1f000000 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__GARLIC_REQ_CREDITS__SHIFT 0x18 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE_MASK 0x20000000 ++#define MC_FUS_ARB_GARLIC_ISOC_PRI__MM_REL_LATE__SHIFT 0x1d ++#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE_MASK 0xff ++#define MC_FUS_ARB_GARLIC_CNTL__RX_RDRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x0 ++#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE_MASK 0x7f00 ++#define MC_FUS_ARB_GARLIC_CNTL__RX_WRRESP_FIFO_PTR_INIT_VALUE__SHIFT 0x8 ++#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE_MASK 0x8000 ++#define MC_FUS_ARB_GARLIC_CNTL__EN_64_BYTE_WRITE__SHIFT 0xf ++#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE_MASK 0x10000 ++#define MC_FUS_ARB_GARLIC_CNTL__EDC_RESPONSE_ENABLE__SHIFT 0x10 ++#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT_MASK 0x3fe0000 ++#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_RDRESP_LIMIT__SHIFT 0x11 ++#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT_MASK 0xfc000000 ++#define MC_FUS_ARB_GARLIC_CNTL__OUTSTANDING_WRRESP_LIMIT__SHIFT 0x1a ++#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI_MASK 0x3 ++#define MC_FUS_ARB_GARLIC_WR_PRI__CB_WR_PRI__SHIFT 0x0 ++#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI_MASK 0xc ++#define MC_FUS_ARB_GARLIC_WR_PRI__DB_WR_PRI__SHIFT 0x2 ++#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI_MASK 0x30 ++#define MC_FUS_ARB_GARLIC_WR_PRI__TC_WR_PRI__SHIFT 0x4 ++#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI_MASK 0xc0 ++#define MC_FUS_ARB_GARLIC_WR_PRI__CP_WR_PRI__SHIFT 0x6 ++#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI_MASK 0x300 ++#define MC_FUS_ARB_GARLIC_WR_PRI__HDP_WR_PRI__SHIFT 0x8 ++#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI_MASK 0xc00 ++#define MC_FUS_ARB_GARLIC_WR_PRI__XDP_WR_PRI__SHIFT 0xa ++#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI_MASK 0x3000 ++#define MC_FUS_ARB_GARLIC_WR_PRI__UMC_WR_PRI__SHIFT 0xc ++#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI_MASK 0xc000 ++#define MC_FUS_ARB_GARLIC_WR_PRI__UVD_WR_PRI__SHIFT 0xe ++#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI_MASK 0x30000 ++#define MC_FUS_ARB_GARLIC_WR_PRI__RLC_WR_PRI__SHIFT 0x10 ++#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI_MASK 0xc0000 ++#define MC_FUS_ARB_GARLIC_WR_PRI__IH_WR_PRI__SHIFT 0x12 ++#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI_MASK 0x300000 ++#define MC_FUS_ARB_GARLIC_WR_PRI__SDMA_WR_PRI__SHIFT 0x14 ++#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI_MASK 0xc00000 ++#define MC_FUS_ARB_GARLIC_WR_PRI__SEM_WR_PRI__SHIFT 0x16 ++#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI_MASK 0x3000000 ++#define MC_FUS_ARB_GARLIC_WR_PRI__SH_WR_PRI__SHIFT 0x18 ++#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI_MASK 0xc000000 ++#define MC_FUS_ARB_GARLIC_WR_PRI__MCIF_WR_PRI__SHIFT 0x1a ++#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI_MASK 0x30000000 ++#define MC_FUS_ARB_GARLIC_WR_PRI__VCE_WR_PRI__SHIFT 0x1c ++#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI_MASK 0xc0000000 ++#define MC_FUS_ARB_GARLIC_WR_PRI__VCEU_WR_PRI__SHIFT 0x1e ++#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI_MASK 0x3 ++#define MC_FUS_ARB_GARLIC_WR_PRI2__SMU_WR_PRI__SHIFT 0x0 ++#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI_MASK 0xc ++#define MC_FUS_ARB_GARLIC_WR_PRI2__SAM_WR_PRI__SHIFT 0x2 ++#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI_MASK 0x30 ++#define MC_FUS_ARB_GARLIC_WR_PRI2__ACP_WR_PRI__SHIFT 0x4 ++#define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff ++#define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0 ++#define MC_GRUB_PROBE_MAP__ADDR0_TO_TC_MAP_MASK 0x3 ++#define MC_GRUB_PROBE_MAP__ADDR0_TO_TC_MAP__SHIFT 0x0 ++#define MC_GRUB_PROBE_MAP__ADDR1_TO_TC_MAP_MASK 0xc ++#define MC_GRUB_PROBE_MAP__ADDR1_TO_TC_MAP__SHIFT 0x2 ++#define MC_GRUB_PROBE_MAP__ADDR2_TO_TC_MAP_MASK 0x30 ++#define MC_GRUB_PROBE_MAP__ADDR2_TO_TC_MAP__SHIFT 0x4 ++#define MC_GRUB_PROBE_MAP__ADDR3_TO_TC_MAP_MASK 0xc0 ++#define MC_GRUB_PROBE_MAP__ADDR3_TO_TC_MAP__SHIFT 0x6 ++#define MC_GRUB_PROBE_MAP__ADDR0_TO_GRUB_MAP_MASK 0x100 ++#define MC_GRUB_PROBE_MAP__ADDR0_TO_GRUB_MAP__SHIFT 0x8 ++#define MC_GRUB_PROBE_MAP__ADDR1_TO_GRUB_MAP_MASK 0x200 ++#define MC_GRUB_PROBE_MAP__ADDR1_TO_GRUB_MAP__SHIFT 0x9 ++#define MC_GRUB_PROBE_MAP__ADDR2_TO_GRUB_MAP_MASK 0x400 ++#define MC_GRUB_PROBE_MAP__ADDR2_TO_GRUB_MAP__SHIFT 0xa ++#define MC_GRUB_PROBE_MAP__ADDR3_TO_GRUB_MAP_MASK 0x800 ++#define MC_GRUB_PROBE_MAP__ADDR3_TO_GRUB_MAP__SHIFT 0xb ++#define MC_GRUB_POST_PROBE_DELAY__REQ_TO_RSP_DELAY_MASK 0x1f ++#define MC_GRUB_POST_PROBE_DELAY__REQ_TO_RSP_DELAY__SHIFT 0x0 ++#define MC_GRUB_POST_PROBE_DELAY__REQLCL_TO_RET_DELAY_MASK 0x1f00 ++#define MC_GRUB_POST_PROBE_DELAY__REQLCL_TO_RET_DELAY__SHIFT 0x8 ++#define MC_GRUB_POST_PROBE_DELAY__REQREM_TO_RET_DELAY_MASK 0x1f0000 ++#define MC_GRUB_POST_PROBE_DELAY__REQREM_TO_RET_DELAY__SHIFT 0x10 ++#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_LO_MASK 0x3f ++#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_LO__SHIFT 0x0 ++#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_HI_MASK 0x3f00 ++#define MC_GRUB_PROBE_CREDITS__CREDITS_LIMIT_HI__SHIFT 0x8 ++#define MC_GRUB_PROBE_CREDITS__INTPRB_FIFO_LEVEL_MASK 0x8000 ++#define MC_GRUB_PROBE_CREDITS__INTPRB_FIFO_LEVEL__SHIFT 0xf ++#define MC_GRUB_PROBE_CREDITS__INTPRB_TIMEOUT_THRESH_MASK 0x70000 ++#define MC_GRUB_PROBE_CREDITS__INTPRB_TIMEOUT_THRESH__SHIFT 0x10 ++#define MC_GRUB_PROBE_CREDITS__MEM_TIMEOUT_THRESH_MASK 0x700000 ++#define MC_GRUB_PROBE_CREDITS__MEM_TIMEOUT_THRESH__SHIFT 0x14 ++#define MC_GRUB_FEATURES__WR_COMBINE_OFF_MASK 0x1 ++#define MC_GRUB_FEATURES__WR_COMBINE_OFF__SHIFT 0x0 ++#define MC_GRUB_FEATURES__SCLK_CG_DISABLE_MASK 0x2 ++#define MC_GRUB_FEATURES__SCLK_CG_DISABLE__SHIFT 0x1 ++#define MC_GRUB_FEATURES__PRB_FILTER_DISABLE_MASK 0x4 ++#define MC_GRUB_FEATURES__PRB_FILTER_DISABLE__SHIFT 0x2 ++#define MC_GRUB_FEATURES__ARB_NRT_STACK_DISABLE_MASK 0x8 ++#define MC_GRUB_FEATURES__ARB_NRT_STACK_DISABLE__SHIFT 0x3 ++#define MC_GRUB_FEATURES__ARB_FIXED_PRIORITY_MASK 0x10 ++#define MC_GRUB_FEATURES__ARB_FIXED_PRIORITY__SHIFT 0x4 ++#define MC_GRUB_FEATURES__PRIORITY_UPDATE_DISABLE_MASK 0x20 ++#define MC_GRUB_FEATURES__PRIORITY_UPDATE_DISABLE__SHIFT 0x5 ++#define MC_GRUB_FEATURES__RT_BYPASS_OFF_MASK 0x40 ++#define MC_GRUB_FEATURES__RT_BYPASS_OFF__SHIFT 0x6 ++#define MC_GRUB_FEATURES__SYNC_ON_ERROR_DISABLE_MASK 0x80 ++#define MC_GRUB_FEATURES__SYNC_ON_ERROR_DISABLE__SHIFT 0x7 ++#define MC_GRUB_FEATURES__SYNC_REFLECT_DISABLE_MASK 0x100 ++#define MC_GRUB_FEATURES__SYNC_REFLECT_DISABLE__SHIFT 0x8 ++#define MC_GRUB_FEATURES__ARB_STALL_EN_MASK 0x400 ++#define MC_GRUB_FEATURES__ARB_STALL_EN__SHIFT 0xa ++#define MC_GRUB_FEATURES__CREDIT_STALL_EN_MASK 0x800 ++#define MC_GRUB_FEATURES__CREDIT_STALL_EN__SHIFT 0xb ++#define MC_GRUB_FEATURES__ARB_STALL_SET_SEL_MASK 0x3000 ++#define MC_GRUB_FEATURES__ARB_STALL_SET_SEL__SHIFT 0xc ++#define MC_GRUB_FEATURES__ARB_STALL_CLR_SEL_MASK 0xc000 ++#define MC_GRUB_FEATURES__ARB_STALL_CLR_SEL__SHIFT 0xe ++#define MC_GRUB_FEATURES__CREDIT_STALL_SET_SEL_MASK 0x30000 ++#define MC_GRUB_FEATURES__CREDIT_STALL_SET_SEL__SHIFT 0x10 ++#define MC_GRUB_FEATURES__CREDIT_STALL_CLR_SEL_MASK 0xc0000 ++#define MC_GRUB_FEATURES__CREDIT_STALL_CLR_SEL__SHIFT 0x12 ++#define MC_GRUB_FEATURES__WR_REORDER_OFF_MASK 0x100000 ++#define MC_GRUB_FEATURES__WR_REORDER_OFF__SHIFT 0x14 ++#define MC_GRUB_TX_CREDITS__SRCTAG_LIMIT_MASK 0x3f ++#define MC_GRUB_TX_CREDITS__SRCTAG_LIMIT__SHIFT 0x0 ++#define MC_GRUB_TX_CREDITS__SRCTAG_RT_RESERVE_MASK 0xf00 ++#define MC_GRUB_TX_CREDITS__SRCTAG_RT_RESERVE__SHIFT 0x8 ++#define MC_GRUB_TX_CREDITS__NPC_RT_RESERVE_MASK 0xf000 ++#define MC_GRUB_TX_CREDITS__NPC_RT_RESERVE__SHIFT 0xc ++#define MC_GRUB_TX_CREDITS__NPD_RT_RESERVE_MASK 0xf0000 ++#define MC_GRUB_TX_CREDITS__NPD_RT_RESERVE__SHIFT 0x10 ++#define MC_GRUB_TX_CREDITS__TX_FIFO_DEPTH_MASK 0x1f00000 ++#define MC_GRUB_TX_CREDITS__TX_FIFO_DEPTH__SHIFT 0x14 ++#define MC_GRUB_TCB_INDEX__INDEX_MASK 0x7f ++#define MC_GRUB_TCB_INDEX__INDEX__SHIFT 0x0 ++#define MC_GRUB_TCB_INDEX__TCB0_WR_EN_MASK 0x100 ++#define MC_GRUB_TCB_INDEX__TCB0_WR_EN__SHIFT 0x8 ++#define MC_GRUB_TCB_INDEX__TCB1_WR_EN_MASK 0x200 ++#define MC_GRUB_TCB_INDEX__TCB1_WR_EN__SHIFT 0x9 ++#define MC_GRUB_TCB_INDEX__RD_EN_MASK 0x400 ++#define MC_GRUB_TCB_INDEX__RD_EN__SHIFT 0xa ++#define MC_GRUB_TCB_INDEX__TCB_SEL_MASK 0x800 ++#define MC_GRUB_TCB_INDEX__TCB_SEL__SHIFT 0xb ++#define MC_GRUB_TCB_DATA_LO__DATA_MASK 0xffffffff ++#define MC_GRUB_TCB_DATA_LO__DATA__SHIFT 0x0 ++#define MC_GRUB_TCB_DATA_HI__DATA_MASK 0xffffffff ++#define MC_GRUB_TCB_DATA_HI__DATA__SHIFT 0x0 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x1 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x2 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x10 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x20 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x40 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0xf00 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0xf0000 ++#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 ++#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x1fff ++#define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x1 ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x2 ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x70 ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x80 ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0xf00 ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x1fff000 ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000 ++#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c ++#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0xff00 ++#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 ++#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xff000000 ++#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x1 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x2 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x4 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x8 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x10 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0xe0 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0xf00 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x7000 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x8000 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1fff0000 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000 ++#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f ++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x1fff ++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 ++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x2000 ++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd ++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x4000 ++#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x1 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x2 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x4 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x8 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x10 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0xe0 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0xf00 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x7000 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x8000 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1fff0000 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000 ++#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f ++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x1fff ++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 ++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x2000 ++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd ++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x4000 ++#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x1 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x2 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x4 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x8 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x10 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0xe0 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0xf00 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x7000 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x8000 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1fff0000 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000 ++#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f ++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x1fff ++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 ++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x2000 ++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd ++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x4000 ++#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x1 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x2 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x4 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x8 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x10 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0xe0 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0xf00 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x7000 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x8000 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1fff0000 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000 ++#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f ++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x1fff ++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 ++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x2000 ++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd ++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x4000 ++#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe ++#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x3 ++#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 ++#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xfc000000 ++#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x1a ++#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK_MASK 0xffff ++#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0 ++#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000 ++#define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10 ++#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0xff ++#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xffffffff ++#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 ++#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xffffffff ++#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 ++#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x3ffff ++#define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 ++#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xffffffff ++#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 ++#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x3ffff ++#define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 ++#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xffffffff ++#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 ++#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x3ffff ++#define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 ++#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xffffffff ++#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 ++#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x3ffff ++#define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 ++#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xffffffff ++#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 ++#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x3ffff ++#define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 ++#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xffffffff ++#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 ++#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x3ffff ++#define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 ++#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xffffffff ++#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 ++#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x3ffff ++#define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 ++#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xffffffff ++#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 ++#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x3ffff ++#define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 ++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x1 ++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 ++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x10 ++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 ++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x20 ++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 ++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x40 ++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 ++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0xf00 ++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 ++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1fff0000 ++#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 ++#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID_MASK 0xf00 ++#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID__SHIFT 0x8 ++#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK_MASK 0xffff0000 ++#define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK__SHIFT 0x10 ++ ++#endif /* GMC_8_2_SH_MASK_H */ +-- +cgit v0.10.2 + |