diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/0006-yocto-amd-drm-amdgpu-fix-const-warnings-in-amdgpu_connectors-c.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/0006-yocto-amd-drm-amdgpu-fix-const-warnings-in-amdgpu_connectors-c.patch | 31367 |
1 files changed, 31367 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0006-yocto-amd-drm-amdgpu-fix-const-warnings-in-amdgpu_connectors-c.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0006-yocto-amd-drm-amdgpu-fix-const-warnings-in-amdgpu_connectors-c.patch new file mode 100644 index 00000000..25aed9bd --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/0006-yocto-amd-drm-amdgpu-fix-const-warnings-in-amdgpu_connectors-c.patch @@ -0,0 +1,31367 @@ +From ff26fbca833fe9106bdd91c63a2a231273f9f228 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 16 Apr 2015 15:18:28 -0400 +Subject: drm/amdgpu: add DCE 11.0 register headers + +These are register headers for the DCE (Display and Composition Engine) +block on the GPU. + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com> + + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h +new file mode 100644 +index 0000000..c39234e +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h +@@ -0,0 +1,7648 @@ ++/* ++ * DCE_11_0 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef DCE_11_0_D_H ++#define DCE_11_0_D_H ++ ++#define mmPIPE0_PG_CONFIG 0x2c0 ++#define mmPIPE0_PG_ENABLE 0x2c1 ++#define mmPIPE0_PG_STATUS 0x2c2 ++#define mmPIPE1_PG_CONFIG 0x2c3 ++#define mmPIPE1_PG_ENABLE 0x2c4 ++#define mmPIPE1_PG_STATUS 0x2c5 ++#define mmPIPE2_PG_CONFIG 0x2c6 ++#define mmPIPE2_PG_ENABLE 0x2c7 ++#define mmPIPE2_PG_STATUS 0x2c8 ++#define mmDCFEV0_PG_CONFIG 0x2db ++#define mmDCFEV0_PG_ENABLE 0x2dc ++#define mmDCFEV0_PG_STATUS 0x2dd ++#define mmDCPG_INTERRUPT_STATUS 0x2de ++#define mmDCPG_INTERRUPT_CONTROL 0x2df ++#define mmDC_IP_REQUEST_CNTL 0x2d2 ++#define mmDC_PGFSM_CONFIG_REG 0x2d3 ++#define mmDC_PGFSM_WRITE_REG 0x2d4 ++#define mmDC_PGCNTL_STATUS_REG 0x2d5 ++#define mmDCPG_TEST_DEBUG_INDEX 0x2d6 ++#define mmDCPG_TEST_DEBUG_DATA 0x2d7 ++#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 ++#define mmBL1_PWM_USER_LEVEL 0x1629 ++#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a ++#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b ++#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c ++#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d ++#define mmBL1_PWM_ABM_CNTL 0x162e ++#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f ++#define mmBL1_PWM_GRP2_REG_LOCK 0x1630 ++#define mmDC_ABM1_CNTL 0x1638 ++#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 ++#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a ++#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b ++#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c ++#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d ++#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e ++#define mmDC_ABM1_ACE_THRES_12 0x163f ++#define mmDC_ABM1_ACE_THRES_34 0x1640 ++#define mmDC_ABM1_ACE_CNTL_MISC 0x1641 ++#define mmDC_ABM1_DEBUG_MISC 0x1649 ++#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a ++#define mmDC_ABM1_HG_MISC_CTRL 0x164b ++#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c ++#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d ++#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e ++#define mmDC_ABM1_LS_PIXEL_COUNT 0x164f ++#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 ++#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 ++#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 ++#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 ++#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 ++#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 ++#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 ++#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 ++#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 ++#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 ++#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a ++#define mmDC_ABM1_HG_RESULT_1 0x165b ++#define mmDC_ABM1_HG_RESULT_2 0x165c ++#define mmDC_ABM1_HG_RESULT_3 0x165d ++#define mmDC_ABM1_HG_RESULT_4 0x165e ++#define mmDC_ABM1_HG_RESULT_5 0x165f ++#define mmDC_ABM1_HG_RESULT_6 0x1660 ++#define mmDC_ABM1_HG_RESULT_7 0x1661 ++#define mmDC_ABM1_HG_RESULT_8 0x1662 ++#define mmDC_ABM1_HG_RESULT_9 0x1663 ++#define mmDC_ABM1_HG_RESULT_10 0x1664 ++#define mmDC_ABM1_HG_RESULT_11 0x1665 ++#define mmDC_ABM1_HG_RESULT_12 0x1666 ++#define mmDC_ABM1_HG_RESULT_13 0x1667 ++#define mmDC_ABM1_HG_RESULT_14 0x1668 ++#define mmDC_ABM1_HG_RESULT_15 0x1669 ++#define mmDC_ABM1_HG_RESULT_16 0x166a ++#define mmDC_ABM1_HG_RESULT_17 0x166b ++#define mmDC_ABM1_HG_RESULT_18 0x166c ++#define mmDC_ABM1_HG_RESULT_19 0x166d ++#define mmDC_ABM1_HG_RESULT_20 0x166e ++#define mmDC_ABM1_HG_RESULT_21 0x166f ++#define mmDC_ABM1_HG_RESULT_22 0x1670 ++#define mmDC_ABM1_HG_RESULT_23 0x1671 ++#define mmDC_ABM1_HG_RESULT_24 0x1672 ++#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b ++#define mmDC_ABM1_BL_MASTER_LOCK 0x169c ++#define mmABM_TEST_DEBUG_INDEX 0x169e ++#define mmABM_TEST_DEBUG_DATA 0x169f ++#define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d ++#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d ++#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d ++#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d ++#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d ++#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d ++#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d ++#define mmCRTC_H_TOTAL 0x1b80 ++#define mmCRTC0_CRTC_H_TOTAL 0x1b80 ++#define mmCRTC1_CRTC_H_TOTAL 0x1d80 ++#define mmCRTC2_CRTC_H_TOTAL 0x1f80 ++#define mmCRTC3_CRTC_H_TOTAL 0x4180 ++#define mmCRTC4_CRTC_H_TOTAL 0x4380 ++#define mmCRTC5_CRTC_H_TOTAL 0x4580 ++#define mmCRTC_H_BLANK_START_END 0x1b81 ++#define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 ++#define mmCRTC1_CRTC_H_BLANK_START_END 0x1d81 ++#define mmCRTC2_CRTC_H_BLANK_START_END 0x1f81 ++#define mmCRTC3_CRTC_H_BLANK_START_END 0x4181 ++#define mmCRTC4_CRTC_H_BLANK_START_END 0x4381 ++#define mmCRTC5_CRTC_H_BLANK_START_END 0x4581 ++#define mmCRTC_H_SYNC_A 0x1b82 ++#define mmCRTC0_CRTC_H_SYNC_A 0x1b82 ++#define mmCRTC1_CRTC_H_SYNC_A 0x1d82 ++#define mmCRTC2_CRTC_H_SYNC_A 0x1f82 ++#define mmCRTC3_CRTC_H_SYNC_A 0x4182 ++#define mmCRTC4_CRTC_H_SYNC_A 0x4382 ++#define mmCRTC5_CRTC_H_SYNC_A 0x4582 ++#define mmCRTC_H_SYNC_A_CNTL 0x1b83 ++#define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 ++#define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83 ++#define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83 ++#define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183 ++#define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383 ++#define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583 ++#define mmCRTC_H_SYNC_B 0x1b84 ++#define mmCRTC0_CRTC_H_SYNC_B 0x1b84 ++#define mmCRTC1_CRTC_H_SYNC_B 0x1d84 ++#define mmCRTC2_CRTC_H_SYNC_B 0x1f84 ++#define mmCRTC3_CRTC_H_SYNC_B 0x4184 ++#define mmCRTC4_CRTC_H_SYNC_B 0x4384 ++#define mmCRTC5_CRTC_H_SYNC_B 0x4584 ++#define mmCRTC_H_SYNC_B_CNTL 0x1b85 ++#define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 ++#define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85 ++#define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85 ++#define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185 ++#define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385 ++#define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585 ++#define mmCRTC_VBI_END 0x1b86 ++#define mmCRTC0_CRTC_VBI_END 0x1b86 ++#define mmCRTC1_CRTC_VBI_END 0x1d86 ++#define mmCRTC2_CRTC_VBI_END 0x1f86 ++#define mmCRTC3_CRTC_VBI_END 0x4186 ++#define mmCRTC4_CRTC_VBI_END 0x4386 ++#define mmCRTC5_CRTC_VBI_END 0x4586 ++#define mmCRTC_V_TOTAL 0x1b87 ++#define mmCRTC0_CRTC_V_TOTAL 0x1b87 ++#define mmCRTC1_CRTC_V_TOTAL 0x1d87 ++#define mmCRTC2_CRTC_V_TOTAL 0x1f87 ++#define mmCRTC3_CRTC_V_TOTAL 0x4187 ++#define mmCRTC4_CRTC_V_TOTAL 0x4387 ++#define mmCRTC5_CRTC_V_TOTAL 0x4587 ++#define mmCRTC_V_TOTAL_MIN 0x1b88 ++#define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 ++#define mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88 ++#define mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88 ++#define mmCRTC3_CRTC_V_TOTAL_MIN 0x4188 ++#define mmCRTC4_CRTC_V_TOTAL_MIN 0x4388 ++#define mmCRTC5_CRTC_V_TOTAL_MIN 0x4588 ++#define mmCRTC_V_TOTAL_MAX 0x1b89 ++#define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 ++#define mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89 ++#define mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89 ++#define mmCRTC3_CRTC_V_TOTAL_MAX 0x4189 ++#define mmCRTC4_CRTC_V_TOTAL_MAX 0x4389 ++#define mmCRTC5_CRTC_V_TOTAL_MAX 0x4589 ++#define mmCRTC_V_TOTAL_CONTROL 0x1b8a ++#define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a ++#define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a ++#define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a ++#define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a ++#define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a ++#define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a ++#define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b ++#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b ++#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b ++#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b ++#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b ++#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b ++#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b ++#define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c ++#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c ++#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c ++#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c ++#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c ++#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c ++#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c ++#define mmCRTC_V_BLANK_START_END 0x1b8d ++#define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d ++#define mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d ++#define mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d ++#define mmCRTC3_CRTC_V_BLANK_START_END 0x418d ++#define mmCRTC4_CRTC_V_BLANK_START_END 0x438d ++#define mmCRTC5_CRTC_V_BLANK_START_END 0x458d ++#define mmCRTC_V_SYNC_A 0x1b8e ++#define mmCRTC0_CRTC_V_SYNC_A 0x1b8e ++#define mmCRTC1_CRTC_V_SYNC_A 0x1d8e ++#define mmCRTC2_CRTC_V_SYNC_A 0x1f8e ++#define mmCRTC3_CRTC_V_SYNC_A 0x418e ++#define mmCRTC4_CRTC_V_SYNC_A 0x438e ++#define mmCRTC5_CRTC_V_SYNC_A 0x458e ++#define mmCRTC_V_SYNC_A_CNTL 0x1b8f ++#define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f ++#define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f ++#define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f ++#define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f ++#define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f ++#define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f ++#define mmCRTC_V_SYNC_B 0x1b90 ++#define mmCRTC0_CRTC_V_SYNC_B 0x1b90 ++#define mmCRTC1_CRTC_V_SYNC_B 0x1d90 ++#define mmCRTC2_CRTC_V_SYNC_B 0x1f90 ++#define mmCRTC3_CRTC_V_SYNC_B 0x4190 ++#define mmCRTC4_CRTC_V_SYNC_B 0x4390 ++#define mmCRTC5_CRTC_V_SYNC_B 0x4590 ++#define mmCRTC_V_SYNC_B_CNTL 0x1b91 ++#define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 ++#define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91 ++#define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91 ++#define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191 ++#define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391 ++#define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591 ++#define mmCRTC_DTMTEST_CNTL 0x1b92 ++#define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 ++#define mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92 ++#define mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92 ++#define mmCRTC3_CRTC_DTMTEST_CNTL 0x4192 ++#define mmCRTC4_CRTC_DTMTEST_CNTL 0x4392 ++#define mmCRTC5_CRTC_DTMTEST_CNTL 0x4592 ++#define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 ++#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 ++#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93 ++#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93 ++#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193 ++#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393 ++#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593 ++#define mmCRTC_TRIGA_CNTL 0x1b94 ++#define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 ++#define mmCRTC1_CRTC_TRIGA_CNTL 0x1d94 ++#define mmCRTC2_CRTC_TRIGA_CNTL 0x1f94 ++#define mmCRTC3_CRTC_TRIGA_CNTL 0x4194 ++#define mmCRTC4_CRTC_TRIGA_CNTL 0x4394 ++#define mmCRTC5_CRTC_TRIGA_CNTL 0x4594 ++#define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 ++#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 ++#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95 ++#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95 ++#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195 ++#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395 ++#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595 ++#define mmCRTC_TRIGB_CNTL 0x1b96 ++#define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 ++#define mmCRTC1_CRTC_TRIGB_CNTL 0x1d96 ++#define mmCRTC2_CRTC_TRIGB_CNTL 0x1f96 ++#define mmCRTC3_CRTC_TRIGB_CNTL 0x4196 ++#define mmCRTC4_CRTC_TRIGB_CNTL 0x4396 ++#define mmCRTC5_CRTC_TRIGB_CNTL 0x4596 ++#define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 ++#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 ++#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97 ++#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97 ++#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197 ++#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397 ++#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597 ++#define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 ++#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 ++#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98 ++#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98 ++#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 ++#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398 ++#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598 ++#define mmCRTC_FLOW_CONTROL 0x1b99 ++#define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 ++#define mmCRTC1_CRTC_FLOW_CONTROL 0x1d99 ++#define mmCRTC2_CRTC_FLOW_CONTROL 0x1f99 ++#define mmCRTC3_CRTC_FLOW_CONTROL 0x4199 ++#define mmCRTC4_CRTC_FLOW_CONTROL 0x4399 ++#define mmCRTC5_CRTC_FLOW_CONTROL 0x4599 ++#define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a ++#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a ++#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a ++#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a ++#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a ++#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a ++#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a ++#define mmCRTC_AVSYNC_COUNTER 0x1b9b ++#define mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b ++#define mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b ++#define mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b ++#define mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b ++#define mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b ++#define mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b ++#define mmCRTC_CONTROL 0x1b9c ++#define mmCRTC0_CRTC_CONTROL 0x1b9c ++#define mmCRTC1_CRTC_CONTROL 0x1d9c ++#define mmCRTC2_CRTC_CONTROL 0x1f9c ++#define mmCRTC3_CRTC_CONTROL 0x419c ++#define mmCRTC4_CRTC_CONTROL 0x439c ++#define mmCRTC5_CRTC_CONTROL 0x459c ++#define mmCRTC_BLANK_CONTROL 0x1b9d ++#define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d ++#define mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d ++#define mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d ++#define mmCRTC3_CRTC_BLANK_CONTROL 0x419d ++#define mmCRTC4_CRTC_BLANK_CONTROL 0x439d ++#define mmCRTC5_CRTC_BLANK_CONTROL 0x459d ++#define mmCRTC_INTERLACE_CONTROL 0x1b9e ++#define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e ++#define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e ++#define mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e ++#define mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e ++#define mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e ++#define mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e ++#define mmCRTC_INTERLACE_STATUS 0x1b9f ++#define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f ++#define mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f ++#define mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f ++#define mmCRTC3_CRTC_INTERLACE_STATUS 0x419f ++#define mmCRTC4_CRTC_INTERLACE_STATUS 0x439f ++#define mmCRTC5_CRTC_INTERLACE_STATUS 0x459f ++#define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 ++#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 ++#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0 ++#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0 ++#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0 ++#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0 ++#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0 ++#define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 ++#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 ++#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1 ++#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1 ++#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1 ++#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1 ++#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1 ++#define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 ++#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 ++#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2 ++#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2 ++#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2 ++#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2 ++#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2 ++#define mmCRTC_STATUS 0x1ba3 ++#define mmCRTC0_CRTC_STATUS 0x1ba3 ++#define mmCRTC1_CRTC_STATUS 0x1da3 ++#define mmCRTC2_CRTC_STATUS 0x1fa3 ++#define mmCRTC3_CRTC_STATUS 0x41a3 ++#define mmCRTC4_CRTC_STATUS 0x43a3 ++#define mmCRTC5_CRTC_STATUS 0x45a3 ++#define mmCRTC_STATUS_POSITION 0x1ba4 ++#define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 ++#define mmCRTC1_CRTC_STATUS_POSITION 0x1da4 ++#define mmCRTC2_CRTC_STATUS_POSITION 0x1fa4 ++#define mmCRTC3_CRTC_STATUS_POSITION 0x41a4 ++#define mmCRTC4_CRTC_STATUS_POSITION 0x43a4 ++#define mmCRTC5_CRTC_STATUS_POSITION 0x45a4 ++#define mmCRTC_NOM_VERT_POSITION 0x1ba5 ++#define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 ++#define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5 ++#define mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5 ++#define mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5 ++#define mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5 ++#define mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5 ++#define mmCRTC_STATUS_FRAME_COUNT 0x1ba6 ++#define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 ++#define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6 ++#define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6 ++#define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6 ++#define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6 ++#define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6 ++#define mmCRTC_STATUS_VF_COUNT 0x1ba7 ++#define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 ++#define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7 ++#define mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7 ++#define mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7 ++#define mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7 ++#define mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7 ++#define mmCRTC_STATUS_HV_COUNT 0x1ba8 ++#define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 ++#define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8 ++#define mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8 ++#define mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8 ++#define mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8 ++#define mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8 ++#define mmCRTC_COUNT_CONTROL 0x1ba9 ++#define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 ++#define mmCRTC1_CRTC_COUNT_CONTROL 0x1da9 ++#define mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9 ++#define mmCRTC3_CRTC_COUNT_CONTROL 0x41a9 ++#define mmCRTC4_CRTC_COUNT_CONTROL 0x43a9 ++#define mmCRTC5_CRTC_COUNT_CONTROL 0x45a9 ++#define mmCRTC_COUNT_RESET 0x1baa ++#define mmCRTC0_CRTC_COUNT_RESET 0x1baa ++#define mmCRTC1_CRTC_COUNT_RESET 0x1daa ++#define mmCRTC2_CRTC_COUNT_RESET 0x1faa ++#define mmCRTC3_CRTC_COUNT_RESET 0x41aa ++#define mmCRTC4_CRTC_COUNT_RESET 0x43aa ++#define mmCRTC5_CRTC_COUNT_RESET 0x45aa ++#define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab ++#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab ++#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab ++#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab ++#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab ++#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab ++#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab ++#define mmCRTC_VERT_SYNC_CONTROL 0x1bac ++#define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac ++#define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac ++#define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac ++#define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac ++#define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac ++#define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac ++#define mmCRTC_STEREO_STATUS 0x1bad ++#define mmCRTC0_CRTC_STEREO_STATUS 0x1bad ++#define mmCRTC1_CRTC_STEREO_STATUS 0x1dad ++#define mmCRTC2_CRTC_STEREO_STATUS 0x1fad ++#define mmCRTC3_CRTC_STEREO_STATUS 0x41ad ++#define mmCRTC4_CRTC_STEREO_STATUS 0x43ad ++#define mmCRTC5_CRTC_STEREO_STATUS 0x45ad ++#define mmCRTC_STEREO_CONTROL 0x1bae ++#define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae ++#define mmCRTC1_CRTC_STEREO_CONTROL 0x1dae ++#define mmCRTC2_CRTC_STEREO_CONTROL 0x1fae ++#define mmCRTC3_CRTC_STEREO_CONTROL 0x41ae ++#define mmCRTC4_CRTC_STEREO_CONTROL 0x43ae ++#define mmCRTC5_CRTC_STEREO_CONTROL 0x45ae ++#define mmCRTC_SNAPSHOT_STATUS 0x1baf ++#define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf ++#define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf ++#define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf ++#define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af ++#define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af ++#define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af ++#define mmCRTC_SNAPSHOT_CONTROL 0x1bb0 ++#define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 ++#define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0 ++#define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0 ++#define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0 ++#define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0 ++#define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0 ++#define mmCRTC_SNAPSHOT_POSITION 0x1bb1 ++#define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 ++#define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1 ++#define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1 ++#define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1 ++#define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1 ++#define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1 ++#define mmCRTC_SNAPSHOT_FRAME 0x1bb2 ++#define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 ++#define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2 ++#define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2 ++#define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2 ++#define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2 ++#define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2 ++#define mmCRTC_START_LINE_CONTROL 0x1bb3 ++#define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 ++#define mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3 ++#define mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3 ++#define mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3 ++#define mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3 ++#define mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3 ++#define mmCRTC_INTERRUPT_CONTROL 0x1bb4 ++#define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 ++#define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4 ++#define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4 ++#define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4 ++#define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4 ++#define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4 ++#define mmCRTC_UPDATE_LOCK 0x1bb5 ++#define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 ++#define mmCRTC1_CRTC_UPDATE_LOCK 0x1db5 ++#define mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5 ++#define mmCRTC3_CRTC_UPDATE_LOCK 0x41b5 ++#define mmCRTC4_CRTC_UPDATE_LOCK 0x43b5 ++#define mmCRTC5_CRTC_UPDATE_LOCK 0x45b5 ++#define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 ++#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 ++#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6 ++#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6 ++#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 ++#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6 ++#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6 ++#define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 ++#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 ++#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7 ++#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7 ++#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 ++#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7 ++#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7 ++#define mmCRTC_TEST_PATTERN_CONTROL 0x1bba ++#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba ++#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba ++#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba ++#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba ++#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba ++#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba ++#define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb ++#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb ++#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb ++#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb ++#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb ++#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb ++#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb ++#define mmCRTC_TEST_PATTERN_COLOR 0x1bbc ++#define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc ++#define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc ++#define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc ++#define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc ++#define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc ++#define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc ++#define mmCRTC_MASTER_UPDATE_LOCK 0x1bbd ++#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x1bbd ++#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x1dbd ++#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x1fbd ++#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x41bd ++#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x43bd ++#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x45bd ++#define mmCRTC_MASTER_UPDATE_MODE 0x1bbe ++#define mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x1bbe ++#define mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x1dbe ++#define mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x1fbe ++#define mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x41be ++#define mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x43be ++#define mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x45be ++#define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf ++#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf ++#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf ++#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf ++#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf ++#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf ++#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf ++#define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 ++#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 ++#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0 ++#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0 ++#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 ++#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0 ++#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0 ++#define mmCRTC_MVP_STATUS 0x1bc1 ++#define mmCRTC0_CRTC_MVP_STATUS 0x1bc1 ++#define mmCRTC1_CRTC_MVP_STATUS 0x1dc1 ++#define mmCRTC2_CRTC_MVP_STATUS 0x1fc1 ++#define mmCRTC3_CRTC_MVP_STATUS 0x41c1 ++#define mmCRTC4_CRTC_MVP_STATUS 0x43c1 ++#define mmCRTC5_CRTC_MVP_STATUS 0x45c1 ++#define mmCRTC_MASTER_EN 0x1bc2 ++#define mmCRTC0_CRTC_MASTER_EN 0x1bc2 ++#define mmCRTC1_CRTC_MASTER_EN 0x1dc2 ++#define mmCRTC2_CRTC_MASTER_EN 0x1fc2 ++#define mmCRTC3_CRTC_MASTER_EN 0x41c2 ++#define mmCRTC4_CRTC_MASTER_EN 0x43c2 ++#define mmCRTC5_CRTC_MASTER_EN 0x45c2 ++#define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 ++#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 ++#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3 ++#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3 ++#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 ++#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3 ++#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3 ++#define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 ++#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 ++#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4 ++#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4 ++#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4 ++#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4 ++#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4 ++#define mmCRTC_OVERSCAN_COLOR 0x1bc8 ++#define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 ++#define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8 ++#define mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8 ++#define mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8 ++#define mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8 ++#define mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8 ++#define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 ++#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 ++#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9 ++#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9 ++#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9 ++#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9 ++#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9 ++#define mmCRTC_BLANK_DATA_COLOR 0x1bca ++#define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca ++#define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca ++#define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca ++#define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca ++#define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca ++#define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca ++#define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb ++#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb ++#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb ++#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb ++#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb ++#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb ++#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb ++#define mmCRTC_BLACK_COLOR 0x1bcc ++#define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc ++#define mmCRTC1_CRTC_BLACK_COLOR 0x1dcc ++#define mmCRTC2_CRTC_BLACK_COLOR 0x1fcc ++#define mmCRTC3_CRTC_BLACK_COLOR 0x41cc ++#define mmCRTC4_CRTC_BLACK_COLOR 0x43cc ++#define mmCRTC5_CRTC_BLACK_COLOR 0x45cc ++#define mmCRTC_BLACK_COLOR_EXT 0x1bcd ++#define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd ++#define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd ++#define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd ++#define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd ++#define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd ++#define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd ++#define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce ++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce ++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce ++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce ++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce ++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce ++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce ++#define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf ++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf ++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf ++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf ++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf ++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf ++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf ++#define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 ++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 ++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0 ++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0 ++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 ++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0 ++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0 ++#define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 ++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 ++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1 ++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1 ++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 ++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1 ++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1 ++#define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 ++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 ++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2 ++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2 ++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 ++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2 ++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2 ++#define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 ++#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 ++#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3 ++#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3 ++#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 ++#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3 ++#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3 ++#define mmCRTC_CRC_CNTL 0x1bd4 ++#define mmCRTC0_CRTC_CRC_CNTL 0x1bd4 ++#define mmCRTC1_CRTC_CRC_CNTL 0x1dd4 ++#define mmCRTC2_CRTC_CRC_CNTL 0x1fd4 ++#define mmCRTC3_CRTC_CRC_CNTL 0x41d4 ++#define mmCRTC4_CRTC_CRC_CNTL 0x43d4 ++#define mmCRTC5_CRTC_CRC_CNTL 0x45d4 ++#define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 ++#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 ++#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5 ++#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5 ++#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 ++#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5 ++#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5 ++#define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 ++#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 ++#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6 ++#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6 ++#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 ++#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6 ++#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6 ++#define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 ++#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 ++#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7 ++#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7 ++#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 ++#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7 ++#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7 ++#define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 ++#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 ++#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8 ++#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8 ++#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 ++#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8 ++#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8 ++#define mmCRTC_CRC0_DATA_RG 0x1bd9 ++#define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 ++#define mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9 ++#define mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9 ++#define mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9 ++#define mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9 ++#define mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9 ++#define mmCRTC_CRC0_DATA_B 0x1bda ++#define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda ++#define mmCRTC1_CRTC_CRC0_DATA_B 0x1dda ++#define mmCRTC2_CRTC_CRC0_DATA_B 0x1fda ++#define mmCRTC3_CRTC_CRC0_DATA_B 0x41da ++#define mmCRTC4_CRTC_CRC0_DATA_B 0x43da ++#define mmCRTC5_CRTC_CRC0_DATA_B 0x45da ++#define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb ++#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb ++#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb ++#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb ++#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db ++#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db ++#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db ++#define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc ++#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc ++#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc ++#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc ++#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc ++#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc ++#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc ++#define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd ++#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd ++#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd ++#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd ++#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd ++#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd ++#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd ++#define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde ++#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde ++#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde ++#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde ++#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de ++#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de ++#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de ++#define mmCRTC_CRC1_DATA_RG 0x1bdf ++#define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf ++#define mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf ++#define mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf ++#define mmCRTC3_CRTC_CRC1_DATA_RG 0x41df ++#define mmCRTC4_CRTC_CRC1_DATA_RG 0x43df ++#define mmCRTC5_CRTC_CRC1_DATA_RG 0x45df ++#define mmCRTC_CRC1_DATA_B 0x1be0 ++#define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 ++#define mmCRTC1_CRTC_CRC1_DATA_B 0x1de0 ++#define mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0 ++#define mmCRTC3_CRTC_CRC1_DATA_B 0x41e0 ++#define mmCRTC4_CRTC_CRC1_DATA_B 0x43e0 ++#define mmCRTC5_CRTC_CRC1_DATA_B 0x45e0 ++#define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 ++#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 ++#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7 ++#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7 ++#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7 ++#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7 ++#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7 ++#define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 ++#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 ++#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78 ++#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78 ++#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178 ++#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378 ++#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578 ++#define mmCRTC_GSL_VSYNC_GAP 0x1b79 ++#define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 ++#define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79 ++#define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79 ++#define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179 ++#define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379 ++#define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579 ++#define mmCRTC_GSL_WINDOW 0x1b7a ++#define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a ++#define mmCRTC1_CRTC_GSL_WINDOW 0x1d7a ++#define mmCRTC2_CRTC_GSL_WINDOW 0x1f7a ++#define mmCRTC3_CRTC_GSL_WINDOW 0x417a ++#define mmCRTC4_CRTC_GSL_WINDOW 0x437a ++#define mmCRTC5_CRTC_GSL_WINDOW 0x457a ++#define mmCRTC_GSL_CONTROL 0x1b7b ++#define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b ++#define mmCRTC1_CRTC_GSL_CONTROL 0x1d7b ++#define mmCRTC2_CRTC_GSL_CONTROL 0x1f7b ++#define mmCRTC3_CRTC_GSL_CONTROL 0x417b ++#define mmCRTC4_CRTC_GSL_CONTROL 0x437b ++#define mmCRTC5_CRTC_GSL_CONTROL 0x457b ++#define mmCRTC_TEST_DEBUG_INDEX 0x1bc6 ++#define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 ++#define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6 ++#define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6 ++#define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6 ++#define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6 ++#define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6 ++#define mmCRTC_TEST_DEBUG_DATA 0x1bc7 ++#define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 ++#define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7 ++#define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7 ++#define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7 ++#define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7 ++#define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7 ++#define mmDAC_ENABLE 0x16aa ++#define mmDAC_SOURCE_SELECT 0x16ab ++#define mmDAC_CRC_EN 0x16ac ++#define mmDAC_CRC_CONTROL 0x16ad ++#define mmDAC_CRC_SIG_RGB_MASK 0x16ae ++#define mmDAC_CRC_SIG_CONTROL_MASK 0x16af ++#define mmDAC_CRC_SIG_RGB 0x16b0 ++#define mmDAC_CRC_SIG_CONTROL 0x16b1 ++#define mmDAC_SYNC_TRISTATE_CONTROL 0x16b2 ++#define mmDAC_STEREOSYNC_SELECT 0x16b3 ++#define mmDAC_AUTODETECT_CONTROL 0x16b4 ++#define mmDAC_AUTODETECT_CONTROL2 0x16b5 ++#define mmDAC_AUTODETECT_CONTROL3 0x16b6 ++#define mmDAC_AUTODETECT_STATUS 0x16b7 ++#define mmDAC_AUTODETECT_INT_CONTROL 0x16b8 ++#define mmDAC_FORCE_OUTPUT_CNTL 0x16b9 ++#define mmDAC_FORCE_DATA 0x16ba ++#define mmDAC_POWERDOWN 0x16bb ++#define mmDAC_CONTROL 0x16bc ++#define mmDAC_COMPARATOR_ENABLE 0x16bd ++#define mmDAC_COMPARATOR_OUTPUT 0x16be ++#define mmDAC_PWR_CNTL 0x16bf ++#define mmDAC_DFT_CONFIG 0x16c0 ++#define mmDAC_FIFO_STATUS 0x16c1 ++#define mmDAC_TEST_DEBUG_INDEX 0x16c2 ++#define mmDAC_TEST_DEBUG_DATA 0x16c3 ++#define mmPERFCOUNTER_CNTL 0x170 ++#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 ++#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x364 ++#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x18c8 ++#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1b24 ++#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1d24 ++#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1f24 ++#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4124 ++#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4324 ++#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4524 ++#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4724 ++#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x59a0 ++#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x5f68 ++#define mmPERFCOUNTER_STATE 0x171 ++#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 ++#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x365 ++#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x18c9 ++#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x1b25 ++#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x1d25 ++#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x1f25 ++#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x4125 ++#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4325 ++#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4525 ++#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4725 ++#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x59a1 ++#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x5f69 ++#define mmPERFMON_CNTL 0x173 ++#define mmDC_PERFMON0_PERFMON_CNTL 0x173 ++#define mmDC_PERFMON1_PERFMON_CNTL 0x367 ++#define mmDC_PERFMON2_PERFMON_CNTL 0x18cb ++#define mmDC_PERFMON3_PERFMON_CNTL 0x1b27 ++#define mmDC_PERFMON4_PERFMON_CNTL 0x1d27 ++#define mmDC_PERFMON5_PERFMON_CNTL 0x1f27 ++#define mmDC_PERFMON6_PERFMON_CNTL 0x4127 ++#define mmDC_PERFMON7_PERFMON_CNTL 0x4327 ++#define mmDC_PERFMON8_PERFMON_CNTL 0x4527 ++#define mmDC_PERFMON9_PERFMON_CNTL 0x4727 ++#define mmDC_PERFMON10_PERFMON_CNTL 0x59a3 ++#define mmDC_PERFMON11_PERFMON_CNTL 0x5f6b ++#define mmPERFMON_CNTL2 0x17a ++#define mmDC_PERFMON0_PERFMON_CNTL2 0x17a ++#define mmDC_PERFMON1_PERFMON_CNTL2 0x36e ++#define mmDC_PERFMON2_PERFMON_CNTL2 0x18d2 ++#define mmDC_PERFMON3_PERFMON_CNTL2 0x1b2e ++#define mmDC_PERFMON4_PERFMON_CNTL2 0x1d2e ++#define mmDC_PERFMON5_PERFMON_CNTL2 0x1f2e ++#define mmDC_PERFMON6_PERFMON_CNTL2 0x412e ++#define mmDC_PERFMON7_PERFMON_CNTL2 0x432e ++#define mmDC_PERFMON8_PERFMON_CNTL2 0x452e ++#define mmDC_PERFMON9_PERFMON_CNTL2 0x472e ++#define mmDC_PERFMON10_PERFMON_CNTL2 0x59aa ++#define mmDC_PERFMON11_PERFMON_CNTL2 0x5f72 ++#define mmPERFMON_CVALUE_INT_MISC 0x172 ++#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 ++#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x366 ++#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x18ca ++#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1b26 ++#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1d26 ++#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1f26 ++#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4126 ++#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4326 ++#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4526 ++#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4726 ++#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x59a2 ++#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x5f6a ++#define mmPERFMON_CVALUE_LOW 0x174 ++#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 ++#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x368 ++#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x18cc ++#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1b28 ++#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1d28 ++#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1f28 ++#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4128 ++#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4328 ++#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4528 ++#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4728 ++#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x59a4 ++#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x5f6c ++#define mmPERFMON_HI 0x175 ++#define mmDC_PERFMON0_PERFMON_HI 0x175 ++#define mmDC_PERFMON1_PERFMON_HI 0x369 ++#define mmDC_PERFMON2_PERFMON_HI 0x18cd ++#define mmDC_PERFMON3_PERFMON_HI 0x1b29 ++#define mmDC_PERFMON4_PERFMON_HI 0x1d29 ++#define mmDC_PERFMON5_PERFMON_HI 0x1f29 ++#define mmDC_PERFMON6_PERFMON_HI 0x4129 ++#define mmDC_PERFMON7_PERFMON_HI 0x4329 ++#define mmDC_PERFMON8_PERFMON_HI 0x4529 ++#define mmDC_PERFMON9_PERFMON_HI 0x4729 ++#define mmDC_PERFMON10_PERFMON_HI 0x59a5 ++#define mmDC_PERFMON11_PERFMON_HI 0x5f6d ++#define mmPERFMON_LOW 0x176 ++#define mmDC_PERFMON0_PERFMON_LOW 0x176 ++#define mmDC_PERFMON1_PERFMON_LOW 0x36a ++#define mmDC_PERFMON2_PERFMON_LOW 0x18ce ++#define mmDC_PERFMON3_PERFMON_LOW 0x1b2a ++#define mmDC_PERFMON4_PERFMON_LOW 0x1d2a ++#define mmDC_PERFMON5_PERFMON_LOW 0x1f2a ++#define mmDC_PERFMON6_PERFMON_LOW 0x412a ++#define mmDC_PERFMON7_PERFMON_LOW 0x432a ++#define mmDC_PERFMON8_PERFMON_LOW 0x452a ++#define mmDC_PERFMON9_PERFMON_LOW 0x472a ++#define mmDC_PERFMON10_PERFMON_LOW 0x59a6 ++#define mmDC_PERFMON11_PERFMON_LOW 0x5f6e ++#define mmPERFMON_TEST_DEBUG_INDEX 0x177 ++#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 ++#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x36b ++#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x18cf ++#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1b2b ++#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1d2b ++#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1f2b ++#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x412b ++#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x432b ++#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x452b ++#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x472b ++#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x59a7 ++#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x5f6f ++#define mmPERFMON_TEST_DEBUG_DATA 0x178 ++#define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 ++#define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x36c ++#define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x18d0 ++#define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1b2c ++#define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1d2c ++#define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1f2c ++#define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x412c ++#define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x432c ++#define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x452c ++#define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x472c ++#define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x59a8 ++#define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x5f70 ++#define mmREFCLK_CNTL 0x109 ++#define mmDCCG_CBUS_WRCMD_DELAY 0x110 ++#define mmDPREFCLK_CNTL 0x118 ++#define mmDCE_VERSION 0x11e ++#define mmAVSYNC_COUNTER_WRITE 0x12a ++#define mmAVSYNC_COUNTER_CONTROL 0x12b ++#define mmAVSYNC_COUNTER_READ 0x12f ++#define mmDCCG_GTC_CNTL 0x120 ++#define mmDCCG_GTC_DTO_INCR 0x121 ++#define mmDCCG_GTC_DTO_MODULO 0x122 ++#define mmDCCG_GTC_CURRENT 0x123 ++#define mmDCCG_DS_DTO_INCR 0x113 ++#define mmDCCG_DS_DTO_MODULO 0x114 ++#define mmDCCG_DS_CNTL 0x115 ++#define mmDCCG_DS_HW_CAL_INTERVAL 0x116 ++#define mmDCCG_DS_DEBUG_CNTL 0x112 ++#define mmDMCU_SMU_INTERRUPT_CNTL 0x12c ++#define mmSMU_CONTROL 0x12d ++#define mmSMU_INTERRUPT_CONTROL 0x12e ++#define mmDAC_CLK_ENABLE 0x128 ++#define mmDVO_CLK_ENABLE 0x129 ++#define mmDCCG_GATE_DISABLE_CNTL 0x134 ++#define mmDCCG_GATE_DISABLE_CNTL2 0x13c ++#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 ++#define mmSCLK_CGTT_BLK_CTRL_REG 0x136 ++#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108 ++#define mmREFCLK_CGTT_BLK_CTRL_REG 0x10b ++#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x13d ++#define mmDCCG_CAC_STATUS 0x137 ++#define mmPIXCLK1_RESYNC_CNTL 0x138 ++#define mmPIXCLK2_RESYNC_CNTL 0x139 ++#define mmPIXCLK0_RESYNC_CNTL 0x13a ++#define mmPHYPLL_PIXCLK_CNTL 0x13e ++#define mmMICROSECOND_TIME_BASE_DIV 0x13b ++#define mmDCCG_DISP_CNTL_REG 0x13f ++#define mmMILLISECOND_TIME_BASE_DIV 0x130 ++#define mmDISPCLK_FREQ_CHANGE_CNTL 0x131 ++#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132 ++#define mmDCCG_PERFMON_CNTL 0x133 ++#define mmDCCG_PERFMON_CNTL2 0x10e ++#define mmCRTC0_PIXEL_RATE_CNTL 0x140 ++#define mmDP_DTO0_PHASE 0x141 ++#define mmDP_DTO0_MODULO 0x142 ++#define mmCRTC1_PIXEL_RATE_CNTL 0x144 ++#define mmDP_DTO1_PHASE 0x145 ++#define mmDP_DTO1_MODULO 0x146 ++#define mmCRTC2_PIXEL_RATE_CNTL 0x148 ++#define mmDP_DTO2_PHASE 0x149 ++#define mmDP_DTO2_MODULO 0x14a ++#define mmCRTC3_PIXEL_RATE_CNTL 0x14c ++#define mmDP_DTO3_PHASE 0x14d ++#define mmDP_DTO3_MODULO 0x14e ++#define mmCRTC4_PIXEL_RATE_CNTL 0x150 ++#define mmDP_DTO4_PHASE 0x151 ++#define mmDP_DTO4_MODULO 0x152 ++#define mmCRTC5_PIXEL_RATE_CNTL 0x154 ++#define mmDP_DTO5_PHASE 0x155 ++#define mmDP_DTO5_MODULO 0x156 ++#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x104 ++#define mmDCCG_SOFT_RESET 0x15f ++#define mmSYMCLKA_CLOCK_ENABLE 0x160 ++#define mmSYMCLKB_CLOCK_ENABLE 0x161 ++#define mmSYMCLKC_CLOCK_ENABLE 0x162 ++#define mmSYMCLKD_CLOCK_ENABLE 0x163 ++#define mmSYMCLKE_CLOCK_ENABLE 0x164 ++#define mmSYMCLKF_CLOCK_ENABLE 0x165 ++#define mmSYMCLKG_CLOCK_ENABLE 0x117 ++#define mmDPDBG_CLK_FORCE_CONTROL 0x10d ++#define mmDCCG_AUDIO_DTO_SOURCE 0x16b ++#define mmDCCG_AUDIO_DTO0_PHASE 0x16c ++#define mmDCCG_AUDIO_DTO0_MODULE 0x16d ++#define mmDCCG_AUDIO_DTO1_PHASE 0x16e ++#define mmDCCG_AUDIO_DTO1_MODULE 0x16f ++#define mmDCCG_TEST_DEBUG_INDEX 0x17c ++#define mmDCCG_TEST_DEBUG_DATA 0x17d ++#define mmDCCG_TEST_CLK_SEL 0x17e ++#define mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0 ++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0 ++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc ++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8 ++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4 ++#define mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1 ++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1 ++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd ++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9 ++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5 ++#define mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2 ++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2 ++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde ++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea ++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6 ++#define mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3 ++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3 ++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf ++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb ++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7 ++#define mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4 ++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4 ++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0 ++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec ++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8 ++#define mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5 ++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5 ++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1 ++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed ++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9 ++#define mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6 ++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6 ++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2 ++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee ++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa ++#define mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7 ++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7 ++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3 ++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef ++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb ++#define mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8 ++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8 ++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4 ++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0 ++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc ++#define mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9 ++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9 ++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5 ++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1 ++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd ++#define mmCPLL_MACRO_CNTL_RESERVED10 0x5fda ++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda ++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6 ++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2 ++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe ++#define mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb ++#define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb ++#define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7 ++#define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3 ++#define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff ++#define mmPLL_MACRO_CNTL_RESERVED0 0x1700 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754 ++#define mmPLL_MACRO_CNTL_RESERVED1 0x1701 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755 ++#define mmPLL_MACRO_CNTL_RESERVED2 0x1702 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756 ++#define mmPLL_MACRO_CNTL_RESERVED3 0x1703 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757 ++#define mmPLL_MACRO_CNTL_RESERVED4 0x1704 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758 ++#define mmPLL_MACRO_CNTL_RESERVED5 0x1705 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759 ++#define mmPLL_MACRO_CNTL_RESERVED6 0x1706 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a ++#define mmPLL_MACRO_CNTL_RESERVED7 0x1707 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b ++#define mmPLL_MACRO_CNTL_RESERVED8 0x1708 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c ++#define mmPLL_MACRO_CNTL_RESERVED9 0x1709 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d ++#define mmPLL_MACRO_CNTL_RESERVED10 0x170a ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e ++#define mmPLL_MACRO_CNTL_RESERVED11 0x170b ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f ++#define mmPLL_MACRO_CNTL_RESERVED12 0x170c ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760 ++#define mmPLL_MACRO_CNTL_RESERVED13 0x170d ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761 ++#define mmPLL_MACRO_CNTL_RESERVED14 0x170e ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762 ++#define mmPLL_MACRO_CNTL_RESERVED15 0x170f ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763 ++#define mmPLL_MACRO_CNTL_RESERVED16 0x1710 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764 ++#define mmPLL_MACRO_CNTL_RESERVED17 0x1711 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765 ++#define mmPLL_MACRO_CNTL_RESERVED18 0x1712 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766 ++#define mmPLL_MACRO_CNTL_RESERVED19 0x1713 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767 ++#define mmPLL_MACRO_CNTL_RESERVED20 0x1714 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768 ++#define mmPLL_MACRO_CNTL_RESERVED21 0x1715 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769 ++#define mmPLL_MACRO_CNTL_RESERVED22 0x1716 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a ++#define mmPLL_MACRO_CNTL_RESERVED23 0x1717 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b ++#define mmPLL_MACRO_CNTL_RESERVED24 0x1718 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c ++#define mmPLL_MACRO_CNTL_RESERVED25 0x1719 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d ++#define mmPLL_MACRO_CNTL_RESERVED26 0x171a ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e ++#define mmPLL_MACRO_CNTL_RESERVED27 0x171b ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f ++#define mmPLL_MACRO_CNTL_RESERVED28 0x171c ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770 ++#define mmPLL_MACRO_CNTL_RESERVED29 0x171d ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771 ++#define mmPLL_MACRO_CNTL_RESERVED30 0x171e ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772 ++#define mmPLL_MACRO_CNTL_RESERVED31 0x171f ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773 ++#define mmPLL_MACRO_CNTL_RESERVED32 0x1720 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774 ++#define mmPLL_MACRO_CNTL_RESERVED33 0x1721 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775 ++#define mmPLL_MACRO_CNTL_RESERVED34 0x1722 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776 ++#define mmPLL_MACRO_CNTL_RESERVED35 0x1723 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777 ++#define mmPLL_MACRO_CNTL_RESERVED36 0x1724 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778 ++#define mmPLL_MACRO_CNTL_RESERVED37 0x1725 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779 ++#define mmPLL_MACRO_CNTL_RESERVED38 0x1726 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a ++#define mmPLL_MACRO_CNTL_RESERVED39 0x1727 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b ++#define mmPLL_MACRO_CNTL_RESERVED40 0x1728 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c ++#define mmPLL_MACRO_CNTL_RESERVED41 0x1729 ++#define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729 ++#define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753 ++#define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d ++#define mmDENTIST_DISPCLK_CNTL 0x124 ++#define mmDCDEBUG_BUS_CLK1_SEL 0x16c4 ++#define mmDCDEBUG_BUS_CLK2_SEL 0x16c5 ++#define mmDCDEBUG_BUS_CLK3_SEL 0x16c6 ++#define mmDCDEBUG_BUS_CLK4_SEL 0x16c7 ++#define mmDCDEBUG_BUS_CLK5_SEL 0x16c8 ++#define mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9 ++#define mmDCDEBUG_OUT_CNTL 0x16ca ++#define mmDCDEBUG_OUT_DATA 0x16cb ++#define mmDMIF_ADDR_CONFIG 0x2f5 ++#define mmDMIF_CONTROL 0x2f6 ++#define mmDMIF_STATUS 0x2f7 ++#define mmDMIF_HW_DEBUG 0x2f8 ++#define mmDMIF_ARBITRATION_CONTROL 0x2f9 ++#define mmPIPE0_ARBITRATION_CONTROL3 0x2fa ++#define mmPIPE1_ARBITRATION_CONTROL3 0x2fb ++#define mmPIPE2_ARBITRATION_CONTROL3 0x2fc ++#define mmPIPE3_ARBITRATION_CONTROL3 0x2fd ++#define mmPIPE4_ARBITRATION_CONTROL3 0x2fe ++#define mmPIPE5_ARBITRATION_CONTROL3 0x2ff ++#define mmPIPE6_ARBITRATION_CONTROL3 0x32a ++#define mmPIPE7_ARBITRATION_CONTROL3 0x32b ++#define mmDMIF_P_VMID 0x300 ++#define mmDMIF_URG_OVERRIDE 0x329 ++#define mmDMIF_TEST_DEBUG_INDEX 0x301 ++#define mmDMIF_TEST_DEBUG_DATA 0x302 ++#define ixDMIF_DEBUG02_CORE0 0x2 ++#define ixDMIF_DEBUG02_CORE1 0xa ++#define mmDMIF_ADDR_CALC 0x303 ++#define mmDMIF_STATUS2 0x304 ++#define mmPIPE0_MAX_REQUESTS 0x305 ++#define mmPIPE1_MAX_REQUESTS 0x306 ++#define mmPIPE2_MAX_REQUESTS 0x307 ++#define mmPIPE3_MAX_REQUESTS 0x308 ++#define mmPIPE4_MAX_REQUESTS 0x309 ++#define mmPIPE5_MAX_REQUESTS 0x30a ++#define mmPIPE6_MAX_REQUESTS 0x32c ++#define mmPIPE7_MAX_REQUESTS 0x32d ++#define mmDVMM_REG_RD_STATUS 0x32e ++#define mmDVMM_REG_RD_DATA 0x32f ++#define mmDVMM_PTE_REQ 0x330 ++#define mmDVMM_CNTL 0x331 ++#define mmDVMM_FAULT_STATUS 0x332 ++#define mmDVMM_FAULT_ADDR 0x333 ++#define mmLOW_POWER_TILING_CONTROL 0x30b ++#define mmMCIF_CONTROL 0x30c ++#define mmMCIF_WRITE_COMBINE_CONTROL 0x30d ++#define mmMCIF_TEST_DEBUG_INDEX 0x30e ++#define mmMCIF_TEST_DEBUG_DATA 0x30f ++#define ixIDDCCIF02_DBG_DCCIF_C 0x9 ++#define ixIDDCCIF04_DBG_DCCIF_E 0xb ++#define ixIDDCCIF05_DBG_DCCIF_F 0xc ++#define mmMCIF_VMID 0x310 ++#define mmMCIF_MEM_CONTROL 0x311 ++#define mmCC_DC_PIPE_DIS 0x312 ++#define mmMC_DC_INTERFACE_NACK_STATUS 0x313 ++#define mmRBBMIF_TIMEOUT 0x314 ++#define mmRBBMIF_STATUS 0x315 ++#define mmRBBMIF_TIMEOUT_DIS 0x316 ++#define mmRBBMIF_STATUS_FLAG 0x327 ++#define mmDCI_MEM_PWR_STATUS 0x317 ++#define mmDCI_MEM_PWR_STATUS2 0x318 ++#define mmDCI_CLK_CNTL 0x319 ++#define mmDCI_CLK_RAMP_CNTL 0x31a ++#define mmDCI_MEM_PWR_CNTL 0x31b ++#define mmDCI_MEM_PWR_CNTL2 0x31c ++#define mmDCI_MEM_PWR_CNTL3 0x31d ++#define mmDVMM_PTE_PGMEM_CONTROL 0x335 ++#define mmDVMM_PTE_PGMEM_STATE 0x336 ++#define mmDCI_SOFT_RESET 0x328 ++#define mmDCI_MISC 0x334 ++#define mmDCI_TEST_DEBUG_INDEX 0x31e ++#define mmDCI_TEST_DEBUG_DATA 0x31f ++#define mmDCI_DEBUG_CONFIG 0x320 ++#define mmPIPE0_DMIF_BUFFER_CONTROL 0x321 ++#define mmPIPE1_DMIF_BUFFER_CONTROL 0x322 ++#define mmPIPE2_DMIF_BUFFER_CONTROL 0x323 ++#define mmPIPE3_DMIF_BUFFER_CONTROL 0x324 ++#define mmPIPE4_DMIF_BUFFER_CONTROL 0x325 ++#define mmPIPE5_DMIF_BUFFER_CONTROL 0x326 ++#define mmDC_GENERICA 0x4800 ++#define mmDC_GENERICB 0x4801 ++#define mmDC_PAD_EXTERN_SIG 0x4802 ++#define mmDC_REF_CLK_CNTL 0x4803 ++#define mmDC_GPIO_DEBUG 0x4804 ++#define mmUNIPHYA_LINK_CNTL 0x4805 ++#define mmUNIPHYB_LINK_CNTL 0x4807 ++#define mmUNIPHYC_LINK_CNTL 0x4809 ++#define mmUNIPHYD_LINK_CNTL 0x480b ++#define mmUNIPHYE_LINK_CNTL 0x480d ++#define mmUNIPHYF_LINK_CNTL 0x480f ++#define mmUNIPHYG_LINK_CNTL 0x4811 ++#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806 ++#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808 ++#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a ++#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c ++#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e ++#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810 ++#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812 ++#define mmUNIPHYLPA_LINK_CNTL 0x4847 ++#define mmUNIPHYLPB_LINK_CNTL 0x4848 ++#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x4849 ++#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x484a ++#define mmUNIPHY_IMPCAL_LINKA 0x4838 ++#define mmUNIPHY_IMPCAL_LINKB 0x4839 ++#define mmUNIPHY_IMPCAL_LINKC 0x483f ++#define mmUNIPHY_IMPCAL_LINKD 0x4840 ++#define mmUNIPHY_IMPCAL_LINKE 0x4843 ++#define mmUNIPHY_IMPCAL_LINKF 0x4844 ++#define mmUNIPHY_IMPCAL_PERIOD 0x483a ++#define mmAUXP_IMPCAL 0x483b ++#define mmAUXN_IMPCAL 0x483c ++#define mmDCIO_IMPCAL_CNTL 0x483d ++#define mmUNIPHY_IMPCAL_PSW_AB 0x483e ++#define mmDCIO_IMPCAL_CNTL_CD 0x4841 ++#define mmUNIPHY_IMPCAL_PSW_CD 0x4842 ++#define mmDCIO_IMPCAL_CNTL_EF 0x4845 ++#define mmUNIPHY_IMPCAL_PSW_EF 0x4846 ++#define mmDCIO_WRCMD_DELAY 0x4816 ++#define mmDC_PINSTRAPS 0x4818 ++#define mmDC_DVODATA_CONFIG 0x481a ++#define mmLVTMA_PWRSEQ_CNTL 0x481b ++#define mmLVTMA_PWRSEQ_STATE 0x481c ++#define mmLVTMA_PWRSEQ_REF_DIV 0x481d ++#define mmLVTMA_PWRSEQ_DELAY1 0x481e ++#define mmLVTMA_PWRSEQ_DELAY2 0x481f ++#define mmBL_PWM_CNTL 0x4820 ++#define mmBL_PWM_CNTL2 0x4821 ++#define mmBL_PWM_PERIOD_CNTL 0x4822 ++#define mmBL_PWM_GRP1_REG_LOCK 0x4823 ++#define mmDCIO_GSL_GENLK_PAD_CNTL 0x4824 ++#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825 ++#define mmDCIO_GSL0_CNTL 0x4826 ++#define mmDCIO_GSL1_CNTL 0x4827 ++#define mmDCIO_GSL2_CNTL 0x4828 ++#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829 ++#define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a ++#define mmDC_GPU_TIMER_READ 0x482b ++#define mmDC_GPU_TIMER_READ_CNTL 0x482c ++#define mmDCIO_CLOCK_CNTL 0x482d ++#define mmDCIO_DEBUG 0x482f ++#define mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830 ++#define mmDBG_OUT_CNTL 0x4834 ++#define mmDCIO_DEBUG_CONFIG 0x4835 ++#define mmDCIO_SOFT_RESET 0x4836 ++#define mmDCIO_DPHY_SEL 0x4837 ++#define mmDCIO_TEST_DEBUG_INDEX 0x4831 ++#define mmDCIO_TEST_DEBUG_DATA 0x4832 ++#define ixDCIO_DEBUG1 0x1 ++#define ixDCIO_DEBUG2 0x2 ++#define ixDCIO_DEBUG3 0x3 ++#define ixDCIO_DEBUG4 0x4 ++#define ixDCIO_DEBUG5 0x5 ++#define ixDCIO_DEBUG6 0x6 ++#define ixDCIO_DEBUG7 0x7 ++#define ixDCIO_DEBUG8 0x8 ++#define ixDCIO_DEBUG9 0x9 ++#define ixDCIO_DEBUGA 0xa ++#define ixDCIO_DEBUGB 0xb ++#define ixDCIO_DEBUGC 0xc ++#define ixDCIO_DEBUGD 0xd ++#define ixDCIO_DEBUGE 0xe ++#define ixDCIO_DEBUGF 0xf ++#define ixDCIO_DEBUG10 0x10 ++#define ixDCIO_DEBUG11 0x11 ++#define ixDCIO_DEBUG12 0x12 ++#define ixDCIO_DEBUG13 0x13 ++#define ixDCIO_DEBUG14 0x14 ++#define ixDCIO_DEBUG15 0x15 ++#define ixDCIO_DEBUG16 0x16 ++#define ixDCIO_DEBUG17 0x17 ++#define ixDCIO_DEBUG18 0x18 ++#define ixDCIO_DEBUG19 0x19 ++#define ixDCIO_DEBUG1A 0x1a ++#define ixDCIO_DEBUG1B 0x1b ++#define ixDCIO_DEBUG_ID 0x0 ++#define mmDC_GPIO_GENERIC_MASK 0x4860 ++#define mmDC_GPIO_GENERIC_A 0x4861 ++#define mmDC_GPIO_GENERIC_EN 0x4862 ++#define mmDC_GPIO_GENERIC_Y 0x4863 ++#define mmDC_GPIO_DVODATA_MASK 0x4864 ++#define mmDC_GPIO_DVODATA_A 0x4865 ++#define mmDC_GPIO_DVODATA_EN 0x4866 ++#define mmDC_GPIO_DVODATA_Y 0x4867 ++#define mmDC_GPIO_DDC1_MASK 0x4868 ++#define mmDC_GPIO_DDC1_A 0x4869 ++#define mmDC_GPIO_DDC1_EN 0x486a ++#define mmDC_GPIO_DDC1_Y 0x486b ++#define mmDC_GPIO_DDC2_MASK 0x486c ++#define mmDC_GPIO_DDC2_A 0x486d ++#define mmDC_GPIO_DDC2_EN 0x486e ++#define mmDC_GPIO_DDC2_Y 0x486f ++#define mmDC_GPIO_DDC3_MASK 0x4870 ++#define mmDC_GPIO_DDC3_A 0x4871 ++#define mmDC_GPIO_DDC3_EN 0x4872 ++#define mmDC_GPIO_DDC3_Y 0x4873 ++#define mmDC_GPIO_DDC4_MASK 0x4874 ++#define mmDC_GPIO_DDC4_A 0x4875 ++#define mmDC_GPIO_DDC4_EN 0x4876 ++#define mmDC_GPIO_DDC4_Y 0x4877 ++#define mmDC_GPIO_DDC5_MASK 0x4878 ++#define mmDC_GPIO_DDC5_A 0x4879 ++#define mmDC_GPIO_DDC5_EN 0x487a ++#define mmDC_GPIO_DDC5_Y 0x487b ++#define mmDC_GPIO_DDC6_MASK 0x487c ++#define mmDC_GPIO_DDC6_A 0x487d ++#define mmDC_GPIO_DDC6_EN 0x487e ++#define mmDC_GPIO_DDC6_Y 0x487f ++#define mmDC_GPIO_DDCVGA_MASK 0x4880 ++#define mmDC_GPIO_DDCVGA_A 0x4881 ++#define mmDC_GPIO_DDCVGA_EN 0x4882 ++#define mmDC_GPIO_DDCVGA_Y 0x4883 ++#define mmDC_GPIO_SYNCA_MASK 0x4884 ++#define mmDC_GPIO_SYNCA_A 0x4885 ++#define mmDC_GPIO_SYNCA_EN 0x4886 ++#define mmDC_GPIO_SYNCA_Y 0x4887 ++#define mmDC_GPIO_GENLK_MASK 0x4888 ++#define mmDC_GPIO_GENLK_A 0x4889 ++#define mmDC_GPIO_GENLK_EN 0x488a ++#define mmDC_GPIO_GENLK_Y 0x488b ++#define mmDC_GPIO_HPD_MASK 0x488c ++#define mmDC_GPIO_HPD_A 0x488d ++#define mmDC_GPIO_HPD_EN 0x488e ++#define mmDC_GPIO_HPD_Y 0x488f ++#define mmDC_GPIO_PWRSEQ_MASK 0x4890 ++#define mmDC_GPIO_PWRSEQ_A 0x4891 ++#define mmDC_GPIO_PWRSEQ_EN 0x4892 ++#define mmDC_GPIO_PWRSEQ_Y 0x4893 ++#define mmDC_GPIO_PAD_STRENGTH_1 0x4894 ++#define mmDC_GPIO_PAD_STRENGTH_2 0x4895 ++#define mmPHY_AUX_CNTL 0x4897 ++#define mmDC_GPIO_I2CPAD_MASK 0x4898 ++#define mmDC_GPIO_I2CPAD_A 0x4899 ++#define mmDC_GPIO_I2CPAD_EN 0x489a ++#define mmDC_GPIO_I2CPAD_Y 0x489b ++#define mmDC_GPIO_I2CPAD_STRENGTH 0x489c ++#define mmDVO_VREF_CONTROL 0x489e ++#define mmDVO_SKEW_ADJUST 0x489f ++#define mmDAC_MACRO_CNTL_RESERVED0 0x48b8 ++#define mmDAC_MACRO_CNTL_RESERVED1 0x48b9 ++#define mmDAC_MACRO_CNTL_RESERVED2 0x48ba ++#define mmDAC_MACRO_CNTL_RESERVED3 0x48bb ++#define mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x48e0 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x4900 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x4920 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x4940 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x4960 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x4980 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0 0x49c0 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0x49e0 ++#define mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x48e1 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x4901 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x4921 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x4941 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x4961 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x4981 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1 0x49c1 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0x49e1 ++#define mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x48e2 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x4902 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x4922 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x4942 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x4962 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x4982 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2 0x49c2 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0x49e2 ++#define mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x48e3 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x4903 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x4923 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x4943 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x4963 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x4983 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3 0x49c3 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0x49e3 ++#define mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x48e4 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x4904 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x4924 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x4944 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x4964 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x4984 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4 0x49c4 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0x49e4 ++#define mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x48e5 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x4905 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x4925 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x4945 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x4965 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x4985 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5 0x49c5 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0x49e5 ++#define mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x48e6 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x4906 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x4926 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x4946 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x4966 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x4986 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6 0x49c6 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0x49e6 ++#define mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x48e7 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x4907 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x4927 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x4947 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x4967 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x4987 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7 0x49c7 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0x49e7 ++#define mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x48e8 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x4908 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x4928 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x4948 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x4968 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x4988 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8 0x49c8 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0x49e8 ++#define mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x48e9 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x4909 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x4929 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x4949 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x4969 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x4989 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9 0x49c9 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0x49e9 ++#define mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x48ea ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x490a ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x492a ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x494a ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x496a ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x498a ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10 0x49ca ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0x49ea ++#define mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x48eb ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x490b ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x492b ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x494b ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x496b ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x498b ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11 0x49cb ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0x49eb ++#define mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x48ec ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x490c ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x492c ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x494c ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x496c ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x498c ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12 0x49cc ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0x49ec ++#define mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x48ed ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x490d ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x492d ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x494d ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x496d ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x498d ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13 0x49cd ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0x49ed ++#define mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x48ee ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x490e ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x492e ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x494e ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x496e ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x498e ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14 0x49ce ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0x49ee ++#define mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x48ef ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x490f ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x492f ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x494f ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x496f ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x498f ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15 0x49cf ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0x49ef ++#define mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x48f0 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x4910 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x4930 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x4950 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x4970 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x4990 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16 0x49d0 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0x49f0 ++#define mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x48f1 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x4911 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x4931 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x4951 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x4971 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x4991 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17 0x49d1 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0x49f1 ++#define mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x48f2 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x4912 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x4932 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x4952 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x4972 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x4992 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18 0x49d2 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0x49f2 ++#define mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x48f3 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x4913 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x4933 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x4953 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x4973 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x4993 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19 0x49d3 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0x49f3 ++#define mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x48f4 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x4914 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x4934 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x4954 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x4974 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x4994 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20 0x49d4 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0x49f4 ++#define mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x48f5 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x4915 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x4935 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x4955 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x4975 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x4995 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21 0x49d5 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0x49f5 ++#define mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x48f6 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x4916 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x4936 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x4956 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x4976 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x4996 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22 0x49d6 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0x49f6 ++#define mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x48f7 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x4917 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x4937 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x4957 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x4977 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x4997 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23 0x49d7 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0x49f7 ++#define mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x48f8 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x4918 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x4938 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x4958 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x4978 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x4998 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24 0x49d8 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0x49f8 ++#define mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9 ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9 ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x48f9 ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x4919 ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x4939 ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x4959 ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x4979 ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x4999 ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25 0x49d9 ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0x49f9 ++#define mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x48fa ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x491a ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x493a ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x495a ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x497a ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x499a ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26 0x49da ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0x49fa ++#define mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x48fb ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x491b ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x493b ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x495b ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x497b ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x499b ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27 0x49db ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0x49fb ++#define mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x48fc ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x491c ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x493c ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x495c ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x497c ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x499c ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28 0x49dc ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0x49fc ++#define mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x48fd ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x491d ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x493d ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x495d ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x497d ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x499d ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29 0x49dd ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0x49fd ++#define mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x48fe ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x491e ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x493e ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x495e ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x497e ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x499e ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30 0x49de ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0x49fe ++#define mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df ++#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df ++#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x48ff ++#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x491f ++#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x493f ++#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x495f ++#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x497f ++#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x499f ++#define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31 0x49df ++#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0x49ff ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9 ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe ++#define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff ++#define mmDPHY_MACRO_CNTL_RESERVED0 0x5d98 ++#define mmDPHY_MACRO_CNTL_RESERVED1 0x5d99 ++#define mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a ++#define mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b ++#define mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c ++#define mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d ++#define mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e ++#define mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f ++#define mmDPHY_MACRO_CNTL_RESERVED8 0x5da0 ++#define mmDPHY_MACRO_CNTL_RESERVED9 0x5da1 ++#define mmDPHY_MACRO_CNTL_RESERVED10 0x5da2 ++#define mmDPHY_MACRO_CNTL_RESERVED11 0x5da3 ++#define mmDPHY_MACRO_CNTL_RESERVED12 0x5da4 ++#define mmDPHY_MACRO_CNTL_RESERVED13 0x5da5 ++#define mmDPHY_MACRO_CNTL_RESERVED14 0x5da6 ++#define mmDPHY_MACRO_CNTL_RESERVED15 0x5da7 ++#define mmDPHY_MACRO_CNTL_RESERVED16 0x5da8 ++#define mmDPHY_MACRO_CNTL_RESERVED17 0x5da9 ++#define mmDPHY_MACRO_CNTL_RESERVED18 0x5daa ++#define mmDPHY_MACRO_CNTL_RESERVED19 0x5dab ++#define mmDPHY_MACRO_CNTL_RESERVED20 0x5dac ++#define mmDPHY_MACRO_CNTL_RESERVED21 0x5dad ++#define mmDPHY_MACRO_CNTL_RESERVED22 0x5dae ++#define mmDPHY_MACRO_CNTL_RESERVED23 0x5daf ++#define mmDPHY_MACRO_CNTL_RESERVED24 0x5db0 ++#define mmDPHY_MACRO_CNTL_RESERVED25 0x5db1 ++#define mmDPHY_MACRO_CNTL_RESERVED26 0x5db2 ++#define mmDPHY_MACRO_CNTL_RESERVED27 0x5db3 ++#define mmDPHY_MACRO_CNTL_RESERVED28 0x5db4 ++#define mmDPHY_MACRO_CNTL_RESERVED29 0x5db5 ++#define mmDPHY_MACRO_CNTL_RESERVED30 0x5db6 ++#define mmDPHY_MACRO_CNTL_RESERVED31 0x5db7 ++#define mmDPHY_MACRO_CNTL_RESERVED32 0x5db8 ++#define mmDPHY_MACRO_CNTL_RESERVED33 0x5db9 ++#define mmDPHY_MACRO_CNTL_RESERVED34 0x5dba ++#define mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb ++#define mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc ++#define mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd ++#define mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe ++#define mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf ++#define mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0 ++#define mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1 ++#define mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2 ++#define mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3 ++#define mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4 ++#define mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5 ++#define mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6 ++#define mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7 ++#define mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8 ++#define mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9 ++#define mmDPHY_MACRO_CNTL_RESERVED50 0x5dca ++#define mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb ++#define mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc ++#define mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd ++#define mmDPHY_MACRO_CNTL_RESERVED54 0x5dce ++#define mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf ++#define mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0 ++#define mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1 ++#define mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2 ++#define mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3 ++#define mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4 ++#define mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5 ++#define mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6 ++#define mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7 ++#define mmGRPH_ENABLE 0x1a00 ++#define mmDCP0_GRPH_ENABLE 0x1a00 ++#define mmDCP1_GRPH_ENABLE 0x1c00 ++#define mmDCP2_GRPH_ENABLE 0x1e00 ++#define mmDCP3_GRPH_ENABLE 0x4000 ++#define mmDCP4_GRPH_ENABLE 0x4200 ++#define mmDCP5_GRPH_ENABLE 0x4400 ++#define mmGRPH_CONTROL 0x1a01 ++#define mmDCP0_GRPH_CONTROL 0x1a01 ++#define mmDCP1_GRPH_CONTROL 0x1c01 ++#define mmDCP2_GRPH_CONTROL 0x1e01 ++#define mmDCP3_GRPH_CONTROL 0x4001 ++#define mmDCP4_GRPH_CONTROL 0x4201 ++#define mmDCP5_GRPH_CONTROL 0x4401 ++#define mmGRPH_LUT_10BIT_BYPASS 0x1a02 ++#define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 ++#define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02 ++#define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02 ++#define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002 ++#define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202 ++#define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402 ++#define mmGRPH_SWAP_CNTL 0x1a03 ++#define mmDCP0_GRPH_SWAP_CNTL 0x1a03 ++#define mmDCP1_GRPH_SWAP_CNTL 0x1c03 ++#define mmDCP2_GRPH_SWAP_CNTL 0x1e03 ++#define mmDCP3_GRPH_SWAP_CNTL 0x4003 ++#define mmDCP4_GRPH_SWAP_CNTL 0x4203 ++#define mmDCP5_GRPH_SWAP_CNTL 0x4403 ++#define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 ++#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 ++#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04 ++#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04 ++#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 ++#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204 ++#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404 ++#define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 ++#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 ++#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05 ++#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05 ++#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 ++#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205 ++#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405 ++#define mmGRPH_PITCH 0x1a06 ++#define mmDCP0_GRPH_PITCH 0x1a06 ++#define mmDCP1_GRPH_PITCH 0x1c06 ++#define mmDCP2_GRPH_PITCH 0x1e06 ++#define mmDCP3_GRPH_PITCH 0x4006 ++#define mmDCP4_GRPH_PITCH 0x4206 ++#define mmDCP5_GRPH_PITCH 0x4406 ++#define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 ++#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 ++#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07 ++#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07 ++#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 ++#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207 ++#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407 ++#define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 ++#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 ++#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08 ++#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08 ++#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 ++#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208 ++#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408 ++#define mmGRPH_SURFACE_OFFSET_X 0x1a09 ++#define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 ++#define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09 ++#define mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09 ++#define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009 ++#define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209 ++#define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409 ++#define mmGRPH_SURFACE_OFFSET_Y 0x1a0a ++#define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a ++#define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a ++#define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a ++#define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a ++#define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a ++#define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a ++#define mmGRPH_X_START 0x1a0b ++#define mmDCP0_GRPH_X_START 0x1a0b ++#define mmDCP1_GRPH_X_START 0x1c0b ++#define mmDCP2_GRPH_X_START 0x1e0b ++#define mmDCP3_GRPH_X_START 0x400b ++#define mmDCP4_GRPH_X_START 0x420b ++#define mmDCP5_GRPH_X_START 0x440b ++#define mmGRPH_Y_START 0x1a0c ++#define mmDCP0_GRPH_Y_START 0x1a0c ++#define mmDCP1_GRPH_Y_START 0x1c0c ++#define mmDCP2_GRPH_Y_START 0x1e0c ++#define mmDCP3_GRPH_Y_START 0x400c ++#define mmDCP4_GRPH_Y_START 0x420c ++#define mmDCP5_GRPH_Y_START 0x440c ++#define mmGRPH_X_END 0x1a0d ++#define mmDCP0_GRPH_X_END 0x1a0d ++#define mmDCP1_GRPH_X_END 0x1c0d ++#define mmDCP2_GRPH_X_END 0x1e0d ++#define mmDCP3_GRPH_X_END 0x400d ++#define mmDCP4_GRPH_X_END 0x420d ++#define mmDCP5_GRPH_X_END 0x440d ++#define mmGRPH_Y_END 0x1a0e ++#define mmDCP0_GRPH_Y_END 0x1a0e ++#define mmDCP1_GRPH_Y_END 0x1c0e ++#define mmDCP2_GRPH_Y_END 0x1e0e ++#define mmDCP3_GRPH_Y_END 0x400e ++#define mmDCP4_GRPH_Y_END 0x420e ++#define mmDCP5_GRPH_Y_END 0x440e ++#define mmINPUT_GAMMA_CONTROL 0x1a10 ++#define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 ++#define mmDCP1_INPUT_GAMMA_CONTROL 0x1c10 ++#define mmDCP2_INPUT_GAMMA_CONTROL 0x1e10 ++#define mmDCP3_INPUT_GAMMA_CONTROL 0x4010 ++#define mmDCP4_INPUT_GAMMA_CONTROL 0x4210 ++#define mmDCP5_INPUT_GAMMA_CONTROL 0x4410 ++#define mmGRPH_UPDATE 0x1a11 ++#define mmDCP0_GRPH_UPDATE 0x1a11 ++#define mmDCP1_GRPH_UPDATE 0x1c11 ++#define mmDCP2_GRPH_UPDATE 0x1e11 ++#define mmDCP3_GRPH_UPDATE 0x4011 ++#define mmDCP4_GRPH_UPDATE 0x4211 ++#define mmDCP5_GRPH_UPDATE 0x4411 ++#define mmGRPH_FLIP_CONTROL 0x1a12 ++#define mmDCP0_GRPH_FLIP_CONTROL 0x1a12 ++#define mmDCP1_GRPH_FLIP_CONTROL 0x1c12 ++#define mmDCP2_GRPH_FLIP_CONTROL 0x1e12 ++#define mmDCP3_GRPH_FLIP_CONTROL 0x4012 ++#define mmDCP4_GRPH_FLIP_CONTROL 0x4212 ++#define mmDCP5_GRPH_FLIP_CONTROL 0x4412 ++#define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 ++#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 ++#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13 ++#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13 ++#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013 ++#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213 ++#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413 ++#define mmGRPH_DFQ_CONTROL 0x1a14 ++#define mmDCP0_GRPH_DFQ_CONTROL 0x1a14 ++#define mmDCP1_GRPH_DFQ_CONTROL 0x1c14 ++#define mmDCP2_GRPH_DFQ_CONTROL 0x1e14 ++#define mmDCP3_GRPH_DFQ_CONTROL 0x4014 ++#define mmDCP4_GRPH_DFQ_CONTROL 0x4214 ++#define mmDCP5_GRPH_DFQ_CONTROL 0x4414 ++#define mmGRPH_DFQ_STATUS 0x1a15 ++#define mmDCP0_GRPH_DFQ_STATUS 0x1a15 ++#define mmDCP1_GRPH_DFQ_STATUS 0x1c15 ++#define mmDCP2_GRPH_DFQ_STATUS 0x1e15 ++#define mmDCP3_GRPH_DFQ_STATUS 0x4015 ++#define mmDCP4_GRPH_DFQ_STATUS 0x4215 ++#define mmDCP5_GRPH_DFQ_STATUS 0x4415 ++#define mmGRPH_INTERRUPT_STATUS 0x1a16 ++#define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 ++#define mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16 ++#define mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16 ++#define mmDCP3_GRPH_INTERRUPT_STATUS 0x4016 ++#define mmDCP4_GRPH_INTERRUPT_STATUS 0x4216 ++#define mmDCP5_GRPH_INTERRUPT_STATUS 0x4416 ++#define mmGRPH_INTERRUPT_CONTROL 0x1a17 ++#define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 ++#define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17 ++#define mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17 ++#define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017 ++#define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217 ++#define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417 ++#define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 ++#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 ++#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18 ++#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18 ++#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 ++#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218 ++#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418 ++#define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 ++#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 ++#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19 ++#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19 ++#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 ++#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219 ++#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419 ++#define mmGRPH_COMPRESS_PITCH 0x1a1a ++#define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a ++#define mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a ++#define mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a ++#define mmDCP3_GRPH_COMPRESS_PITCH 0x401a ++#define mmDCP4_GRPH_COMPRESS_PITCH 0x421a ++#define mmDCP5_GRPH_COMPRESS_PITCH 0x441a ++#define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b ++#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b ++#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b ++#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b ++#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b ++#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b ++#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b ++#define mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c ++#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c ++#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1c1c ++#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1e1c ++#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x401c ++#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x421c ++#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x441c ++#define mmPRESCALE_GRPH_CONTROL 0x1a2d ++#define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d ++#define mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d ++#define mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d ++#define mmDCP3_PRESCALE_GRPH_CONTROL 0x402d ++#define mmDCP4_PRESCALE_GRPH_CONTROL 0x422d ++#define mmDCP5_PRESCALE_GRPH_CONTROL 0x442d ++#define mmPRESCALE_VALUES_GRPH_R 0x1a2e ++#define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e ++#define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e ++#define mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e ++#define mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e ++#define mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e ++#define mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e ++#define mmPRESCALE_VALUES_GRPH_G 0x1a2f ++#define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f ++#define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f ++#define mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f ++#define mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f ++#define mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f ++#define mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f ++#define mmPRESCALE_VALUES_GRPH_B 0x1a30 ++#define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 ++#define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30 ++#define mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30 ++#define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030 ++#define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230 ++#define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430 ++#define mmINPUT_CSC_CONTROL 0x1a35 ++#define mmDCP0_INPUT_CSC_CONTROL 0x1a35 ++#define mmDCP1_INPUT_CSC_CONTROL 0x1c35 ++#define mmDCP2_INPUT_CSC_CONTROL 0x1e35 ++#define mmDCP3_INPUT_CSC_CONTROL 0x4035 ++#define mmDCP4_INPUT_CSC_CONTROL 0x4235 ++#define mmDCP5_INPUT_CSC_CONTROL 0x4435 ++#define mmINPUT_CSC_C11_C12 0x1a36 ++#define mmDCP0_INPUT_CSC_C11_C12 0x1a36 ++#define mmDCP1_INPUT_CSC_C11_C12 0x1c36 ++#define mmDCP2_INPUT_CSC_C11_C12 0x1e36 ++#define mmDCP3_INPUT_CSC_C11_C12 0x4036 ++#define mmDCP4_INPUT_CSC_C11_C12 0x4236 ++#define mmDCP5_INPUT_CSC_C11_C12 0x4436 ++#define mmINPUT_CSC_C13_C14 0x1a37 ++#define mmDCP0_INPUT_CSC_C13_C14 0x1a37 ++#define mmDCP1_INPUT_CSC_C13_C14 0x1c37 ++#define mmDCP2_INPUT_CSC_C13_C14 0x1e37 ++#define mmDCP3_INPUT_CSC_C13_C14 0x4037 ++#define mmDCP4_INPUT_CSC_C13_C14 0x4237 ++#define mmDCP5_INPUT_CSC_C13_C14 0x4437 ++#define mmINPUT_CSC_C21_C22 0x1a38 ++#define mmDCP0_INPUT_CSC_C21_C22 0x1a38 ++#define mmDCP1_INPUT_CSC_C21_C22 0x1c38 ++#define mmDCP2_INPUT_CSC_C21_C22 0x1e38 ++#define mmDCP3_INPUT_CSC_C21_C22 0x4038 ++#define mmDCP4_INPUT_CSC_C21_C22 0x4238 ++#define mmDCP5_INPUT_CSC_C21_C22 0x4438 ++#define mmINPUT_CSC_C23_C24 0x1a39 ++#define mmDCP0_INPUT_CSC_C23_C24 0x1a39 ++#define mmDCP1_INPUT_CSC_C23_C24 0x1c39 ++#define mmDCP2_INPUT_CSC_C23_C24 0x1e39 ++#define mmDCP3_INPUT_CSC_C23_C24 0x4039 ++#define mmDCP4_INPUT_CSC_C23_C24 0x4239 ++#define mmDCP5_INPUT_CSC_C23_C24 0x4439 ++#define mmINPUT_CSC_C31_C32 0x1a3a ++#define mmDCP0_INPUT_CSC_C31_C32 0x1a3a ++#define mmDCP1_INPUT_CSC_C31_C32 0x1c3a ++#define mmDCP2_INPUT_CSC_C31_C32 0x1e3a ++#define mmDCP3_INPUT_CSC_C31_C32 0x403a ++#define mmDCP4_INPUT_CSC_C31_C32 0x423a ++#define mmDCP5_INPUT_CSC_C31_C32 0x443a ++#define mmINPUT_CSC_C33_C34 0x1a3b ++#define mmDCP0_INPUT_CSC_C33_C34 0x1a3b ++#define mmDCP1_INPUT_CSC_C33_C34 0x1c3b ++#define mmDCP2_INPUT_CSC_C33_C34 0x1e3b ++#define mmDCP3_INPUT_CSC_C33_C34 0x403b ++#define mmDCP4_INPUT_CSC_C33_C34 0x423b ++#define mmDCP5_INPUT_CSC_C33_C34 0x443b ++#define mmOUTPUT_CSC_CONTROL 0x1a3c ++#define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c ++#define mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c ++#define mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c ++#define mmDCP3_OUTPUT_CSC_CONTROL 0x403c ++#define mmDCP4_OUTPUT_CSC_CONTROL 0x423c ++#define mmDCP5_OUTPUT_CSC_CONTROL 0x443c ++#define mmOUTPUT_CSC_C11_C12 0x1a3d ++#define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d ++#define mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d ++#define mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d ++#define mmDCP3_OUTPUT_CSC_C11_C12 0x403d ++#define mmDCP4_OUTPUT_CSC_C11_C12 0x423d ++#define mmDCP5_OUTPUT_CSC_C11_C12 0x443d ++#define mmOUTPUT_CSC_C13_C14 0x1a3e ++#define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e ++#define mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e ++#define mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e ++#define mmDCP3_OUTPUT_CSC_C13_C14 0x403e ++#define mmDCP4_OUTPUT_CSC_C13_C14 0x423e ++#define mmDCP5_OUTPUT_CSC_C13_C14 0x443e ++#define mmOUTPUT_CSC_C21_C22 0x1a3f ++#define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f ++#define mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f ++#define mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f ++#define mmDCP3_OUTPUT_CSC_C21_C22 0x403f ++#define mmDCP4_OUTPUT_CSC_C21_C22 0x423f ++#define mmDCP5_OUTPUT_CSC_C21_C22 0x443f ++#define mmOUTPUT_CSC_C23_C24 0x1a40 ++#define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 ++#define mmDCP1_OUTPUT_CSC_C23_C24 0x1c40 ++#define mmDCP2_OUTPUT_CSC_C23_C24 0x1e40 ++#define mmDCP3_OUTPUT_CSC_C23_C24 0x4040 ++#define mmDCP4_OUTPUT_CSC_C23_C24 0x4240 ++#define mmDCP5_OUTPUT_CSC_C23_C24 0x4440 ++#define mmOUTPUT_CSC_C31_C32 0x1a41 ++#define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 ++#define mmDCP1_OUTPUT_CSC_C31_C32 0x1c41 ++#define mmDCP2_OUTPUT_CSC_C31_C32 0x1e41 ++#define mmDCP3_OUTPUT_CSC_C31_C32 0x4041 ++#define mmDCP4_OUTPUT_CSC_C31_C32 0x4241 ++#define mmDCP5_OUTPUT_CSC_C31_C32 0x4441 ++#define mmOUTPUT_CSC_C33_C34 0x1a42 ++#define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 ++#define mmDCP1_OUTPUT_CSC_C33_C34 0x1c42 ++#define mmDCP2_OUTPUT_CSC_C33_C34 0x1e42 ++#define mmDCP3_OUTPUT_CSC_C33_C34 0x4042 ++#define mmDCP4_OUTPUT_CSC_C33_C34 0x4242 ++#define mmDCP5_OUTPUT_CSC_C33_C34 0x4442 ++#define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 ++#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 ++#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43 ++#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43 ++#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043 ++#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243 ++#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443 ++#define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 ++#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 ++#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44 ++#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44 ++#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044 ++#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244 ++#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444 ++#define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 ++#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 ++#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45 ++#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45 ++#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045 ++#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245 ++#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445 ++#define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 ++#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 ++#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46 ++#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46 ++#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046 ++#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246 ++#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446 ++#define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 ++#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 ++#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47 ++#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47 ++#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047 ++#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247 ++#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447 ++#define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 ++#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 ++#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48 ++#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48 ++#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048 ++#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248 ++#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448 ++#define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 ++#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 ++#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49 ++#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49 ++#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049 ++#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249 ++#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449 ++#define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a ++#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a ++#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a ++#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a ++#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a ++#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a ++#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a ++#define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b ++#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b ++#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b ++#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b ++#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b ++#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b ++#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b ++#define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c ++#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c ++#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c ++#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c ++#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c ++#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c ++#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c ++#define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d ++#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d ++#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d ++#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d ++#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d ++#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d ++#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d ++#define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e ++#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e ++#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e ++#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e ++#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e ++#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e ++#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e ++#define mmDENORM_CONTROL 0x1a50 ++#define mmDCP0_DENORM_CONTROL 0x1a50 ++#define mmDCP1_DENORM_CONTROL 0x1c50 ++#define mmDCP2_DENORM_CONTROL 0x1e50 ++#define mmDCP3_DENORM_CONTROL 0x4050 ++#define mmDCP4_DENORM_CONTROL 0x4250 ++#define mmDCP5_DENORM_CONTROL 0x4450 ++#define mmOUT_ROUND_CONTROL 0x1a51 ++#define mmDCP0_OUT_ROUND_CONTROL 0x1a51 ++#define mmDCP1_OUT_ROUND_CONTROL 0x1c51 ++#define mmDCP2_OUT_ROUND_CONTROL 0x1e51 ++#define mmDCP3_OUT_ROUND_CONTROL 0x4051 ++#define mmDCP4_OUT_ROUND_CONTROL 0x4251 ++#define mmDCP5_OUT_ROUND_CONTROL 0x4451 ++#define mmOUT_CLAMP_CONTROL_R_CR 0x1a52 ++#define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 ++#define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52 ++#define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52 ++#define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052 ++#define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252 ++#define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452 ++#define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c ++#define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c ++#define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c ++#define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c ++#define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c ++#define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c ++#define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c ++#define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d ++#define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d ++#define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d ++#define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d ++#define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d ++#define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d ++#define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d ++#define mmKEY_CONTROL 0x1a53 ++#define mmDCP0_KEY_CONTROL 0x1a53 ++#define mmDCP1_KEY_CONTROL 0x1c53 ++#define mmDCP2_KEY_CONTROL 0x1e53 ++#define mmDCP3_KEY_CONTROL 0x4053 ++#define mmDCP4_KEY_CONTROL 0x4253 ++#define mmDCP5_KEY_CONTROL 0x4453 ++#define mmKEY_RANGE_ALPHA 0x1a54 ++#define mmDCP0_KEY_RANGE_ALPHA 0x1a54 ++#define mmDCP1_KEY_RANGE_ALPHA 0x1c54 ++#define mmDCP2_KEY_RANGE_ALPHA 0x1e54 ++#define mmDCP3_KEY_RANGE_ALPHA 0x4054 ++#define mmDCP4_KEY_RANGE_ALPHA 0x4254 ++#define mmDCP5_KEY_RANGE_ALPHA 0x4454 ++#define mmKEY_RANGE_RED 0x1a55 ++#define mmDCP0_KEY_RANGE_RED 0x1a55 ++#define mmDCP1_KEY_RANGE_RED 0x1c55 ++#define mmDCP2_KEY_RANGE_RED 0x1e55 ++#define mmDCP3_KEY_RANGE_RED 0x4055 ++#define mmDCP4_KEY_RANGE_RED 0x4255 ++#define mmDCP5_KEY_RANGE_RED 0x4455 ++#define mmKEY_RANGE_GREEN 0x1a56 ++#define mmDCP0_KEY_RANGE_GREEN 0x1a56 ++#define mmDCP1_KEY_RANGE_GREEN 0x1c56 ++#define mmDCP2_KEY_RANGE_GREEN 0x1e56 ++#define mmDCP3_KEY_RANGE_GREEN 0x4056 ++#define mmDCP4_KEY_RANGE_GREEN 0x4256 ++#define mmDCP5_KEY_RANGE_GREEN 0x4456 ++#define mmKEY_RANGE_BLUE 0x1a57 ++#define mmDCP0_KEY_RANGE_BLUE 0x1a57 ++#define mmDCP1_KEY_RANGE_BLUE 0x1c57 ++#define mmDCP2_KEY_RANGE_BLUE 0x1e57 ++#define mmDCP3_KEY_RANGE_BLUE 0x4057 ++#define mmDCP4_KEY_RANGE_BLUE 0x4257 ++#define mmDCP5_KEY_RANGE_BLUE 0x4457 ++#define mmDEGAMMA_CONTROL 0x1a58 ++#define mmDCP0_DEGAMMA_CONTROL 0x1a58 ++#define mmDCP1_DEGAMMA_CONTROL 0x1c58 ++#define mmDCP2_DEGAMMA_CONTROL 0x1e58 ++#define mmDCP3_DEGAMMA_CONTROL 0x4058 ++#define mmDCP4_DEGAMMA_CONTROL 0x4258 ++#define mmDCP5_DEGAMMA_CONTROL 0x4458 ++#define mmGAMUT_REMAP_CONTROL 0x1a59 ++#define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 ++#define mmDCP1_GAMUT_REMAP_CONTROL 0x1c59 ++#define mmDCP2_GAMUT_REMAP_CONTROL 0x1e59 ++#define mmDCP3_GAMUT_REMAP_CONTROL 0x4059 ++#define mmDCP4_GAMUT_REMAP_CONTROL 0x4259 ++#define mmDCP5_GAMUT_REMAP_CONTROL 0x4459 ++#define mmGAMUT_REMAP_C11_C12 0x1a5a ++#define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a ++#define mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a ++#define mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a ++#define mmDCP3_GAMUT_REMAP_C11_C12 0x405a ++#define mmDCP4_GAMUT_REMAP_C11_C12 0x425a ++#define mmDCP5_GAMUT_REMAP_C11_C12 0x445a ++#define mmGAMUT_REMAP_C13_C14 0x1a5b ++#define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b ++#define mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b ++#define mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b ++#define mmDCP3_GAMUT_REMAP_C13_C14 0x405b ++#define mmDCP4_GAMUT_REMAP_C13_C14 0x425b ++#define mmDCP5_GAMUT_REMAP_C13_C14 0x445b ++#define mmGAMUT_REMAP_C21_C22 0x1a5c ++#define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c ++#define mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c ++#define mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c ++#define mmDCP3_GAMUT_REMAP_C21_C22 0x405c ++#define mmDCP4_GAMUT_REMAP_C21_C22 0x425c ++#define mmDCP5_GAMUT_REMAP_C21_C22 0x445c ++#define mmGAMUT_REMAP_C23_C24 0x1a5d ++#define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d ++#define mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d ++#define mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d ++#define mmDCP3_GAMUT_REMAP_C23_C24 0x405d ++#define mmDCP4_GAMUT_REMAP_C23_C24 0x425d ++#define mmDCP5_GAMUT_REMAP_C23_C24 0x445d ++#define mmGAMUT_REMAP_C31_C32 0x1a5e ++#define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e ++#define mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e ++#define mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e ++#define mmDCP3_GAMUT_REMAP_C31_C32 0x405e ++#define mmDCP4_GAMUT_REMAP_C31_C32 0x425e ++#define mmDCP5_GAMUT_REMAP_C31_C32 0x445e ++#define mmGAMUT_REMAP_C33_C34 0x1a5f ++#define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f ++#define mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f ++#define mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f ++#define mmDCP3_GAMUT_REMAP_C33_C34 0x405f ++#define mmDCP4_GAMUT_REMAP_C33_C34 0x425f ++#define mmDCP5_GAMUT_REMAP_C33_C34 0x445f ++#define mmDCP_SPATIAL_DITHER_CNTL 0x1a60 ++#define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 ++#define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60 ++#define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60 ++#define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060 ++#define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260 ++#define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460 ++#define mmDCP_FP_CONVERTED_FIELD 0x1a65 ++#define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 ++#define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65 ++#define mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65 ++#define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065 ++#define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265 ++#define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465 ++#define mmCUR_CONTROL 0x1a66 ++#define mmDCP0_CUR_CONTROL 0x1a66 ++#define mmDCP1_CUR_CONTROL 0x1c66 ++#define mmDCP2_CUR_CONTROL 0x1e66 ++#define mmDCP3_CUR_CONTROL 0x4066 ++#define mmDCP4_CUR_CONTROL 0x4266 ++#define mmDCP5_CUR_CONTROL 0x4466 ++#define mmCUR_SURFACE_ADDRESS 0x1a67 ++#define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 ++#define mmDCP1_CUR_SURFACE_ADDRESS 0x1c67 ++#define mmDCP2_CUR_SURFACE_ADDRESS 0x1e67 ++#define mmDCP3_CUR_SURFACE_ADDRESS 0x4067 ++#define mmDCP4_CUR_SURFACE_ADDRESS 0x4267 ++#define mmDCP5_CUR_SURFACE_ADDRESS 0x4467 ++#define mmCUR_SIZE 0x1a68 ++#define mmDCP0_CUR_SIZE 0x1a68 ++#define mmDCP1_CUR_SIZE 0x1c68 ++#define mmDCP2_CUR_SIZE 0x1e68 ++#define mmDCP3_CUR_SIZE 0x4068 ++#define mmDCP4_CUR_SIZE 0x4268 ++#define mmDCP5_CUR_SIZE 0x4468 ++#define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 ++#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 ++#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69 ++#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69 ++#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069 ++#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269 ++#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469 ++#define mmCUR_POSITION 0x1a6a ++#define mmDCP0_CUR_POSITION 0x1a6a ++#define mmDCP1_CUR_POSITION 0x1c6a ++#define mmDCP2_CUR_POSITION 0x1e6a ++#define mmDCP3_CUR_POSITION 0x406a ++#define mmDCP4_CUR_POSITION 0x426a ++#define mmDCP5_CUR_POSITION 0x446a ++#define mmCUR_HOT_SPOT 0x1a6b ++#define mmDCP0_CUR_HOT_SPOT 0x1a6b ++#define mmDCP1_CUR_HOT_SPOT 0x1c6b ++#define mmDCP2_CUR_HOT_SPOT 0x1e6b ++#define mmDCP3_CUR_HOT_SPOT 0x406b ++#define mmDCP4_CUR_HOT_SPOT 0x426b ++#define mmDCP5_CUR_HOT_SPOT 0x446b ++#define mmCUR_COLOR1 0x1a6c ++#define mmDCP0_CUR_COLOR1 0x1a6c ++#define mmDCP1_CUR_COLOR1 0x1c6c ++#define mmDCP2_CUR_COLOR1 0x1e6c ++#define mmDCP3_CUR_COLOR1 0x406c ++#define mmDCP4_CUR_COLOR1 0x426c ++#define mmDCP5_CUR_COLOR1 0x446c ++#define mmCUR_COLOR2 0x1a6d ++#define mmDCP0_CUR_COLOR2 0x1a6d ++#define mmDCP1_CUR_COLOR2 0x1c6d ++#define mmDCP2_CUR_COLOR2 0x1e6d ++#define mmDCP3_CUR_COLOR2 0x406d ++#define mmDCP4_CUR_COLOR2 0x426d ++#define mmDCP5_CUR_COLOR2 0x446d ++#define mmCUR_UPDATE 0x1a6e ++#define mmDCP0_CUR_UPDATE 0x1a6e ++#define mmDCP1_CUR_UPDATE 0x1c6e ++#define mmDCP2_CUR_UPDATE 0x1e6e ++#define mmDCP3_CUR_UPDATE 0x406e ++#define mmDCP4_CUR_UPDATE 0x426e ++#define mmDCP5_CUR_UPDATE 0x446e ++#define mmCUR_REQUEST_FILTER_CNTL 0x1a99 ++#define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 ++#define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99 ++#define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99 ++#define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099 ++#define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299 ++#define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499 ++#define mmCUR_STEREO_CONTROL 0x1a9a ++#define mmDCP0_CUR_STEREO_CONTROL 0x1a9a ++#define mmDCP1_CUR_STEREO_CONTROL 0x1c9a ++#define mmDCP2_CUR_STEREO_CONTROL 0x1e9a ++#define mmDCP3_CUR_STEREO_CONTROL 0x409a ++#define mmDCP4_CUR_STEREO_CONTROL 0x429a ++#define mmDCP5_CUR_STEREO_CONTROL 0x449a ++#define mmDC_LUT_RW_MODE 0x1a78 ++#define mmDCP0_DC_LUT_RW_MODE 0x1a78 ++#define mmDCP1_DC_LUT_RW_MODE 0x1c78 ++#define mmDCP2_DC_LUT_RW_MODE 0x1e78 ++#define mmDCP3_DC_LUT_RW_MODE 0x4078 ++#define mmDCP4_DC_LUT_RW_MODE 0x4278 ++#define mmDCP5_DC_LUT_RW_MODE 0x4478 ++#define mmDC_LUT_RW_INDEX 0x1a79 ++#define mmDCP0_DC_LUT_RW_INDEX 0x1a79 ++#define mmDCP1_DC_LUT_RW_INDEX 0x1c79 ++#define mmDCP2_DC_LUT_RW_INDEX 0x1e79 ++#define mmDCP3_DC_LUT_RW_INDEX 0x4079 ++#define mmDCP4_DC_LUT_RW_INDEX 0x4279 ++#define mmDCP5_DC_LUT_RW_INDEX 0x4479 ++#define mmDC_LUT_SEQ_COLOR 0x1a7a ++#define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a ++#define mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a ++#define mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a ++#define mmDCP3_DC_LUT_SEQ_COLOR 0x407a ++#define mmDCP4_DC_LUT_SEQ_COLOR 0x427a ++#define mmDCP5_DC_LUT_SEQ_COLOR 0x447a ++#define mmDC_LUT_PWL_DATA 0x1a7b ++#define mmDCP0_DC_LUT_PWL_DATA 0x1a7b ++#define mmDCP1_DC_LUT_PWL_DATA 0x1c7b ++#define mmDCP2_DC_LUT_PWL_DATA 0x1e7b ++#define mmDCP3_DC_LUT_PWL_DATA 0x407b ++#define mmDCP4_DC_LUT_PWL_DATA 0x427b ++#define mmDCP5_DC_LUT_PWL_DATA 0x447b ++#define mmDC_LUT_30_COLOR 0x1a7c ++#define mmDCP0_DC_LUT_30_COLOR 0x1a7c ++#define mmDCP1_DC_LUT_30_COLOR 0x1c7c ++#define mmDCP2_DC_LUT_30_COLOR 0x1e7c ++#define mmDCP3_DC_LUT_30_COLOR 0x407c ++#define mmDCP4_DC_LUT_30_COLOR 0x427c ++#define mmDCP5_DC_LUT_30_COLOR 0x447c ++#define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d ++#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d ++#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d ++#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d ++#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d ++#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d ++#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d ++#define mmDC_LUT_WRITE_EN_MASK 0x1a7e ++#define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e ++#define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e ++#define mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e ++#define mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e ++#define mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e ++#define mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e ++#define mmDC_LUT_AUTOFILL 0x1a7f ++#define mmDCP0_DC_LUT_AUTOFILL 0x1a7f ++#define mmDCP1_DC_LUT_AUTOFILL 0x1c7f ++#define mmDCP2_DC_LUT_AUTOFILL 0x1e7f ++#define mmDCP3_DC_LUT_AUTOFILL 0x407f ++#define mmDCP4_DC_LUT_AUTOFILL 0x427f ++#define mmDCP5_DC_LUT_AUTOFILL 0x447f ++#define mmDC_LUT_CONTROL 0x1a80 ++#define mmDCP0_DC_LUT_CONTROL 0x1a80 ++#define mmDCP1_DC_LUT_CONTROL 0x1c80 ++#define mmDCP2_DC_LUT_CONTROL 0x1e80 ++#define mmDCP3_DC_LUT_CONTROL 0x4080 ++#define mmDCP4_DC_LUT_CONTROL 0x4280 ++#define mmDCP5_DC_LUT_CONTROL 0x4480 ++#define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 ++#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 ++#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81 ++#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81 ++#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081 ++#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281 ++#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481 ++#define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 ++#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 ++#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82 ++#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82 ++#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082 ++#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282 ++#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482 ++#define mmDC_LUT_BLACK_OFFSET_RED 0x1a83 ++#define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 ++#define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83 ++#define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83 ++#define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083 ++#define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283 ++#define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483 ++#define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 ++#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 ++#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84 ++#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84 ++#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084 ++#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284 ++#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484 ++#define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 ++#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 ++#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85 ++#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85 ++#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085 ++#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285 ++#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485 ++#define mmDC_LUT_WHITE_OFFSET_RED 0x1a86 ++#define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 ++#define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86 ++#define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86 ++#define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086 ++#define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286 ++#define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486 ++#define mmDCP_CRC_CONTROL 0x1a87 ++#define mmDCP0_DCP_CRC_CONTROL 0x1a87 ++#define mmDCP1_DCP_CRC_CONTROL 0x1c87 ++#define mmDCP2_DCP_CRC_CONTROL 0x1e87 ++#define mmDCP3_DCP_CRC_CONTROL 0x4087 ++#define mmDCP4_DCP_CRC_CONTROL 0x4287 ++#define mmDCP5_DCP_CRC_CONTROL 0x4487 ++#define mmDCP_CRC_MASK 0x1a88 ++#define mmDCP0_DCP_CRC_MASK 0x1a88 ++#define mmDCP1_DCP_CRC_MASK 0x1c88 ++#define mmDCP2_DCP_CRC_MASK 0x1e88 ++#define mmDCP3_DCP_CRC_MASK 0x4088 ++#define mmDCP4_DCP_CRC_MASK 0x4288 ++#define mmDCP5_DCP_CRC_MASK 0x4488 ++#define mmDCP_CRC_CURRENT 0x1a89 ++#define mmDCP0_DCP_CRC_CURRENT 0x1a89 ++#define mmDCP1_DCP_CRC_CURRENT 0x1c89 ++#define mmDCP2_DCP_CRC_CURRENT 0x1e89 ++#define mmDCP3_DCP_CRC_CURRENT 0x4089 ++#define mmDCP4_DCP_CRC_CURRENT 0x4289 ++#define mmDCP5_DCP_CRC_CURRENT 0x4489 ++#define mmDVMM_PTE_CONTROL 0x1a8a ++#define mmDCP0_DVMM_PTE_CONTROL 0x1a8a ++#define mmDCP1_DVMM_PTE_CONTROL 0x1c8a ++#define mmDCP2_DVMM_PTE_CONTROL 0x1e8a ++#define mmDCP3_DVMM_PTE_CONTROL 0x408a ++#define mmDCP4_DVMM_PTE_CONTROL 0x428a ++#define mmDCP5_DVMM_PTE_CONTROL 0x448a ++#define mmDCP_CRC_LAST 0x1a8b ++#define mmDCP0_DCP_CRC_LAST 0x1a8b ++#define mmDCP1_DCP_CRC_LAST 0x1c8b ++#define mmDCP2_DCP_CRC_LAST 0x1e8b ++#define mmDCP3_DCP_CRC_LAST 0x408b ++#define mmDCP4_DCP_CRC_LAST 0x428b ++#define mmDCP5_DCP_CRC_LAST 0x448b ++#define mmDVMM_PTE_ARB_CONTROL 0x1a8c ++#define mmDCP0_DVMM_PTE_ARB_CONTROL 0x1a8c ++#define mmDCP1_DVMM_PTE_ARB_CONTROL 0x1c8c ++#define mmDCP2_DVMM_PTE_ARB_CONTROL 0x1e8c ++#define mmDCP3_DVMM_PTE_ARB_CONTROL 0x408c ++#define mmDCP4_DVMM_PTE_ARB_CONTROL 0x428c ++#define mmDCP5_DVMM_PTE_ARB_CONTROL 0x448c ++#define mmDCP_DEBUG 0x1a8d ++#define mmDCP0_DCP_DEBUG 0x1a8d ++#define mmDCP1_DCP_DEBUG 0x1c8d ++#define mmDCP2_DCP_DEBUG 0x1e8d ++#define mmDCP3_DCP_DEBUG 0x408d ++#define mmDCP4_DCP_DEBUG 0x428d ++#define mmDCP5_DCP_DEBUG 0x448d ++#define mmGRPH_FLIP_RATE_CNTL 0x1a8e ++#define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e ++#define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e ++#define mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e ++#define mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e ++#define mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e ++#define mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e ++#define mmDCP_GSL_CONTROL 0x1a90 ++#define mmDCP0_DCP_GSL_CONTROL 0x1a90 ++#define mmDCP1_DCP_GSL_CONTROL 0x1c90 ++#define mmDCP2_DCP_GSL_CONTROL 0x1e90 ++#define mmDCP3_DCP_GSL_CONTROL 0x4090 ++#define mmDCP4_DCP_GSL_CONTROL 0x4290 ++#define mmDCP5_DCP_GSL_CONTROL 0x4490 ++#define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 ++#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 ++#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91 ++#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91 ++#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 ++#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291 ++#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491 ++#define mmDCP_DEBUG_SG 0x1a92 ++#define mmDCP0_DCP_DEBUG_SG 0x1a92 ++#define mmDCP1_DCP_DEBUG_SG 0x1c92 ++#define mmDCP2_DCP_DEBUG_SG 0x1e92 ++#define mmDCP3_DCP_DEBUG_SG 0x4092 ++#define mmDCP4_DCP_DEBUG_SG 0x4292 ++#define mmDCP5_DCP_DEBUG_SG 0x4492 ++#define mmDCP_DEBUG_SG2 0x1a94 ++#define mmDCP0_DCP_DEBUG_SG2 0x1a94 ++#define mmDCP1_DCP_DEBUG_SG2 0x1c94 ++#define mmDCP2_DCP_DEBUG_SG2 0x1e94 ++#define mmDCP3_DCP_DEBUG_SG2 0x4094 ++#define mmDCP4_DCP_DEBUG_SG2 0x4294 ++#define mmDCP5_DCP_DEBUG_SG2 0x4494 ++#define mmDCP_DVMM_DEBUG 0x1a93 ++#define mmDCP0_DCP_DVMM_DEBUG 0x1a93 ++#define mmDCP1_DCP_DVMM_DEBUG 0x1c93 ++#define mmDCP2_DCP_DVMM_DEBUG 0x1e93 ++#define mmDCP3_DCP_DVMM_DEBUG 0x4093 ++#define mmDCP4_DCP_DVMM_DEBUG 0x4293 ++#define mmDCP5_DCP_DVMM_DEBUG 0x4493 ++#define mmDCP_TEST_DEBUG_INDEX 0x1a95 ++#define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 ++#define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95 ++#define mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95 ++#define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095 ++#define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295 ++#define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495 ++#define mmDCP_TEST_DEBUG_DATA 0x1a96 ++#define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 ++#define mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96 ++#define mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96 ++#define mmDCP3_DCP_TEST_DEBUG_DATA 0x4096 ++#define mmDCP4_DCP_TEST_DEBUG_DATA 0x4296 ++#define mmDCP5_DCP_TEST_DEBUG_DATA 0x4496 ++#define mmGRPH_STEREOSYNC_FLIP 0x1a97 ++#define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 ++#define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97 ++#define mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97 ++#define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097 ++#define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297 ++#define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497 ++#define mmDCP_DEBUG2 0x1a98 ++#define mmDCP0_DCP_DEBUG2 0x1a98 ++#define mmDCP1_DCP_DEBUG2 0x1c98 ++#define mmDCP2_DCP_DEBUG2 0x1e98 ++#define mmDCP3_DCP_DEBUG2 0x4098 ++#define mmDCP4_DCP_DEBUG2 0x4298 ++#define mmDCP5_DCP_DEBUG2 0x4498 ++#define mmHW_ROTATION 0x1a9e ++#define mmDCP0_HW_ROTATION 0x1a9e ++#define mmDCP1_HW_ROTATION 0x1c9e ++#define mmDCP2_HW_ROTATION 0x1e9e ++#define mmDCP3_HW_ROTATION 0x409e ++#define mmDCP4_HW_ROTATION 0x429e ++#define mmDCP5_HW_ROTATION 0x449e ++#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f ++#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f ++#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f ++#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f ++#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f ++#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f ++#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f ++#define mmREGAMMA_CONTROL 0x1aa0 ++#define mmDCP0_REGAMMA_CONTROL 0x1aa0 ++#define mmDCP1_REGAMMA_CONTROL 0x1ca0 ++#define mmDCP2_REGAMMA_CONTROL 0x1ea0 ++#define mmDCP3_REGAMMA_CONTROL 0x40a0 ++#define mmDCP4_REGAMMA_CONTROL 0x42a0 ++#define mmDCP5_REGAMMA_CONTROL 0x44a0 ++#define mmREGAMMA_LUT_INDEX 0x1aa1 ++#define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 ++#define mmDCP1_REGAMMA_LUT_INDEX 0x1ca1 ++#define mmDCP2_REGAMMA_LUT_INDEX 0x1ea1 ++#define mmDCP3_REGAMMA_LUT_INDEX 0x40a1 ++#define mmDCP4_REGAMMA_LUT_INDEX 0x42a1 ++#define mmDCP5_REGAMMA_LUT_INDEX 0x44a1 ++#define mmREGAMMA_LUT_DATA 0x1aa2 ++#define mmDCP0_REGAMMA_LUT_DATA 0x1aa2 ++#define mmDCP1_REGAMMA_LUT_DATA 0x1ca2 ++#define mmDCP2_REGAMMA_LUT_DATA 0x1ea2 ++#define mmDCP3_REGAMMA_LUT_DATA 0x40a2 ++#define mmDCP4_REGAMMA_LUT_DATA 0x42a2 ++#define mmDCP5_REGAMMA_LUT_DATA 0x44a2 ++#define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 ++#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 ++#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3 ++#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3 ++#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 ++#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3 ++#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3 ++#define mmREGAMMA_CNTLA_START_CNTL 0x1aa4 ++#define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 ++#define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4 ++#define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4 ++#define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4 ++#define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4 ++#define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4 ++#define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 ++#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 ++#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5 ++#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5 ++#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 ++#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5 ++#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5 ++#define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 ++#define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 ++#define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6 ++#define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6 ++#define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6 ++#define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6 ++#define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6 ++#define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 ++#define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 ++#define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7 ++#define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7 ++#define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7 ++#define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7 ++#define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7 ++#define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 ++#define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 ++#define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8 ++#define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8 ++#define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8 ++#define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8 ++#define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8 ++#define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 ++#define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 ++#define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9 ++#define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9 ++#define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9 ++#define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9 ++#define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9 ++#define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa ++#define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa ++#define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa ++#define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa ++#define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa ++#define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa ++#define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa ++#define mmREGAMMA_CNTLA_REGION_6_7 0x1aab ++#define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab ++#define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab ++#define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab ++#define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab ++#define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab ++#define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab ++#define mmREGAMMA_CNTLA_REGION_8_9 0x1aac ++#define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac ++#define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac ++#define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac ++#define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac ++#define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac ++#define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac ++#define mmREGAMMA_CNTLA_REGION_10_11 0x1aad ++#define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad ++#define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad ++#define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead ++#define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad ++#define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad ++#define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad ++#define mmREGAMMA_CNTLA_REGION_12_13 0x1aae ++#define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae ++#define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae ++#define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae ++#define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae ++#define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae ++#define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae ++#define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf ++#define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf ++#define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf ++#define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf ++#define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af ++#define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af ++#define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af ++#define mmREGAMMA_CNTLB_START_CNTL 0x1ab0 ++#define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 ++#define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0 ++#define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0 ++#define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0 ++#define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0 ++#define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0 ++#define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 ++#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 ++#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1 ++#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1 ++#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 ++#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1 ++#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1 ++#define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 ++#define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 ++#define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2 ++#define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2 ++#define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2 ++#define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2 ++#define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2 ++#define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 ++#define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 ++#define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3 ++#define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3 ++#define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3 ++#define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3 ++#define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3 ++#define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 ++#define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 ++#define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4 ++#define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4 ++#define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4 ++#define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4 ++#define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4 ++#define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 ++#define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 ++#define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5 ++#define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5 ++#define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5 ++#define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5 ++#define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5 ++#define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 ++#define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 ++#define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6 ++#define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6 ++#define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6 ++#define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6 ++#define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6 ++#define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 ++#define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 ++#define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7 ++#define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7 ++#define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7 ++#define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7 ++#define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7 ++#define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 ++#define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 ++#define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8 ++#define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8 ++#define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8 ++#define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8 ++#define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8 ++#define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 ++#define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 ++#define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9 ++#define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9 ++#define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9 ++#define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9 ++#define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9 ++#define mmREGAMMA_CNTLB_REGION_12_13 0x1aba ++#define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba ++#define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba ++#define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba ++#define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba ++#define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba ++#define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba ++#define mmREGAMMA_CNTLB_REGION_14_15 0x1abb ++#define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb ++#define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb ++#define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb ++#define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb ++#define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb ++#define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb ++#define mmALPHA_CONTROL 0x1abc ++#define mmDCP0_ALPHA_CONTROL 0x1abc ++#define mmDCP1_ALPHA_CONTROL 0x1cbc ++#define mmDCP2_ALPHA_CONTROL 0x1ebc ++#define mmDCP3_ALPHA_CONTROL 0x40bc ++#define mmDCP4_ALPHA_CONTROL 0x42bc ++#define mmDCP5_ALPHA_CONTROL 0x44bc ++#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd ++#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd ++#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd ++#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd ++#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd ++#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd ++#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd ++#define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe ++#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe ++#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe ++#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe ++#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be ++#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be ++#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be ++#define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf ++#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf ++#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf ++#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf ++#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf ++#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf ++#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf ++#define mmGRPH_SURFACE_COUNTER_CONTROL 0x1a0f ++#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x1a0f ++#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x1c0f ++#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x1e0f ++#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x400f ++#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x420f ++#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x440f ++#define mmGRPH_SURFACE_COUNTER_OUTPUT 0x1a1d ++#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x1a1d ++#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x1c1d ++#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x1e1d ++#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x401d ++#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x421d ++#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x441d ++#define mmDIG_FE_CNTL 0x4a00 ++#define mmDIG0_DIG_FE_CNTL 0x4a00 ++#define mmDIG1_DIG_FE_CNTL 0x4b00 ++#define mmDIG2_DIG_FE_CNTL 0x4c00 ++#define mmDIG3_DIG_FE_CNTL 0x4d00 ++#define mmDIG4_DIG_FE_CNTL 0x4e00 ++#define mmDIG5_DIG_FE_CNTL 0x4f00 ++#define mmDIG6_DIG_FE_CNTL 0x5400 ++#define mmDIG7_DIG_FE_CNTL 0x5600 ++#define mmDIG8_DIG_FE_CNTL 0x5700 ++#define mmDIG_OUTPUT_CRC_CNTL 0x4a01 ++#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01 ++#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01 ++#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01 ++#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01 ++#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01 ++#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01 ++#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401 ++#define mmDIG7_DIG_OUTPUT_CRC_CNTL 0x5601 ++#define mmDIG8_DIG_OUTPUT_CRC_CNTL 0x5701 ++#define mmDIG_OUTPUT_CRC_RESULT 0x4a02 ++#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02 ++#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02 ++#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02 ++#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02 ++#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02 ++#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02 ++#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402 ++#define mmDIG7_DIG_OUTPUT_CRC_RESULT 0x5602 ++#define mmDIG8_DIG_OUTPUT_CRC_RESULT 0x5702 ++#define mmDIG_CLOCK_PATTERN 0x4a03 ++#define mmDIG0_DIG_CLOCK_PATTERN 0x4a03 ++#define mmDIG1_DIG_CLOCK_PATTERN 0x4b03 ++#define mmDIG2_DIG_CLOCK_PATTERN 0x4c03 ++#define mmDIG3_DIG_CLOCK_PATTERN 0x4d03 ++#define mmDIG4_DIG_CLOCK_PATTERN 0x4e03 ++#define mmDIG5_DIG_CLOCK_PATTERN 0x4f03 ++#define mmDIG6_DIG_CLOCK_PATTERN 0x5403 ++#define mmDIG7_DIG_CLOCK_PATTERN 0x5603 ++#define mmDIG8_DIG_CLOCK_PATTERN 0x5703 ++#define mmDIG_TEST_PATTERN 0x4a04 ++#define mmDIG0_DIG_TEST_PATTERN 0x4a04 ++#define mmDIG1_DIG_TEST_PATTERN 0x4b04 ++#define mmDIG2_DIG_TEST_PATTERN 0x4c04 ++#define mmDIG3_DIG_TEST_PATTERN 0x4d04 ++#define mmDIG4_DIG_TEST_PATTERN 0x4e04 ++#define mmDIG5_DIG_TEST_PATTERN 0x4f04 ++#define mmDIG6_DIG_TEST_PATTERN 0x5404 ++#define mmDIG7_DIG_TEST_PATTERN 0x5604 ++#define mmDIG8_DIG_TEST_PATTERN 0x5704 ++#define mmDIG_RANDOM_PATTERN_SEED 0x4a05 ++#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05 ++#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05 ++#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05 ++#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05 ++#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05 ++#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05 ++#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405 ++#define mmDIG7_DIG_RANDOM_PATTERN_SEED 0x5605 ++#define mmDIG8_DIG_RANDOM_PATTERN_SEED 0x5705 ++#define mmDIG_FIFO_STATUS 0x4a06 ++#define mmDIG0_DIG_FIFO_STATUS 0x4a06 ++#define mmDIG1_DIG_FIFO_STATUS 0x4b06 ++#define mmDIG2_DIG_FIFO_STATUS 0x4c06 ++#define mmDIG3_DIG_FIFO_STATUS 0x4d06 ++#define mmDIG4_DIG_FIFO_STATUS 0x4e06 ++#define mmDIG5_DIG_FIFO_STATUS 0x4f06 ++#define mmDIG6_DIG_FIFO_STATUS 0x5406 ++#define mmDIG7_DIG_FIFO_STATUS 0x5606 ++#define mmDIG8_DIG_FIFO_STATUS 0x5706 ++#define mmDIG_DISPCLK_SWITCH_CNTL 0x4a07 ++#define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07 ++#define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07 ++#define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07 ++#define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07 ++#define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07 ++#define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07 ++#define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407 ++#define mmDIG7_DIG_DISPCLK_SWITCH_CNTL 0x5607 ++#define mmDIG8_DIG_DISPCLK_SWITCH_CNTL 0x5707 ++#define mmDIG_DISPCLK_SWITCH_STATUS 0x4a08 ++#define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08 ++#define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08 ++#define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08 ++#define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08 ++#define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08 ++#define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08 ++#define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408 ++#define mmDIG7_DIG_DISPCLK_SWITCH_STATUS 0x5608 ++#define mmDIG8_DIG_DISPCLK_SWITCH_STATUS 0x5708 ++#define mmHDMI_CONTROL 0x4a09 ++#define mmDIG0_HDMI_CONTROL 0x4a09 ++#define mmDIG1_HDMI_CONTROL 0x4b09 ++#define mmDIG2_HDMI_CONTROL 0x4c09 ++#define mmDIG3_HDMI_CONTROL 0x4d09 ++#define mmDIG4_HDMI_CONTROL 0x4e09 ++#define mmDIG5_HDMI_CONTROL 0x4f09 ++#define mmDIG6_HDMI_CONTROL 0x5409 ++#define mmDIG7_HDMI_CONTROL 0x5609 ++#define mmDIG8_HDMI_CONTROL 0x5709 ++#define mmHDMI_STATUS 0x4a0a ++#define mmDIG0_HDMI_STATUS 0x4a0a ++#define mmDIG1_HDMI_STATUS 0x4b0a ++#define mmDIG2_HDMI_STATUS 0x4c0a ++#define mmDIG3_HDMI_STATUS 0x4d0a ++#define mmDIG4_HDMI_STATUS 0x4e0a ++#define mmDIG5_HDMI_STATUS 0x4f0a ++#define mmDIG6_HDMI_STATUS 0x540a ++#define mmDIG7_HDMI_STATUS 0x560a ++#define mmDIG8_HDMI_STATUS 0x570a ++#define mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b ++#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b ++#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b ++#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b ++#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b ++#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b ++#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b ++#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b ++#define mmDIG7_HDMI_AUDIO_PACKET_CONTROL 0x560b ++#define mmDIG8_HDMI_AUDIO_PACKET_CONTROL 0x570b ++#define mmHDMI_ACR_PACKET_CONTROL 0x4a0c ++#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c ++#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c ++#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c ++#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c ++#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c ++#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c ++#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c ++#define mmDIG7_HDMI_ACR_PACKET_CONTROL 0x560c ++#define mmDIG8_HDMI_ACR_PACKET_CONTROL 0x570c ++#define mmHDMI_VBI_PACKET_CONTROL 0x4a0d ++#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d ++#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d ++#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d ++#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d ++#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d ++#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d ++#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d ++#define mmDIG7_HDMI_VBI_PACKET_CONTROL 0x560d ++#define mmDIG8_HDMI_VBI_PACKET_CONTROL 0x570d ++#define mmHDMI_INFOFRAME_CONTROL0 0x4a0e ++#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e ++#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e ++#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e ++#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e ++#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e ++#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e ++#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e ++#define mmDIG7_HDMI_INFOFRAME_CONTROL0 0x560e ++#define mmDIG8_HDMI_INFOFRAME_CONTROL0 0x570e ++#define mmHDMI_INFOFRAME_CONTROL1 0x4a0f ++#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f ++#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f ++#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f ++#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f ++#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f ++#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f ++#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f ++#define mmDIG7_HDMI_INFOFRAME_CONTROL1 0x560f ++#define mmDIG8_HDMI_INFOFRAME_CONTROL1 0x570f ++#define mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10 ++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10 ++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10 ++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10 ++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10 ++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10 ++#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10 ++#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410 ++#define mmDIG7_HDMI_GENERIC_PACKET_CONTROL0 0x5610 ++#define mmDIG8_HDMI_GENERIC_PACKET_CONTROL0 0x5710 ++#define mmAFMT_INTERRUPT_STATUS 0x4a11 ++#define mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11 ++#define mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11 ++#define mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11 ++#define mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11 ++#define mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11 ++#define mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11 ++#define mmDIG6_AFMT_INTERRUPT_STATUS 0x5411 ++#define mmDIG7_AFMT_INTERRUPT_STATUS 0x5611 ++#define mmDIG8_AFMT_INTERRUPT_STATUS 0x5711 ++#define mmHDMI_GC 0x4a13 ++#define mmDIG0_HDMI_GC 0x4a13 ++#define mmDIG1_HDMI_GC 0x4b13 ++#define mmDIG2_HDMI_GC 0x4c13 ++#define mmDIG3_HDMI_GC 0x4d13 ++#define mmDIG4_HDMI_GC 0x4e13 ++#define mmDIG5_HDMI_GC 0x4f13 ++#define mmDIG6_HDMI_GC 0x5413 ++#define mmDIG7_HDMI_GC 0x5613 ++#define mmDIG8_HDMI_GC 0x5713 ++#define mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14 ++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14 ++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14 ++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14 ++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14 ++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14 ++#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14 ++#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414 ++#define mmDIG7_AFMT_AUDIO_PACKET_CONTROL2 0x5614 ++#define mmDIG8_AFMT_AUDIO_PACKET_CONTROL2 0x5714 ++#define mmAFMT_ISRC1_0 0x4a15 ++#define mmDIG0_AFMT_ISRC1_0 0x4a15 ++#define mmDIG1_AFMT_ISRC1_0 0x4b15 ++#define mmDIG2_AFMT_ISRC1_0 0x4c15 ++#define mmDIG3_AFMT_ISRC1_0 0x4d15 ++#define mmDIG4_AFMT_ISRC1_0 0x4e15 ++#define mmDIG5_AFMT_ISRC1_0 0x4f15 ++#define mmDIG6_AFMT_ISRC1_0 0x5415 ++#define mmDIG7_AFMT_ISRC1_0 0x5615 ++#define mmDIG8_AFMT_ISRC1_0 0x5715 ++#define mmAFMT_ISRC1_1 0x4a16 ++#define mmDIG0_AFMT_ISRC1_1 0x4a16 ++#define mmDIG1_AFMT_ISRC1_1 0x4b16 ++#define mmDIG2_AFMT_ISRC1_1 0x4c16 ++#define mmDIG3_AFMT_ISRC1_1 0x4d16 ++#define mmDIG4_AFMT_ISRC1_1 0x4e16 ++#define mmDIG5_AFMT_ISRC1_1 0x4f16 ++#define mmDIG6_AFMT_ISRC1_1 0x5416 ++#define mmDIG7_AFMT_ISRC1_1 0x5616 ++#define mmDIG8_AFMT_ISRC1_1 0x5716 ++#define mmAFMT_ISRC1_2 0x4a17 ++#define mmDIG0_AFMT_ISRC1_2 0x4a17 ++#define mmDIG1_AFMT_ISRC1_2 0x4b17 ++#define mmDIG2_AFMT_ISRC1_2 0x4c17 ++#define mmDIG3_AFMT_ISRC1_2 0x4d17 ++#define mmDIG4_AFMT_ISRC1_2 0x4e17 ++#define mmDIG5_AFMT_ISRC1_2 0x4f17 ++#define mmDIG6_AFMT_ISRC1_2 0x5417 ++#define mmDIG7_AFMT_ISRC1_2 0x5617 ++#define mmDIG8_AFMT_ISRC1_2 0x5717 ++#define mmAFMT_ISRC1_3 0x4a18 ++#define mmDIG0_AFMT_ISRC1_3 0x4a18 ++#define mmDIG1_AFMT_ISRC1_3 0x4b18 ++#define mmDIG2_AFMT_ISRC1_3 0x4c18 ++#define mmDIG3_AFMT_ISRC1_3 0x4d18 ++#define mmDIG4_AFMT_ISRC1_3 0x4e18 ++#define mmDIG5_AFMT_ISRC1_3 0x4f18 ++#define mmDIG6_AFMT_ISRC1_3 0x5418 ++#define mmDIG7_AFMT_ISRC1_3 0x5618 ++#define mmDIG8_AFMT_ISRC1_3 0x5718 ++#define mmAFMT_ISRC1_4 0x4a19 ++#define mmDIG0_AFMT_ISRC1_4 0x4a19 ++#define mmDIG1_AFMT_ISRC1_4 0x4b19 ++#define mmDIG2_AFMT_ISRC1_4 0x4c19 ++#define mmDIG3_AFMT_ISRC1_4 0x4d19 ++#define mmDIG4_AFMT_ISRC1_4 0x4e19 ++#define mmDIG5_AFMT_ISRC1_4 0x4f19 ++#define mmDIG6_AFMT_ISRC1_4 0x5419 ++#define mmDIG7_AFMT_ISRC1_4 0x5619 ++#define mmDIG8_AFMT_ISRC1_4 0x5719 ++#define mmAFMT_ISRC2_0 0x4a1a ++#define mmDIG0_AFMT_ISRC2_0 0x4a1a ++#define mmDIG1_AFMT_ISRC2_0 0x4b1a ++#define mmDIG2_AFMT_ISRC2_0 0x4c1a ++#define mmDIG3_AFMT_ISRC2_0 0x4d1a ++#define mmDIG4_AFMT_ISRC2_0 0x4e1a ++#define mmDIG5_AFMT_ISRC2_0 0x4f1a ++#define mmDIG6_AFMT_ISRC2_0 0x541a ++#define mmDIG7_AFMT_ISRC2_0 0x561a ++#define mmDIG8_AFMT_ISRC2_0 0x571a ++#define mmAFMT_ISRC2_1 0x4a1b ++#define mmDIG0_AFMT_ISRC2_1 0x4a1b ++#define mmDIG1_AFMT_ISRC2_1 0x4b1b ++#define mmDIG2_AFMT_ISRC2_1 0x4c1b ++#define mmDIG3_AFMT_ISRC2_1 0x4d1b ++#define mmDIG4_AFMT_ISRC2_1 0x4e1b ++#define mmDIG5_AFMT_ISRC2_1 0x4f1b ++#define mmDIG6_AFMT_ISRC2_1 0x541b ++#define mmDIG7_AFMT_ISRC2_1 0x561b ++#define mmDIG8_AFMT_ISRC2_1 0x571b ++#define mmAFMT_ISRC2_2 0x4a1c ++#define mmDIG0_AFMT_ISRC2_2 0x4a1c ++#define mmDIG1_AFMT_ISRC2_2 0x4b1c ++#define mmDIG2_AFMT_ISRC2_2 0x4c1c ++#define mmDIG3_AFMT_ISRC2_2 0x4d1c ++#define mmDIG4_AFMT_ISRC2_2 0x4e1c ++#define mmDIG5_AFMT_ISRC2_2 0x4f1c ++#define mmDIG6_AFMT_ISRC2_2 0x541c ++#define mmDIG7_AFMT_ISRC2_2 0x561c ++#define mmDIG8_AFMT_ISRC2_2 0x571c ++#define mmAFMT_ISRC2_3 0x4a1d ++#define mmDIG0_AFMT_ISRC2_3 0x4a1d ++#define mmDIG1_AFMT_ISRC2_3 0x4b1d ++#define mmDIG2_AFMT_ISRC2_3 0x4c1d ++#define mmDIG3_AFMT_ISRC2_3 0x4d1d ++#define mmDIG4_AFMT_ISRC2_3 0x4e1d ++#define mmDIG5_AFMT_ISRC2_3 0x4f1d ++#define mmDIG6_AFMT_ISRC2_3 0x541d ++#define mmDIG7_AFMT_ISRC2_3 0x561d ++#define mmDIG8_AFMT_ISRC2_3 0x571d ++#define mmAFMT_AVI_INFO0 0x4a1e ++#define mmDIG0_AFMT_AVI_INFO0 0x4a1e ++#define mmDIG1_AFMT_AVI_INFO0 0x4b1e ++#define mmDIG2_AFMT_AVI_INFO0 0x4c1e ++#define mmDIG3_AFMT_AVI_INFO0 0x4d1e ++#define mmDIG4_AFMT_AVI_INFO0 0x4e1e ++#define mmDIG5_AFMT_AVI_INFO0 0x4f1e ++#define mmDIG6_AFMT_AVI_INFO0 0x541e ++#define mmDIG7_AFMT_AVI_INFO0 0x561e ++#define mmDIG8_AFMT_AVI_INFO0 0x571e ++#define mmAFMT_AVI_INFO1 0x4a1f ++#define mmDIG0_AFMT_AVI_INFO1 0x4a1f ++#define mmDIG1_AFMT_AVI_INFO1 0x4b1f ++#define mmDIG2_AFMT_AVI_INFO1 0x4c1f ++#define mmDIG3_AFMT_AVI_INFO1 0x4d1f ++#define mmDIG4_AFMT_AVI_INFO1 0x4e1f ++#define mmDIG5_AFMT_AVI_INFO1 0x4f1f ++#define mmDIG6_AFMT_AVI_INFO1 0x541f ++#define mmDIG7_AFMT_AVI_INFO1 0x561f ++#define mmDIG8_AFMT_AVI_INFO1 0x571f ++#define mmAFMT_AVI_INFO2 0x4a20 ++#define mmDIG0_AFMT_AVI_INFO2 0x4a20 ++#define mmDIG1_AFMT_AVI_INFO2 0x4b20 ++#define mmDIG2_AFMT_AVI_INFO2 0x4c20 ++#define mmDIG3_AFMT_AVI_INFO2 0x4d20 ++#define mmDIG4_AFMT_AVI_INFO2 0x4e20 ++#define mmDIG5_AFMT_AVI_INFO2 0x4f20 ++#define mmDIG6_AFMT_AVI_INFO2 0x5420 ++#define mmDIG7_AFMT_AVI_INFO2 0x5620 ++#define mmDIG8_AFMT_AVI_INFO2 0x5720 ++#define mmAFMT_AVI_INFO3 0x4a21 ++#define mmDIG0_AFMT_AVI_INFO3 0x4a21 ++#define mmDIG1_AFMT_AVI_INFO3 0x4b21 ++#define mmDIG2_AFMT_AVI_INFO3 0x4c21 ++#define mmDIG3_AFMT_AVI_INFO3 0x4d21 ++#define mmDIG4_AFMT_AVI_INFO3 0x4e21 ++#define mmDIG5_AFMT_AVI_INFO3 0x4f21 ++#define mmDIG6_AFMT_AVI_INFO3 0x5421 ++#define mmDIG7_AFMT_AVI_INFO3 0x5621 ++#define mmDIG8_AFMT_AVI_INFO3 0x5721 ++#define mmAFMT_MPEG_INFO0 0x4a22 ++#define mmDIG0_AFMT_MPEG_INFO0 0x4a22 ++#define mmDIG1_AFMT_MPEG_INFO0 0x4b22 ++#define mmDIG2_AFMT_MPEG_INFO0 0x4c22 ++#define mmDIG3_AFMT_MPEG_INFO0 0x4d22 ++#define mmDIG4_AFMT_MPEG_INFO0 0x4e22 ++#define mmDIG5_AFMT_MPEG_INFO0 0x4f22 ++#define mmDIG6_AFMT_MPEG_INFO0 0x5422 ++#define mmDIG7_AFMT_MPEG_INFO0 0x5622 ++#define mmDIG8_AFMT_MPEG_INFO0 0x5722 ++#define mmAFMT_MPEG_INFO1 0x4a23 ++#define mmDIG0_AFMT_MPEG_INFO1 0x4a23 ++#define mmDIG1_AFMT_MPEG_INFO1 0x4b23 ++#define mmDIG2_AFMT_MPEG_INFO1 0x4c23 ++#define mmDIG3_AFMT_MPEG_INFO1 0x4d23 ++#define mmDIG4_AFMT_MPEG_INFO1 0x4e23 ++#define mmDIG5_AFMT_MPEG_INFO1 0x4f23 ++#define mmDIG6_AFMT_MPEG_INFO1 0x5423 ++#define mmDIG7_AFMT_MPEG_INFO1 0x5623 ++#define mmDIG8_AFMT_MPEG_INFO1 0x5723 ++#define mmAFMT_GENERIC_HDR 0x4a24 ++#define mmDIG0_AFMT_GENERIC_HDR 0x4a24 ++#define mmDIG1_AFMT_GENERIC_HDR 0x4b24 ++#define mmDIG2_AFMT_GENERIC_HDR 0x4c24 ++#define mmDIG3_AFMT_GENERIC_HDR 0x4d24 ++#define mmDIG4_AFMT_GENERIC_HDR 0x4e24 ++#define mmDIG5_AFMT_GENERIC_HDR 0x4f24 ++#define mmDIG6_AFMT_GENERIC_HDR 0x5424 ++#define mmDIG7_AFMT_GENERIC_HDR 0x5624 ++#define mmDIG8_AFMT_GENERIC_HDR 0x5724 ++#define mmAFMT_GENERIC_0 0x4a25 ++#define mmDIG0_AFMT_GENERIC_0 0x4a25 ++#define mmDIG1_AFMT_GENERIC_0 0x4b25 ++#define mmDIG2_AFMT_GENERIC_0 0x4c25 ++#define mmDIG3_AFMT_GENERIC_0 0x4d25 ++#define mmDIG4_AFMT_GENERIC_0 0x4e25 ++#define mmDIG5_AFMT_GENERIC_0 0x4f25 ++#define mmDIG6_AFMT_GENERIC_0 0x5425 ++#define mmDIG7_AFMT_GENERIC_0 0x5625 ++#define mmDIG8_AFMT_GENERIC_0 0x5725 ++#define mmAFMT_GENERIC_1 0x4a26 ++#define mmDIG0_AFMT_GENERIC_1 0x4a26 ++#define mmDIG1_AFMT_GENERIC_1 0x4b26 ++#define mmDIG2_AFMT_GENERIC_1 0x4c26 ++#define mmDIG3_AFMT_GENERIC_1 0x4d26 ++#define mmDIG4_AFMT_GENERIC_1 0x4e26 ++#define mmDIG5_AFMT_GENERIC_1 0x4f26 ++#define mmDIG6_AFMT_GENERIC_1 0x5426 ++#define mmDIG7_AFMT_GENERIC_1 0x5626 ++#define mmDIG8_AFMT_GENERIC_1 0x5726 ++#define mmAFMT_GENERIC_2 0x4a27 ++#define mmDIG0_AFMT_GENERIC_2 0x4a27 ++#define mmDIG1_AFMT_GENERIC_2 0x4b27 ++#define mmDIG2_AFMT_GENERIC_2 0x4c27 ++#define mmDIG3_AFMT_GENERIC_2 0x4d27 ++#define mmDIG4_AFMT_GENERIC_2 0x4e27 ++#define mmDIG5_AFMT_GENERIC_2 0x4f27 ++#define mmDIG6_AFMT_GENERIC_2 0x5427 ++#define mmDIG7_AFMT_GENERIC_2 0x5627 ++#define mmDIG8_AFMT_GENERIC_2 0x5727 ++#define mmAFMT_GENERIC_3 0x4a28 ++#define mmDIG0_AFMT_GENERIC_3 0x4a28 ++#define mmDIG1_AFMT_GENERIC_3 0x4b28 ++#define mmDIG2_AFMT_GENERIC_3 0x4c28 ++#define mmDIG3_AFMT_GENERIC_3 0x4d28 ++#define mmDIG4_AFMT_GENERIC_3 0x4e28 ++#define mmDIG5_AFMT_GENERIC_3 0x4f28 ++#define mmDIG6_AFMT_GENERIC_3 0x5428 ++#define mmDIG7_AFMT_GENERIC_3 0x5628 ++#define mmDIG8_AFMT_GENERIC_3 0x5728 ++#define mmAFMT_GENERIC_4 0x4a29 ++#define mmDIG0_AFMT_GENERIC_4 0x4a29 ++#define mmDIG1_AFMT_GENERIC_4 0x4b29 ++#define mmDIG2_AFMT_GENERIC_4 0x4c29 ++#define mmDIG3_AFMT_GENERIC_4 0x4d29 ++#define mmDIG4_AFMT_GENERIC_4 0x4e29 ++#define mmDIG5_AFMT_GENERIC_4 0x4f29 ++#define mmDIG6_AFMT_GENERIC_4 0x5429 ++#define mmDIG7_AFMT_GENERIC_4 0x5629 ++#define mmDIG8_AFMT_GENERIC_4 0x5729 ++#define mmAFMT_GENERIC_5 0x4a2a ++#define mmDIG0_AFMT_GENERIC_5 0x4a2a ++#define mmDIG1_AFMT_GENERIC_5 0x4b2a ++#define mmDIG2_AFMT_GENERIC_5 0x4c2a ++#define mmDIG3_AFMT_GENERIC_5 0x4d2a ++#define mmDIG4_AFMT_GENERIC_5 0x4e2a ++#define mmDIG5_AFMT_GENERIC_5 0x4f2a ++#define mmDIG6_AFMT_GENERIC_5 0x542a ++#define mmDIG7_AFMT_GENERIC_5 0x562a ++#define mmDIG8_AFMT_GENERIC_5 0x572a ++#define mmAFMT_GENERIC_6 0x4a2b ++#define mmDIG0_AFMT_GENERIC_6 0x4a2b ++#define mmDIG1_AFMT_GENERIC_6 0x4b2b ++#define mmDIG2_AFMT_GENERIC_6 0x4c2b ++#define mmDIG3_AFMT_GENERIC_6 0x4d2b ++#define mmDIG4_AFMT_GENERIC_6 0x4e2b ++#define mmDIG5_AFMT_GENERIC_6 0x4f2b ++#define mmDIG6_AFMT_GENERIC_6 0x542b ++#define mmDIG7_AFMT_GENERIC_6 0x562b ++#define mmDIG8_AFMT_GENERIC_6 0x572b ++#define mmAFMT_GENERIC_7 0x4a2c ++#define mmDIG0_AFMT_GENERIC_7 0x4a2c ++#define mmDIG1_AFMT_GENERIC_7 0x4b2c ++#define mmDIG2_AFMT_GENERIC_7 0x4c2c ++#define mmDIG3_AFMT_GENERIC_7 0x4d2c ++#define mmDIG4_AFMT_GENERIC_7 0x4e2c ++#define mmDIG5_AFMT_GENERIC_7 0x4f2c ++#define mmDIG6_AFMT_GENERIC_7 0x542c ++#define mmDIG7_AFMT_GENERIC_7 0x562c ++#define mmDIG8_AFMT_GENERIC_7 0x572c ++#define mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d ++#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d ++#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d ++#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d ++#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d ++#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d ++#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d ++#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d ++#define mmDIG7_HDMI_GENERIC_PACKET_CONTROL1 0x562d ++#define mmDIG8_HDMI_GENERIC_PACKET_CONTROL1 0x572d ++#define mmHDMI_ACR_32_0 0x4a2e ++#define mmDIG0_HDMI_ACR_32_0 0x4a2e ++#define mmDIG1_HDMI_ACR_32_0 0x4b2e ++#define mmDIG2_HDMI_ACR_32_0 0x4c2e ++#define mmDIG3_HDMI_ACR_32_0 0x4d2e ++#define mmDIG4_HDMI_ACR_32_0 0x4e2e ++#define mmDIG5_HDMI_ACR_32_0 0x4f2e ++#define mmDIG6_HDMI_ACR_32_0 0x542e ++#define mmDIG7_HDMI_ACR_32_0 0x562e ++#define mmDIG8_HDMI_ACR_32_0 0x572e ++#define mmHDMI_ACR_32_1 0x4a2f ++#define mmDIG0_HDMI_ACR_32_1 0x4a2f ++#define mmDIG1_HDMI_ACR_32_1 0x4b2f ++#define mmDIG2_HDMI_ACR_32_1 0x4c2f ++#define mmDIG3_HDMI_ACR_32_1 0x4d2f ++#define mmDIG4_HDMI_ACR_32_1 0x4e2f ++#define mmDIG5_HDMI_ACR_32_1 0x4f2f ++#define mmDIG6_HDMI_ACR_32_1 0x542f ++#define mmDIG7_HDMI_ACR_32_1 0x562f ++#define mmDIG8_HDMI_ACR_32_1 0x572f ++#define mmHDMI_ACR_44_0 0x4a30 ++#define mmDIG0_HDMI_ACR_44_0 0x4a30 ++#define mmDIG1_HDMI_ACR_44_0 0x4b30 ++#define mmDIG2_HDMI_ACR_44_0 0x4c30 ++#define mmDIG3_HDMI_ACR_44_0 0x4d30 ++#define mmDIG4_HDMI_ACR_44_0 0x4e30 ++#define mmDIG5_HDMI_ACR_44_0 0x4f30 ++#define mmDIG6_HDMI_ACR_44_0 0x5430 ++#define mmDIG7_HDMI_ACR_44_0 0x5630 ++#define mmDIG8_HDMI_ACR_44_0 0x5730 ++#define mmHDMI_ACR_44_1 0x4a31 ++#define mmDIG0_HDMI_ACR_44_1 0x4a31 ++#define mmDIG1_HDMI_ACR_44_1 0x4b31 ++#define mmDIG2_HDMI_ACR_44_1 0x4c31 ++#define mmDIG3_HDMI_ACR_44_1 0x4d31 ++#define mmDIG4_HDMI_ACR_44_1 0x4e31 ++#define mmDIG5_HDMI_ACR_44_1 0x4f31 ++#define mmDIG6_HDMI_ACR_44_1 0x5431 ++#define mmDIG7_HDMI_ACR_44_1 0x5631 ++#define mmDIG8_HDMI_ACR_44_1 0x5731 ++#define mmHDMI_ACR_48_0 0x4a32 ++#define mmDIG0_HDMI_ACR_48_0 0x4a32 ++#define mmDIG1_HDMI_ACR_48_0 0x4b32 ++#define mmDIG2_HDMI_ACR_48_0 0x4c32 ++#define mmDIG3_HDMI_ACR_48_0 0x4d32 ++#define mmDIG4_HDMI_ACR_48_0 0x4e32 ++#define mmDIG5_HDMI_ACR_48_0 0x4f32 ++#define mmDIG6_HDMI_ACR_48_0 0x5432 ++#define mmDIG7_HDMI_ACR_48_0 0x5632 ++#define mmDIG8_HDMI_ACR_48_0 0x5732 ++#define mmHDMI_ACR_48_1 0x4a33 ++#define mmDIG0_HDMI_ACR_48_1 0x4a33 ++#define mmDIG1_HDMI_ACR_48_1 0x4b33 ++#define mmDIG2_HDMI_ACR_48_1 0x4c33 ++#define mmDIG3_HDMI_ACR_48_1 0x4d33 ++#define mmDIG4_HDMI_ACR_48_1 0x4e33 ++#define mmDIG5_HDMI_ACR_48_1 0x4f33 ++#define mmDIG6_HDMI_ACR_48_1 0x5433 ++#define mmDIG7_HDMI_ACR_48_1 0x5633 ++#define mmDIG8_HDMI_ACR_48_1 0x5733 ++#define mmHDMI_ACR_STATUS_0 0x4a34 ++#define mmDIG0_HDMI_ACR_STATUS_0 0x4a34 ++#define mmDIG1_HDMI_ACR_STATUS_0 0x4b34 ++#define mmDIG2_HDMI_ACR_STATUS_0 0x4c34 ++#define mmDIG3_HDMI_ACR_STATUS_0 0x4d34 ++#define mmDIG4_HDMI_ACR_STATUS_0 0x4e34 ++#define mmDIG5_HDMI_ACR_STATUS_0 0x4f34 ++#define mmDIG6_HDMI_ACR_STATUS_0 0x5434 ++#define mmDIG7_HDMI_ACR_STATUS_0 0x5634 ++#define mmDIG8_HDMI_ACR_STATUS_0 0x5734 ++#define mmHDMI_ACR_STATUS_1 0x4a35 ++#define mmDIG0_HDMI_ACR_STATUS_1 0x4a35 ++#define mmDIG1_HDMI_ACR_STATUS_1 0x4b35 ++#define mmDIG2_HDMI_ACR_STATUS_1 0x4c35 ++#define mmDIG3_HDMI_ACR_STATUS_1 0x4d35 ++#define mmDIG4_HDMI_ACR_STATUS_1 0x4e35 ++#define mmDIG5_HDMI_ACR_STATUS_1 0x4f35 ++#define mmDIG6_HDMI_ACR_STATUS_1 0x5435 ++#define mmDIG7_HDMI_ACR_STATUS_1 0x5635 ++#define mmDIG8_HDMI_ACR_STATUS_1 0x5735 ++#define mmAFMT_AUDIO_INFO0 0x4a36 ++#define mmDIG0_AFMT_AUDIO_INFO0 0x4a36 ++#define mmDIG1_AFMT_AUDIO_INFO0 0x4b36 ++#define mmDIG2_AFMT_AUDIO_INFO0 0x4c36 ++#define mmDIG3_AFMT_AUDIO_INFO0 0x4d36 ++#define mmDIG4_AFMT_AUDIO_INFO0 0x4e36 ++#define mmDIG5_AFMT_AUDIO_INFO0 0x4f36 ++#define mmDIG6_AFMT_AUDIO_INFO0 0x5436 ++#define mmDIG7_AFMT_AUDIO_INFO0 0x5636 ++#define mmDIG8_AFMT_AUDIO_INFO0 0x5736 ++#define mmAFMT_AUDIO_INFO1 0x4a37 ++#define mmDIG0_AFMT_AUDIO_INFO1 0x4a37 ++#define mmDIG1_AFMT_AUDIO_INFO1 0x4b37 ++#define mmDIG2_AFMT_AUDIO_INFO1 0x4c37 ++#define mmDIG3_AFMT_AUDIO_INFO1 0x4d37 ++#define mmDIG4_AFMT_AUDIO_INFO1 0x4e37 ++#define mmDIG5_AFMT_AUDIO_INFO1 0x4f37 ++#define mmDIG6_AFMT_AUDIO_INFO1 0x5437 ++#define mmDIG7_AFMT_AUDIO_INFO1 0x5637 ++#define mmDIG8_AFMT_AUDIO_INFO1 0x5737 ++#define mmAFMT_60958_0 0x4a38 ++#define mmDIG0_AFMT_60958_0 0x4a38 ++#define mmDIG1_AFMT_60958_0 0x4b38 ++#define mmDIG2_AFMT_60958_0 0x4c38 ++#define mmDIG3_AFMT_60958_0 0x4d38 ++#define mmDIG4_AFMT_60958_0 0x4e38 ++#define mmDIG5_AFMT_60958_0 0x4f38 ++#define mmDIG6_AFMT_60958_0 0x5438 ++#define mmDIG7_AFMT_60958_0 0x5638 ++#define mmDIG8_AFMT_60958_0 0x5738 ++#define mmAFMT_60958_1 0x4a39 ++#define mmDIG0_AFMT_60958_1 0x4a39 ++#define mmDIG1_AFMT_60958_1 0x4b39 ++#define mmDIG2_AFMT_60958_1 0x4c39 ++#define mmDIG3_AFMT_60958_1 0x4d39 ++#define mmDIG4_AFMT_60958_1 0x4e39 ++#define mmDIG5_AFMT_60958_1 0x4f39 ++#define mmDIG6_AFMT_60958_1 0x5439 ++#define mmDIG7_AFMT_60958_1 0x5639 ++#define mmDIG8_AFMT_60958_1 0x5739 ++#define mmAFMT_AUDIO_CRC_CONTROL 0x4a3a ++#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a ++#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a ++#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a ++#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a ++#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a ++#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a ++#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a ++#define mmDIG7_AFMT_AUDIO_CRC_CONTROL 0x563a ++#define mmDIG8_AFMT_AUDIO_CRC_CONTROL 0x573a ++#define mmAFMT_RAMP_CONTROL0 0x4a3b ++#define mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b ++#define mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b ++#define mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b ++#define mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b ++#define mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b ++#define mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b ++#define mmDIG6_AFMT_RAMP_CONTROL0 0x543b ++#define mmDIG7_AFMT_RAMP_CONTROL0 0x563b ++#define mmDIG8_AFMT_RAMP_CONTROL0 0x573b ++#define mmAFMT_RAMP_CONTROL1 0x4a3c ++#define mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c ++#define mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c ++#define mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c ++#define mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c ++#define mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c ++#define mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c ++#define mmDIG6_AFMT_RAMP_CONTROL1 0x543c ++#define mmDIG7_AFMT_RAMP_CONTROL1 0x563c ++#define mmDIG8_AFMT_RAMP_CONTROL1 0x573c ++#define mmAFMT_RAMP_CONTROL2 0x4a3d ++#define mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d ++#define mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d ++#define mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d ++#define mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d ++#define mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d ++#define mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d ++#define mmDIG6_AFMT_RAMP_CONTROL2 0x543d ++#define mmDIG7_AFMT_RAMP_CONTROL2 0x563d ++#define mmDIG8_AFMT_RAMP_CONTROL2 0x573d ++#define mmAFMT_RAMP_CONTROL3 0x4a3e ++#define mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e ++#define mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e ++#define mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e ++#define mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e ++#define mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e ++#define mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e ++#define mmDIG6_AFMT_RAMP_CONTROL3 0x543e ++#define mmDIG7_AFMT_RAMP_CONTROL3 0x563e ++#define mmDIG8_AFMT_RAMP_CONTROL3 0x573e ++#define mmAFMT_60958_2 0x4a3f ++#define mmDIG0_AFMT_60958_2 0x4a3f ++#define mmDIG1_AFMT_60958_2 0x4b3f ++#define mmDIG2_AFMT_60958_2 0x4c3f ++#define mmDIG3_AFMT_60958_2 0x4d3f ++#define mmDIG4_AFMT_60958_2 0x4e3f ++#define mmDIG5_AFMT_60958_2 0x4f3f ++#define mmDIG6_AFMT_60958_2 0x543f ++#define mmDIG7_AFMT_60958_2 0x563f ++#define mmDIG8_AFMT_60958_2 0x573f ++#define mmAFMT_AUDIO_CRC_RESULT 0x4a40 ++#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40 ++#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40 ++#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40 ++#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40 ++#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40 ++#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40 ++#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440 ++#define mmDIG7_AFMT_AUDIO_CRC_RESULT 0x5640 ++#define mmDIG8_AFMT_AUDIO_CRC_RESULT 0x5740 ++#define mmAFMT_STATUS 0x4a41 ++#define mmDIG0_AFMT_STATUS 0x4a41 ++#define mmDIG1_AFMT_STATUS 0x4b41 ++#define mmDIG2_AFMT_STATUS 0x4c41 ++#define mmDIG3_AFMT_STATUS 0x4d41 ++#define mmDIG4_AFMT_STATUS 0x4e41 ++#define mmDIG5_AFMT_STATUS 0x4f41 ++#define mmDIG6_AFMT_STATUS 0x5441 ++#define mmDIG7_AFMT_STATUS 0x5641 ++#define mmDIG8_AFMT_STATUS 0x5741 ++#define mmAFMT_AUDIO_PACKET_CONTROL 0x4a42 ++#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42 ++#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42 ++#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42 ++#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42 ++#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42 ++#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42 ++#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442 ++#define mmDIG7_AFMT_AUDIO_PACKET_CONTROL 0x5642 ++#define mmDIG8_AFMT_AUDIO_PACKET_CONTROL 0x5742 ++#define mmAFMT_VBI_PACKET_CONTROL 0x4a43 ++#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43 ++#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43 ++#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43 ++#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43 ++#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43 ++#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43 ++#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443 ++#define mmDIG7_AFMT_VBI_PACKET_CONTROL 0x5643 ++#define mmDIG8_AFMT_VBI_PACKET_CONTROL 0x5743 ++#define mmAFMT_INFOFRAME_CONTROL0 0x4a44 ++#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44 ++#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44 ++#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44 ++#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44 ++#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44 ++#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44 ++#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444 ++#define mmDIG7_AFMT_INFOFRAME_CONTROL0 0x5644 ++#define mmDIG8_AFMT_INFOFRAME_CONTROL0 0x5744 ++#define mmAFMT_AUDIO_SRC_CONTROL 0x4a45 ++#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45 ++#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45 ++#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45 ++#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45 ++#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45 ++#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45 ++#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445 ++#define mmDIG7_AFMT_AUDIO_SRC_CONTROL 0x5645 ++#define mmDIG8_AFMT_AUDIO_SRC_CONTROL 0x5745 ++#define mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46 ++#define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46 ++#define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46 ++#define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46 ++#define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46 ++#define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46 ++#define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46 ++#define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446 ++#define mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL 0x5646 ++#define mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL 0x5746 ++#define mmAFMT_CNTL 0x4a7e ++#define mmDIG0_AFMT_CNTL 0x4a7e ++#define mmDIG1_AFMT_CNTL 0x4b7e ++#define mmDIG2_AFMT_CNTL 0x4c7e ++#define mmDIG3_AFMT_CNTL 0x4d7e ++#define mmDIG4_AFMT_CNTL 0x4e7e ++#define mmDIG5_AFMT_CNTL 0x4f7e ++#define mmDIG6_AFMT_CNTL 0x547e ++#define mmDIG7_AFMT_CNTL 0x567e ++#define mmDIG8_AFMT_CNTL 0x577e ++#define mmDIG_BE_CNTL 0x4a47 ++#define mmDIG0_DIG_BE_CNTL 0x4a47 ++#define mmDIG1_DIG_BE_CNTL 0x4b47 ++#define mmDIG2_DIG_BE_CNTL 0x4c47 ++#define mmDIG3_DIG_BE_CNTL 0x4d47 ++#define mmDIG4_DIG_BE_CNTL 0x4e47 ++#define mmDIG5_DIG_BE_CNTL 0x4f47 ++#define mmDIG6_DIG_BE_CNTL 0x5447 ++#define mmDIG7_DIG_BE_CNTL 0x5647 ++#define mmDIG8_DIG_BE_CNTL 0x5747 ++#define mmDIG_BE_EN_CNTL 0x4a48 ++#define mmDIG0_DIG_BE_EN_CNTL 0x4a48 ++#define mmDIG1_DIG_BE_EN_CNTL 0x4b48 ++#define mmDIG2_DIG_BE_EN_CNTL 0x4c48 ++#define mmDIG3_DIG_BE_EN_CNTL 0x4d48 ++#define mmDIG4_DIG_BE_EN_CNTL 0x4e48 ++#define mmDIG5_DIG_BE_EN_CNTL 0x4f48 ++#define mmDIG6_DIG_BE_EN_CNTL 0x5448 ++#define mmDIG7_DIG_BE_EN_CNTL 0x5648 ++#define mmDIG8_DIG_BE_EN_CNTL 0x5748 ++#define mmTMDS_CNTL 0x4a6b ++#define mmDIG0_TMDS_CNTL 0x4a6b ++#define mmDIG1_TMDS_CNTL 0x4b6b ++#define mmDIG2_TMDS_CNTL 0x4c6b ++#define mmDIG3_TMDS_CNTL 0x4d6b ++#define mmDIG4_TMDS_CNTL 0x4e6b ++#define mmDIG5_TMDS_CNTL 0x4f6b ++#define mmDIG6_TMDS_CNTL 0x546b ++#define mmDIG7_TMDS_CNTL 0x566b ++#define mmDIG8_TMDS_CNTL 0x576b ++#define mmTMDS_CONTROL_CHAR 0x4a6c ++#define mmDIG0_TMDS_CONTROL_CHAR 0x4a6c ++#define mmDIG1_TMDS_CONTROL_CHAR 0x4b6c ++#define mmDIG2_TMDS_CONTROL_CHAR 0x4c6c ++#define mmDIG3_TMDS_CONTROL_CHAR 0x4d6c ++#define mmDIG4_TMDS_CONTROL_CHAR 0x4e6c ++#define mmDIG5_TMDS_CONTROL_CHAR 0x4f6c ++#define mmDIG6_TMDS_CONTROL_CHAR 0x546c ++#define mmDIG7_TMDS_CONTROL_CHAR 0x566c ++#define mmDIG8_TMDS_CONTROL_CHAR 0x576c ++#define mmTMDS_CONTROL0_FEEDBACK 0x4a6d ++#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d ++#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d ++#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d ++#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d ++#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d ++#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d ++#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d ++#define mmDIG7_TMDS_CONTROL0_FEEDBACK 0x566d ++#define mmDIG8_TMDS_CONTROL0_FEEDBACK 0x576d ++#define mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e ++#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e ++#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e ++#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e ++#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e ++#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e ++#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e ++#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e ++#define mmDIG7_TMDS_STEREOSYNC_CTL_SEL 0x566e ++#define mmDIG8_TMDS_STEREOSYNC_CTL_SEL 0x576e ++#define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f ++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f ++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f ++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f ++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f ++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f ++#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f ++#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f ++#define mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1 0x566f ++#define mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1 0x576f ++#define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 ++#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 ++#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70 ++#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70 ++#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70 ++#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70 ++#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70 ++#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470 ++#define mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3 0x5670 ++#define mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3 0x5770 ++#define mmTMDS_DEBUG 0x4a71 ++#define mmDIG0_TMDS_DEBUG 0x4a71 ++#define mmDIG1_TMDS_DEBUG 0x4b71 ++#define mmDIG2_TMDS_DEBUG 0x4c71 ++#define mmDIG3_TMDS_DEBUG 0x4d71 ++#define mmDIG4_TMDS_DEBUG 0x4e71 ++#define mmDIG5_TMDS_DEBUG 0x4f71 ++#define mmDIG6_TMDS_DEBUG 0x5471 ++#define mmDIG7_TMDS_DEBUG 0x5671 ++#define mmDIG8_TMDS_DEBUG 0x5771 ++#define mmTMDS_CTL_BITS 0x4a72 ++#define mmDIG0_TMDS_CTL_BITS 0x4a72 ++#define mmDIG1_TMDS_CTL_BITS 0x4b72 ++#define mmDIG2_TMDS_CTL_BITS 0x4c72 ++#define mmDIG3_TMDS_CTL_BITS 0x4d72 ++#define mmDIG4_TMDS_CTL_BITS 0x4e72 ++#define mmDIG5_TMDS_CTL_BITS 0x4f72 ++#define mmDIG6_TMDS_CTL_BITS 0x5472 ++#define mmDIG7_TMDS_CTL_BITS 0x5672 ++#define mmDIG8_TMDS_CTL_BITS 0x5772 ++#define mmTMDS_DCBALANCER_CONTROL 0x4a73 ++#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 ++#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 ++#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73 ++#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73 ++#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73 ++#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 ++#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473 ++#define mmDIG7_TMDS_DCBALANCER_CONTROL 0x5673 ++#define mmDIG8_TMDS_DCBALANCER_CONTROL 0x5773 ++#define mmTMDS_CTL0_1_GEN_CNTL 0x4a75 ++#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 ++#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75 ++#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75 ++#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75 ++#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75 ++#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75 ++#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475 ++#define mmDIG7_TMDS_CTL0_1_GEN_CNTL 0x5675 ++#define mmDIG8_TMDS_CTL0_1_GEN_CNTL 0x5775 ++#define mmTMDS_CTL2_3_GEN_CNTL 0x4a76 ++#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76 ++#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76 ++#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76 ++#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76 ++#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76 ++#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76 ++#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476 ++#define mmDIG7_TMDS_CTL2_3_GEN_CNTL 0x5676 ++#define mmDIG8_TMDS_CTL2_3_GEN_CNTL 0x5776 ++#define mmDIG_VERSION 0x4a78 ++#define mmDIG0_DIG_VERSION 0x4a78 ++#define mmDIG1_DIG_VERSION 0x4b78 ++#define mmDIG2_DIG_VERSION 0x4c78 ++#define mmDIG3_DIG_VERSION 0x4d78 ++#define mmDIG4_DIG_VERSION 0x4e78 ++#define mmDIG5_DIG_VERSION 0x4f78 ++#define mmDIG6_DIG_VERSION 0x5478 ++#define mmDIG7_DIG_VERSION 0x5678 ++#define mmDIG8_DIG_VERSION 0x5778 ++#define mmDIG_LANE_ENABLE 0x4a79 ++#define mmDIG0_DIG_LANE_ENABLE 0x4a79 ++#define mmDIG1_DIG_LANE_ENABLE 0x4b79 ++#define mmDIG2_DIG_LANE_ENABLE 0x4c79 ++#define mmDIG3_DIG_LANE_ENABLE 0x4d79 ++#define mmDIG4_DIG_LANE_ENABLE 0x4e79 ++#define mmDIG5_DIG_LANE_ENABLE 0x4f79 ++#define mmDIG6_DIG_LANE_ENABLE 0x5479 ++#define mmDIG7_DIG_LANE_ENABLE 0x5679 ++#define mmDIG8_DIG_LANE_ENABLE 0x5779 ++#define mmDIG_TEST_DEBUG_INDEX 0x4a7a ++#define mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a ++#define mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a ++#define mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a ++#define mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a ++#define mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a ++#define mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a ++#define mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a ++#define mmDIG7_DIG_TEST_DEBUG_INDEX 0x567a ++#define mmDIG8_DIG_TEST_DEBUG_INDEX 0x577a ++#define mmDIG_TEST_DEBUG_DATA 0x4a7b ++#define mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b ++#define mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b ++#define mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b ++#define mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b ++#define mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b ++#define mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b ++#define mmDIG6_DIG_TEST_DEBUG_DATA 0x547b ++#define mmDIG7_DIG_TEST_DEBUG_DATA 0x567b ++#define mmDIG8_DIG_TEST_DEBUG_DATA 0x577b ++#define mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c ++#define mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c ++#define mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c ++#define mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c ++#define mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c ++#define mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c ++#define mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c ++#define mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c ++#define mmDIG7_DIG_FE_TEST_DEBUG_INDEX 0x567c ++#define mmDIG8_DIG_FE_TEST_DEBUG_INDEX 0x577c ++#define mmDIG_FE_TEST_DEBUG_DATA 0x4a7d ++#define mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d ++#define mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d ++#define mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d ++#define mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d ++#define mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d ++#define mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d ++#define mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d ++#define mmDIG7_DIG_FE_TEST_DEBUG_DATA 0x567d ++#define mmDIG8_DIG_FE_TEST_DEBUG_DATA 0x577d ++#define mmDMCU_CTRL 0x1600 ++#define mmDMCU_STATUS 0x1601 ++#define mmDMCU_PC_START_ADDR 0x1602 ++#define mmDMCU_FW_START_ADDR 0x1603 ++#define mmDMCU_FW_END_ADDR 0x1604 ++#define mmDMCU_FW_ISR_START_ADDR 0x1605 ++#define mmDMCU_FW_CS_HI 0x1606 ++#define mmDMCU_FW_CS_LO 0x1607 ++#define mmDMCU_RAM_ACCESS_CTRL 0x1608 ++#define mmDMCU_ERAM_WR_CTRL 0x1609 ++#define mmDMCU_ERAM_WR_DATA 0x160a ++#define mmDMCU_ERAM_RD_CTRL 0x160b ++#define mmDMCU_ERAM_RD_DATA 0x160c ++#define mmDMCU_IRAM_WR_CTRL 0x160d ++#define mmDMCU_IRAM_WR_DATA 0x160e ++#define mmDMCU_IRAM_RD_CTRL 0x160f ++#define mmDMCU_IRAM_RD_DATA 0x1610 ++#define mmDMCU_EVENT_TRIGGER 0x1611 ++#define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 ++#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 ++#define mmDMCU_INTERRUPT_STATUS 0x1614 ++#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 ++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 ++#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x1631 ++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 ++#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x1632 ++#define mmDC_DMCU_SCRATCH 0x1618 ++#define mmDMCU_INT_CNT 0x1619 ++#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a ++#define mmDMCU_UC_CLK_GATING_CNTL 0x161b ++#define mmMASTER_COMM_DATA_REG1 0x161c ++#define mmMASTER_COMM_DATA_REG2 0x161d ++#define mmMASTER_COMM_DATA_REG3 0x161e ++#define mmMASTER_COMM_CMD_REG 0x161f ++#define mmMASTER_COMM_CNTL_REG 0x1620 ++#define mmSLAVE_COMM_DATA_REG1 0x1621 ++#define mmSLAVE_COMM_DATA_REG2 0x1622 ++#define mmSLAVE_COMM_DATA_REG3 0x1623 ++#define mmSLAVE_COMM_CMD_REG 0x1624 ++#define mmSLAVE_COMM_CNTL_REG 0x1625 ++#define mmDMCU_TEST_DEBUG_INDEX 0x1626 ++#define mmDMCU_TEST_DEBUG_DATA 0x1627 ++#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644 ++#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645 ++#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646 ++#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647 ++#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642 ++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674 ++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675 ++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676 ++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677 ++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643 ++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 ++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679 ++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a ++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b ++#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673 ++#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634 ++#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635 ++#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636 ++#define mmDP_LINK_CNTL 0x4aa0 ++#define mmDP0_DP_LINK_CNTL 0x4aa0 ++#define mmDP1_DP_LINK_CNTL 0x4ba0 ++#define mmDP2_DP_LINK_CNTL 0x4ca0 ++#define mmDP3_DP_LINK_CNTL 0x4da0 ++#define mmDP4_DP_LINK_CNTL 0x4ea0 ++#define mmDP5_DP_LINK_CNTL 0x4fa0 ++#define mmDP6_DP_LINK_CNTL 0x54a0 ++#define mmDP7_DP_LINK_CNTL 0x56a0 ++#define mmDP8_DP_LINK_CNTL 0x57a0 ++#define mmDP_PIXEL_FORMAT 0x4aa1 ++#define mmDP0_DP_PIXEL_FORMAT 0x4aa1 ++#define mmDP1_DP_PIXEL_FORMAT 0x4ba1 ++#define mmDP2_DP_PIXEL_FORMAT 0x4ca1 ++#define mmDP3_DP_PIXEL_FORMAT 0x4da1 ++#define mmDP4_DP_PIXEL_FORMAT 0x4ea1 ++#define mmDP5_DP_PIXEL_FORMAT 0x4fa1 ++#define mmDP6_DP_PIXEL_FORMAT 0x54a1 ++#define mmDP7_DP_PIXEL_FORMAT 0x56a1 ++#define mmDP8_DP_PIXEL_FORMAT 0x57a1 ++#define mmDP_MSA_COLORIMETRY 0x4aa2 ++#define mmDP0_DP_MSA_COLORIMETRY 0x4aa2 ++#define mmDP1_DP_MSA_COLORIMETRY 0x4ba2 ++#define mmDP2_DP_MSA_COLORIMETRY 0x4ca2 ++#define mmDP3_DP_MSA_COLORIMETRY 0x4da2 ++#define mmDP4_DP_MSA_COLORIMETRY 0x4ea2 ++#define mmDP5_DP_MSA_COLORIMETRY 0x4fa2 ++#define mmDP6_DP_MSA_COLORIMETRY 0x54a2 ++#define mmDP7_DP_MSA_COLORIMETRY 0x56a2 ++#define mmDP8_DP_MSA_COLORIMETRY 0x57a2 ++#define mmDP_CONFIG 0x4aa3 ++#define mmDP0_DP_CONFIG 0x4aa3 ++#define mmDP1_DP_CONFIG 0x4ba3 ++#define mmDP2_DP_CONFIG 0x4ca3 ++#define mmDP3_DP_CONFIG 0x4da3 ++#define mmDP4_DP_CONFIG 0x4ea3 ++#define mmDP5_DP_CONFIG 0x4fa3 ++#define mmDP6_DP_CONFIG 0x54a3 ++#define mmDP7_DP_CONFIG 0x56a3 ++#define mmDP8_DP_CONFIG 0x57a3 ++#define mmDP_VID_STREAM_CNTL 0x4aa4 ++#define mmDP0_DP_VID_STREAM_CNTL 0x4aa4 ++#define mmDP1_DP_VID_STREAM_CNTL 0x4ba4 ++#define mmDP2_DP_VID_STREAM_CNTL 0x4ca4 ++#define mmDP3_DP_VID_STREAM_CNTL 0x4da4 ++#define mmDP4_DP_VID_STREAM_CNTL 0x4ea4 ++#define mmDP5_DP_VID_STREAM_CNTL 0x4fa4 ++#define mmDP6_DP_VID_STREAM_CNTL 0x54a4 ++#define mmDP7_DP_VID_STREAM_CNTL 0x56a4 ++#define mmDP8_DP_VID_STREAM_CNTL 0x57a4 ++#define mmDP_STEER_FIFO 0x4aa5 ++#define mmDP0_DP_STEER_FIFO 0x4aa5 ++#define mmDP1_DP_STEER_FIFO 0x4ba5 ++#define mmDP2_DP_STEER_FIFO 0x4ca5 ++#define mmDP3_DP_STEER_FIFO 0x4da5 ++#define mmDP4_DP_STEER_FIFO 0x4ea5 ++#define mmDP5_DP_STEER_FIFO 0x4fa5 ++#define mmDP6_DP_STEER_FIFO 0x54a5 ++#define mmDP7_DP_STEER_FIFO 0x56a5 ++#define mmDP8_DP_STEER_FIFO 0x57a5 ++#define mmDP_MSA_MISC 0x4aa6 ++#define mmDP0_DP_MSA_MISC 0x4aa6 ++#define mmDP1_DP_MSA_MISC 0x4ba6 ++#define mmDP2_DP_MSA_MISC 0x4ca6 ++#define mmDP3_DP_MSA_MISC 0x4da6 ++#define mmDP4_DP_MSA_MISC 0x4ea6 ++#define mmDP5_DP_MSA_MISC 0x4fa6 ++#define mmDP6_DP_MSA_MISC 0x54a6 ++#define mmDP7_DP_MSA_MISC 0x56a6 ++#define mmDP8_DP_MSA_MISC 0x57a6 ++#define mmDP_VID_TIMING 0x4aa8 ++#define mmDP0_DP_VID_TIMING 0x4aa8 ++#define mmDP1_DP_VID_TIMING 0x4ba8 ++#define mmDP2_DP_VID_TIMING 0x4ca8 ++#define mmDP3_DP_VID_TIMING 0x4da8 ++#define mmDP4_DP_VID_TIMING 0x4ea8 ++#define mmDP5_DP_VID_TIMING 0x4fa8 ++#define mmDP6_DP_VID_TIMING 0x54a8 ++#define mmDP7_DP_VID_TIMING 0x56a8 ++#define mmDP8_DP_VID_TIMING 0x57a8 ++#define mmDP_VID_N 0x4aa9 ++#define mmDP0_DP_VID_N 0x4aa9 ++#define mmDP1_DP_VID_N 0x4ba9 ++#define mmDP2_DP_VID_N 0x4ca9 ++#define mmDP3_DP_VID_N 0x4da9 ++#define mmDP4_DP_VID_N 0x4ea9 ++#define mmDP5_DP_VID_N 0x4fa9 ++#define mmDP6_DP_VID_N 0x54a9 ++#define mmDP7_DP_VID_N 0x56a9 ++#define mmDP8_DP_VID_N 0x57a9 ++#define mmDP_VID_M 0x4aaa ++#define mmDP0_DP_VID_M 0x4aaa ++#define mmDP1_DP_VID_M 0x4baa ++#define mmDP2_DP_VID_M 0x4caa ++#define mmDP3_DP_VID_M 0x4daa ++#define mmDP4_DP_VID_M 0x4eaa ++#define mmDP5_DP_VID_M 0x4faa ++#define mmDP6_DP_VID_M 0x54aa ++#define mmDP7_DP_VID_M 0x56aa ++#define mmDP8_DP_VID_M 0x57aa ++#define mmDP_LINK_FRAMING_CNTL 0x4aab ++#define mmDP0_DP_LINK_FRAMING_CNTL 0x4aab ++#define mmDP1_DP_LINK_FRAMING_CNTL 0x4bab ++#define mmDP2_DP_LINK_FRAMING_CNTL 0x4cab ++#define mmDP3_DP_LINK_FRAMING_CNTL 0x4dab ++#define mmDP4_DP_LINK_FRAMING_CNTL 0x4eab ++#define mmDP5_DP_LINK_FRAMING_CNTL 0x4fab ++#define mmDP6_DP_LINK_FRAMING_CNTL 0x54ab ++#define mmDP7_DP_LINK_FRAMING_CNTL 0x56ab ++#define mmDP8_DP_LINK_FRAMING_CNTL 0x57ab ++#define mmDP_HBR2_EYE_PATTERN 0x4aac ++#define mmDP0_DP_HBR2_EYE_PATTERN 0x4aac ++#define mmDP1_DP_HBR2_EYE_PATTERN 0x4bac ++#define mmDP2_DP_HBR2_EYE_PATTERN 0x4cac ++#define mmDP3_DP_HBR2_EYE_PATTERN 0x4dac ++#define mmDP4_DP_HBR2_EYE_PATTERN 0x4eac ++#define mmDP5_DP_HBR2_EYE_PATTERN 0x4fac ++#define mmDP6_DP_HBR2_EYE_PATTERN 0x54ac ++#define mmDP7_DP_HBR2_EYE_PATTERN 0x56ac ++#define mmDP8_DP_HBR2_EYE_PATTERN 0x57ac ++#define mmDP_VID_MSA_VBID 0x4aad ++#define mmDP0_DP_VID_MSA_VBID 0x4aad ++#define mmDP1_DP_VID_MSA_VBID 0x4bad ++#define mmDP2_DP_VID_MSA_VBID 0x4cad ++#define mmDP3_DP_VID_MSA_VBID 0x4dad ++#define mmDP4_DP_VID_MSA_VBID 0x4ead ++#define mmDP5_DP_VID_MSA_VBID 0x4fad ++#define mmDP6_DP_VID_MSA_VBID 0x54ad ++#define mmDP7_DP_VID_MSA_VBID 0x56ad ++#define mmDP8_DP_VID_MSA_VBID 0x57ad ++#define mmDP_VID_INTERRUPT_CNTL 0x4aae ++#define mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae ++#define mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae ++#define mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae ++#define mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae ++#define mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae ++#define mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae ++#define mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae ++#define mmDP7_DP_VID_INTERRUPT_CNTL 0x56ae ++#define mmDP8_DP_VID_INTERRUPT_CNTL 0x57ae ++#define mmDP_DPHY_CNTL 0x4aaf ++#define mmDP0_DP_DPHY_CNTL 0x4aaf ++#define mmDP1_DP_DPHY_CNTL 0x4baf ++#define mmDP2_DP_DPHY_CNTL 0x4caf ++#define mmDP3_DP_DPHY_CNTL 0x4daf ++#define mmDP4_DP_DPHY_CNTL 0x4eaf ++#define mmDP5_DP_DPHY_CNTL 0x4faf ++#define mmDP6_DP_DPHY_CNTL 0x54af ++#define mmDP7_DP_DPHY_CNTL 0x56af ++#define mmDP8_DP_DPHY_CNTL 0x57af ++#define mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 ++#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 ++#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0 ++#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 ++#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 ++#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 ++#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0 ++#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0 ++#define mmDP7_DP_DPHY_TRAINING_PATTERN_SEL 0x56b0 ++#define mmDP8_DP_DPHY_TRAINING_PATTERN_SEL 0x57b0 ++#define mmDP_DPHY_SYM0 0x4ab1 ++#define mmDP0_DP_DPHY_SYM0 0x4ab1 ++#define mmDP1_DP_DPHY_SYM0 0x4bb1 ++#define mmDP2_DP_DPHY_SYM0 0x4cb1 ++#define mmDP3_DP_DPHY_SYM0 0x4db1 ++#define mmDP4_DP_DPHY_SYM0 0x4eb1 ++#define mmDP5_DP_DPHY_SYM0 0x4fb1 ++#define mmDP6_DP_DPHY_SYM0 0x54b1 ++#define mmDP7_DP_DPHY_SYM0 0x56b1 ++#define mmDP8_DP_DPHY_SYM0 0x57b1 ++#define mmDP_DPHY_SYM1 0x4ab2 ++#define mmDP0_DP_DPHY_SYM1 0x4ab2 ++#define mmDP1_DP_DPHY_SYM1 0x4bb2 ++#define mmDP2_DP_DPHY_SYM1 0x4cb2 ++#define mmDP3_DP_DPHY_SYM1 0x4db2 ++#define mmDP4_DP_DPHY_SYM1 0x4eb2 ++#define mmDP5_DP_DPHY_SYM1 0x4fb2 ++#define mmDP6_DP_DPHY_SYM1 0x54b2 ++#define mmDP7_DP_DPHY_SYM1 0x56b2 ++#define mmDP8_DP_DPHY_SYM1 0x57b2 ++#define mmDP_DPHY_SYM2 0x4ab3 ++#define mmDP0_DP_DPHY_SYM2 0x4ab3 ++#define mmDP1_DP_DPHY_SYM2 0x4bb3 ++#define mmDP2_DP_DPHY_SYM2 0x4cb3 ++#define mmDP3_DP_DPHY_SYM2 0x4db3 ++#define mmDP4_DP_DPHY_SYM2 0x4eb3 ++#define mmDP5_DP_DPHY_SYM2 0x4fb3 ++#define mmDP6_DP_DPHY_SYM2 0x54b3 ++#define mmDP7_DP_DPHY_SYM2 0x56b3 ++#define mmDP8_DP_DPHY_SYM2 0x57b3 ++#define mmDP_DPHY_8B10B_CNTL 0x4ab4 ++#define mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4 ++#define mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4 ++#define mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4 ++#define mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 ++#define mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4 ++#define mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4 ++#define mmDP6_DP_DPHY_8B10B_CNTL 0x54b4 ++#define mmDP7_DP_DPHY_8B10B_CNTL 0x56b4 ++#define mmDP8_DP_DPHY_8B10B_CNTL 0x57b4 ++#define mmDP_DPHY_PRBS_CNTL 0x4ab5 ++#define mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 ++#define mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 ++#define mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5 ++#define mmDP3_DP_DPHY_PRBS_CNTL 0x4db5 ++#define mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5 ++#define mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5 ++#define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 ++#define mmDP7_DP_DPHY_PRBS_CNTL 0x56b5 ++#define mmDP8_DP_DPHY_PRBS_CNTL 0x57b5 ++#define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc ++#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc ++#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc ++#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4cdc ++#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc ++#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4edc ++#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4fdc ++#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54dc ++#define mmDP7_DP_DPHY_BS_SR_SWAP_CNTL 0x56dc ++#define mmDP8_DP_DPHY_BS_SR_SWAP_CNTL 0x57dc ++#define mmDP_DPHY_CRC_EN 0x4ab7 ++#define mmDP0_DP_DPHY_CRC_EN 0x4ab7 ++#define mmDP1_DP_DPHY_CRC_EN 0x4bb7 ++#define mmDP2_DP_DPHY_CRC_EN 0x4cb7 ++#define mmDP3_DP_DPHY_CRC_EN 0x4db7 ++#define mmDP4_DP_DPHY_CRC_EN 0x4eb7 ++#define mmDP5_DP_DPHY_CRC_EN 0x4fb7 ++#define mmDP6_DP_DPHY_CRC_EN 0x54b7 ++#define mmDP7_DP_DPHY_CRC_EN 0x56b7 ++#define mmDP8_DP_DPHY_CRC_EN 0x57b7 ++#define mmDP_DPHY_CRC_CNTL 0x4ab8 ++#define mmDP0_DP_DPHY_CRC_CNTL 0x4ab8 ++#define mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 ++#define mmDP2_DP_DPHY_CRC_CNTL 0x4cb8 ++#define mmDP3_DP_DPHY_CRC_CNTL 0x4db8 ++#define mmDP4_DP_DPHY_CRC_CNTL 0x4eb8 ++#define mmDP5_DP_DPHY_CRC_CNTL 0x4fb8 ++#define mmDP6_DP_DPHY_CRC_CNTL 0x54b8 ++#define mmDP7_DP_DPHY_CRC_CNTL 0x56b8 ++#define mmDP8_DP_DPHY_CRC_CNTL 0x57b8 ++#define mmDP_DPHY_CRC_RESULT 0x4ab9 ++#define mmDP0_DP_DPHY_CRC_RESULT 0x4ab9 ++#define mmDP1_DP_DPHY_CRC_RESULT 0x4bb9 ++#define mmDP2_DP_DPHY_CRC_RESULT 0x4cb9 ++#define mmDP3_DP_DPHY_CRC_RESULT 0x4db9 ++#define mmDP4_DP_DPHY_CRC_RESULT 0x4eb9 ++#define mmDP5_DP_DPHY_CRC_RESULT 0x4fb9 ++#define mmDP6_DP_DPHY_CRC_RESULT 0x54b9 ++#define mmDP7_DP_DPHY_CRC_RESULT 0x56b9 ++#define mmDP8_DP_DPHY_CRC_RESULT 0x57b9 ++#define mmDP_DPHY_CRC_MST_CNTL 0x4aba ++#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba ++#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba ++#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba ++#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba ++#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba ++#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba ++#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba ++#define mmDP7_DP_DPHY_CRC_MST_CNTL 0x56ba ++#define mmDP8_DP_DPHY_CRC_MST_CNTL 0x57ba ++#define mmDP_DPHY_CRC_MST_STATUS 0x4abb ++#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb ++#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb ++#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb ++#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb ++#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb ++#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb ++#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb ++#define mmDP7_DP_DPHY_CRC_MST_STATUS 0x56bb ++#define mmDP8_DP_DPHY_CRC_MST_STATUS 0x57bb ++#define mmDP_DPHY_FAST_TRAINING 0x4abc ++#define mmDP0_DP_DPHY_FAST_TRAINING 0x4abc ++#define mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc ++#define mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc ++#define mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc ++#define mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc ++#define mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc ++#define mmDP6_DP_DPHY_FAST_TRAINING 0x54bc ++#define mmDP7_DP_DPHY_FAST_TRAINING 0x56bc ++#define mmDP8_DP_DPHY_FAST_TRAINING 0x57bc ++#define mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd ++#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd ++#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd ++#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd ++#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd ++#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd ++#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd ++#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd ++#define mmDP7_DP_DPHY_FAST_TRAINING_STATUS 0x56bd ++#define mmDP8_DP_DPHY_FAST_TRAINING_STATUS 0x57bd ++#define mmDP_DPHY_HBR2_PATTERN_CONTROL 0x4add ++#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x4add ++#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x4bdd ++#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x4cdd ++#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x4ddd ++#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x4edd ++#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x4fdd ++#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x54dd ++#define mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL 0x56dd ++#define mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL 0x57dd ++#define mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe ++#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe ++#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe ++#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe ++#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe ++#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe ++#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe ++#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be ++#define mmDP7_DP_MSA_V_TIMING_OVERRIDE1 0x56be ++#define mmDP8_DP_MSA_V_TIMING_OVERRIDE1 0x57be ++#define mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf ++#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf ++#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf ++#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf ++#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf ++#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf ++#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf ++#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf ++#define mmDP7_DP_MSA_V_TIMING_OVERRIDE2 0x56bf ++#define mmDP8_DP_MSA_V_TIMING_OVERRIDE2 0x57bf ++#define mmDP_SEC_CNTL 0x4ac3 ++#define mmDP0_DP_SEC_CNTL 0x4ac3 ++#define mmDP1_DP_SEC_CNTL 0x4bc3 ++#define mmDP2_DP_SEC_CNTL 0x4cc3 ++#define mmDP3_DP_SEC_CNTL 0x4dc3 ++#define mmDP4_DP_SEC_CNTL 0x4ec3 ++#define mmDP5_DP_SEC_CNTL 0x4fc3 ++#define mmDP6_DP_SEC_CNTL 0x54c3 ++#define mmDP7_DP_SEC_CNTL 0x56c3 ++#define mmDP8_DP_SEC_CNTL 0x57c3 ++#define mmDP_SEC_CNTL1 0x4ac4 ++#define mmDP0_DP_SEC_CNTL1 0x4ac4 ++#define mmDP1_DP_SEC_CNTL1 0x4bc4 ++#define mmDP2_DP_SEC_CNTL1 0x4cc4 ++#define mmDP3_DP_SEC_CNTL1 0x4dc4 ++#define mmDP4_DP_SEC_CNTL1 0x4ec4 ++#define mmDP5_DP_SEC_CNTL1 0x4fc4 ++#define mmDP6_DP_SEC_CNTL1 0x54c4 ++#define mmDP7_DP_SEC_CNTL1 0x56c4 ++#define mmDP8_DP_SEC_CNTL1 0x57c4 ++#define mmDP_SEC_FRAMING1 0x4ac5 ++#define mmDP0_DP_SEC_FRAMING1 0x4ac5 ++#define mmDP1_DP_SEC_FRAMING1 0x4bc5 ++#define mmDP2_DP_SEC_FRAMING1 0x4cc5 ++#define mmDP3_DP_SEC_FRAMING1 0x4dc5 ++#define mmDP4_DP_SEC_FRAMING1 0x4ec5 ++#define mmDP5_DP_SEC_FRAMING1 0x4fc5 ++#define mmDP6_DP_SEC_FRAMING1 0x54c5 ++#define mmDP7_DP_SEC_FRAMING1 0x56c5 ++#define mmDP8_DP_SEC_FRAMING1 0x57c5 ++#define mmDP_SEC_FRAMING2 0x4ac6 ++#define mmDP0_DP_SEC_FRAMING2 0x4ac6 ++#define mmDP1_DP_SEC_FRAMING2 0x4bc6 ++#define mmDP2_DP_SEC_FRAMING2 0x4cc6 ++#define mmDP3_DP_SEC_FRAMING2 0x4dc6 ++#define mmDP4_DP_SEC_FRAMING2 0x4ec6 ++#define mmDP5_DP_SEC_FRAMING2 0x4fc6 ++#define mmDP6_DP_SEC_FRAMING2 0x54c6 ++#define mmDP7_DP_SEC_FRAMING2 0x56c6 ++#define mmDP8_DP_SEC_FRAMING2 0x57c6 ++#define mmDP_SEC_FRAMING3 0x4ac7 ++#define mmDP0_DP_SEC_FRAMING3 0x4ac7 ++#define mmDP1_DP_SEC_FRAMING3 0x4bc7 ++#define mmDP2_DP_SEC_FRAMING3 0x4cc7 ++#define mmDP3_DP_SEC_FRAMING3 0x4dc7 ++#define mmDP4_DP_SEC_FRAMING3 0x4ec7 ++#define mmDP5_DP_SEC_FRAMING3 0x4fc7 ++#define mmDP6_DP_SEC_FRAMING3 0x54c7 ++#define mmDP7_DP_SEC_FRAMING3 0x56c7 ++#define mmDP8_DP_SEC_FRAMING3 0x57c7 ++#define mmDP_SEC_FRAMING4 0x4ac8 ++#define mmDP0_DP_SEC_FRAMING4 0x4ac8 ++#define mmDP1_DP_SEC_FRAMING4 0x4bc8 ++#define mmDP2_DP_SEC_FRAMING4 0x4cc8 ++#define mmDP3_DP_SEC_FRAMING4 0x4dc8 ++#define mmDP4_DP_SEC_FRAMING4 0x4ec8 ++#define mmDP5_DP_SEC_FRAMING4 0x4fc8 ++#define mmDP6_DP_SEC_FRAMING4 0x54c8 ++#define mmDP7_DP_SEC_FRAMING4 0x56c8 ++#define mmDP8_DP_SEC_FRAMING4 0x57c8 ++#define mmDP_SEC_AUD_N 0x4ac9 ++#define mmDP0_DP_SEC_AUD_N 0x4ac9 ++#define mmDP1_DP_SEC_AUD_N 0x4bc9 ++#define mmDP2_DP_SEC_AUD_N 0x4cc9 ++#define mmDP3_DP_SEC_AUD_N 0x4dc9 ++#define mmDP4_DP_SEC_AUD_N 0x4ec9 ++#define mmDP5_DP_SEC_AUD_N 0x4fc9 ++#define mmDP6_DP_SEC_AUD_N 0x54c9 ++#define mmDP7_DP_SEC_AUD_N 0x56c9 ++#define mmDP8_DP_SEC_AUD_N 0x57c9 ++#define mmDP_SEC_AUD_N_READBACK 0x4aca ++#define mmDP0_DP_SEC_AUD_N_READBACK 0x4aca ++#define mmDP1_DP_SEC_AUD_N_READBACK 0x4bca ++#define mmDP2_DP_SEC_AUD_N_READBACK 0x4cca ++#define mmDP3_DP_SEC_AUD_N_READBACK 0x4dca ++#define mmDP4_DP_SEC_AUD_N_READBACK 0x4eca ++#define mmDP5_DP_SEC_AUD_N_READBACK 0x4fca ++#define mmDP6_DP_SEC_AUD_N_READBACK 0x54ca ++#define mmDP7_DP_SEC_AUD_N_READBACK 0x56ca ++#define mmDP8_DP_SEC_AUD_N_READBACK 0x57ca ++#define mmDP_SEC_AUD_M 0x4acb ++#define mmDP0_DP_SEC_AUD_M 0x4acb ++#define mmDP1_DP_SEC_AUD_M 0x4bcb ++#define mmDP2_DP_SEC_AUD_M 0x4ccb ++#define mmDP3_DP_SEC_AUD_M 0x4dcb ++#define mmDP4_DP_SEC_AUD_M 0x4ecb ++#define mmDP5_DP_SEC_AUD_M 0x4fcb ++#define mmDP6_DP_SEC_AUD_M 0x54cb ++#define mmDP7_DP_SEC_AUD_M 0x56cb ++#define mmDP8_DP_SEC_AUD_M 0x57cb ++#define mmDP_SEC_AUD_M_READBACK 0x4acc ++#define mmDP0_DP_SEC_AUD_M_READBACK 0x4acc ++#define mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc ++#define mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc ++#define mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc ++#define mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc ++#define mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc ++#define mmDP6_DP_SEC_AUD_M_READBACK 0x54cc ++#define mmDP7_DP_SEC_AUD_M_READBACK 0x56cc ++#define mmDP8_DP_SEC_AUD_M_READBACK 0x57cc ++#define mmDP_SEC_TIMESTAMP 0x4acd ++#define mmDP0_DP_SEC_TIMESTAMP 0x4acd ++#define mmDP1_DP_SEC_TIMESTAMP 0x4bcd ++#define mmDP2_DP_SEC_TIMESTAMP 0x4ccd ++#define mmDP3_DP_SEC_TIMESTAMP 0x4dcd ++#define mmDP4_DP_SEC_TIMESTAMP 0x4ecd ++#define mmDP5_DP_SEC_TIMESTAMP 0x4fcd ++#define mmDP6_DP_SEC_TIMESTAMP 0x54cd ++#define mmDP7_DP_SEC_TIMESTAMP 0x56cd ++#define mmDP8_DP_SEC_TIMESTAMP 0x57cd ++#define mmDP_SEC_PACKET_CNTL 0x4ace ++#define mmDP0_DP_SEC_PACKET_CNTL 0x4ace ++#define mmDP1_DP_SEC_PACKET_CNTL 0x4bce ++#define mmDP2_DP_SEC_PACKET_CNTL 0x4cce ++#define mmDP3_DP_SEC_PACKET_CNTL 0x4dce ++#define mmDP4_DP_SEC_PACKET_CNTL 0x4ece ++#define mmDP5_DP_SEC_PACKET_CNTL 0x4fce ++#define mmDP6_DP_SEC_PACKET_CNTL 0x54ce ++#define mmDP7_DP_SEC_PACKET_CNTL 0x56ce ++#define mmDP8_DP_SEC_PACKET_CNTL 0x57ce ++#define mmDP_MSE_RATE_CNTL 0x4acf ++#define mmDP0_DP_MSE_RATE_CNTL 0x4acf ++#define mmDP1_DP_MSE_RATE_CNTL 0x4bcf ++#define mmDP2_DP_MSE_RATE_CNTL 0x4ccf ++#define mmDP3_DP_MSE_RATE_CNTL 0x4dcf ++#define mmDP4_DP_MSE_RATE_CNTL 0x4ecf ++#define mmDP5_DP_MSE_RATE_CNTL 0x4fcf ++#define mmDP6_DP_MSE_RATE_CNTL 0x54cf ++#define mmDP7_DP_MSE_RATE_CNTL 0x56cf ++#define mmDP8_DP_MSE_RATE_CNTL 0x57cf ++#define mmDP_MSE_RATE_UPDATE 0x4ad1 ++#define mmDP0_DP_MSE_RATE_UPDATE 0x4ad1 ++#define mmDP1_DP_MSE_RATE_UPDATE 0x4bd1 ++#define mmDP2_DP_MSE_RATE_UPDATE 0x4cd1 ++#define mmDP3_DP_MSE_RATE_UPDATE 0x4dd1 ++#define mmDP4_DP_MSE_RATE_UPDATE 0x4ed1 ++#define mmDP5_DP_MSE_RATE_UPDATE 0x4fd1 ++#define mmDP6_DP_MSE_RATE_UPDATE 0x54d1 ++#define mmDP7_DP_MSE_RATE_UPDATE 0x56d1 ++#define mmDP8_DP_MSE_RATE_UPDATE 0x57d1 ++#define mmDP_MSE_SAT0 0x4ad2 ++#define mmDP0_DP_MSE_SAT0 0x4ad2 ++#define mmDP1_DP_MSE_SAT0 0x4bd2 ++#define mmDP2_DP_MSE_SAT0 0x4cd2 ++#define mmDP3_DP_MSE_SAT0 0x4dd2 ++#define mmDP4_DP_MSE_SAT0 0x4ed2 ++#define mmDP5_DP_MSE_SAT0 0x4fd2 ++#define mmDP6_DP_MSE_SAT0 0x54d2 ++#define mmDP7_DP_MSE_SAT0 0x56d2 ++#define mmDP8_DP_MSE_SAT0 0x57d2 ++#define mmDP_MSE_SAT1 0x4ad3 ++#define mmDP0_DP_MSE_SAT1 0x4ad3 ++#define mmDP1_DP_MSE_SAT1 0x4bd3 ++#define mmDP2_DP_MSE_SAT1 0x4cd3 ++#define mmDP3_DP_MSE_SAT1 0x4dd3 ++#define mmDP4_DP_MSE_SAT1 0x4ed3 ++#define mmDP5_DP_MSE_SAT1 0x4fd3 ++#define mmDP6_DP_MSE_SAT1 0x54d3 ++#define mmDP7_DP_MSE_SAT1 0x56d3 ++#define mmDP8_DP_MSE_SAT1 0x57d3 ++#define mmDP_MSE_SAT2 0x4ad4 ++#define mmDP0_DP_MSE_SAT2 0x4ad4 ++#define mmDP1_DP_MSE_SAT2 0x4bd4 ++#define mmDP2_DP_MSE_SAT2 0x4cd4 ++#define mmDP3_DP_MSE_SAT2 0x4dd4 ++#define mmDP4_DP_MSE_SAT2 0x4ed4 ++#define mmDP5_DP_MSE_SAT2 0x4fd4 ++#define mmDP6_DP_MSE_SAT2 0x54d4 ++#define mmDP7_DP_MSE_SAT2 0x56d4 ++#define mmDP8_DP_MSE_SAT2 0x57d4 ++#define mmDP_MSE_SAT_UPDATE 0x4ad5 ++#define mmDP0_DP_MSE_SAT_UPDATE 0x4ad5 ++#define mmDP1_DP_MSE_SAT_UPDATE 0x4bd5 ++#define mmDP2_DP_MSE_SAT_UPDATE 0x4cd5 ++#define mmDP3_DP_MSE_SAT_UPDATE 0x4dd5 ++#define mmDP4_DP_MSE_SAT_UPDATE 0x4ed5 ++#define mmDP5_DP_MSE_SAT_UPDATE 0x4fd5 ++#define mmDP6_DP_MSE_SAT_UPDATE 0x54d5 ++#define mmDP7_DP_MSE_SAT_UPDATE 0x56d5 ++#define mmDP8_DP_MSE_SAT_UPDATE 0x57d5 ++#define mmDP_MSE_LINK_TIMING 0x4ad6 ++#define mmDP0_DP_MSE_LINK_TIMING 0x4ad6 ++#define mmDP1_DP_MSE_LINK_TIMING 0x4bd6 ++#define mmDP2_DP_MSE_LINK_TIMING 0x4cd6 ++#define mmDP3_DP_MSE_LINK_TIMING 0x4dd6 ++#define mmDP4_DP_MSE_LINK_TIMING 0x4ed6 ++#define mmDP5_DP_MSE_LINK_TIMING 0x4fd6 ++#define mmDP6_DP_MSE_LINK_TIMING 0x54d6 ++#define mmDP7_DP_MSE_LINK_TIMING 0x56d6 ++#define mmDP8_DP_MSE_LINK_TIMING 0x57d6 ++#define mmDP_MSE_MISC_CNTL 0x4ad7 ++#define mmDP0_DP_MSE_MISC_CNTL 0x4ad7 ++#define mmDP1_DP_MSE_MISC_CNTL 0x4bd7 ++#define mmDP2_DP_MSE_MISC_CNTL 0x4cd7 ++#define mmDP3_DP_MSE_MISC_CNTL 0x4dd7 ++#define mmDP4_DP_MSE_MISC_CNTL 0x4ed7 ++#define mmDP5_DP_MSE_MISC_CNTL 0x4fd7 ++#define mmDP6_DP_MSE_MISC_CNTL 0x54d7 ++#define mmDP7_DP_MSE_MISC_CNTL 0x56d7 ++#define mmDP8_DP_MSE_MISC_CNTL 0x57d7 ++#define mmDP_TEST_DEBUG_INDEX 0x4ad8 ++#define mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8 ++#define mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8 ++#define mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8 ++#define mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8 ++#define mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8 ++#define mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8 ++#define mmDP6_DP_TEST_DEBUG_INDEX 0x54d8 ++#define mmDP7_DP_TEST_DEBUG_INDEX 0x56d8 ++#define mmDP8_DP_TEST_DEBUG_INDEX 0x57d8 ++#define mmDP_TEST_DEBUG_DATA 0x4ad9 ++#define mmDP0_DP_TEST_DEBUG_DATA 0x4ad9 ++#define mmDP1_DP_TEST_DEBUG_DATA 0x4bd9 ++#define mmDP2_DP_TEST_DEBUG_DATA 0x4cd9 ++#define mmDP3_DP_TEST_DEBUG_DATA 0x4dd9 ++#define mmDP4_DP_TEST_DEBUG_DATA 0x4ed9 ++#define mmDP5_DP_TEST_DEBUG_DATA 0x4fd9 ++#define mmDP6_DP_TEST_DEBUG_DATA 0x54d9 ++#define mmDP7_DP_TEST_DEBUG_DATA 0x56d9 ++#define mmDP8_DP_TEST_DEBUG_DATA 0x57d9 ++#define mmDP_FE_TEST_DEBUG_INDEX 0x4ada ++#define mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada ++#define mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda ++#define mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda ++#define mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda ++#define mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda ++#define mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda ++#define mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da ++#define mmDP7_DP_FE_TEST_DEBUG_INDEX 0x56da ++#define mmDP8_DP_FE_TEST_DEBUG_INDEX 0x57da ++#define mmDP_FE_TEST_DEBUG_DATA 0x4adb ++#define mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb ++#define mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb ++#define mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb ++#define mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb ++#define mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb ++#define mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb ++#define mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db ++#define mmDP7_DP_FE_TEST_DEBUG_DATA 0x56db ++#define mmDP8_DP_FE_TEST_DEBUG_DATA 0x57db ++#define mmAUX_CONTROL 0x5c00 ++#define mmDP_AUX0_AUX_CONTROL 0x5c00 ++#define mmDP_AUX1_AUX_CONTROL 0x5c1c ++#define mmDP_AUX2_AUX_CONTROL 0x5c38 ++#define mmDP_AUX3_AUX_CONTROL 0x5c54 ++#define mmDP_AUX4_AUX_CONTROL 0x5c70 ++#define mmDP_AUX5_AUX_CONTROL 0x5c8c ++#define mmAUX_SW_CONTROL 0x5c01 ++#define mmDP_AUX0_AUX_SW_CONTROL 0x5c01 ++#define mmDP_AUX1_AUX_SW_CONTROL 0x5c1d ++#define mmDP_AUX2_AUX_SW_CONTROL 0x5c39 ++#define mmDP_AUX3_AUX_SW_CONTROL 0x5c55 ++#define mmDP_AUX4_AUX_SW_CONTROL 0x5c71 ++#define mmDP_AUX5_AUX_SW_CONTROL 0x5c8d ++#define mmAUX_ARB_CONTROL 0x5c02 ++#define mmDP_AUX0_AUX_ARB_CONTROL 0x5c02 ++#define mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e ++#define mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a ++#define mmDP_AUX3_AUX_ARB_CONTROL 0x5c56 ++#define mmDP_AUX4_AUX_ARB_CONTROL 0x5c72 ++#define mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e ++#define mmAUX_INTERRUPT_CONTROL 0x5c03 ++#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03 ++#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f ++#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b ++#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57 ++#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73 ++#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f ++#define mmAUX_SW_STATUS 0x5c04 ++#define mmDP_AUX0_AUX_SW_STATUS 0x5c04 ++#define mmDP_AUX1_AUX_SW_STATUS 0x5c20 ++#define mmDP_AUX2_AUX_SW_STATUS 0x5c3c ++#define mmDP_AUX3_AUX_SW_STATUS 0x5c58 ++#define mmDP_AUX4_AUX_SW_STATUS 0x5c74 ++#define mmDP_AUX5_AUX_SW_STATUS 0x5c90 ++#define mmAUX_LS_STATUS 0x5c05 ++#define mmDP_AUX0_AUX_LS_STATUS 0x5c05 ++#define mmDP_AUX1_AUX_LS_STATUS 0x5c21 ++#define mmDP_AUX2_AUX_LS_STATUS 0x5c3d ++#define mmDP_AUX3_AUX_LS_STATUS 0x5c59 ++#define mmDP_AUX4_AUX_LS_STATUS 0x5c75 ++#define mmDP_AUX5_AUX_LS_STATUS 0x5c91 ++#define mmAUX_SW_DATA 0x5c06 ++#define mmDP_AUX0_AUX_SW_DATA 0x5c06 ++#define mmDP_AUX1_AUX_SW_DATA 0x5c22 ++#define mmDP_AUX2_AUX_SW_DATA 0x5c3e ++#define mmDP_AUX3_AUX_SW_DATA 0x5c5a ++#define mmDP_AUX4_AUX_SW_DATA 0x5c76 ++#define mmDP_AUX5_AUX_SW_DATA 0x5c92 ++#define mmAUX_LS_DATA 0x5c07 ++#define mmDP_AUX0_AUX_LS_DATA 0x5c07 ++#define mmDP_AUX1_AUX_LS_DATA 0x5c23 ++#define mmDP_AUX2_AUX_LS_DATA 0x5c3f ++#define mmDP_AUX3_AUX_LS_DATA 0x5c5b ++#define mmDP_AUX4_AUX_LS_DATA 0x5c77 ++#define mmDP_AUX5_AUX_LS_DATA 0x5c93 ++#define mmAUX_DPHY_TX_REF_CONTROL 0x5c08 ++#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08 ++#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24 ++#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40 ++#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c ++#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78 ++#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94 ++#define mmAUX_DPHY_TX_CONTROL 0x5c09 ++#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09 ++#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25 ++#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41 ++#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d ++#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79 ++#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95 ++#define mmAUX_DPHY_RX_CONTROL0 0x5c0a ++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a ++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26 ++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42 ++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e ++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a ++#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96 ++#define mmAUX_DPHY_RX_CONTROL1 0x5c0b ++#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b ++#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27 ++#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43 ++#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f ++#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b ++#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97 ++#define mmAUX_DPHY_TX_STATUS 0x5c0c ++#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c ++#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28 ++#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44 ++#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60 ++#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c ++#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98 ++#define mmAUX_DPHY_RX_STATUS 0x5c0d ++#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d ++#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29 ++#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45 ++#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61 ++#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d ++#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99 ++#define mmAUX_GTC_SYNC_CONTROL 0x5c0e ++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x5c0e ++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x5c2a ++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x5c46 ++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x5c62 ++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x5c7e ++#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x5c9a ++#define mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f ++#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f ++#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b ++#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47 ++#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63 ++#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f ++#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b ++#define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 ++#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 ++#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c ++#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48 ++#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64 ++#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80 ++#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c ++#define mmAUX_GTC_SYNC_STATUS 0x5c11 ++#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11 ++#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d ++#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49 ++#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65 ++#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81 ++#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d ++#define mmAUX_GTC_SYNC_DATA 0x5c12 ++#define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x5c12 ++#define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x5c2e ++#define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x5c4a ++#define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x5c66 ++#define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x5c82 ++#define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x5c9e ++#define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 ++#define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 ++#define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c2f ++#define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c4b ++#define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c67 ++#define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c83 ++#define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c9f ++#define mmAUX_TEST_DEBUG_INDEX 0x5c14 ++#define mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14 ++#define mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30 ++#define mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c ++#define mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68 ++#define mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84 ++#define mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0 ++#define mmAUX_TEST_DEBUG_DATA 0x5c15 ++#define mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15 ++#define mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31 ++#define mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d ++#define mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69 ++#define mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85 ++#define mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1 ++#define ixDP_AUX_DEBUG_A 0x10 ++#define ixDP_AUX_DEBUG_B 0x11 ++#define ixDP_AUX_DEBUG_C 0x12 ++#define ixDP_AUX_DEBUG_D 0x13 ++#define ixDP_AUX_DEBUG_E 0x14 ++#define ixDP_AUX_DEBUG_F 0x15 ++#define ixDP_AUX_DEBUG_G 0x16 ++#define ixDP_AUX_DEBUG_H 0x17 ++#define ixDP_AUX_DEBUG_I 0x18 ++#define ixDP_AUX_DEBUG_J 0x19 ++#define ixDP_AUX_DEBUG_K 0x1a ++#define ixDP_AUX_DEBUG_L 0x1b ++#define ixDP_AUX_DEBUG_M 0x1c ++#define ixDP_AUX_DEBUG_N 0x1d ++#define ixDP_AUX_DEBUG_O 0x1e ++#define ixDP_AUX_DEBUG_P 0x1f ++#define ixDP_AUX_DEBUG_Q 0x20 ++#define mmDVO_ENABLE 0x16a0 ++#define mmDVO_SOURCE_SELECT 0x16a1 ++#define mmDVO_OUTPUT 0x16a2 ++#define mmDVO_CONTROL 0x16a3 ++#define mmDVO_CRC_EN 0x16a4 ++#define mmDVO_CRC2_SIG_MASK 0x16a5 ++#define mmDVO_CRC2_SIG_RESULT 0x16a6 ++#define mmDVO_FIFO_ERROR_STATUS 0x16a7 ++#define mmDVO_TEST_DEBUG_INDEX 0x16a8 ++#define mmDVO_TEST_DEBUG_DATA 0x16a9 ++#define mmFBC_CNTL 0x280 ++#define mmFBC_IDLE_MASK 0x281 ++#define mmFBC_IDLE_FORCE_CLEAR_MASK 0x282 ++#define mmFBC_START_STOP_DELAY 0x283 ++#define mmFBC_COMP_CNTL 0x284 ++#define mmFBC_COMP_MODE 0x285 ++#define mmFBC_DEBUG0 0x286 ++#define mmFBC_DEBUG1 0x287 ++#define mmFBC_DEBUG2 0x288 ++#define mmFBC_IND_LUT0 0x289 ++#define mmFBC_IND_LUT1 0x28a ++#define mmFBC_IND_LUT2 0x28b ++#define mmFBC_IND_LUT3 0x28c ++#define mmFBC_IND_LUT4 0x28d ++#define mmFBC_IND_LUT5 0x28e ++#define mmFBC_IND_LUT6 0x28f ++#define mmFBC_IND_LUT7 0x290 ++#define mmFBC_IND_LUT8 0x291 ++#define mmFBC_IND_LUT9 0x292 ++#define mmFBC_IND_LUT10 0x293 ++#define mmFBC_IND_LUT11 0x294 ++#define mmFBC_IND_LUT12 0x295 ++#define mmFBC_IND_LUT13 0x296 ++#define mmFBC_IND_LUT14 0x297 ++#define mmFBC_IND_LUT15 0x298 ++#define mmFBC_CSM_REGION_OFFSET_01 0x299 ++#define mmFBC_CSM_REGION_OFFSET_23 0x29a ++#define mmFBC_CLIENT_REGION_MASK 0x29b ++#define mmFBC_DEBUG_COMP 0x29c ++#define mmFBC_DEBUG_CSR 0x29d ++#define mmFBC_DEBUG_CSR_RDATA 0x29e ++#define mmFBC_DEBUG_CSR_WDATA 0x29f ++#define mmFBC_DEBUG_CSR_RDATA_HI 0x2a0 ++#define mmFBC_DEBUG_CSR_WDATA_HI 0x2a1 ++#define mmFBC_MISC 0x2a2 ++#define mmFBC_STATUS 0x2a3 ++#define mmFBC_TEST_DEBUG_INDEX 0x2a4 ++#define mmFBC_TEST_DEBUG_DATA 0x2a5 ++#define mmFMT_CLAMP_COMPONENT_R 0x1be8 ++#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 ++#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8 ++#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8 ++#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8 ++#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8 ++#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8 ++#define mmFMT_CLAMP_COMPONENT_G 0x1be9 ++#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 ++#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9 ++#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9 ++#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9 ++#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9 ++#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9 ++#define mmFMT_CLAMP_COMPONENT_B 0x1bea ++#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea ++#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea ++#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea ++#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea ++#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea ++#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea ++#define mmFMT_DYNAMIC_EXP_CNTL 0x1bed ++#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed ++#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded ++#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed ++#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed ++#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed ++#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed ++#define mmFMT_CONTROL 0x1bee ++#define mmFMT0_FMT_CONTROL 0x1bee ++#define mmFMT1_FMT_CONTROL 0x1dee ++#define mmFMT2_FMT_CONTROL 0x1fee ++#define mmFMT3_FMT_CONTROL 0x41ee ++#define mmFMT4_FMT_CONTROL 0x43ee ++#define mmFMT5_FMT_CONTROL 0x45ee ++#define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 ++#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 ++#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2 ++#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2 ++#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2 ++#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2 ++#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2 ++#define mmFMT_DITHER_RAND_R_SEED 0x1bf3 ++#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 ++#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3 ++#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3 ++#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3 ++#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3 ++#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3 ++#define mmFMT_DITHER_RAND_G_SEED 0x1bf4 ++#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 ++#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4 ++#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4 ++#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4 ++#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4 ++#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4 ++#define mmFMT_DITHER_RAND_B_SEED 0x1bf5 ++#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 ++#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5 ++#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5 ++#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5 ++#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5 ++#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5 ++#define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 ++#define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 ++#define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6 ++#define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6 ++#define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 ++#define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6 ++#define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6 ++#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 ++#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 ++#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7 ++#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7 ++#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 ++#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7 ++#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7 ++#define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 ++#define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 ++#define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8 ++#define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8 ++#define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 ++#define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8 ++#define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8 ++#define mmFMT_CLAMP_CNTL 0x1bf9 ++#define mmFMT0_FMT_CLAMP_CNTL 0x1bf9 ++#define mmFMT1_FMT_CLAMP_CNTL 0x1df9 ++#define mmFMT2_FMT_CLAMP_CNTL 0x1ff9 ++#define mmFMT3_FMT_CLAMP_CNTL 0x41f9 ++#define mmFMT4_FMT_CLAMP_CNTL 0x43f9 ++#define mmFMT5_FMT_CLAMP_CNTL 0x45f9 ++#define mmFMT_CRC_CNTL 0x1bfa ++#define mmFMT0_FMT_CRC_CNTL 0x1bfa ++#define mmFMT1_FMT_CRC_CNTL 0x1dfa ++#define mmFMT2_FMT_CRC_CNTL 0x1ffa ++#define mmFMT3_FMT_CRC_CNTL 0x41fa ++#define mmFMT4_FMT_CRC_CNTL 0x43fa ++#define mmFMT5_FMT_CRC_CNTL 0x45fa ++#define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb ++#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb ++#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb ++#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb ++#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb ++#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb ++#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb ++#define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc ++#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc ++#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc ++#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc ++#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc ++#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc ++#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc ++#define mmFMT_CRC_SIG_RED_GREEN 0x1bfd ++#define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd ++#define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd ++#define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd ++#define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd ++#define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd ++#define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd ++#define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe ++#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe ++#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe ++#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe ++#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe ++#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe ++#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe ++#define mmFMT_DEBUG_CNTL 0x1bff ++#define mmFMT0_FMT_DEBUG_CNTL 0x1bff ++#define mmFMT1_FMT_DEBUG_CNTL 0x1dff ++#define mmFMT2_FMT_DEBUG_CNTL 0x1fff ++#define mmFMT3_FMT_DEBUG_CNTL 0x41ff ++#define mmFMT4_FMT_DEBUG_CNTL 0x43ff ++#define mmFMT5_FMT_DEBUG_CNTL 0x45ff ++#define mmFMT_TEST_DEBUG_INDEX 0x1beb ++#define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb ++#define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb ++#define mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb ++#define mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb ++#define mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb ++#define mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb ++#define mmFMT_TEST_DEBUG_DATA 0x1bec ++#define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec ++#define mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec ++#define mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec ++#define mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec ++#define mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec ++#define mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec ++#define ixFMT_DEBUG0 0x1 ++#define ixFMT_DEBUG1 0x2 ++#define ixFMT_DEBUG2 0x3 ++#define ixFMT_DEBUG_ID 0x0 ++#define mmLB_DATA_FORMAT 0x1ac0 ++#define mmLB0_LB_DATA_FORMAT 0x1ac0 ++#define mmLB1_LB_DATA_FORMAT 0x1cc0 ++#define mmLB2_LB_DATA_FORMAT 0x1ec0 ++#define mmLB3_LB_DATA_FORMAT 0x40c0 ++#define mmLB4_LB_DATA_FORMAT 0x42c0 ++#define mmLB5_LB_DATA_FORMAT 0x44c0 ++#define mmLB_MEMORY_CTRL 0x1ac1 ++#define mmLB0_LB_MEMORY_CTRL 0x1ac1 ++#define mmLB1_LB_MEMORY_CTRL 0x1cc1 ++#define mmLB2_LB_MEMORY_CTRL 0x1ec1 ++#define mmLB3_LB_MEMORY_CTRL 0x40c1 ++#define mmLB4_LB_MEMORY_CTRL 0x42c1 ++#define mmLB5_LB_MEMORY_CTRL 0x44c1 ++#define mmLB_MEMORY_SIZE_STATUS 0x1ac2 ++#define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 ++#define mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2 ++#define mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2 ++#define mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2 ++#define mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2 ++#define mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2 ++#define mmLB_DESKTOP_HEIGHT 0x1ac3 ++#define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 ++#define mmLB1_LB_DESKTOP_HEIGHT 0x1cc3 ++#define mmLB2_LB_DESKTOP_HEIGHT 0x1ec3 ++#define mmLB3_LB_DESKTOP_HEIGHT 0x40c3 ++#define mmLB4_LB_DESKTOP_HEIGHT 0x42c3 ++#define mmLB5_LB_DESKTOP_HEIGHT 0x44c3 ++#define mmLB_VLINE_START_END 0x1ac4 ++#define mmLB0_LB_VLINE_START_END 0x1ac4 ++#define mmLB1_LB_VLINE_START_END 0x1cc4 ++#define mmLB2_LB_VLINE_START_END 0x1ec4 ++#define mmLB3_LB_VLINE_START_END 0x40c4 ++#define mmLB4_LB_VLINE_START_END 0x42c4 ++#define mmLB5_LB_VLINE_START_END 0x44c4 ++#define mmLB_VLINE2_START_END 0x1ac5 ++#define mmLB0_LB_VLINE2_START_END 0x1ac5 ++#define mmLB1_LB_VLINE2_START_END 0x1cc5 ++#define mmLB2_LB_VLINE2_START_END 0x1ec5 ++#define mmLB3_LB_VLINE2_START_END 0x40c5 ++#define mmLB4_LB_VLINE2_START_END 0x42c5 ++#define mmLB5_LB_VLINE2_START_END 0x44c5 ++#define mmLB_V_COUNTER 0x1ac6 ++#define mmLB0_LB_V_COUNTER 0x1ac6 ++#define mmLB1_LB_V_COUNTER 0x1cc6 ++#define mmLB2_LB_V_COUNTER 0x1ec6 ++#define mmLB3_LB_V_COUNTER 0x40c6 ++#define mmLB4_LB_V_COUNTER 0x42c6 ++#define mmLB5_LB_V_COUNTER 0x44c6 ++#define mmLB_SNAPSHOT_V_COUNTER 0x1ac7 ++#define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 ++#define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7 ++#define mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7 ++#define mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7 ++#define mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7 ++#define mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7 ++#define mmLB_INTERRUPT_MASK 0x1ac8 ++#define mmLB0_LB_INTERRUPT_MASK 0x1ac8 ++#define mmLB1_LB_INTERRUPT_MASK 0x1cc8 ++#define mmLB2_LB_INTERRUPT_MASK 0x1ec8 ++#define mmLB3_LB_INTERRUPT_MASK 0x40c8 ++#define mmLB4_LB_INTERRUPT_MASK 0x42c8 ++#define mmLB5_LB_INTERRUPT_MASK 0x44c8 ++#define mmLB_VLINE_STATUS 0x1ac9 ++#define mmLB0_LB_VLINE_STATUS 0x1ac9 ++#define mmLB1_LB_VLINE_STATUS 0x1cc9 ++#define mmLB2_LB_VLINE_STATUS 0x1ec9 ++#define mmLB3_LB_VLINE_STATUS 0x40c9 ++#define mmLB4_LB_VLINE_STATUS 0x42c9 ++#define mmLB5_LB_VLINE_STATUS 0x44c9 ++#define mmLB_VLINE2_STATUS 0x1aca ++#define mmLB0_LB_VLINE2_STATUS 0x1aca ++#define mmLB1_LB_VLINE2_STATUS 0x1cca ++#define mmLB2_LB_VLINE2_STATUS 0x1eca ++#define mmLB3_LB_VLINE2_STATUS 0x40ca ++#define mmLB4_LB_VLINE2_STATUS 0x42ca ++#define mmLB5_LB_VLINE2_STATUS 0x44ca ++#define mmLB_VBLANK_STATUS 0x1acb ++#define mmLB0_LB_VBLANK_STATUS 0x1acb ++#define mmLB1_LB_VBLANK_STATUS 0x1ccb ++#define mmLB2_LB_VBLANK_STATUS 0x1ecb ++#define mmLB3_LB_VBLANK_STATUS 0x40cb ++#define mmLB4_LB_VBLANK_STATUS 0x42cb ++#define mmLB5_LB_VBLANK_STATUS 0x44cb ++#define mmLB_SYNC_RESET_SEL 0x1acc ++#define mmLB0_LB_SYNC_RESET_SEL 0x1acc ++#define mmLB1_LB_SYNC_RESET_SEL 0x1ccc ++#define mmLB2_LB_SYNC_RESET_SEL 0x1ecc ++#define mmLB3_LB_SYNC_RESET_SEL 0x40cc ++#define mmLB4_LB_SYNC_RESET_SEL 0x42cc ++#define mmLB5_LB_SYNC_RESET_SEL 0x44cc ++#define mmLB_BLACK_KEYER_R_CR 0x1acd ++#define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd ++#define mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd ++#define mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd ++#define mmLB3_LB_BLACK_KEYER_R_CR 0x40cd ++#define mmLB4_LB_BLACK_KEYER_R_CR 0x42cd ++#define mmLB5_LB_BLACK_KEYER_R_CR 0x44cd ++#define mmLB_BLACK_KEYER_G_Y 0x1ace ++#define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace ++#define mmLB1_LB_BLACK_KEYER_G_Y 0x1cce ++#define mmLB2_LB_BLACK_KEYER_G_Y 0x1ece ++#define mmLB3_LB_BLACK_KEYER_G_Y 0x40ce ++#define mmLB4_LB_BLACK_KEYER_G_Y 0x42ce ++#define mmLB5_LB_BLACK_KEYER_G_Y 0x44ce ++#define mmLB_BLACK_KEYER_B_CB 0x1acf ++#define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf ++#define mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf ++#define mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf ++#define mmLB3_LB_BLACK_KEYER_B_CB 0x40cf ++#define mmLB4_LB_BLACK_KEYER_B_CB 0x42cf ++#define mmLB5_LB_BLACK_KEYER_B_CB 0x44cf ++#define mmLB_KEYER_COLOR_CTRL 0x1ad0 ++#define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 ++#define mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0 ++#define mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0 ++#define mmLB3_LB_KEYER_COLOR_CTRL 0x40d0 ++#define mmLB4_LB_KEYER_COLOR_CTRL 0x42d0 ++#define mmLB5_LB_KEYER_COLOR_CTRL 0x44d0 ++#define mmLB_KEYER_COLOR_R_CR 0x1ad1 ++#define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 ++#define mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1 ++#define mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1 ++#define mmLB3_LB_KEYER_COLOR_R_CR 0x40d1 ++#define mmLB4_LB_KEYER_COLOR_R_CR 0x42d1 ++#define mmLB5_LB_KEYER_COLOR_R_CR 0x44d1 ++#define mmLB_KEYER_COLOR_G_Y 0x1ad2 ++#define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 ++#define mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2 ++#define mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2 ++#define mmLB3_LB_KEYER_COLOR_G_Y 0x40d2 ++#define mmLB4_LB_KEYER_COLOR_G_Y 0x42d2 ++#define mmLB5_LB_KEYER_COLOR_G_Y 0x44d2 ++#define mmLB_KEYER_COLOR_B_CB 0x1ad3 ++#define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 ++#define mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3 ++#define mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3 ++#define mmLB3_LB_KEYER_COLOR_B_CB 0x40d3 ++#define mmLB4_LB_KEYER_COLOR_B_CB 0x42d3 ++#define mmLB5_LB_KEYER_COLOR_B_CB 0x44d3 ++#define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 ++#define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 ++#define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4 ++#define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4 ++#define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4 ++#define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4 ++#define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4 ++#define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 ++#define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 ++#define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5 ++#define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5 ++#define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5 ++#define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5 ++#define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5 ++#define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 ++#define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 ++#define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6 ++#define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6 ++#define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6 ++#define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6 ++#define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6 ++#define mmLB_BUFFER_LEVEL_STATUS 0x1ad7 ++#define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 ++#define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7 ++#define mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7 ++#define mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7 ++#define mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7 ++#define mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7 ++#define mmLB_BUFFER_URGENCY_CTRL 0x1ad8 ++#define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 ++#define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8 ++#define mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8 ++#define mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8 ++#define mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8 ++#define mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8 ++#define mmLB_BUFFER_URGENCY_STATUS 0x1ad9 ++#define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 ++#define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9 ++#define mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9 ++#define mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9 ++#define mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9 ++#define mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9 ++#define mmLB_BUFFER_STATUS 0x1ada ++#define mmLB0_LB_BUFFER_STATUS 0x1ada ++#define mmLB1_LB_BUFFER_STATUS 0x1cda ++#define mmLB2_LB_BUFFER_STATUS 0x1eda ++#define mmLB3_LB_BUFFER_STATUS 0x40da ++#define mmLB4_LB_BUFFER_STATUS 0x42da ++#define mmLB5_LB_BUFFER_STATUS 0x44da ++#define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc ++#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc ++#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc ++#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc ++#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc ++#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc ++#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc ++#define mmMVP_AFR_FLIP_MODE 0x1ae0 ++#define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 ++#define mmLB1_MVP_AFR_FLIP_MODE 0x1ce0 ++#define mmLB2_MVP_AFR_FLIP_MODE 0x1ee0 ++#define mmLB3_MVP_AFR_FLIP_MODE 0x40e0 ++#define mmLB4_MVP_AFR_FLIP_MODE 0x42e0 ++#define mmLB5_MVP_AFR_FLIP_MODE 0x44e0 ++#define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 ++#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 ++#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1 ++#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1 ++#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 ++#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1 ++#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1 ++#define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 ++#define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 ++#define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2 ++#define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2 ++#define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2 ++#define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2 ++#define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2 ++#define mmDC_MVP_LB_CONTROL 0x1ae3 ++#define mmLB0_DC_MVP_LB_CONTROL 0x1ae3 ++#define mmLB1_DC_MVP_LB_CONTROL 0x1ce3 ++#define mmLB2_DC_MVP_LB_CONTROL 0x1ee3 ++#define mmLB3_DC_MVP_LB_CONTROL 0x40e3 ++#define mmLB4_DC_MVP_LB_CONTROL 0x42e3 ++#define mmLB5_DC_MVP_LB_CONTROL 0x44e3 ++#define mmLB_DEBUG 0x1ae4 ++#define mmLB0_LB_DEBUG 0x1ae4 ++#define mmLB1_LB_DEBUG 0x1ce4 ++#define mmLB2_LB_DEBUG 0x1ee4 ++#define mmLB3_LB_DEBUG 0x40e4 ++#define mmLB4_LB_DEBUG 0x42e4 ++#define mmLB5_LB_DEBUG 0x44e4 ++#define mmLB_DEBUG2 0x1ae5 ++#define mmLB0_LB_DEBUG2 0x1ae5 ++#define mmLB1_LB_DEBUG2 0x1ce5 ++#define mmLB2_LB_DEBUG2 0x1ee5 ++#define mmLB3_LB_DEBUG2 0x40e5 ++#define mmLB4_LB_DEBUG2 0x42e5 ++#define mmLB5_LB_DEBUG2 0x44e5 ++#define mmLB_DEBUG3 0x1ae6 ++#define mmLB0_LB_DEBUG3 0x1ae6 ++#define mmLB1_LB_DEBUG3 0x1ce6 ++#define mmLB2_LB_DEBUG3 0x1ee6 ++#define mmLB3_LB_DEBUG3 0x40e6 ++#define mmLB4_LB_DEBUG3 0x42e6 ++#define mmLB5_LB_DEBUG3 0x44e6 ++#define mmLB_TEST_DEBUG_INDEX 0x1afe ++#define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe ++#define mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe ++#define mmLB2_LB_TEST_DEBUG_INDEX 0x1efe ++#define mmLB3_LB_TEST_DEBUG_INDEX 0x40fe ++#define mmLB4_LB_TEST_DEBUG_INDEX 0x42fe ++#define mmLB5_LB_TEST_DEBUG_INDEX 0x44fe ++#define mmLB_TEST_DEBUG_DATA 0x1aff ++#define mmLB0_LB_TEST_DEBUG_DATA 0x1aff ++#define mmLB1_LB_TEST_DEBUG_DATA 0x1cff ++#define mmLB2_LB_TEST_DEBUG_DATA 0x1eff ++#define mmLB3_LB_TEST_DEBUG_DATA 0x40ff ++#define mmLB4_LB_TEST_DEBUG_DATA 0x42ff ++#define mmLB5_LB_TEST_DEBUG_DATA 0x44ff ++#define mmLBV_DATA_FORMAT 0x463c ++#define mmLBV_MEMORY_CTRL 0x463d ++#define mmLBV_MEMORY_SIZE_STATUS 0x463e ++#define mmLBV_DESKTOP_HEIGHT 0x463f ++#define mmLBV_VLINE_START_END 0x4640 ++#define mmLBV_VLINE2_START_END 0x4641 ++#define mmLBV_V_COUNTER 0x4642 ++#define mmLBV_SNAPSHOT_V_COUNTER 0x4643 ++#define mmLBV_V_COUNTER_CHROMA 0x4644 ++#define mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645 ++#define mmLBV_INTERRUPT_MASK 0x4646 ++#define mmLBV_VLINE_STATUS 0x4647 ++#define mmLBV_VLINE2_STATUS 0x4648 ++#define mmLBV_VBLANK_STATUS 0x4649 ++#define mmLBV_SYNC_RESET_SEL 0x464a ++#define mmLBV_BLACK_KEYER_R_CR 0x464b ++#define mmLBV_BLACK_KEYER_G_Y 0x464c ++#define mmLBV_BLACK_KEYER_B_CB 0x464d ++#define mmLBV_KEYER_COLOR_CTRL 0x464e ++#define mmLBV_KEYER_COLOR_R_CR 0x464f ++#define mmLBV_KEYER_COLOR_G_Y 0x4650 ++#define mmLBV_KEYER_COLOR_B_CB 0x4651 ++#define mmLBV_KEYER_COLOR_REP_R_CR 0x4652 ++#define mmLBV_KEYER_COLOR_REP_G_Y 0x4653 ++#define mmLBV_KEYER_COLOR_REP_B_CB 0x4654 ++#define mmLBV_BUFFER_LEVEL_STATUS 0x4655 ++#define mmLBV_BUFFER_URGENCY_CTRL 0x4656 ++#define mmLBV_BUFFER_URGENCY_STATUS 0x4657 ++#define mmLBV_BUFFER_STATUS 0x4658 ++#define mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659 ++#define mmLBV_DEBUG 0x465a ++#define mmLBV_DEBUG2 0x465b ++#define mmLBV_DEBUG3 0x465c ++#define mmLBV_TEST_DEBUG_INDEX 0x4666 ++#define mmLBV_TEST_DEBUG_DATA 0x4667 ++#define mmMVP_CONTROL1 0x2ac ++#define mmMVP_CONTROL2 0x2ad ++#define mmMVP_FIFO_CONTROL 0x2ae ++#define mmMVP_FIFO_STATUS 0x2af ++#define mmMVP_SLAVE_STATUS 0x2b0 ++#define mmMVP_INBAND_CNTL_CAP 0x2b1 ++#define mmMVP_BLACK_KEYER 0x2b2 ++#define mmMVP_CRC_CNTL 0x2b3 ++#define mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4 ++#define mmMVP_CRC_RESULT_RED 0x2b5 ++#define mmMVP_CONTROL3 0x2b6 ++#define mmMVP_RECEIVE_CNT_CNTL1 0x2b7 ++#define mmMVP_RECEIVE_CNT_CNTL2 0x2b8 ++#define mmMVP_DEBUG 0x2bb ++#define mmMVP_TEST_DEBUG_INDEX 0x2b9 ++#define mmMVP_TEST_DEBUG_DATA 0x2ba ++#define ixMVP_DEBUG_12 0xc ++#define ixMVP_DEBUG_13 0xd ++#define ixMVP_DEBUG_14 0xe ++#define ixMVP_DEBUG_15 0xf ++#define ixMVP_DEBUG_16 0x10 ++#define ixMVP_DEBUG_17 0x11 ++#define mmSCL_COEF_RAM_SELECT 0x1b40 ++#define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 ++#define mmSCL1_SCL_COEF_RAM_SELECT 0x1d40 ++#define mmSCL2_SCL_COEF_RAM_SELECT 0x1f40 ++#define mmSCL3_SCL_COEF_RAM_SELECT 0x4140 ++#define mmSCL4_SCL_COEF_RAM_SELECT 0x4340 ++#define mmSCL5_SCL_COEF_RAM_SELECT 0x4540 ++#define mmSCL_COEF_RAM_TAP_DATA 0x1b41 ++#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 ++#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41 ++#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41 ++#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141 ++#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341 ++#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 ++#define mmSCL_MODE 0x1b42 ++#define mmSCL0_SCL_MODE 0x1b42 ++#define mmSCL1_SCL_MODE 0x1d42 ++#define mmSCL2_SCL_MODE 0x1f42 ++#define mmSCL3_SCL_MODE 0x4142 ++#define mmSCL4_SCL_MODE 0x4342 ++#define mmSCL5_SCL_MODE 0x4542 ++#define mmSCL_TAP_CONTROL 0x1b43 ++#define mmSCL0_SCL_TAP_CONTROL 0x1b43 ++#define mmSCL1_SCL_TAP_CONTROL 0x1d43 ++#define mmSCL2_SCL_TAP_CONTROL 0x1f43 ++#define mmSCL3_SCL_TAP_CONTROL 0x4143 ++#define mmSCL4_SCL_TAP_CONTROL 0x4343 ++#define mmSCL5_SCL_TAP_CONTROL 0x4543 ++#define mmSCL_CONTROL 0x1b44 ++#define mmSCL0_SCL_CONTROL 0x1b44 ++#define mmSCL1_SCL_CONTROL 0x1d44 ++#define mmSCL2_SCL_CONTROL 0x1f44 ++#define mmSCL3_SCL_CONTROL 0x4144 ++#define mmSCL4_SCL_CONTROL 0x4344 ++#define mmSCL5_SCL_CONTROL 0x4544 ++#define mmSCL_BYPASS_CONTROL 0x1b45 ++#define mmSCL0_SCL_BYPASS_CONTROL 0x1b45 ++#define mmSCL1_SCL_BYPASS_CONTROL 0x1d45 ++#define mmSCL2_SCL_BYPASS_CONTROL 0x1f45 ++#define mmSCL3_SCL_BYPASS_CONTROL 0x4145 ++#define mmSCL4_SCL_BYPASS_CONTROL 0x4345 ++#define mmSCL5_SCL_BYPASS_CONTROL 0x4545 ++#define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 ++#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 ++#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46 ++#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46 ++#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146 ++#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346 ++#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546 ++#define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 ++#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 ++#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47 ++#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47 ++#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147 ++#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347 ++#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547 ++#define mmSCL_HORZ_FILTER_CONTROL 0x1b48 ++#define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 ++#define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48 ++#define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48 ++#define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148 ++#define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348 ++#define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548 ++#define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 ++#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 ++#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49 ++#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49 ++#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 ++#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349 ++#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549 ++#define mmSCL_HORZ_FILTER_INIT 0x1b4a ++#define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a ++#define mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a ++#define mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a ++#define mmSCL3_SCL_HORZ_FILTER_INIT 0x414a ++#define mmSCL4_SCL_HORZ_FILTER_INIT 0x434a ++#define mmSCL5_SCL_HORZ_FILTER_INIT 0x454a ++#define mmSCL_VERT_FILTER_CONTROL 0x1b4b ++#define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b ++#define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b ++#define mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b ++#define mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b ++#define mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b ++#define mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b ++#define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c ++#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c ++#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c ++#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c ++#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c ++#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c ++#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c ++#define mmSCL_VERT_FILTER_INIT 0x1b4d ++#define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d ++#define mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d ++#define mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d ++#define mmSCL3_SCL_VERT_FILTER_INIT 0x414d ++#define mmSCL4_SCL_VERT_FILTER_INIT 0x434d ++#define mmSCL5_SCL_VERT_FILTER_INIT 0x454d ++#define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e ++#define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e ++#define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e ++#define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e ++#define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e ++#define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e ++#define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e ++#define mmSCL_ROUND_OFFSET 0x1b4f ++#define mmSCL0_SCL_ROUND_OFFSET 0x1b4f ++#define mmSCL1_SCL_ROUND_OFFSET 0x1d4f ++#define mmSCL2_SCL_ROUND_OFFSET 0x1f4f ++#define mmSCL3_SCL_ROUND_OFFSET 0x414f ++#define mmSCL4_SCL_ROUND_OFFSET 0x434f ++#define mmSCL5_SCL_ROUND_OFFSET 0x454f ++#define mmSCL_UPDATE 0x1b51 ++#define mmSCL0_SCL_UPDATE 0x1b51 ++#define mmSCL1_SCL_UPDATE 0x1d51 ++#define mmSCL2_SCL_UPDATE 0x1f51 ++#define mmSCL3_SCL_UPDATE 0x4151 ++#define mmSCL4_SCL_UPDATE 0x4351 ++#define mmSCL5_SCL_UPDATE 0x4551 ++#define mmSCL_F_SHARP_CONTROL 0x1b53 ++#define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 ++#define mmSCL1_SCL_F_SHARP_CONTROL 0x1d53 ++#define mmSCL2_SCL_F_SHARP_CONTROL 0x1f53 ++#define mmSCL3_SCL_F_SHARP_CONTROL 0x4153 ++#define mmSCL4_SCL_F_SHARP_CONTROL 0x4353 ++#define mmSCL5_SCL_F_SHARP_CONTROL 0x4553 ++#define mmSCL_ALU_CONTROL 0x1b54 ++#define mmSCL0_SCL_ALU_CONTROL 0x1b54 ++#define mmSCL1_SCL_ALU_CONTROL 0x1d54 ++#define mmSCL2_SCL_ALU_CONTROL 0x1f54 ++#define mmSCL3_SCL_ALU_CONTROL 0x4154 ++#define mmSCL4_SCL_ALU_CONTROL 0x4354 ++#define mmSCL5_SCL_ALU_CONTROL 0x4554 ++#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 ++#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 ++#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55 ++#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55 ++#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 ++#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355 ++#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555 ++#define mmVIEWPORT_START_SECONDARY 0x1b5b ++#define mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b ++#define mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b ++#define mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b ++#define mmSCL3_VIEWPORT_START_SECONDARY 0x415b ++#define mmSCL4_VIEWPORT_START_SECONDARY 0x435b ++#define mmSCL5_VIEWPORT_START_SECONDARY 0x455b ++#define mmVIEWPORT_START 0x1b5c ++#define mmSCL0_VIEWPORT_START 0x1b5c ++#define mmSCL1_VIEWPORT_START 0x1d5c ++#define mmSCL2_VIEWPORT_START 0x1f5c ++#define mmSCL3_VIEWPORT_START 0x415c ++#define mmSCL4_VIEWPORT_START 0x435c ++#define mmSCL5_VIEWPORT_START 0x455c ++#define mmVIEWPORT_SIZE 0x1b5d ++#define mmSCL0_VIEWPORT_SIZE 0x1b5d ++#define mmSCL1_VIEWPORT_SIZE 0x1d5d ++#define mmSCL2_VIEWPORT_SIZE 0x1f5d ++#define mmSCL3_VIEWPORT_SIZE 0x415d ++#define mmSCL4_VIEWPORT_SIZE 0x435d ++#define mmSCL5_VIEWPORT_SIZE 0x455d ++#define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e ++#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e ++#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e ++#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e ++#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e ++#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e ++#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e ++#define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f ++#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f ++#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f ++#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f ++#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f ++#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f ++#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f ++#define mmSCL_MODE_CHANGE_DET1 0x1b60 ++#define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 ++#define mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60 ++#define mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60 ++#define mmSCL3_SCL_MODE_CHANGE_DET1 0x4160 ++#define mmSCL4_SCL_MODE_CHANGE_DET1 0x4360 ++#define mmSCL5_SCL_MODE_CHANGE_DET1 0x4560 ++#define mmSCL_MODE_CHANGE_DET2 0x1b61 ++#define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 ++#define mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61 ++#define mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61 ++#define mmSCL3_SCL_MODE_CHANGE_DET2 0x4161 ++#define mmSCL4_SCL_MODE_CHANGE_DET2 0x4361 ++#define mmSCL5_SCL_MODE_CHANGE_DET2 0x4561 ++#define mmSCL_MODE_CHANGE_DET3 0x1b62 ++#define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 ++#define mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62 ++#define mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62 ++#define mmSCL3_SCL_MODE_CHANGE_DET3 0x4162 ++#define mmSCL4_SCL_MODE_CHANGE_DET3 0x4362 ++#define mmSCL5_SCL_MODE_CHANGE_DET3 0x4562 ++#define mmSCL_MODE_CHANGE_MASK 0x1b63 ++#define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 ++#define mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63 ++#define mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63 ++#define mmSCL3_SCL_MODE_CHANGE_MASK 0x4163 ++#define mmSCL4_SCL_MODE_CHANGE_MASK 0x4363 ++#define mmSCL5_SCL_MODE_CHANGE_MASK 0x4563 ++#define mmSCL_DEBUG2 0x1b69 ++#define mmSCL0_SCL_DEBUG2 0x1b69 ++#define mmSCL1_SCL_DEBUG2 0x1d69 ++#define mmSCL2_SCL_DEBUG2 0x1f69 ++#define mmSCL3_SCL_DEBUG2 0x4169 ++#define mmSCL4_SCL_DEBUG2 0x4369 ++#define mmSCL5_SCL_DEBUG2 0x4569 ++#define mmSCL_DEBUG 0x1b6a ++#define mmSCL0_SCL_DEBUG 0x1b6a ++#define mmSCL1_SCL_DEBUG 0x1d6a ++#define mmSCL2_SCL_DEBUG 0x1f6a ++#define mmSCL3_SCL_DEBUG 0x416a ++#define mmSCL4_SCL_DEBUG 0x436a ++#define mmSCL5_SCL_DEBUG 0x456a ++#define mmSCL_TEST_DEBUG_INDEX 0x1b6b ++#define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b ++#define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b ++#define mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b ++#define mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b ++#define mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b ++#define mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b ++#define mmSCL_TEST_DEBUG_DATA 0x1b6c ++#define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c ++#define mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c ++#define mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c ++#define mmSCL3_SCL_TEST_DEBUG_DATA 0x416c ++#define mmSCL4_SCL_TEST_DEBUG_DATA 0x436c ++#define mmSCL5_SCL_TEST_DEBUG_DATA 0x456c ++#define mmSCLV_COEF_RAM_SELECT 0x4670 ++#define mmSCLV_COEF_RAM_TAP_DATA 0x4671 ++#define mmSCLV_MODE 0x4672 ++#define mmSCLV_TAP_CONTROL 0x4673 ++#define mmSCLV_CONTROL 0x4674 ++#define mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675 ++#define mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676 ++#define mmSCLV_HORZ_FILTER_CONTROL 0x4677 ++#define mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678 ++#define mmSCLV_HORZ_FILTER_INIT 0x4679 ++#define mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a ++#define mmSCLV_HORZ_FILTER_INIT_C 0x467b ++#define mmSCLV_VERT_FILTER_CONTROL 0x467c ++#define mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d ++#define mmSCLV_VERT_FILTER_INIT 0x467e ++#define mmSCLV_VERT_FILTER_INIT_BOT 0x467f ++#define mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680 ++#define mmSCLV_VERT_FILTER_INIT_C 0x4681 ++#define mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682 ++#define mmSCLV_ROUND_OFFSET 0x4683 ++#define mmSCLV_UPDATE 0x4684 ++#define mmSCLV_ALU_CONTROL 0x4685 ++#define mmSCLV_VIEWPORT_START 0x4686 ++#define mmSCLV_VIEWPORT_START_SECONDARY 0x4687 ++#define mmSCLV_VIEWPORT_SIZE 0x4688 ++#define mmSCLV_VIEWPORT_START_C 0x4689 ++#define mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a ++#define mmSCLV_VIEWPORT_SIZE_C 0x468b ++#define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c ++#define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d ++#define mmSCLV_MODE_CHANGE_DET1 0x468e ++#define mmSCLV_MODE_CHANGE_DET2 0x468f ++#define mmSCLV_MODE_CHANGE_DET3 0x4690 ++#define mmSCLV_MODE_CHANGE_MASK 0x4691 ++#define mmSCLV_HORZ_FILTER_INIT_BOT 0x4692 ++#define mmSCLV_HORZ_FILTER_INIT_BOT_C 0x4693 ++#define mmSCLV_DEBUG2 0x4694 ++#define mmSCLV_DEBUG 0x4695 ++#define mmSCLV_TEST_DEBUG_INDEX 0x4696 ++#define mmSCLV_TEST_DEBUG_DATA 0x4697 ++#define mmCOL_MAN_UPDATE 0x46a4 ++#define mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5 ++#define mmINPUT_CSC_C11_C12_A 0x46a6 ++#define mmINPUT_CSC_C13_C14_A 0x46a7 ++#define mmINPUT_CSC_C21_C22_A 0x46a8 ++#define mmINPUT_CSC_C23_C24_A 0x46a9 ++#define mmINPUT_CSC_C31_C32_A 0x46aa ++#define mmINPUT_CSC_C33_C34_A 0x46ab ++#define mmINPUT_CSC_C11_C12_B 0x46ac ++#define mmINPUT_CSC_C13_C14_B 0x46ad ++#define mmINPUT_CSC_C21_C22_B 0x46ae ++#define mmINPUT_CSC_C23_C24_B 0x46af ++#define mmINPUT_CSC_C31_C32_B 0x46b0 ++#define mmINPUT_CSC_C33_C34_B 0x46b1 ++#define mmPRESCALE_CONTROL 0x46b2 ++#define mmPRESCALE_VALUES_R 0x46b3 ++#define mmPRESCALE_VALUES_G 0x46b4 ++#define mmPRESCALE_VALUES_B 0x46b5 ++#define mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6 ++#define mmOUTPUT_CSC_C11_C12_A 0x46b7 ++#define mmOUTPUT_CSC_C13_C14_A 0x46b8 ++#define mmOUTPUT_CSC_C21_C22_A 0x46b9 ++#define mmOUTPUT_CSC_C23_C24_A 0x46ba ++#define mmOUTPUT_CSC_C31_C32_A 0x46bb ++#define mmOUTPUT_CSC_C33_C34_A 0x46bc ++#define mmOUTPUT_CSC_C11_C12_B 0x46bd ++#define mmOUTPUT_CSC_C13_C14_B 0x46be ++#define mmOUTPUT_CSC_C21_C22_B 0x46bf ++#define mmOUTPUT_CSC_C23_C24_B 0x46c0 ++#define mmOUTPUT_CSC_C31_C32_B 0x46c1 ++#define mmOUTPUT_CSC_C33_C34_B 0x46c2 ++#define mmDENORM_CLAMP_CONTROL 0x46c3 ++#define mmDENORM_CLAMP_RANGE_R_CR 0x46c4 ++#define mmDENORM_CLAMP_RANGE_G_Y 0x46c5 ++#define mmDENORM_CLAMP_RANGE_B_CB 0x46c6 ++#define mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7 ++#define mmGAMMA_CORR_CONTROL 0x46c8 ++#define mmGAMMA_CORR_LUT_INDEX 0x46c9 ++#define mmGAMMA_CORR_LUT_DATA 0x46ca ++#define mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb ++#define mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc ++#define mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd ++#define mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce ++#define mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf ++#define mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0 ++#define mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1 ++#define mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2 ++#define mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3 ++#define mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4 ++#define mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5 ++#define mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6 ++#define mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7 ++#define mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8 ++#define mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9 ++#define mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da ++#define mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db ++#define mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc ++#define mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd ++#define mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de ++#define mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df ++#define mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0 ++#define mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1 ++#define mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2 ++#define mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3 ++#define mmPACK_FIFO_ERROR 0x46e4 ++#define mmOUTPUT_FIFO_ERROR 0x46e5 ++#define mmINPUT_GAMMA_LUT_AUTOFILL 0x46e6 ++#define mmINPUT_GAMMA_LUT_RW_INDEX 0x46e7 ++#define mmINPUT_GAMMA_LUT_SEQ_COLOR 0x46e8 ++#define mmINPUT_GAMMA_LUT_PWL_DATA 0x46e9 ++#define mmINPUT_GAMMA_LUT_30_COLOR 0x46ea ++#define mmCOL_MAN_INPUT_GAMMA_CONTROL1 0x46eb ++#define mmCOL_MAN_INPUT_GAMMA_CONTROL2 0x46ec ++#define mmINPUT_GAMMA_BW_OFFSETS_B 0x46ed ++#define mmINPUT_GAMMA_BW_OFFSETS_G 0x46ee ++#define mmINPUT_GAMMA_BW_OFFSETS_R 0x46ef ++#define mmCOL_MAN_DEBUG_CONTROL 0x46f0 ++#define mmCOL_MAN_TEST_DEBUG_INDEX 0x46f1 ++#define mmCOL_MAN_TEST_DEBUG_DATA 0x46f3 ++#define mmUNP_GRPH_ENABLE 0x4600 ++#define mmUNP_GRPH_CONTROL 0x4601 ++#define mmUNP_GRPH_CONTROL_C 0x4602 ++#define mmUNP_GRPH_CONTROL_EXP 0x4603 ++#define mmUNP_GRPH_SWAP_CNTL 0x4605 ++#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606 ++#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607 ++#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608 ++#define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609 ++#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a ++#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b ++#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c ++#define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d ++#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e ++#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f ++#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610 ++#define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611 ++#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612 ++#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613 ++#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614 ++#define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615 ++#define mmUNP_GRPH_PITCH_L 0x4616 ++#define mmUNP_GRPH_PITCH_C 0x4617 ++#define mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618 ++#define mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619 ++#define mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a ++#define mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b ++#define mmUNP_GRPH_X_START_L 0x461c ++#define mmUNP_GRPH_X_START_C 0x461d ++#define mmUNP_GRPH_Y_START_L 0x461e ++#define mmUNP_GRPH_Y_START_C 0x461f ++#define mmUNP_GRPH_X_END_L 0x4620 ++#define mmUNP_GRPH_X_END_C 0x4621 ++#define mmUNP_GRPH_Y_END_L 0x4622 ++#define mmUNP_GRPH_Y_END_C 0x4623 ++#define mmUNP_GRPH_UPDATE 0x4624 ++#define mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x463a ++#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625 ++#define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626 ++#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627 ++#define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628 ++#define mmUNP_DVMM_PTE_CONTROL 0x4629 ++#define mmUNP_DVMM_PTE_CONTROL_C 0x4604 ++#define mmUNP_DVMM_PTE_ARB_CONTROL 0x462a ++#define mmUNP_DVMM_PTE_ARB_CONTROL_C 0x462d ++#define mmUNP_GRPH_INTERRUPT_STATUS 0x462b ++#define mmUNP_GRPH_INTERRUPT_CONTROL 0x462c ++#define mmUNP_GRPH_STEREOSYNC_FLIP 0x462e ++#define mmUNP_FLIP_CONTROL 0x462f ++#define mmUNP_CRC_CONTROL 0x4630 ++#define mmUNP_CRC_MASK 0x4631 ++#define mmUNP_CRC_CURRENT 0x4632 ++#define mmUNP_CRC_LAST 0x4633 ++#define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634 ++#define mmUNP_HW_ROTATION 0x4635 ++#define mmUNP_DEBUG 0x4636 ++#define mmUNP_DEBUG2 0x4637 ++#define mmUNP_DVMM_DEBUG 0x463b ++#define mmUNP_TEST_DEBUG_INDEX 0x4638 ++#define mmUNP_TEST_DEBUG_DATA 0x4639 ++#define mmGENMO_WT 0xf0 ++#define mmGENMO_RD 0xf3 ++#define mmGENENB 0xf0 ++#define mmGENFC_WT 0xee ++#define mmVGA0_GENFC_WT 0xee ++#define mmVGA1_GENFC_WT 0xf6 ++#define mmGENFC_RD 0xf2 ++#define mmGENS0 0xf0 ++#define mmGENS1 0xee ++#define mmVGA0_GENS1 0xee ++#define mmVGA1_GENS1 0xf6 ++#define mmDAC_DATA 0xf2 ++#define mmDAC_MASK 0xf1 ++#define mmDAC_R_INDEX 0xf1 ++#define mmDAC_W_INDEX 0xf2 ++#define mmSEQ8_IDX 0xf1 ++#define mmSEQ8_DATA 0xf1 ++#define ixSEQ00 0x0 ++#define ixSEQ01 0x1 ++#define ixSEQ02 0x2 ++#define ixSEQ03 0x3 ++#define ixSEQ04 0x4 ++#define mmCRTC8_IDX 0xed ++#define mmVGA0_CRTC8_IDX 0xed ++#define mmVGA1_CRTC8_IDX 0xf5 ++#define mmCRTC8_DATA 0xed ++#define mmVGA0_CRTC8_DATA 0xed ++#define mmVGA1_CRTC8_DATA 0xf5 ++#define ixCRT00 0x0 ++#define ixCRT01 0x1 ++#define ixCRT02 0x2 ++#define ixCRT03 0x3 ++#define ixCRT04 0x4 ++#define ixCRT05 0x5 ++#define ixCRT06 0x6 ++#define ixCRT07 0x7 ++#define ixCRT08 0x8 ++#define ixCRT09 0x9 ++#define ixCRT0A 0xa ++#define ixCRT0B 0xb ++#define ixCRT0C 0xc ++#define ixCRT0D 0xd ++#define ixCRT0E 0xe ++#define ixCRT0F 0xf ++#define ixCRT10 0x10 ++#define ixCRT11 0x11 ++#define ixCRT12 0x12 ++#define ixCRT13 0x13 ++#define ixCRT14 0x14 ++#define ixCRT15 0x15 ++#define ixCRT16 0x16 ++#define ixCRT17 0x17 ++#define ixCRT18 0x18 ++#define ixCRT1E 0x1e ++#define ixCRT1F 0x1f ++#define ixCRT22 0x22 ++#define mmGRPH8_IDX 0xf3 ++#define mmGRPH8_DATA 0xf3 ++#define ixGRA00 0x0 ++#define ixGRA01 0x1 ++#define ixGRA02 0x2 ++#define ixGRA03 0x3 ++#define ixGRA04 0x4 ++#define ixGRA05 0x5 ++#define ixGRA06 0x6 ++#define ixGRA07 0x7 ++#define ixGRA08 0x8 ++#define mmATTRX 0xf0 ++#define mmATTRDW 0xf0 ++#define mmATTRDR 0xf0 ++#define ixATTR00 0x0 ++#define ixATTR01 0x1 ++#define ixATTR02 0x2 ++#define ixATTR03 0x3 ++#define ixATTR04 0x4 ++#define ixATTR05 0x5 ++#define ixATTR06 0x6 ++#define ixATTR07 0x7 ++#define ixATTR08 0x8 ++#define ixATTR09 0x9 ++#define ixATTR0A 0xa ++#define ixATTR0B 0xb ++#define ixATTR0C 0xc ++#define ixATTR0D 0xd ++#define ixATTR0E 0xe ++#define ixATTR0F 0xf ++#define ixATTR10 0x10 ++#define ixATTR11 0x11 ++#define ixATTR12 0x12 ++#define ixATTR13 0x13 ++#define ixATTR14 0x14 ++#define mmVGA_RENDER_CONTROL 0xc0 ++#define mmVGA_SOURCE_SELECT 0xfc ++#define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 ++#define mmVGA_MODE_CONTROL 0xc2 ++#define mmVGA_SURFACE_PITCH_SELECT 0xc3 ++#define mmVGA_MEMORY_BASE_ADDRESS 0xc4 ++#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 ++#define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 ++#define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 ++#define mmVGA_HDP_CONTROL 0xca ++#define mmVGA_CACHE_CONTROL 0xcb ++#define mmD1VGA_CONTROL 0xcc ++#define mmD2VGA_CONTROL 0xce ++#define mmD3VGA_CONTROL 0xf8 ++#define mmD4VGA_CONTROL 0xf9 ++#define mmD5VGA_CONTROL 0xfa ++#define mmD6VGA_CONTROL 0xfb ++#define mmVGA_HW_DEBUG 0xcf ++#define mmVGA_STATUS 0xd0 ++#define mmVGA_INTERRUPT_CONTROL 0xd1 ++#define mmVGA_STATUS_CLEAR 0xd2 ++#define mmVGA_INTERRUPT_STATUS 0xd3 ++#define mmVGA_MAIN_CONTROL 0xd4 ++#define mmVGA_TEST_CONTROL 0xd5 ++#define mmVGA_DEBUG_READBACK_INDEX 0xd6 ++#define mmVGA_DEBUG_READBACK_DATA 0xd7 ++#define mmVGA_MEM_WRITE_PAGE_ADDR 0x12 ++#define mmVGA_MEM_READ_PAGE_ADDR 0x13 ++#define mmVGA_TEST_DEBUG_INDEX 0xc5 ++#define mmVGA_TEST_DEBUG_DATA 0xc7 ++#define ixVGADCC_DBG_DCCIF_C 0x7e ++#define mmBPHYC_DAC_MACRO_CNTL 0x48b9 ++#define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba ++#define mmPLL_REF_DIV 0x1700 ++#define mmBPHYC_PLL0_PLL_REF_DIV 0x1700 ++#define mmBPHYC_PLL1_PLL_REF_DIV 0x172a ++#define mmBPHYC_PLL2_PLL_REF_DIV 0x1754 ++#define mmPLL_FB_DIV 0x1701 ++#define mmBPHYC_PLL0_PLL_FB_DIV 0x1701 ++#define mmBPHYC_PLL1_PLL_FB_DIV 0x172b ++#define mmBPHYC_PLL2_PLL_FB_DIV 0x1755 ++#define mmPLL_POST_DIV 0x1702 ++#define mmBPHYC_PLL0_PLL_POST_DIV 0x1702 ++#define mmBPHYC_PLL1_PLL_POST_DIV 0x172c ++#define mmBPHYC_PLL2_PLL_POST_DIV 0x1756 ++#define mmPLL_SS_AMOUNT_DSFRAC 0x1703 ++#define mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 ++#define mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC 0x172d ++#define mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1757 ++#define mmPLL_SS_CNTL 0x1704 ++#define mmBPHYC_PLL0_PLL_SS_CNTL 0x1704 ++#define mmBPHYC_PLL1_PLL_SS_CNTL 0x172e ++#define mmBPHYC_PLL2_PLL_SS_CNTL 0x1758 ++#define mmPLL_DS_CNTL 0x1705 ++#define mmBPHYC_PLL0_PLL_DS_CNTL 0x1705 ++#define mmBPHYC_PLL1_PLL_DS_CNTL 0x172f ++#define mmBPHYC_PLL2_PLL_DS_CNTL 0x1759 ++#define mmPLL_IDCLK_CNTL 0x1706 ++#define mmBPHYC_PLL0_PLL_IDCLK_CNTL 0x1706 ++#define mmBPHYC_PLL1_PLL_IDCLK_CNTL 0x1730 ++#define mmBPHYC_PLL2_PLL_IDCLK_CNTL 0x175a ++#define mmPLL_CNTL 0x1707 ++#define mmBPHYC_PLL0_PLL_CNTL 0x1707 ++#define mmBPHYC_PLL1_PLL_CNTL 0x1731 ++#define mmBPHYC_PLL2_PLL_CNTL 0x175b ++#define mmPLL_ANALOG 0x1708 ++#define mmBPHYC_PLL0_PLL_ANALOG 0x1708 ++#define mmBPHYC_PLL1_PLL_ANALOG 0x1732 ++#define mmBPHYC_PLL2_PLL_ANALOG 0x175c ++#define mmPLL_VREG_CNTL 0x1709 ++#define mmBPHYC_PLL0_PLL_VREG_CNTL 0x1709 ++#define mmBPHYC_PLL1_PLL_VREG_CNTL 0x1733 ++#define mmBPHYC_PLL2_PLL_VREG_CNTL 0x175d ++#define mmPLL_UNLOCK_DETECT_CNTL 0x170a ++#define mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a ++#define mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL 0x1734 ++#define mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL 0x175e ++#define mmPLL_DEBUG_CNTL 0x170b ++#define mmBPHYC_PLL0_PLL_DEBUG_CNTL 0x170b ++#define mmBPHYC_PLL1_PLL_DEBUG_CNTL 0x1735 ++#define mmBPHYC_PLL2_PLL_DEBUG_CNTL 0x175f ++#define mmPLL_UPDATE_LOCK 0x170c ++#define mmBPHYC_PLL0_PLL_UPDATE_LOCK 0x170c ++#define mmBPHYC_PLL1_PLL_UPDATE_LOCK 0x1736 ++#define mmBPHYC_PLL2_PLL_UPDATE_LOCK 0x1760 ++#define mmPLL_UPDATE_CNTL 0x170d ++#define mmBPHYC_PLL0_PLL_UPDATE_CNTL 0x170d ++#define mmBPHYC_PLL1_PLL_UPDATE_CNTL 0x1737 ++#define mmBPHYC_PLL2_PLL_UPDATE_CNTL 0x1761 ++#define mmPLL_XOR_LOCK 0x1710 ++#define mmBPHYC_PLL0_PLL_XOR_LOCK 0x1710 ++#define mmBPHYC_PLL1_PLL_XOR_LOCK 0x173a ++#define mmBPHYC_PLL2_PLL_XOR_LOCK 0x1764 ++#define mmPLL_ANALOG_CNTL 0x1711 ++#define mmBPHYC_PLL0_PLL_ANALOG_CNTL 0x1711 ++#define mmBPHYC_PLL1_PLL_ANALOG_CNTL 0x173b ++#define mmBPHYC_PLL2_PLL_ANALOG_CNTL 0x1765 ++#define mmVGA25_PPLL_REF_DIV 0x1712 ++#define mmBPHYC_PLL0_VGA25_PPLL_REF_DIV 0x1712 ++#define mmBPHYC_PLL1_VGA25_PPLL_REF_DIV 0x173c ++#define mmBPHYC_PLL2_VGA25_PPLL_REF_DIV 0x1766 ++#define mmVGA28_PPLL_REF_DIV 0x1713 ++#define mmBPHYC_PLL0_VGA28_PPLL_REF_DIV 0x1713 ++#define mmBPHYC_PLL1_VGA28_PPLL_REF_DIV 0x173d ++#define mmBPHYC_PLL2_VGA28_PPLL_REF_DIV 0x1767 ++#define mmVGA41_PPLL_REF_DIV 0x1714 ++#define mmBPHYC_PLL0_VGA41_PPLL_REF_DIV 0x1714 ++#define mmBPHYC_PLL1_VGA41_PPLL_REF_DIV 0x173e ++#define mmBPHYC_PLL2_VGA41_PPLL_REF_DIV 0x1768 ++#define mmVGA25_PPLL_FB_DIV 0x1715 ++#define mmBPHYC_PLL0_VGA25_PPLL_FB_DIV 0x1715 ++#define mmBPHYC_PLL1_VGA25_PPLL_FB_DIV 0x173f ++#define mmBPHYC_PLL2_VGA25_PPLL_FB_DIV 0x1769 ++#define mmVGA28_PPLL_FB_DIV 0x1716 ++#define mmBPHYC_PLL0_VGA28_PPLL_FB_DIV 0x1716 ++#define mmBPHYC_PLL1_VGA28_PPLL_FB_DIV 0x1740 ++#define mmBPHYC_PLL2_VGA28_PPLL_FB_DIV 0x176a ++#define mmVGA41_PPLL_FB_DIV 0x1717 ++#define mmBPHYC_PLL0_VGA41_PPLL_FB_DIV 0x1717 ++#define mmBPHYC_PLL1_VGA41_PPLL_FB_DIV 0x1741 ++#define mmBPHYC_PLL2_VGA41_PPLL_FB_DIV 0x176b ++#define mmVGA25_PPLL_POST_DIV 0x1718 ++#define mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718 ++#define mmBPHYC_PLL1_VGA25_PPLL_POST_DIV 0x1742 ++#define mmBPHYC_PLL2_VGA25_PPLL_POST_DIV 0x176c ++#define mmVGA28_PPLL_POST_DIV 0x1719 ++#define mmBPHYC_PLL0_VGA28_PPLL_POST_DIV 0x1719 ++#define mmBPHYC_PLL1_VGA28_PPLL_POST_DIV 0x1743 ++#define mmBPHYC_PLL2_VGA28_PPLL_POST_DIV 0x176d ++#define mmVGA41_PPLL_POST_DIV 0x171a ++#define mmBPHYC_PLL0_VGA41_PPLL_POST_DIV 0x171a ++#define mmBPHYC_PLL1_VGA41_PPLL_POST_DIV 0x1744 ++#define mmBPHYC_PLL2_VGA41_PPLL_POST_DIV 0x176e ++#define mmVGA25_PPLL_ANALOG 0x171b ++#define mmBPHYC_PLL0_VGA25_PPLL_ANALOG 0x171b ++#define mmBPHYC_PLL1_VGA25_PPLL_ANALOG 0x1745 ++#define mmBPHYC_PLL2_VGA25_PPLL_ANALOG 0x176f ++#define mmVGA28_PPLL_ANALOG 0x171c ++#define mmBPHYC_PLL0_VGA28_PPLL_ANALOG 0x171c ++#define mmBPHYC_PLL1_VGA28_PPLL_ANALOG 0x1746 ++#define mmBPHYC_PLL2_VGA28_PPLL_ANALOG 0x1770 ++#define mmVGA41_PPLL_ANALOG 0x171d ++#define mmBPHYC_PLL0_VGA41_PPLL_ANALOG 0x171d ++#define mmBPHYC_PLL1_VGA41_PPLL_ANALOG 0x1747 ++#define mmBPHYC_PLL2_VGA41_PPLL_ANALOG 0x1771 ++#define mmDISPPLL_BG_CNTL 0x171e ++#define mmBPHYC_PLL0_DISPPLL_BG_CNTL 0x171e ++#define mmBPHYC_PLL1_DISPPLL_BG_CNTL 0x1748 ++#define mmBPHYC_PLL2_DISPPLL_BG_CNTL 0x1772 ++#define mmPPLL_DIV_UPDATE_DEBUG 0x171f ++#define mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG 0x171f ++#define mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG 0x1749 ++#define mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG 0x1773 ++#define mmPPLL_STATUS_DEBUG 0x1720 ++#define mmBPHYC_PLL0_PPLL_STATUS_DEBUG 0x1720 ++#define mmBPHYC_PLL1_PPLL_STATUS_DEBUG 0x174a ++#define mmBPHYC_PLL2_PPLL_STATUS_DEBUG 0x1774 ++#define mmPPLL_DEBUG_MUX_CNTL 0x1721 ++#define mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL 0x1721 ++#define mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL 0x174b ++#define mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL 0x1775 ++#define mmPPLL_SPARE0 0x1722 ++#define mmBPHYC_PLL0_PPLL_SPARE0 0x1722 ++#define mmBPHYC_PLL1_PPLL_SPARE0 0x174c ++#define mmBPHYC_PLL2_PPLL_SPARE0 0x1776 ++#define mmPPLL_SPARE1 0x1723 ++#define mmBPHYC_PLL0_PPLL_SPARE1 0x1723 ++#define mmBPHYC_PLL1_PPLL_SPARE1 0x174d ++#define mmBPHYC_PLL2_PPLL_SPARE1 0x1777 ++#define mmUNIPHY_TX_CONTROL1 0x48c0 ++#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 0x48c0 ++#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 0x48e0 ++#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 0x4900 ++#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 0x4920 ++#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 0x4940 ++#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 0x4960 ++#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 0x4980 ++#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL1 0x49c0 ++#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL1 0x49e0 ++#define mmUNIPHY_TX_CONTROL2 0x48c1 ++#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 0x48c1 ++#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 0x48e1 ++#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 0x4901 ++#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 0x4921 ++#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 0x4941 ++#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 0x4961 ++#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 0x4981 ++#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL2 0x49c1 ++#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL2 0x49e1 ++#define mmUNIPHY_TX_CONTROL3 0x48c2 ++#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 0x48c2 ++#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 0x48e2 ++#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 0x4902 ++#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 0x4922 ++#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 0x4942 ++#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 0x4962 ++#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 0x4982 ++#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL3 0x49c2 ++#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL3 0x49e2 ++#define mmUNIPHY_TX_CONTROL4 0x48c3 ++#define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 0x48c3 ++#define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 0x48e3 ++#define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 0x4903 ++#define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 0x4923 ++#define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 0x4943 ++#define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 0x4963 ++#define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 0x4983 ++#define mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL4 0x49c3 ++#define mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL4 0x49e3 ++#define mmUNIPHY_POWER_CONTROL 0x48c4 ++#define mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL 0x48c4 ++#define mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL 0x48e4 ++#define mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL 0x4904 ++#define mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL 0x4924 ++#define mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL 0x4944 ++#define mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL 0x4964 ++#define mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL 0x4984 ++#define mmBPHYC_UNIPHY7_UNIPHY_POWER_CONTROL 0x49c4 ++#define mmBPHYC_UNIPHY8_UNIPHY_POWER_CONTROL 0x49e4 ++#define mmUNIPHY_PLL_FBDIV 0x48c5 ++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV 0x48c5 ++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV 0x48e5 ++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV 0x4905 ++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV 0x4925 ++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV 0x4945 ++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV 0x4965 ++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV 0x4985 ++#define mmBPHYC_UNIPHY7_UNIPHY_PLL_FBDIV 0x49c5 ++#define mmBPHYC_UNIPHY8_UNIPHY_PLL_FBDIV 0x49e5 ++#define mmUNIPHY_PLL_CONTROL1 0x48c6 ++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 0x48c6 ++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 0x48e6 ++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 0x4906 ++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 0x4926 ++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 0x4946 ++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 0x4966 ++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4986 ++#define mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL1 0x49c6 ++#define mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL1 0x49e6 ++#define mmUNIPHY_PLL_CONTROL2 0x48c7 ++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 0x48c7 ++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 0x48e7 ++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 0x4907 ++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 0x4927 ++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 0x4947 ++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 0x4967 ++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4987 ++#define mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL2 0x49c7 ++#define mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL2 0x49e7 ++#define mmUNIPHY_PLL_SS_STEP_SIZE 0x48c8 ++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x48c8 ++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x48e8 ++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x4908 ++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x4928 ++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x4948 ++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x4968 ++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4988 ++#define mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_STEP_SIZE 0x49c8 ++#define mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_STEP_SIZE 0x49e8 ++#define mmUNIPHY_PLL_SS_CNTL 0x48c9 ++#define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x48c9 ++#define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x48e9 ++#define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x4909 ++#define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x4929 ++#define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x4949 ++#define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x4969 ++#define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4989 ++#define mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_CNTL 0x49c9 ++#define mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_CNTL 0x49e9 ++#define mmUNIPHY_DATA_SYNCHRONIZATION 0x48ca ++#define mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x48ca ++#define mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x48ea ++#define mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x490a ++#define mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x492a ++#define mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x494a ++#define mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x496a ++#define mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x498a ++#define mmBPHYC_UNIPHY7_UNIPHY_DATA_SYNCHRONIZATION 0x49ca ++#define mmBPHYC_UNIPHY8_UNIPHY_DATA_SYNCHRONIZATION 0x49ea ++#define mmUNIPHY_REG_TEST_OUTPUT 0x48cb ++#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x48cb ++#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x48eb ++#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x490b ++#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x492b ++#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x494b ++#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x496b ++#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x498b ++#define mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT 0x49cb ++#define mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT 0x49eb ++#define mmUNIPHY_ANG_BIST_CNTL 0x48cc ++#define mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x48cc ++#define mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x48ec ++#define mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x490c ++#define mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x492c ++#define mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x494c ++#define mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x496c ++#define mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x498c ++#define mmBPHYC_UNIPHY7_UNIPHY_ANG_BIST_CNTL 0x49cc ++#define mmBPHYC_UNIPHY8_UNIPHY_ANG_BIST_CNTL 0x49ec ++#define mmUNIPHY_REG_TEST_OUTPUT2 0x48cd ++#define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x48cd ++#define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x48ed ++#define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x490d ++#define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x492d ++#define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x494d ++#define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x496d ++#define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x498d ++#define mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT2 0x49cd ++#define mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT2 0x49ed ++#define mmUNIPHY_TMDP_REG0 0x48ce ++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0 0x48ce ++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0 0x48ee ++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0 0x490e ++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0 0x492e ++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0 0x494e ++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0 0x496e ++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0 0x498e ++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG0 0x49ce ++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG0 0x49ee ++#define mmUNIPHY_TMDP_REG1 0x48cf ++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1 0x48cf ++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1 0x48ef ++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1 0x490f ++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1 0x492f ++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1 0x494f ++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1 0x496f ++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1 0x498f ++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG1 0x49cf ++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG1 0x49ef ++#define mmUNIPHY_TMDP_REG2 0x48d0 ++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2 0x48d0 ++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2 0x48f0 ++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2 0x4910 ++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2 0x4930 ++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2 0x4950 ++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2 0x4970 ++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2 0x4990 ++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG2 0x49d0 ++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG2 0x49f0 ++#define mmUNIPHY_TMDP_REG3 0x48d1 ++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3 0x48d1 ++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3 0x48f1 ++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3 0x4911 ++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3 0x4931 ++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3 0x4951 ++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3 0x4971 ++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3 0x4991 ++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG3 0x49d1 ++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG3 0x49f1 ++#define mmUNIPHY_TMDP_REG4 0x48d2 ++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4 0x48d2 ++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4 0x48f2 ++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4 0x4912 ++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4 0x4932 ++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4 0x4952 ++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4 0x4972 ++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4 0x4992 ++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG4 0x49d2 ++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG4 0x49f2 ++#define mmUNIPHY_TMDP_REG5 0x48d3 ++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5 0x48d3 ++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5 0x48f3 ++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5 0x4913 ++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5 0x4933 ++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5 0x4953 ++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5 0x4973 ++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5 0x4993 ++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG5 0x49d3 ++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG5 0x49f3 ++#define mmUNIPHY_TMDP_REG6 0x48d4 ++#define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6 0x48d4 ++#define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6 0x48f4 ++#define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6 0x4914 ++#define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6 0x4934 ++#define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6 0x4954 ++#define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6 0x4974 ++#define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6 0x4994 ++#define mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG6 0x49d4 ++#define mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG6 0x49f4 ++#define mmUNIPHY_TPG_CONTROL 0x48d5 ++#define mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL 0x48d5 ++#define mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL 0x48f5 ++#define mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL 0x4915 ++#define mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL 0x4935 ++#define mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL 0x4955 ++#define mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL 0x4975 ++#define mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL 0x4995 ++#define mmBPHYC_UNIPHY7_UNIPHY_TPG_CONTROL 0x49d5 ++#define mmBPHYC_UNIPHY8_UNIPHY_TPG_CONTROL 0x49f5 ++#define mmUNIPHY_TPG_SEED 0x48d6 ++#define mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED 0x48d6 ++#define mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED 0x48f6 ++#define mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED 0x4916 ++#define mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED 0x4936 ++#define mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED 0x4956 ++#define mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED 0x4976 ++#define mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED 0x4996 ++#define mmBPHYC_UNIPHY7_UNIPHY_TPG_SEED 0x49d6 ++#define mmBPHYC_UNIPHY8_UNIPHY_TPG_SEED 0x49f6 ++#define mmUNIPHY_DEBUG 0x48d7 ++#define mmBPHYC_UNIPHY0_UNIPHY_DEBUG 0x48d7 ++#define mmBPHYC_UNIPHY1_UNIPHY_DEBUG 0x48f7 ++#define mmBPHYC_UNIPHY2_UNIPHY_DEBUG 0x4917 ++#define mmBPHYC_UNIPHY3_UNIPHY_DEBUG 0x4937 ++#define mmBPHYC_UNIPHY4_UNIPHY_DEBUG 0x4957 ++#define mmBPHYC_UNIPHY5_UNIPHY_DEBUG 0x4977 ++#define mmBPHYC_UNIPHY6_UNIPHY_DEBUG 0x4997 ++#define mmBPHYC_UNIPHY7_UNIPHY_DEBUG 0x49d7 ++#define mmBPHYC_UNIPHY8_UNIPHY_DEBUG 0x49f7 ++#define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 ++#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 ++#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30 ++#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30 ++#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 ++#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330 ++#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530 ++#define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 ++#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 ++#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31 ++#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31 ++#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 ++#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331 ++#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531 ++#define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 ++#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 ++#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32 ++#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32 ++#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132 ++#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332 ++#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532 ++#define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 ++#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 ++#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33 ++#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33 ++#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133 ++#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333 ++#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533 ++#define mmDPG_PIPE_DPM_CONTROL 0x1b34 ++#define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 ++#define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34 ++#define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34 ++#define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134 ++#define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334 ++#define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534 ++#define mmDPG_PIPE_STUTTER_CONTROL 0x1b35 ++#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 ++#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35 ++#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35 ++#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135 ++#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335 ++#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535 ++#define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 ++#define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 ++#define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36 ++#define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36 ++#define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 ++#define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336 ++#define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536 ++#define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 ++#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 ++#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37 ++#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37 ++#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 ++#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337 ++#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537 ++#define mmDPG_REPEATER_PROGRAM 0x1b3a ++#define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a ++#define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a ++#define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a ++#define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a ++#define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a ++#define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a ++#define mmDPG_HW_DEBUG_A 0x1b3b ++#define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b ++#define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b ++#define mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b ++#define mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b ++#define mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b ++#define mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b ++#define mmDPG_HW_DEBUG_B 0x1b3c ++#define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c ++#define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c ++#define mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c ++#define mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c ++#define mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c ++#define mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c ++#define mmDPG_HW_DEBUG_11 0x1b3d ++#define mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d ++#define mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d ++#define mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d ++#define mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d ++#define mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d ++#define mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d ++#define mmDPG_CHK_PRE_PROC_CNTL 0x1b3e ++#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x1b3e ++#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x1d3e ++#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x1f3e ++#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x413e ++#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x433e ++#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x453e ++#define mmDPG_TEST_DEBUG_INDEX 0x1b38 ++#define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 ++#define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38 ++#define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38 ++#define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138 ++#define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338 ++#define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538 ++#define mmDPG_TEST_DEBUG_DATA 0x1b39 ++#define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 ++#define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39 ++#define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39 ++#define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139 ++#define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339 ++#define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539 ++#define mmDPGV0_PIPE_ARBITRATION_CONTROL1 0x4730 ++#define mmDPGV1_PIPE_ARBITRATION_CONTROL1 0x473d ++#define mmDPGV0_PIPE_ARBITRATION_CONTROL2 0x4731 ++#define mmDPGV1_PIPE_ARBITRATION_CONTROL2 0x473e ++#define mmDPGV0_WATERMARK_MASK_CONTROL 0x4732 ++#define mmDPGV1_WATERMARK_MASK_CONTROL 0x473f ++#define mmDPGV0_PIPE_URGENCY_CONTROL 0x4733 ++#define mmDPGV1_PIPE_URGENCY_CONTROL 0x4740 ++#define mmDPGV0_PIPE_DPM_CONTROL 0x4734 ++#define mmDPGV1_PIPE_DPM_CONTROL 0x4741 ++#define mmDPGV0_PIPE_STUTTER_CONTROL 0x4735 ++#define mmDPGV1_PIPE_STUTTER_CONTROL 0x4742 ++#define mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 ++#define mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4743 ++#define mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 ++#define mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x4744 ++#define mmDPGV0_REPEATER_PROGRAM 0x4738 ++#define mmDPGV1_REPEATER_PROGRAM 0x4745 ++#define mmDPGV0_HW_DEBUG_A 0x4739 ++#define mmDPGV1_HW_DEBUG_A 0x4746 ++#define mmDPGV0_HW_DEBUG_B 0x473a ++#define mmDPGV1_HW_DEBUG_B 0x4747 ++#define mmDPGV0_HW_DEBUG_11 0x473b ++#define mmDPGV1_HW_DEBUG_11 0x4748 ++#define mmDPGV0_CHK_PRE_PROC_CNTL 0x473c ++#define mmDPGV1_CHK_PRE_PROC_CNTL 0x4749 ++#define mmDPGV_TEST_DEBUG_INDEX 0x474e ++#define mmDPGV_TEST_DEBUG_DATA 0x474f ++#define ixDPGV0_DEBUG00_DMIFARB 0x1 ++#define ixDPGV1_DEBUG00_DMIFARB 0x6a ++#define ixDPGV0_DEBUG01_DMIFARB 0x2 ++#define ixDPGV1_DEBUG01_DMIFARB 0x6b ++#define ixDPGV0_DEBUG02_DMIFARB 0x3 ++#define ixDPGV1_DEBUG02_DMIFARB 0x6c ++#define ixDPGV0_DEBUG03_DMIFARB 0x4 ++#define ixDPGV1_DEBUG03_DMIFARB 0x6d ++#define ixDPGV0_DEBUG04_DMIFARB 0x5 ++#define ixDPGV1_DEBUG04_DMIFARB 0x6e ++#define ixDPGV0_DEBUG00 0x6 ++#define ixDPGV1_DEBUG00 0x6f ++#define ixDPGV0_DEBUG01 0x7 ++#define ixDPGV1_DEBUG01 0x70 ++#define ixDPGV0_DEBUG02 0x8 ++#define ixDPGV1_DEBUG02 0x71 ++#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 ++#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 ++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 ++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 ++#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 ++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 ++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 ++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a ++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b ++#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f ++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 ++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff ++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 ++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 ++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 ++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 ++#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 ++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828 ++#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829 ++#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a ++#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b ++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c ++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d ++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e ++#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f ++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830 ++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831 ++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832 ++#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833 ++#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834 ++#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835 ++#define mmAZALIA_F0_CODEC_DEBUG 0x1836 ++#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837 ++#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838 ++#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839 ++#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a ++#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b ++#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c ++#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d ++#define mmGLOBAL_CAPABILITIES 0x0 ++#define mmMINOR_VERSION 0x0 ++#define mmMAJOR_VERSION 0x0 ++#define mmOUTPUT_PAYLOAD_CAPABILITY 0x1 ++#define mmINPUT_PAYLOAD_CAPABILITY 0x1 ++#define mmGLOBAL_CONTROL 0x2 ++#define mmWAKE_ENABLE 0x3 ++#define mmSTATE_CHANGE_STATUS 0x3 ++#define mmGLOBAL_STATUS 0x4 ++#define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 ++#define mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6 ++#define mmINTERRUPT_CONTROL 0x8 ++#define mmINTERRUPT_STATUS 0x9 ++#define mmWALL_CLOCK_COUNTER 0xc ++#define mmSTREAM_SYNCHRONIZATION 0xe ++#define mmCORB_LOWER_BASE_ADDRESS 0x10 ++#define mmCORB_UPPER_BASE_ADDRESS 0x11 ++#define mmCORB_WRITE_POINTER 0x12 ++#define mmCORB_READ_POINTER 0x12 ++#define mmCORB_CONTROL 0x13 ++#define mmCORB_STATUS 0x13 ++#define mmCORB_SIZE 0x13 ++#define mmRIRB_LOWER_BASE_ADDRESS 0x14 ++#define mmRIRB_UPPER_BASE_ADDRESS 0x15 ++#define mmRIRB_WRITE_POINTER 0x16 ++#define mmRESPONSE_INTERRUPT_COUNT 0x16 ++#define mmRIRB_CONTROL 0x17 ++#define mmRIRB_STATUS 0x17 ++#define mmRIRB_SIZE 0x17 ++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 ++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 ++#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 ++#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 ++#define mmIMMEDIATE_COMMAND_STATUS 0x1a ++#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c ++#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d ++#define mmWALL_CLOCK_COUNTER_ALIAS 0x80c ++#define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 ++#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 ++#define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 ++#define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 ++#define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 ++#define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 ++#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 ++#define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 ++#define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 ++#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 ++#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 ++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 ++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a ++#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b ++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 ++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 ++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d ++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e ++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e ++#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 ++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 ++#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 ++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 ++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c ++#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 ++#define ixAUDIO_DESCRIPTOR0 0x1 ++#define ixAUDIO_DESCRIPTOR1 0x2 ++#define ixAUDIO_DESCRIPTOR2 0x3 ++#define ixAUDIO_DESCRIPTOR3 0x4 ++#define ixAUDIO_DESCRIPTOR4 0x5 ++#define ixAUDIO_DESCRIPTOR5 0x6 ++#define ixAUDIO_DESCRIPTOR6 0x7 ++#define ixAUDIO_DESCRIPTOR7 0x8 ++#define ixAUDIO_DESCRIPTOR8 0x9 ++#define ixAUDIO_DESCRIPTOR9 0xa ++#define ixAUDIO_DESCRIPTOR10 0xb ++#define ixAUDIO_DESCRIPTOR11 0xc ++#define ixAUDIO_DESCRIPTOR12 0xd ++#define ixAUDIO_DESCRIPTOR13 0xe ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 ++#define ixSINK_DESCRIPTION0 0x5 ++#define ixSINK_DESCRIPTION1 0x6 ++#define ixSINK_DESCRIPTION2 0x7 ++#define ixSINK_DESCRIPTION3 0x8 ++#define ixSINK_DESCRIPTION4 0x9 ++#define ixSINK_DESCRIPTION5 0xa ++#define ixSINK_DESCRIPTION6 0xb ++#define ixSINK_DESCRIPTION7 0xc ++#define ixSINK_DESCRIPTION8 0xd ++#define ixSINK_DESCRIPTION9 0xe ++#define ixSINK_DESCRIPTION10 0xf ++#define ixSINK_DESCRIPTION11 0x10 ++#define ixSINK_DESCRIPTION12 0x11 ++#define ixSINK_DESCRIPTION13 0x12 ++#define ixSINK_DESCRIPTION14 0x13 ++#define ixSINK_DESCRIPTION15 0x14 ++#define ixSINK_DESCRIPTION16 0x15 ++#define ixSINK_DESCRIPTION17 0x16 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 ++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a ++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b ++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c ++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d ++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e ++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f ++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 ++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 ++#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 ++#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d ++#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e ++#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4 ++#define mmAZALIA_AUDIO_DTO 0x17e5 ++#define mmAZALIA_AUDIO_DTO_CONTROL 0x17e6 ++#define mmAZALIA_SCLK_CONTROL 0x17e7 ++#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8 ++#define mmAZALIA_DATA_DMA_CONTROL 0x17e9 ++#define mmAZALIA_BDL_DMA_CONTROL 0x17ea ++#define mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb ++#define mmAZALIA_CORB_DMA_CONTROL 0x17ec ++#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3 ++#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4 ++#define mmAZALIA_GLOBAL_CAPABILITIES 0x17f5 ++#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6 ++#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7 ++#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8 ++#define mmAZALIA_CONTROLLER_DEBUG 0x17f9 ++#define mmAZALIA_MEM_PWR_CTRL 0x1810 ++#define mmAZALIA_MEM_PWR_STATUS 0x1811 ++#define mmDCI_PG_DEBUG_CONFIG 0x1812 ++#define mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb ++#define mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc ++#define mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd ++#define mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe ++#define mmAZALIA_INPUT_CRC0_RESULT 0x17ff ++#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0 ++#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 ++#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 ++#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x3 ++#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x4 ++#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 ++#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x6 ++#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x7 ++#define mmAZALIA_INPUT_CRC1_CONTROL0 0x1800 ++#define mmAZALIA_INPUT_CRC1_CONTROL1 0x1801 ++#define mmAZALIA_INPUT_CRC1_CONTROL2 0x1802 ++#define mmAZALIA_INPUT_CRC1_CONTROL3 0x1803 ++#define mmAZALIA_INPUT_CRC1_RESULT 0x1804 ++#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 ++#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x1 ++#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 ++#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x3 ++#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x4 ++#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 ++#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x6 ++#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x7 ++#define mmAZALIA_CRC0_CONTROL0 0x1805 ++#define mmAZALIA_CRC0_CONTROL1 0x1806 ++#define mmAZALIA_CRC0_CONTROL2 0x1807 ++#define mmAZALIA_CRC0_CONTROL3 0x1808 ++#define mmAZALIA_CRC0_RESULT 0x1809 ++#define ixAZALIA_CRC0_CHANNEL0 0x0 ++#define ixAZALIA_CRC0_CHANNEL1 0x1 ++#define ixAZALIA_CRC0_CHANNEL2 0x2 ++#define ixAZALIA_CRC0_CHANNEL3 0x3 ++#define ixAZALIA_CRC0_CHANNEL4 0x4 ++#define ixAZALIA_CRC0_CHANNEL5 0x5 ++#define ixAZALIA_CRC0_CHANNEL6 0x6 ++#define ixAZALIA_CRC0_CHANNEL7 0x7 ++#define mmAZALIA_CRC1_CONTROL0 0x180a ++#define mmAZALIA_CRC1_CONTROL1 0x180b ++#define mmAZALIA_CRC1_CONTROL2 0x180c ++#define mmAZALIA_CRC1_CONTROL3 0x180d ++#define mmAZALIA_CRC1_RESULT 0x180e ++#define ixAZALIA_CRC1_CHANNEL0 0x0 ++#define ixAZALIA_CRC1_CHANNEL1 0x1 ++#define ixAZALIA_CRC1_CHANNEL2 0x2 ++#define ixAZALIA_CRC1_CHANNEL3 0x3 ++#define ixAZALIA_CRC1_CHANNEL4 0x4 ++#define ixAZALIA_CRC1_CHANNEL5 0x5 ++#define ixAZALIA_CRC1_CHANNEL6 0x6 ++#define ixAZALIA_CRC1_CHANNEL7 0x7 ++#define mmAZ_TEST_DEBUG_INDEX 0x181f ++#define mmAZ_TEST_DEBUG_DATA 0x1820 ++#define mmAZALIA_STREAM_INDEX 0x1780 ++#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780 ++#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782 ++#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784 ++#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786 ++#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788 ++#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a ++#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c ++#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e ++#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0 ++#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2 ++#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4 ++#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6 ++#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8 ++#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca ++#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc ++#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce ++#define mmAZALIA_STREAM_DATA 0x1781 ++#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781 ++#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783 ++#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785 ++#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787 ++#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789 ++#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b ++#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d ++#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f ++#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1 ++#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3 ++#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5 ++#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7 ++#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9 ++#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb ++#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd ++#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf ++#define ixAZALIA_FIFO_SIZE_CONTROL 0x0 ++#define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 ++#define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 ++#define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 ++#define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 ++#define ixAZALIA_STREAM_DEBUG 0x5 ++#define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 ++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 ++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac ++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0 ++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4 ++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8 ++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc ++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0 ++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4 ++#define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 ++#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 ++#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad ++#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1 ++#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5 ++#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9 ++#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd ++#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1 ++#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5 ++#define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 ++#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 ++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 ++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 ++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 ++#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 ++#define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 ++#define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 ++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 ++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 ++#define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa ++#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc ++#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd ++#define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe ++#define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 ++#define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 ++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 ++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a ++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b ++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c ++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d ++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e ++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f ++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 ++#define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 ++#define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69 ++#define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a ++#define ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b ++#define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c ++#define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d ++#define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e ++#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 ++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 ++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8 ++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc ++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0 ++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4 ++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8 ++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec ++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0 ++#define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 ++#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 ++#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9 ++#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd ++#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1 ++#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5 ++#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9 ++#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed ++#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1 ++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0 ++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 ++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 ++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 ++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 ++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 ++#define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65 ++#define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 ++#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18 ++#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18 ++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 ++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a ++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b ++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 ++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 ++#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d ++#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 ++#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a ++#define mmBLND_CONTROL 0x1b6d ++#define mmBLND0_BLND_CONTROL 0x1b6d ++#define mmBLND1_BLND_CONTROL 0x1d6d ++#define mmBLND2_BLND_CONTROL 0x1f6d ++#define mmBLND3_BLND_CONTROL 0x416d ++#define mmBLND4_BLND_CONTROL 0x436d ++#define mmBLND5_BLND_CONTROL 0x456d ++#define mmBLND_SM_CONTROL2 0x1b6e ++#define mmBLND0_BLND_SM_CONTROL2 0x1b6e ++#define mmBLND1_BLND_SM_CONTROL2 0x1d6e ++#define mmBLND2_BLND_SM_CONTROL2 0x1f6e ++#define mmBLND3_BLND_SM_CONTROL2 0x416e ++#define mmBLND4_BLND_SM_CONTROL2 0x436e ++#define mmBLND5_BLND_SM_CONTROL2 0x456e ++#define mmBLND_CONTROL2 0x1b6f ++#define mmBLND0_BLND_CONTROL2 0x1b6f ++#define mmBLND1_BLND_CONTROL2 0x1d6f ++#define mmBLND2_BLND_CONTROL2 0x1f6f ++#define mmBLND3_BLND_CONTROL2 0x416f ++#define mmBLND4_BLND_CONTROL2 0x436f ++#define mmBLND5_BLND_CONTROL2 0x456f ++#define mmBLND_UPDATE 0x1b70 ++#define mmBLND0_BLND_UPDATE 0x1b70 ++#define mmBLND1_BLND_UPDATE 0x1d70 ++#define mmBLND2_BLND_UPDATE 0x1f70 ++#define mmBLND3_BLND_UPDATE 0x4170 ++#define mmBLND4_BLND_UPDATE 0x4370 ++#define mmBLND5_BLND_UPDATE 0x4570 ++#define mmBLND_UNDERFLOW_INTERRUPT 0x1b71 ++#define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 ++#define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71 ++#define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71 ++#define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171 ++#define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371 ++#define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571 ++#define mmBLND_V_UPDATE_LOCK 0x1b73 ++#define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 ++#define mmBLND1_BLND_V_UPDATE_LOCK 0x1d73 ++#define mmBLND2_BLND_V_UPDATE_LOCK 0x1f73 ++#define mmBLND3_BLND_V_UPDATE_LOCK 0x4173 ++#define mmBLND4_BLND_V_UPDATE_LOCK 0x4373 ++#define mmBLND5_BLND_V_UPDATE_LOCK 0x4573 ++#define mmBLND_REG_UPDATE_STATUS 0x1b77 ++#define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 ++#define mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77 ++#define mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77 ++#define mmBLND3_BLND_REG_UPDATE_STATUS 0x4177 ++#define mmBLND4_BLND_REG_UPDATE_STATUS 0x4377 ++#define mmBLND5_BLND_REG_UPDATE_STATUS 0x4577 ++#define mmBLND_DEBUG 0x1b74 ++#define mmBLND0_BLND_DEBUG 0x1b74 ++#define mmBLND1_BLND_DEBUG 0x1d74 ++#define mmBLND2_BLND_DEBUG 0x1f74 ++#define mmBLND3_BLND_DEBUG 0x4174 ++#define mmBLND4_BLND_DEBUG 0x4374 ++#define mmBLND5_BLND_DEBUG 0x4574 ++#define mmBLND_TEST_DEBUG_INDEX 0x1b75 ++#define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 ++#define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75 ++#define mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75 ++#define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175 ++#define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375 ++#define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575 ++#define mmBLND_TEST_DEBUG_DATA 0x1b76 ++#define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 ++#define mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76 ++#define mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76 ++#define mmBLND3_BLND_TEST_DEBUG_DATA 0x4176 ++#define mmBLND4_BLND_TEST_DEBUG_DATA 0x4376 ++#define mmBLND5_BLND_TEST_DEBUG_DATA 0x4576 ++#define mmWB_ENABLE 0x5e18 ++#define mmWB_EC_CONFIG 0x5e19 ++#define mmCNV_MODE 0x5e1a ++#define mmCNV_WINDOW_START 0x5e1b ++#define mmCNV_WINDOW_SIZE 0x5e1c ++#define mmCNV_UPDATE 0x5e1d ++#define mmCNV_SOURCE_SIZE 0x5e1e ++#define mmCNV_CSC_CONTROL 0x5e1f ++#define mmCNV_CSC_C11_C12 0x5e20 ++#define mmCNV_CSC_C13_C14 0x5e21 ++#define mmCNV_CSC_C21_C22 0x5e22 ++#define mmCNV_CSC_C23_C24 0x5e23 ++#define mmCNV_CSC_C31_C32 0x5e24 ++#define mmCNV_CSC_C33_C34 0x5e25 ++#define mmCNV_CSC_ROUND_OFFSET_R 0x5e26 ++#define mmCNV_CSC_ROUND_OFFSET_G 0x5e27 ++#define mmCNV_CSC_ROUND_OFFSET_B 0x5e28 ++#define mmCNV_CSC_CLAMP_R 0x5e29 ++#define mmCNV_CSC_CLAMP_G 0x5e2a ++#define mmCNV_CSC_CLAMP_B 0x5e2b ++#define mmCNV_TEST_CNTL 0x5e2c ++#define mmCNV_TEST_CRC_RED 0x5e2d ++#define mmCNV_TEST_CRC_GREEN 0x5e2e ++#define mmCNV_TEST_CRC_BLUE 0x5e2f ++#define mmWB_DEBUG_CTRL 0x5e30 ++#define mmWB_DBG_MODE 0x5e31 ++#define mmWB_HW_DEBUG 0x5e32 ++#define mmCNV_INPUT_SELECT 0x5e33 ++#define mmWB_SOFT_RESET 0x5e36 ++#define mmCNV_TEST_DEBUG_INDEX 0x5e34 ++#define mmCNV_TEST_DEBUG_DATA 0x5e35 ++#define mmDCFE_CLOCK_CONTROL 0x1b00 ++#define mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00 ++#define mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00 ++#define mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00 ++#define mmDCFE3_DCFE_CLOCK_CONTROL 0x4100 ++#define mmDCFE4_DCFE_CLOCK_CONTROL 0x4300 ++#define mmDCFE5_DCFE_CLOCK_CONTROL 0x4500 ++#define mmDCFE_SOFT_RESET 0x1b01 ++#define mmDCFE0_DCFE_SOFT_RESET 0x1b01 ++#define mmDCFE1_DCFE_SOFT_RESET 0x1d01 ++#define mmDCFE2_DCFE_SOFT_RESET 0x1f01 ++#define mmDCFE3_DCFE_SOFT_RESET 0x4101 ++#define mmDCFE4_DCFE_SOFT_RESET 0x4301 ++#define mmDCFE5_DCFE_SOFT_RESET 0x4501 ++#define mmDCFE_DBG_CONFIG 0x1b02 ++#define mmDCFE0_DCFE_DBG_CONFIG 0x1b02 ++#define mmDCFE1_DCFE_DBG_CONFIG 0x1d02 ++#define mmDCFE2_DCFE_DBG_CONFIG 0x1f02 ++#define mmDCFE3_DCFE_DBG_CONFIG 0x4102 ++#define mmDCFE4_DCFE_DBG_CONFIG 0x4302 ++#define mmDCFE5_DCFE_DBG_CONFIG 0x4502 ++#define mmDCFE_MEM_PWR_CTRL 0x1b03 ++#define mmDCFE0_DCFE_MEM_PWR_CTRL 0x1b03 ++#define mmDCFE1_DCFE_MEM_PWR_CTRL 0x1d03 ++#define mmDCFE2_DCFE_MEM_PWR_CTRL 0x1f03 ++#define mmDCFE3_DCFE_MEM_PWR_CTRL 0x4103 ++#define mmDCFE4_DCFE_MEM_PWR_CTRL 0x4303 ++#define mmDCFE5_DCFE_MEM_PWR_CTRL 0x4503 ++#define mmDCFE_MEM_PWR_CTRL2 0x1b04 ++#define mmDCFE0_DCFE_MEM_PWR_CTRL2 0x1b04 ++#define mmDCFE1_DCFE_MEM_PWR_CTRL2 0x1d04 ++#define mmDCFE2_DCFE_MEM_PWR_CTRL2 0x1f04 ++#define mmDCFE3_DCFE_MEM_PWR_CTRL2 0x4104 ++#define mmDCFE4_DCFE_MEM_PWR_CTRL2 0x4304 ++#define mmDCFE5_DCFE_MEM_PWR_CTRL2 0x4504 ++#define mmDCFE_MEM_PWR_STATUS 0x1b05 ++#define mmDCFE0_DCFE_MEM_PWR_STATUS 0x1b05 ++#define mmDCFE1_DCFE_MEM_PWR_STATUS 0x1d05 ++#define mmDCFE2_DCFE_MEM_PWR_STATUS 0x1f05 ++#define mmDCFE3_DCFE_MEM_PWR_STATUS 0x4105 ++#define mmDCFE4_DCFE_MEM_PWR_STATUS 0x4305 ++#define mmDCFE5_DCFE_MEM_PWR_STATUS 0x4505 ++#define mmDCFE_MISC 0x1b06 ++#define mmDCFE0_DCFE_MISC 0x1b06 ++#define mmDCFE1_DCFE_MISC 0x1d06 ++#define mmDCFE2_DCFE_MISC 0x1f06 ++#define mmDCFE3_DCFE_MISC 0x4106 ++#define mmDCFE4_DCFE_MISC 0x4306 ++#define mmDCFE5_DCFE_MISC 0x4506 ++#define mmDCFEV_CLOCK_CONTROL 0x46f4 ++#define mmDCFEV_SOFT_RESET 0x46f5 ++#define mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6 ++#define mmDCFEV_DBG_CONFIG 0x46f7 ++#define mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8 ++#define mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9 ++#define mmDCFEV_MEM_PWR_CTRL 0x46fa ++#define mmDCFEV_MEM_PWR_CTRL2 0x46fb ++#define mmDCFEV_MEM_PWR_STATUS 0x46fc ++#define mmDCFEV_DMIFV_DEBUG 0x46fd ++#define mmDCFEV_MISC 0x46fe ++#define mmDC_HPD_INT_STATUS 0x1898 ++#define mmHPD0_DC_HPD_INT_STATUS 0x1898 ++#define mmHPD1_DC_HPD_INT_STATUS 0x18a0 ++#define mmHPD2_DC_HPD_INT_STATUS 0x18a8 ++#define mmHPD3_DC_HPD_INT_STATUS 0x18b0 ++#define mmHPD4_DC_HPD_INT_STATUS 0x18b8 ++#define mmHPD5_DC_HPD_INT_STATUS 0x18c0 ++#define mmDC_HPD_INT_CONTROL 0x1899 ++#define mmHPD0_DC_HPD_INT_CONTROL 0x1899 ++#define mmHPD1_DC_HPD_INT_CONTROL 0x18a1 ++#define mmHPD2_DC_HPD_INT_CONTROL 0x18a9 ++#define mmHPD3_DC_HPD_INT_CONTROL 0x18b1 ++#define mmHPD4_DC_HPD_INT_CONTROL 0x18b9 ++#define mmHPD5_DC_HPD_INT_CONTROL 0x18c1 ++#define mmDC_HPD_CONTROL 0x189a ++#define mmHPD0_DC_HPD_CONTROL 0x189a ++#define mmHPD1_DC_HPD_CONTROL 0x18a2 ++#define mmHPD2_DC_HPD_CONTROL 0x18aa ++#define mmHPD3_DC_HPD_CONTROL 0x18b2 ++#define mmHPD4_DC_HPD_CONTROL 0x18ba ++#define mmHPD5_DC_HPD_CONTROL 0x18c2 ++#define mmDC_HPD_FAST_TRAIN_CNTL 0x189b ++#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b ++#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3 ++#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab ++#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3 ++#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb ++#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3 ++#define mmDC_HPD_TOGGLE_FILT_CNTL 0x189c ++#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c ++#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4 ++#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac ++#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4 ++#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc ++#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4 ++#define mmDCO_SCRATCH0 0x184e ++#define mmDCO_SCRATCH1 0x184f ++#define mmDCO_SCRATCH2 0x1850 ++#define mmDCO_SCRATCH3 0x1851 ++#define mmDCO_SCRATCH4 0x1852 ++#define mmDCO_SCRATCH5 0x1853 ++#define mmDCO_SCRATCH6 0x1854 ++#define mmDCO_SCRATCH7 0x1855 ++#define mmDCE_VCE_CONTROL 0x1856 ++#define mmDISP_INTERRUPT_STATUS 0x1857 ++#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858 ++#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859 ++#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a ++#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b ++#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c ++#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d ++#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e ++#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f ++#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860 ++#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x1875 ++#define mmDCO_MEM_PWR_STATUS 0x1861 ++#define mmDCO_MEM_PWR_STATUS1 0x1874 ++#define mmDCO_MEM_PWR_CTRL 0x1862 ++#define mmDCO_MEM_PWR_CTRL2 0x1863 ++#define mmDCO_CLK_CNTL 0x1864 ++#define mmDCO_CLK_CNTL2 0x1876 ++#define mmDCO_CLK_CNTL3 0x1877 ++#define mmDPDBG_CNTL 0x1866 ++#define mmDPDBG_INTERRUPT 0x1867 ++#define mmDCO_POWER_MANAGEMENT_CNTL 0x1868 ++#define mmDCO_SOFT_RESET 0x1871 ++#define mmDIG_SOFT_RESET 0x1872 ++#define mmDIG_SOFT_RESET_2 0x186a ++#define mmDCO_STEREOSYNC_SEL 0x186e ++#define mmDCO_TEST_DEBUG_INDEX 0x186f ++#define mmDCO_TEST_DEBUG_DATA 0x1870 ++#define mmDC_I2C_CONTROL 0x16d4 ++#define mmDC_I2C_ARBITRATION 0x16d5 ++#define mmDC_I2C_INTERRUPT_CONTROL 0x16d6 ++#define mmDC_I2C_SW_STATUS 0x16d7 ++#define mmDC_I2C_DDC1_HW_STATUS 0x16d8 ++#define mmDC_I2C_DDC2_HW_STATUS 0x16d9 ++#define mmDC_I2C_DDC3_HW_STATUS 0x16da ++#define mmDC_I2C_DDC4_HW_STATUS 0x16db ++#define mmDC_I2C_DDC5_HW_STATUS 0x16dc ++#define mmDC_I2C_DDC6_HW_STATUS 0x16dd ++#define mmDC_I2C_DDC1_SPEED 0x16de ++#define mmDC_I2C_DDC1_SETUP 0x16df ++#define mmDC_I2C_DDC2_SPEED 0x16e0 ++#define mmDC_I2C_DDC2_SETUP 0x16e1 ++#define mmDC_I2C_DDC3_SPEED 0x16e2 ++#define mmDC_I2C_DDC3_SETUP 0x16e3 ++#define mmDC_I2C_DDC4_SPEED 0x16e4 ++#define mmDC_I2C_DDC4_SETUP 0x16e5 ++#define mmDC_I2C_DDC5_SPEED 0x16e6 ++#define mmDC_I2C_DDC5_SETUP 0x16e7 ++#define mmDC_I2C_DDC6_SPEED 0x16e8 ++#define mmDC_I2C_DDC6_SETUP 0x16e9 ++#define mmDC_I2C_TRANSACTION0 0x16ea ++#define mmDC_I2C_TRANSACTION1 0x16eb ++#define mmDC_I2C_TRANSACTION2 0x16ec ++#define mmDC_I2C_TRANSACTION3 0x16ed ++#define mmDC_I2C_DATA 0x16ee ++#define mmDC_I2C_DDCVGA_HW_STATUS 0x16ef ++#define mmDC_I2C_DDCVGA_SPEED 0x16f0 ++#define mmDC_I2C_DDCVGA_SETUP 0x16f1 ++#define mmDC_I2C_EDID_DETECT_CTRL 0x16f2 ++#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3 ++#define mmGENERIC_I2C_CONTROL 0x16f4 ++#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5 ++#define mmGENERIC_I2C_STATUS 0x16f6 ++#define mmGENERIC_I2C_SPEED 0x16f7 ++#define mmGENERIC_I2C_SETUP 0x16f8 ++#define mmGENERIC_I2C_TRANSACTION 0x16f9 ++#define mmGENERIC_I2C_DATA 0x16fa ++#define mmGENERIC_I2C_PIN_SELECTION 0x16fb ++#define mmGENERIC_I2C_PIN_DEBUG 0x16fc ++#define mmBLNDV_CONTROL 0x476d ++#define mmBLNDV_SM_CONTROL2 0x476e ++#define mmBLNDV_CONTROL2 0x476f ++#define mmBLNDV_UPDATE 0x4770 ++#define mmBLNDV_UNDERFLOW_INTERRUPT 0x4771 ++#define mmBLNDV_V_UPDATE_LOCK 0x4773 ++#define mmBLNDV_REG_UPDATE_STATUS 0x4777 ++#define mmBLNDV_DEBUG 0x4774 ++#define mmBLNDV_TEST_DEBUG_INDEX 0x4775 ++#define mmBLNDV_TEST_DEBUG_DATA 0x4776 ++#define mmCRTCV_H_BLANK_EARLY_NUM 0x477d ++#define mmCRTCV_H_TOTAL 0x4780 ++#define mmCRTCV_H_BLANK_START_END 0x4781 ++#define mmCRTCV_H_SYNC_A 0x4782 ++#define mmCRTCV_H_SYNC_A_CNTL 0x4783 ++#define mmCRTCV_H_SYNC_B 0x4784 ++#define mmCRTCV_H_SYNC_B_CNTL 0x4785 ++#define mmCRTCV_VBI_END 0x4786 ++#define mmCRTCV_V_TOTAL 0x4787 ++#define mmCRTCV_V_TOTAL_MIN 0x4788 ++#define mmCRTCV_V_TOTAL_MAX 0x4789 ++#define mmCRTCV_V_TOTAL_CONTROL 0x478a ++#define mmCRTCV_V_TOTAL_INT_STATUS 0x478b ++#define mmCRTCV_VSYNC_NOM_INT_STATUS 0x478c ++#define mmCRTCV_V_BLANK_START_END 0x478d ++#define mmCRTCV_V_SYNC_A 0x478e ++#define mmCRTCV_V_SYNC_A_CNTL 0x478f ++#define mmCRTCV_V_SYNC_B 0x4790 ++#define mmCRTCV_V_SYNC_B_CNTL 0x4791 ++#define mmCRTCV_DTMTEST_CNTL 0x4792 ++#define mmCRTCV_DTMTEST_STATUS_POSITION 0x4793 ++#define mmCRTCV_TRIGA_CNTL 0x4794 ++#define mmCRTCV_TRIGA_MANUAL_TRIG 0x4795 ++#define mmCRTCV_TRIGB_CNTL 0x4796 ++#define mmCRTCV_TRIGB_MANUAL_TRIG 0x4797 ++#define mmCRTCV_FORCE_COUNT_NOW_CNTL 0x4798 ++#define mmCRTCV_FLOW_CONTROL 0x4799 ++#define mmCRTCV_STEREO_FORCE_NEXT_EYE 0x479a ++#define mmCRTCV_AVSYNC_COUNTER 0x479b ++#define mmCRTCV_CONTROL 0x479c ++#define mmCRTCV_BLANK_CONTROL 0x479d ++#define mmCRTCV_INTERLACE_CONTROL 0x479e ++#define mmCRTCV_INTERLACE_STATUS 0x479f ++#define mmCRTCV_FIELD_INDICATION_CONTROL 0x47a0 ++#define mmCRTCV_PIXEL_DATA_READBACK0 0x47a1 ++#define mmCRTCV_PIXEL_DATA_READBACK1 0x47a2 ++#define mmCRTCV_STATUS 0x47a3 ++#define mmCRTCV_STATUS_POSITION 0x47a4 ++#define mmCRTCV_NOM_VERT_POSITION 0x47a5 ++#define mmCRTCV_STATUS_FRAME_COUNT 0x47a6 ++#define mmCRTCV_STATUS_VF_COUNT 0x47a7 ++#define mmCRTCV_STATUS_HV_COUNT 0x47a8 ++#define mmCRTCV_COUNT_CONTROL 0x47a9 ++#define mmCRTCV_COUNT_RESET 0x47aa ++#define mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab ++#define mmCRTCV_VERT_SYNC_CONTROL 0x47ac ++#define mmCRTCV_STEREO_STATUS 0x47ad ++#define mmCRTCV_STEREO_CONTROL 0x47ae ++#define mmCRTCV_SNAPSHOT_STATUS 0x47af ++#define mmCRTCV_SNAPSHOT_CONTROL 0x47b0 ++#define mmCRTCV_SNAPSHOT_POSITION 0x47b1 ++#define mmCRTCV_SNAPSHOT_FRAME 0x47b2 ++#define mmCRTCV_START_LINE_CONTROL 0x47b3 ++#define mmCRTCV_INTERRUPT_CONTROL 0x47b4 ++#define mmCRTCV_UPDATE_LOCK 0x47b5 ++#define mmCRTCV_DOUBLE_BUFFER_CONTROL 0x47b6 ++#define mmCRTCV_VGA_PARAMETER_CAPTURE_MODE 0x47b7 ++#define mmCRTCV_TEST_PATTERN_CONTROL 0x47ba ++#define mmCRTCV_TEST_PATTERN_PARAMETERS 0x47bb ++#define mmCRTCV_TEST_PATTERN_COLOR 0x47bc ++#define mmCRTCV_MASTER_UPDATE_LOCK 0x47bd ++#define mmCRTCV_MASTER_UPDATE_MODE 0x47be ++#define mmCRTCV_MVP_INBAND_CNTL_INSERT 0x47bf ++#define mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 ++#define mmCRTCV_MVP_STATUS 0x47c1 ++#define mmCRTCV_MASTER_EN 0x47c2 ++#define mmCRTCV_ALLOW_STOP_OFF_V_CNT 0x47c3 ++#define mmCRTCV_V_UPDATE_INT_STATUS 0x47c4 ++#define mmCRTCV_OVERSCAN_COLOR 0x47c8 ++#define mmCRTCV_OVERSCAN_COLOR_EXT 0x47c9 ++#define mmCRTCV_BLANK_DATA_COLOR 0x47ca ++#define mmCRTCV_BLANK_DATA_COLOR_EXT 0x47cb ++#define mmCRTCV_BLACK_COLOR 0x47cc ++#define mmCRTCV_BLACK_COLOR_EXT 0x47cd ++#define mmCRTCV_VERTICAL_INTERRUPT0_POSITION 0x47ce ++#define mmCRTCV_VERTICAL_INTERRUPT0_CONTROL 0x47cf ++#define mmCRTCV_VERTICAL_INTERRUPT1_POSITION 0x47d0 ++#define mmCRTCV_VERTICAL_INTERRUPT1_CONTROL 0x47d1 ++#define mmCRTCV_VERTICAL_INTERRUPT2_POSITION 0x47d2 ++#define mmCRTCV_VERTICAL_INTERRUPT2_CONTROL 0x47d3 ++#define mmCRTCV_CRC_CNTL 0x47d4 ++#define mmCRTCV_CRC0_WINDOWA_X_CONTROL 0x47d5 ++#define mmCRTCV_CRC0_WINDOWA_Y_CONTROL 0x47d6 ++#define mmCRTCV_CRC0_WINDOWB_X_CONTROL 0x47d7 ++#define mmCRTCV_CRC0_WINDOWB_Y_CONTROL 0x47d8 ++#define mmCRTCV_CRC0_DATA_RG 0x47d9 ++#define mmCRTCV_CRC0_DATA_B 0x47da ++#define mmCRTCV_CRC1_WINDOWA_X_CONTROL 0x47db ++#define mmCRTCV_CRC1_WINDOWA_Y_CONTROL 0x47dc ++#define mmCRTCV_CRC1_WINDOWB_X_CONTROL 0x47dd ++#define mmCRTCV_CRC1_WINDOWB_Y_CONTROL 0x47de ++#define mmCRTCV_CRC1_DATA_RG 0x47df ++#define mmCRTCV_CRC1_DATA_B 0x47e0 ++#define mmCRTCV_STATIC_SCREEN_CONTROL 0x47e7 ++#define mmCRTCV_3D_STRUCTURE_CONTROL 0x4778 ++#define mmCRTCV_GSL_VSYNC_GAP 0x4779 ++#define mmCRTCV_GSL_WINDOW 0x477a ++#define mmCRTCV_GSL_CONTROL 0x477b ++#define mmCRTCV_TEST_DEBUG_INDEX 0x47c6 ++#define mmCRTCV_TEST_DEBUG_DATA 0x47c7 ++#define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 ++#define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 ++#define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 ++#define mmXDMA_INTERRUPT 0x3e3 ++#define mmXDMA_CLOCK_GATING_CNTL 0x3e4 ++#define mmXDMA_MEM_POWER_CNTL 0x3e6 ++#define mmXDMA_IF_BIF_STATUS 0x3e7 ++#define mmXDMA_PERF_MEAS_STATUS 0x3e8 ++#define mmXDMA_IF_STATUS 0x3e9 ++#define mmXDMA_TEST_DEBUG_INDEX 0x3ea ++#define mmXDMA_TEST_DEBUG_DATA 0x3eb ++#define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 ++#define mmXDMA_PG_CONTROL 0x3f9 ++#define mmXDMA_PG_WDATA 0x3fa ++#define mmXDMA_PG_STATUS 0x3fb ++#define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc ++#define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd ++#define mmXDMA_MSTR_CNTL 0x3ec ++#define mmXDMA_MSTR_STATUS 0x3ed ++#define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee ++#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef ++#define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 ++#define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 ++#define mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 ++#define mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 ++#define mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 ++#define mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 ++#define mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 ++#define mmXDMA_MSTR_PIPE_CNTL 0x400 ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 ++#define mmXDMA_MSTR_READ_COMMAND 0x401 ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 ++#define mmXDMA_MSTR_CHANNEL_DIM 0x402 ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 ++#define mmXDMA_MSTR_HEIGHT 0x403 ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403 ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413 ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423 ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433 ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443 ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453 ++#define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 ++#define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 ++#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 ++#define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 ++#define mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 ++#define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 ++#define mmXDMA_MSTR_CACHE 0x40a ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a ++#define mmXDMA_MSTR_CHANNEL_START 0x40b ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b ++#define mmXDMA_MSTR_PERFMEAS_STATUS 0x40e ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e ++#define mmXDMA_MSTR_PERFMEAS_CNTL 0x40f ++#define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f ++#define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f ++#define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f ++#define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f ++#define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f ++#define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f ++#define mmXDMA_SLV_CNTL 0x460 ++#define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 ++#define mmXDMA_SLV_SLS_PITCH 0x462 ++#define mmXDMA_SLV_READ_URGENT_CNTL 0x463 ++#define mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 ++#define mmXDMA_SLV_WB_RATE_CNTL 0x465 ++#define mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 ++#define mmXDMA_SLV_READ_LATENCY_AVE 0x467 ++#define mmXDMA_SLV_PCIE_NACK_STATUS 0x468 ++#define mmXDMA_SLV_MEM_NACK_STATUS 0x469 ++#define mmXDMA_SLV_RDRET_BUF_STATUS 0x46a ++#define mmXDMA_SLV_READ_LATENCY_TIMER 0x46b ++#define mmXDMA_SLV_FLIP_PENDING 0x46c ++#define mmXDMA_SLV_CHANNEL_CNTL 0x470 ++#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 ++#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 ++#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 ++#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 ++#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 ++#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 ++#define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 ++#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 ++#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 ++#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 ++#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 ++#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 ++#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 ++#define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 ++#define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 ++#define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a ++#define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 ++#define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a ++#define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 ++#define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a ++ ++#endif /* DCE_11_0_D_H */ +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h +new file mode 100644 +index 0000000..d74bca7 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h +@@ -0,0 +1,6129 @@ ++/* ++ * DCE_11_0 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef DCE_11_0_ENUM_H ++#define DCE_11_0_ENUM_H ++ ++typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL { ++ CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x0, ++ CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1, ++} CRTC_CONTROL_CRTC_START_POINT_CNTL; ++typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL { ++ CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x0, ++ CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1, ++} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL; ++typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL { ++ CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x0, ++ CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1, ++ CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x2, ++ CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3, ++} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL; ++typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY { ++ CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x0, ++ CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1, ++} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY; ++typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE { ++ CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE= 0x0, ++ CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1, ++} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE; ++typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN { ++ CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x0, ++ CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x1, ++} CRTC_CONTROL_CRTC_SOF_PULL_EN; ++typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL { ++ CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x0, ++ CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x1, ++} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL; ++typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL { ++ CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x0, ++ CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x1, ++} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL; ++typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL { ++ CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x0, ++ CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x1, ++} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL; ++typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN { ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE= 0x0, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1, ++} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN; ++typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC { ++ CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE= 0x0, ++ CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE= 0x1, ++} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC; ++typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT { ++ CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE= 0x0, ++ CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE= 0x1, ++} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT; ++typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK { ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_FRAME_START= 0x0, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_A= 0x1, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_OTHER_CLIENT= 0x4, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION0= 0x5, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION1= 0x6, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION2= 0x7, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION3= 0x8, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_GRAPHIC_UPDATE_PENDING= 0x9, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED2= 0xa, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_INVALID= 0xb, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_DOUBLE_BUFFER= 0xc, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT_NOM= 0xd, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT= 0xe, ++ CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED= 0xf, ++} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK; ++typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK { ++ CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE= 0x0, ++ CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE= 0x1, ++} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK; ++typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR { ++ CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE= 0x0, ++ CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE= 0x1, ++} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR; ++typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL { ++ CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x0, ++ CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x1, ++} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL; ++typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN { ++ CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x0, ++ CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x1, ++} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN; ++typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT { ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER= 0x1, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF= 0x5, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE= 0x6, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x7, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x8, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x9, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0xa, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0xb, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0xc, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD= 0xd, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC= 0xe, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VIDEO = 0xf, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x10, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x11, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x12, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x13, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA= 0x14, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB= 0x15, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW= 0x16, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW= 0x17, ++} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT; ++typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT { ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE= 0x1, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA= 0x4, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB= 0x5, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x6, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC= 0x7, ++} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT; ++typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN { ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE= 0x0, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x1, ++} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN; ++typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR { ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x0, ++ CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x1, ++} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR; ++typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT { ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER= 0x1, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF= 0x5, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE= 0x6, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x7, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x8, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x9, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0xa, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0xb, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0xc, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD= 0xd, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC= 0xe, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VIDEO = 0xf, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x10, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x11, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x12, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x13, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA= 0x14, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB= 0x15, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW= 0x16, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW= 0x17, ++} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT; ++typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT { ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE= 0x1, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA= 0x4, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB= 0x5, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x6, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC= 0x7, ++} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT; ++typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN { ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE= 0x0, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x1, ++} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN; ++typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR { ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x0, ++ CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x1, ++} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR; ++typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE { ++ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE= 0x0, ++ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT= 0x1, ++ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2, ++ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3, ++} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE; ++typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK { ++ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE= 0x0, ++ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE= 0x1, ++} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK; ++typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL { ++ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE= 0x0, ++ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE= 0x1, ++} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL; ++typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR { ++ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE= 0x0, ++ CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE= 0x1, ++} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR; ++typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT { ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0= 0x0, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF= 0x1, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2= 0x4, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA= 0x5, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK= 0x6, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA= 0x7, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK= 0x8, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK= 0x9, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL= 0xa, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1= 0xb, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB= 0xc, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA= 0xd, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD= 0xe, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC= 0xf, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GPIO= 0x10, ++} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT; ++typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY { ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE= 0x0, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE= 0x1, ++} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY; ++typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY { ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE= 0x0, ++ CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE= 0x1, ++} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY; ++typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE { ++ CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO= 0x0, ++ CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT= 0x1, ++ CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2, ++ CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3, ++} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE; ++typedef enum CRTC_CONTROL_CRTC_MASTER_EN { ++ CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x0, ++ CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x1, ++} CRTC_CONTROL_CRTC_MASTER_EN; ++typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN { ++ CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x0, ++ CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x1, ++} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN; ++typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE { ++ CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x0, ++ CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x1, ++} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE; ++typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE { ++ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE= 0x0, ++ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE= 0x1, ++} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE; ++typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD { ++ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT= 0x0, ++ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD= 0x1, ++ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2, ++ CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3, ++} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD; ++typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY { ++ CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE= 0x0, ++ CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE= 0x1, ++} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY; ++typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT { ++ CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE= 0x0, ++ CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE= 0x1, ++} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT; ++typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN { ++ CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x0, ++ CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x1, ++} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN; ++typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE { ++ CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE= 0x0, ++ CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE= 0x1, ++} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE; ++typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR { ++ CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE= 0x0, ++ CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE= 0x1, ++} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR; ++typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE { ++ CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE= 0x0, ++ CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA= 0x1, ++ CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2, ++ CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3, ++} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE; ++typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY { ++ CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE= 0x0, ++ CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE= 0x1, ++} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY; ++typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY { ++ CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE= 0x0, ++ CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE= 0x1, ++} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY; ++typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY { ++ CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE= 0x0, ++ CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE= 0x1, ++} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY; ++typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN { ++ CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x0, ++ CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x1, ++} CRTC_STEREO_CONTROL_CRTC_STEREO_EN; ++typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR { ++ CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x0, ++ CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x1, ++} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR; ++typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL { ++ CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE= 0x0, ++ CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA= 0x1, ++ CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2, ++ CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3, ++} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL; ++typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY { ++ CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE= 0x0, ++ CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE= 0x1, ++} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY; ++typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY { ++ CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE= 0x0, ++ CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE= 0x1, ++} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY; ++typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN { ++ CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE= 0x0, ++ CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE= 0x1, ++} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN; ++typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN { ++ CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x0, ++ CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x1, ++} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK { ++ CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE= 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE= 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE { ++ CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE= 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE= 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK { ++ CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE= 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE= 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE { ++ CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE= 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE= 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK { ++ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE= 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE= 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE { ++ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE= 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE= 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK { ++ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE= 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE= 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE { ++ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE= 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE= 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK { ++ CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE { ++ CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK { ++ CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE { ++ CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK { ++ CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE= 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE= 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE { ++ CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE= 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE= 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK { ++ CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE= 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE= 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK; ++typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE { ++ CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE= 0x0, ++ CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE= 0x1, ++} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE; ++typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK { ++ CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x0, ++ CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x1, ++} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK; ++typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY { ++ CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE= 0x0, ++ CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE= 0x1, ++} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY; ++typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN { ++ CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE= 0x0, ++ CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE= 0x1, ++} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN; ++typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE { ++ CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE= 0x0, ++ CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE= 0x1, ++} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE; ++typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN { ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE= 0x0, ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE= 0x1, ++} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN; ++typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE { ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB= 0x0, ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601= 0x1, ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2, ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS= 0x3, ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS= 0x4, ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB= 0x5, ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB= 0x6, ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS= 0x7, ++} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE; ++typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE { ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE= 0x0, ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE= 0x1, ++} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE; ++typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT { ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC= 0x0, ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC= 0x1, ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2, ++ CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED= 0x3, ++} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT; ++typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK { ++ MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x0, ++ MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x1, ++} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK; ++typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK { ++ MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE= 0x0, ++ MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE= 0x1, ++} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK; ++typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK { ++ MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x0, ++ MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x1, ++} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK; ++typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE { ++ MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x0, ++ MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x1, ++ MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x2, ++ MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x3, ++} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE; ++typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE { ++ MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH= 0x0, ++ MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN= 0x1, ++ MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2, ++ MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED= 0x3, ++} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE; ++typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE { ++ CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE= 0x0, ++ CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG= 0x1, ++ CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2, ++} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE; ++typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR { ++ CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x0, ++ CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x1, ++} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR; ++typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR { ++ CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE= 0x0, ++ CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE= 0x1, ++} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR; ++typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR { ++ CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE= 0x0, ++ CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE= 0x1, ++} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR; ++typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY { ++ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE= 0x0, ++ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE= 0x1, ++} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY; ++typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE { ++ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE= 0x0, ++ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE= 0x1, ++} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE; ++typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR { ++ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE= 0x0, ++ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE= 0x1, ++} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR; ++typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE { ++ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE= 0x0, ++ CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE= 0x1, ++} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE; ++typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR { ++ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE= 0x0, ++ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE= 0x1, ++} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR; ++typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE { ++ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE= 0x0, ++ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE= 0x1, ++} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE; ++typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE { ++ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE= 0x0, ++ CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE= 0x1, ++} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE; ++typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR { ++ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE= 0x0, ++ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE= 0x1, ++} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR; ++typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE { ++ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE= 0x0, ++ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE= 0x1, ++} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE; ++typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE { ++ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE= 0x0, ++ CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE= 0x1, ++} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE; ++typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN { ++ CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x0, ++ CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x1, ++} CRTC_CRC_CNTL_CRTC_CRC_EN; ++typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN { ++ CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x0, ++ CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x1, ++} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN; ++typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE { ++ CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x0, ++ CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x1, ++ CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x2, ++ CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x3, ++} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE; ++typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE { ++ CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x0, ++ CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x1, ++ CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2, ++ CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x3, ++} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE; ++typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS { ++ CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE= 0x0, ++ CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE= 0x1, ++} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS; ++typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT { ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x0, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x1, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x2, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x3, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x4, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x5, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x6, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x7, ++} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT; ++typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT { ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x0, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x1, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x2, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x3, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x4, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x5, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x6, ++ CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x7, ++} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT; ++typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE { ++ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE= 0x0, ++ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE= 0x1, ++} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE; ++typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR { ++ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE= 0x0, ++ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE= 0x1, ++} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR; ++typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE { ++ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE= 0x0, ++ CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE= 0x1, ++} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE; ++typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN { ++ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE= 0x0, ++ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE= 0x1, ++} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN; ++typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB { ++ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE= 0x0, ++ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE= 0x1, ++} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB; ++typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE { ++ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH= 0x0, ++ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE= 0x1, ++ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2, ++ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED= 0x3, ++} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE; ++typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR { ++ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE= 0x0, ++ CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE= 0x1, ++} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR; ++typedef enum CRTC_V_SYNC_A_POL { ++ CRTC_V_SYNC_A_POL_HIGH = 0x0, ++ CRTC_V_SYNC_A_POL_LOW = 0x1, ++} CRTC_V_SYNC_A_POL; ++typedef enum CRTC_H_SYNC_A_POL { ++ CRTC_H_SYNC_A_POL_HIGH = 0x0, ++ CRTC_H_SYNC_A_POL_LOW = 0x1, ++} CRTC_H_SYNC_A_POL; ++typedef enum CRTC_HORZ_REPETITION_COUNT { ++ CRTC_HORZ_REPETITION_COUNT_0 = 0x0, ++ CRTC_HORZ_REPETITION_COUNT_1 = 0x1, ++ CRTC_HORZ_REPETITION_COUNT_2 = 0x2, ++ CRTC_HORZ_REPETITION_COUNT_3 = 0x3, ++ CRTC_HORZ_REPETITION_COUNT_4 = 0x4, ++ CRTC_HORZ_REPETITION_COUNT_5 = 0x5, ++ CRTC_HORZ_REPETITION_COUNT_6 = 0x6, ++ CRTC_HORZ_REPETITION_COUNT_7 = 0x7, ++ CRTC_HORZ_REPETITION_COUNT_8 = 0x8, ++ CRTC_HORZ_REPETITION_COUNT_9 = 0x9, ++ CRTC_HORZ_REPETITION_COUNT_10 = 0xa, ++ CRTC_HORZ_REPETITION_COUNT_11 = 0xb, ++ CRTC_HORZ_REPETITION_COUNT_12 = 0xc, ++ CRTC_HORZ_REPETITION_COUNT_13 = 0xd, ++ CRTC_HORZ_REPETITION_COUNT_14 = 0xe, ++ CRTC_HORZ_REPETITION_COUNT_15 = 0xf, ++} CRTC_HORZ_REPETITION_COUNT; ++typedef enum PERFCOUNTER_CVALUE_SEL { ++ PERFCOUNTER_CVALUE_SEL_47_0 = 0x0, ++ PERFCOUNTER_CVALUE_SEL_15_0 = 0x1, ++ PERFCOUNTER_CVALUE_SEL_31_16 = 0x2, ++ PERFCOUNTER_CVALUE_SEL_47_32 = 0x3, ++ PERFCOUNTER_CVALUE_SEL_11_0 = 0x4, ++ PERFCOUNTER_CVALUE_SEL_23_12 = 0x5, ++ PERFCOUNTER_CVALUE_SEL_35_24 = 0x6, ++ PERFCOUNTER_CVALUE_SEL_47_36 = 0x7, ++} PERFCOUNTER_CVALUE_SEL; ++typedef enum PERFCOUNTER_INC_MODE { ++ PERFCOUNTER_INC_MODE_MULTI_BIT = 0x0, ++ PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x1, ++ PERFCOUNTER_INC_MODE_LSB = 0x2, ++ PERFCOUNTER_INC_MODE_POS_EDGE = 0x3, ++} PERFCOUNTER_INC_MODE; ++typedef enum PERFCOUNTER_HW_CNTL_SEL { ++ PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x0, ++ PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x1, ++} PERFCOUNTER_HW_CNTL_SEL; ++typedef enum PERFCOUNTER_RUNEN_MODE { ++ PERFCOUNTER_RUNEN_MODE_LEVEL = 0x0, ++ PERFCOUNTER_RUNEN_MODE_EDGE = 0x1, ++} PERFCOUNTER_RUNEN_MODE; ++typedef enum PERFCOUNTER_CNTOFF_START_DIS { ++ PERFCOUNTER_CNTOFF_START_ENABLE = 0x0, ++ PERFCOUNTER_CNTOFF_START_DISABLE = 0x1, ++} PERFCOUNTER_CNTOFF_START_DIS; ++typedef enum PERFCOUNTER_RESTART_EN { ++ PERFCOUNTER_RESTART_DISABLE = 0x0, ++ PERFCOUNTER_RESTART_ENABLE = 0x1, ++} PERFCOUNTER_RESTART_EN; ++typedef enum PERFCOUNTER_INT_EN { ++ PERFCOUNTER_INT_DISABLE = 0x0, ++ PERFCOUNTER_INT_ENABLE = 0x1, ++} PERFCOUNTER_INT_EN; ++typedef enum PERFCOUNTER_OFF_MASK { ++ PERFCOUNTER_OFF_MASK_DISABLE = 0x0, ++ PERFCOUNTER_OFF_MASK_ENABLE = 0x1, ++} PERFCOUNTER_OFF_MASK; ++typedef enum PERFCOUNTER_ACTIVE { ++ PERFCOUNTER_IS_IDLE = 0x0, ++ PERFCOUNTER_IS_ACTIVE = 0x1, ++} PERFCOUNTER_ACTIVE; ++typedef enum PERFCOUNTER_INT_TYPE { ++ PERFCOUNTER_INT_TYPE_LEVEL = 0x0, ++ PERFCOUNTER_INT_TYPE_PULSE = 0x1, ++} PERFCOUNTER_INT_TYPE; ++typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE { ++ PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x0, ++ PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x1, ++} PERFCOUNTER_COUNTED_VALUE_TYPE; ++typedef enum PERFCOUNTER_CNTL_SEL { ++ PERFCOUNTER_CNTL_SEL_0 = 0x0, ++ PERFCOUNTER_CNTL_SEL_1 = 0x1, ++ PERFCOUNTER_CNTL_SEL_2 = 0x2, ++ PERFCOUNTER_CNTL_SEL_3 = 0x3, ++ PERFCOUNTER_CNTL_SEL_4 = 0x4, ++ PERFCOUNTER_CNTL_SEL_5 = 0x5, ++ PERFCOUNTER_CNTL_SEL_6 = 0x6, ++ PERFCOUNTER_CNTL_SEL_7 = 0x7, ++} PERFCOUNTER_CNTL_SEL; ++typedef enum PERFCOUNTER_CNT0_STATE { ++ PERFCOUNTER_CNT0_STATE_RESET = 0x0, ++ PERFCOUNTER_CNT0_STATE_START = 0x1, ++ PERFCOUNTER_CNT0_STATE_FREEZE = 0x2, ++ PERFCOUNTER_CNT0_STATE_HW = 0x3, ++} PERFCOUNTER_CNT0_STATE; ++typedef enum PERFCOUNTER_STATE_SEL0 { ++ PERFCOUNTER_STATE_SEL0_GLOBAL = 0x0, ++ PERFCOUNTER_STATE_SEL0_LOCAL = 0x1, ++} PERFCOUNTER_STATE_SEL0; ++typedef enum PERFCOUNTER_CNT1_STATE { ++ PERFCOUNTER_CNT1_STATE_RESET = 0x0, ++ PERFCOUNTER_CNT1_STATE_START = 0x1, ++ PERFCOUNTER_CNT1_STATE_FREEZE = 0x2, ++ PERFCOUNTER_CNT1_STATE_HW = 0x3, ++} PERFCOUNTER_CNT1_STATE; ++typedef enum PERFCOUNTER_STATE_SEL1 { ++ PERFCOUNTER_STATE_SEL1_GLOBAL = 0x0, ++ PERFCOUNTER_STATE_SEL1_LOCAL = 0x1, ++} PERFCOUNTER_STATE_SEL1; ++typedef enum PERFCOUNTER_CNT2_STATE { ++ PERFCOUNTER_CNT2_STATE_RESET = 0x0, ++ PERFCOUNTER_CNT2_STATE_START = 0x1, ++ PERFCOUNTER_CNT2_STATE_FREEZE = 0x2, ++ PERFCOUNTER_CNT2_STATE_HW = 0x3, ++} PERFCOUNTER_CNT2_STATE; ++typedef enum PERFCOUNTER_STATE_SEL2 { ++ PERFCOUNTER_STATE_SEL2_GLOBAL = 0x0, ++ PERFCOUNTER_STATE_SEL2_LOCAL = 0x1, ++} PERFCOUNTER_STATE_SEL2; ++typedef enum PERFCOUNTER_CNT3_STATE { ++ PERFCOUNTER_CNT3_STATE_RESET = 0x0, ++ PERFCOUNTER_CNT3_STATE_START = 0x1, ++ PERFCOUNTER_CNT3_STATE_FREEZE = 0x2, ++ PERFCOUNTER_CNT3_STATE_HW = 0x3, ++} PERFCOUNTER_CNT3_STATE; ++typedef enum PERFCOUNTER_STATE_SEL3 { ++ PERFCOUNTER_STATE_SEL3_GLOBAL = 0x0, ++ PERFCOUNTER_STATE_SEL3_LOCAL = 0x1, ++} PERFCOUNTER_STATE_SEL3; ++typedef enum PERFCOUNTER_CNT4_STATE { ++ PERFCOUNTER_CNT4_STATE_RESET = 0x0, ++ PERFCOUNTER_CNT4_STATE_START = 0x1, ++ PERFCOUNTER_CNT4_STATE_FREEZE = 0x2, ++ PERFCOUNTER_CNT4_STATE_HW = 0x3, ++} PERFCOUNTER_CNT4_STATE; ++typedef enum PERFCOUNTER_STATE_SEL4 { ++ PERFCOUNTER_STATE_SEL4_GLOBAL = 0x0, ++ PERFCOUNTER_STATE_SEL4_LOCAL = 0x1, ++} PERFCOUNTER_STATE_SEL4; ++typedef enum PERFCOUNTER_CNT5_STATE { ++ PERFCOUNTER_CNT5_STATE_RESET = 0x0, ++ PERFCOUNTER_CNT5_STATE_START = 0x1, ++ PERFCOUNTER_CNT5_STATE_FREEZE = 0x2, ++ PERFCOUNTER_CNT5_STATE_HW = 0x3, ++} PERFCOUNTER_CNT5_STATE; ++typedef enum PERFCOUNTER_STATE_SEL5 { ++ PERFCOUNTER_STATE_SEL5_GLOBAL = 0x0, ++ PERFCOUNTER_STATE_SEL5_LOCAL = 0x1, ++} PERFCOUNTER_STATE_SEL5; ++typedef enum PERFCOUNTER_CNT6_STATE { ++ PERFCOUNTER_CNT6_STATE_RESET = 0x0, ++ PERFCOUNTER_CNT6_STATE_START = 0x1, ++ PERFCOUNTER_CNT6_STATE_FREEZE = 0x2, ++ PERFCOUNTER_CNT6_STATE_HW = 0x3, ++} PERFCOUNTER_CNT6_STATE; ++typedef enum PERFCOUNTER_STATE_SEL6 { ++ PERFCOUNTER_STATE_SEL6_GLOBAL = 0x0, ++ PERFCOUNTER_STATE_SEL6_LOCAL = 0x1, ++} PERFCOUNTER_STATE_SEL6; ++typedef enum PERFCOUNTER_CNT7_STATE { ++ PERFCOUNTER_CNT7_STATE_RESET = 0x0, ++ PERFCOUNTER_CNT7_STATE_START = 0x1, ++ PERFCOUNTER_CNT7_STATE_FREEZE = 0x2, ++ PERFCOUNTER_CNT7_STATE_HW = 0x3, ++} PERFCOUNTER_CNT7_STATE; ++typedef enum PERFCOUNTER_STATE_SEL7 { ++ PERFCOUNTER_STATE_SEL7_GLOBAL = 0x0, ++ PERFCOUNTER_STATE_SEL7_LOCAL = 0x1, ++} PERFCOUNTER_STATE_SEL7; ++typedef enum PERFMON_STATE { ++ PERFMON_STATE_RESET = 0x0, ++ PERFMON_STATE_START = 0x1, ++ PERFMON_STATE_FREEZE = 0x2, ++ PERFMON_STATE_HW = 0x3, ++} PERFMON_STATE; ++typedef enum PERFMON_CNTOFF_AND_OR { ++ PERFMON_CNTOFF_OR = 0x0, ++ PERFMON_CNTOFF_AND = 0x1, ++} PERFMON_CNTOFF_AND_OR; ++typedef enum PERFMON_CNTOFF_INT_EN { ++ PERFMON_CNTOFF_INT_DISABLE = 0x0, ++ PERFMON_CNTOFF_INT_ENABLE = 0x1, ++} PERFMON_CNTOFF_INT_EN; ++typedef enum PERFMON_CNTOFF_INT_TYPE { ++ PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x0, ++ PERFMON_CNTOFF_INT_TYPE_PULSE = 0x1, ++} PERFMON_CNTOFF_INT_TYPE; ++typedef enum LptNumBanks { ++ LPT_NUM_BANKS_2BANK = 0x0, ++ LPT_NUM_BANKS_4BANK = 0x1, ++ LPT_NUM_BANKS_8BANK = 0x2, ++ LPT_NUM_BANKS_16BANK = 0x3, ++ LPT_NUM_BANKS_32BANK = 0x4, ++} LptNumBanks; ++typedef enum DCIO_DC_GENERICA_SEL { ++ DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x0, ++ DCIO_GENERICA_SEL_STEREOSYNC = 0x1, ++ DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2, ++ DCIO_GENERICA_SEL_DACB_PIXCLK = 0x3, ++ DCIO_GENERICA_SEL_DVOA_CTL3 = 0x4, ++ DCIO_GENERICA_SEL_P1_PLLCLK = 0x5, ++ DCIO_GENERICA_SEL_P2_PLLCLK = 0x6, ++ DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x7, ++ DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x8, ++ DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x9, ++ DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa, ++ DCIO_GENERICA_SEL_SYNCEN = 0xb, ++ DCIO_GENERICA_SEL_GENERICA_SCG = 0xc, ++ DCIO_GENERICA_SEL_RESERVED_VALUE13 = 0xd, ++ DCIO_GENERICA_SEL_RESERVED_VALUE14 = 0xe, ++ DCIO_GENERICA_SEL_RESERVED_VALUE15 = 0xf, ++ DCIO_GENERICA_SEL_GENERICA_DPRX = 0x10, ++ DCIO_GENERICA_SEL_GENERICB_DPRX = 0x11, ++} DCIO_DC_GENERICA_SEL; ++typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL { ++ DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x0, ++ DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x1, ++ DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2, ++ DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x3, ++ DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x4, ++ DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x5, ++ DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x6, ++ DCIO_UNIPHYLPA_TEST_REFDIV_CLK = 0x7, ++ DCIO_UNIPHYLPB_TEST_REFDIV_CLK = 0x8, ++} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; ++typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL { ++ DCIO_UNIPHYA_FBDIV_CLK = 0x0, ++ DCIO_UNIPHYB_FBDIV_CLK = 0x1, ++ DCIO_UNIPHYC_FBDIV_CLK = 0x2, ++ DCIO_UNIPHYD_FBDIV_CLK = 0x3, ++ DCIO_UNIPHYE_FBDIV_CLK = 0x4, ++ DCIO_UNIPHYF_FBDIV_CLK = 0x5, ++ DCIO_UNIPHYG_FBDIV_CLK = 0x6, ++ DCIO_UNIPHYLPA_FBDIV_CLK = 0x7, ++ DCIO_UNIPHYLPB_FBDIV_CLK = 0x8, ++} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; ++typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL { ++ DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x0, ++ DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x1, ++ DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2, ++ DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x3, ++ DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x4, ++ DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x5, ++ DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x6, ++ DCIO_UNIPHYLPA_FBDIV_SSC_CLK = 0x7, ++ DCIO_UNIPHYLPB_FBDIV_SSC_CLK = 0x8, ++} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; ++typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL { ++ DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x0, ++ DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x1, ++ DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2, ++ DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x3, ++ DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x4, ++ DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x5, ++ DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x6, ++ DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2 = 0x7, ++ DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2 = 0x8, ++} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; ++typedef enum DCIO_DC_GENERICB_SEL { ++ DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x0, ++ DCIO_GENERICB_SEL_STEREOSYNC = 0x1, ++ DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2, ++ DCIO_GENERICB_SEL_DACB_PIXCLK = 0x3, ++ DCIO_GENERICB_SEL_DVOA_CTL3 = 0x4, ++ DCIO_GENERICB_SEL_P1_PLLCLK = 0x5, ++ DCIO_GENERICB_SEL_P2_PLLCLK = 0x6, ++ DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x7, ++ DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x8, ++ DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x9, ++ DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa, ++ DCIO_GENERICB_SEL_SYNCEN = 0xb, ++ DCIO_GENERICB_SEL_GENERICA_SCG = 0xc, ++ DCIO_GENERICB_SEL_RESERVED_VALUE13 = 0xd, ++ DCIO_GENERICB_SEL_RESERVED_VALUE14 = 0xe, ++ DCIO_GENERICB_SEL_RESERVED_VALUE15 = 0xf, ++} DCIO_DC_GENERICB_SEL; ++typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL { ++ DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x0, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x1, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x3, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x4, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x5, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x6, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x7, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x8, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x9, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0xb, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0xc, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0xd, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0xe, ++ DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0xf, ++} DCIO_DC_PAD_EXTERN_SIG_SEL; ++typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS { ++ DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x0, ++ DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x1, ++ DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2, ++ DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x3, ++} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS; ++typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL { ++ DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x0, ++ DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x1, ++ DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2, ++ DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x3, ++} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL; ++typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL { ++ DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x0, ++ DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x1, ++ DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2, ++ DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x3, ++} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; ++typedef enum DCIO_DC_GPIO_VIP_DEBUG { ++ DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x0, ++ DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x1, ++} DCIO_DC_GPIO_VIP_DEBUG; ++typedef enum DCIO_DC_GPIO_MACRO_DEBUG { ++ DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x0, ++ DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x1, ++ DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2, ++ DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x3, ++} DCIO_DC_GPIO_MACRO_DEBUG; ++typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL { ++ DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x0, ++ DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x1, ++} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL; ++typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN { ++ DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x0, ++ DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x1, ++} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN; ++typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE { ++ DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x0, ++ DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x1, ++} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE; ++typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION { ++ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0, ++ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1, ++ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2, ++ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3, ++ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4, ++ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5, ++ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6, ++ DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7, ++} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION; ++typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT { ++ DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x0, ++ DCIO_UNIPHY_CHANNEL_INVERTED = 0x1, ++} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; ++typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK { ++ DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x0, ++ DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x1, ++ DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2, ++ DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3, ++} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; ++typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE { ++ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x0, ++ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x1, ++ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2, ++ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x3, ++} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; ++typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN { ++ DCIO_VIP_MUX_EN_DVO = 0x0, ++ DCIO_VIP_MUX_EN_VIP = 0x1, ++} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN; ++typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN { ++ DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x0, ++ DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x1, ++} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN; ++typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN { ++ DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x0, ++ DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x1, ++} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN; ++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN { ++ DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0, ++ DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1, ++} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN; ++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE { ++ DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x0, ++ DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x1, ++} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE; ++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL { ++ DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x0, ++ DCIO_LVTMA_SYNCEN_POL_INVERT = 0x1, ++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL; ++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON { ++ DCIO_LVTMA_DIGON_OFF = 0x0, ++ DCIO_LVTMA_DIGON_ON = 0x1, ++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON; ++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL { ++ DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x0, ++ DCIO_LVTMA_DIGON_POL_INVERT = 0x1, ++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL; ++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON { ++ DCIO_LVTMA_BLON_OFF = 0x0, ++ DCIO_LVTMA_BLON_ON = 0x1, ++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON; ++typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL { ++ DCIO_LVTMA_BLON_POL_NON_INVERT = 0x0, ++ DCIO_LVTMA_BLON_POL_INVERT = 0x1, ++} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL; ++typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN { ++ DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x0, ++ DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x1, ++} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN; ++typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN { ++ DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x0, ++ DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x1, ++} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; ++typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN { ++ DCIO_BL_PWM_DISABLE = 0x0, ++ DCIO_BL_PWM_ENABLE = 0x1, ++} DCIO_BL_PWM_CNTL_BL_PWM_EN; ++typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT { ++ DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x0, ++ DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x1, ++ DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2, ++ DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x3, ++} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT; ++typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE { ++ DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x0, ++ DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x1, ++} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; ++typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN { ++ DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x0, ++ DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x1, ++} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN; ++typedef enum DCIO_BL_PWM_GRP1_REG_LOCK { ++ DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x0, ++ DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x1, ++} DCIO_BL_PWM_GRP1_REG_LOCK; ++typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START { ++ DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x0, ++ DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x1, ++} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START; ++typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL { ++ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0, ++ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1, ++ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2, ++ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3, ++ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4, ++ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5, ++} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; ++typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN { ++ DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0, ++ DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1, ++} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; ++typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN { ++ DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x0, ++ DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x1, ++} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; ++typedef enum DCIO_GSL_SEL { ++ DCIO_GSL_SEL_GROUP_0 = 0x0, ++ DCIO_GSL_SEL_GROUP_1 = 0x1, ++ DCIO_GSL_SEL_GROUP_2 = 0x2, ++} DCIO_GSL_SEL; ++typedef enum DCIO_GENLK_CLK_GSL_MASK { ++ DCIO_GENLK_CLK_GSL_MASK_NO = 0x0, ++ DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x1, ++ DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2, ++} DCIO_GENLK_CLK_GSL_MASK; ++typedef enum DCIO_GENLK_VSYNC_GSL_MASK { ++ DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x0, ++ DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1, ++ DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2, ++} DCIO_GENLK_VSYNC_GSL_MASK; ++typedef enum DCIO_SWAPLOCK_A_GSL_MASK { ++ DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x0, ++ DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x1, ++ DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2, ++} DCIO_SWAPLOCK_A_GSL_MASK; ++typedef enum DCIO_SWAPLOCK_B_GSL_MASK { ++ DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x0, ++ DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x1, ++ DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2, ++} DCIO_SWAPLOCK_B_GSL_MASK; ++typedef enum DCIO_GSL_VSYNC_SEL { ++ DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0, ++ DCIO_GSL_VSYNC_SEL_PIPE1 = 0x1, ++ DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2, ++ DCIO_GSL_VSYNC_SEL_PIPE3 = 0x3, ++ DCIO_GSL_VSYNC_SEL_PIPE4 = 0x4, ++ DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5, ++} DCIO_GSL_VSYNC_SEL; ++typedef enum DCIO_GSL0_TIMING_SYNC_SEL { ++ DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x0, ++ DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, ++ DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, ++ DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, ++ DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, ++} DCIO_GSL0_TIMING_SYNC_SEL; ++typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL { ++ DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, ++ DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, ++ DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, ++ DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, ++ DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, ++} DCIO_GSL0_GLOBAL_UNLOCK_SEL; ++typedef enum DCIO_GSL1_TIMING_SYNC_SEL { ++ DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x0, ++ DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, ++ DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, ++ DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, ++ DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, ++} DCIO_GSL1_TIMING_SYNC_SEL; ++typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL { ++ DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, ++ DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, ++ DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, ++ DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, ++ DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, ++} DCIO_GSL1_GLOBAL_UNLOCK_SEL; ++typedef enum DCIO_GSL2_TIMING_SYNC_SEL { ++ DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x0, ++ DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, ++ DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, ++ DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, ++ DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, ++} DCIO_GSL2_TIMING_SYNC_SEL; ++typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL { ++ DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, ++ DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, ++ DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, ++ DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, ++ DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, ++} DCIO_GSL2_GLOBAL_UNLOCK_SEL; ++typedef enum DCIO_DC_GPU_TIMER_START_POSITION { ++ DCIO_GPU_TIMER_START_0_END_27 = 0x0, ++ DCIO_GPU_TIMER_START_1_END_28 = 0x1, ++ DCIO_GPU_TIMER_START_2_END_29 = 0x2, ++ DCIO_GPU_TIMER_START_3_END_30 = 0x3, ++ DCIO_GPU_TIMER_START_4_END_31 = 0x4, ++ DCIO_GPU_TIMER_START_6_END_33 = 0x5, ++ DCIO_GPU_TIMER_START_8_END_35 = 0x6, ++ DCIO_GPU_TIMER_START_10_END_37 = 0x7, ++} DCIO_DC_GPU_TIMER_START_POSITION; ++typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL { ++ DCIO_TEST_CLK_SEL_DISPCLK = 0x0, ++ DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x1, ++ DCIO_TEST_CLK_SEL_SCLK = 0x2, ++} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; ++typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS { ++ DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x0, ++ DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x1, ++} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; ++typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX { ++ DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x0, ++ DCIO_EXT_VSYNC_MUX_CRTC0 = 0x1, ++ DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2, ++ DCIO_EXT_VSYNC_MUX_CRTC2 = 0x3, ++ DCIO_EXT_VSYNC_MUX_CRTC3 = 0x4, ++ DCIO_EXT_VSYNC_MUX_CRTC4 = 0x5, ++ DCIO_EXT_VSYNC_MUX_CRTC5 = 0x6, ++ DCIO_EXT_VSYNC_MUX_GENERICB = 0x7, ++} DCIO_DCO_DCFE_EXT_VSYNC_MUX; ++typedef enum DCIO_DCO_EXT_VSYNC_MASK { ++ DCIO_EXT_VSYNC_MASK_NONE = 0x0, ++ DCIO_EXT_VSYNC_MASK_PIPE0 = 0x1, ++ DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2, ++ DCIO_EXT_VSYNC_MASK_PIPE2 = 0x3, ++ DCIO_EXT_VSYNC_MASK_PIPE3 = 0x4, ++ DCIO_EXT_VSYNC_MASK_PIPE4 = 0x5, ++ DCIO_EXT_VSYNC_MASK_PIPE5 = 0x6, ++ DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x7, ++} DCIO_DCO_EXT_VSYNC_MASK; ++typedef enum DCIO_DBG_OUT_PIN_SEL { ++ DCIO_DBG_OUT_PIN_SEL_LOW_12BIT = 0x0, ++ DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT = 0x1, ++} DCIO_DBG_OUT_PIN_SEL; ++typedef enum DCIO_DBG_OUT_12BIT_SEL { ++ DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT = 0x0, ++ DCIO_DBG_OUT_12BIT_SEL_MID_12BIT = 0x1, ++ DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2, ++ DCIO_DBG_OUT_12BIT_SEL_OVERRIDE = 0x3, ++} DCIO_DBG_OUT_12BIT_SEL; ++typedef enum DCIO_DSYNC_SOFT_RESET { ++ DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x0, ++ DCIO_DSYNC_SOFT_RESET_ASSERT = 0x1, ++} DCIO_DSYNC_SOFT_RESET; ++typedef enum DCIO_DACA_SOFT_RESET { ++ DCIO_DACA_SOFT_RESET_DEASSERT = 0x0, ++ DCIO_DACA_SOFT_RESET_ASSERT = 0x1, ++} DCIO_DACA_SOFT_RESET; ++typedef enum DCIO_DCRXPHY_SOFT_RESET { ++ DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x0, ++ DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x1, ++} DCIO_DCRXPHY_SOFT_RESET; ++typedef enum DCIO_DPHY_LANE_SEL { ++ DCIO_DPHY_LANE_SEL_LANE0 = 0x0, ++ DCIO_DPHY_LANE_SEL_LANE1 = 0x1, ++ DCIO_DPHY_LANE_SEL_LANE2 = 0x2, ++ DCIO_DPHY_LANE_SEL_LANE3 = 0x3, ++} DCIO_DPHY_LANE_SEL; ++typedef enum DCIO_DC_GPU_TIMER_READ_SELECT { ++ DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x0, ++ DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x1, ++ DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2, ++ DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x3, ++ DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4, ++ DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x5, ++ DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0xc, ++ DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0xd, ++ DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0xe, ++ DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0xf, ++ DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x10, ++ DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x11, ++ DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x18, ++ DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x19, ++ DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x1a, ++ DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x1b, ++ DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x1c, ++ DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x1d, ++ DCIO_GPU_TIMER_READ_SELECT_LOWER_DCFEV_P_FLIP = 0x24, ++ DCIO_GPU_TIMER_READ_SELECT_UPPER_DCFEV_P_FLIP = 0x25, ++} DCIO_DC_GPU_TIMER_READ_SELECT; ++typedef enum DCIO_IMPCAL_STEP_DELAY { ++ DCIO_IMPCAL_STEP_DELAY_1us = 0x0, ++ DCIO_IMPCAL_STEP_DELAY_2us = 0x1, ++ DCIO_IMPCAL_STEP_DELAY_3us = 0x2, ++ DCIO_IMPCAL_STEP_DELAY_4us = 0x3, ++ DCIO_IMPCAL_STEP_DELAY_5us = 0x4, ++ DCIO_IMPCAL_STEP_DELAY_6us = 0x5, ++ DCIO_IMPCAL_STEP_DELAY_7us = 0x6, ++ DCIO_IMPCAL_STEP_DELAY_8us = 0x7, ++ DCIO_IMPCAL_STEP_DELAY_9us = 0x8, ++ DCIO_IMPCAL_STEP_DELAY_10us = 0x9, ++ DCIO_IMPCAL_STEP_DELAY_11us = 0xa, ++ DCIO_IMPCAL_STEP_DELAY_12us = 0xb, ++ DCIO_IMPCAL_STEP_DELAY_13us = 0xc, ++ DCIO_IMPCAL_STEP_DELAY_14us = 0xd, ++ DCIO_IMPCAL_STEP_DELAY_15us = 0xe, ++ DCIO_IMPCAL_STEP_DELAY_16us = 0xf, ++} DCIO_IMPCAL_STEP_DELAY; ++typedef enum DCIO_UNIPHY_IMPCAL_SEL { ++ DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x0, ++ DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x1, ++} DCIO_UNIPHY_IMPCAL_SEL; ++typedef enum DCIOCHIP_HPD_SEL { ++ DCIOCHIP_HPD_SEL_ASYNC = 0x0, ++ DCIOCHIP_HPD_SEL_CLOCKED = 0x1, ++} DCIOCHIP_HPD_SEL; ++typedef enum DCIOCHIP_PAD_MODE { ++ DCIOCHIP_PAD_MODE_DDC = 0x0, ++ DCIOCHIP_PAD_MODE_DP = 0x1, ++} DCIOCHIP_PAD_MODE; ++typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE { ++ DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x0, ++ DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x1, ++} DCIOCHIP_AUXSLAVE_PAD_MODE; ++typedef enum DCIOCHIP_INVERT { ++ DCIOCHIP_POL_NON_INVERT = 0x0, ++ DCIOCHIP_POL_INVERT = 0x1, ++} DCIOCHIP_INVERT; ++typedef enum DCIOCHIP_PD_EN { ++ DCIOCHIP_PD_EN_NOTALLOW = 0x0, ++ DCIOCHIP_PD_EN_ALLOW = 0x1, ++} DCIOCHIP_PD_EN; ++typedef enum DCIOCHIP_GPIO_MASK_EN { ++ DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x0, ++ DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x1, ++} DCIOCHIP_GPIO_MASK_EN; ++typedef enum DCIOCHIP_MASK { ++ DCIOCHIP_MASK_DISABLE = 0x0, ++ DCIOCHIP_MASK_ENABLE = 0x1, ++} DCIOCHIP_MASK; ++typedef enum DCIOCHIP_GPIO_I2C_MASK { ++ DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x0, ++ DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x1, ++} DCIOCHIP_GPIO_I2C_MASK; ++typedef enum DCIOCHIP_GPIO_I2C_DRIVE { ++ DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x0, ++ DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x1, ++} DCIOCHIP_GPIO_I2C_DRIVE; ++typedef enum DCIOCHIP_GPIO_I2C_EN { ++ DCIOCHIP_GPIO_I2C_DISABLE = 0x0, ++ DCIOCHIP_GPIO_I2C_ENABLE = 0x1, ++} DCIOCHIP_GPIO_I2C_EN; ++typedef enum DCIOCHIP_MASK_4BIT { ++ DCIOCHIP_MASK_4BIT_DISABLE = 0x0, ++ DCIOCHIP_MASK_4BIT_ENABLE = 0xf, ++} DCIOCHIP_MASK_4BIT; ++typedef enum DCIOCHIP_ENABLE_4BIT { ++ DCIOCHIP_4BIT_DISABLE = 0x0, ++ DCIOCHIP_4BIT_ENABLE = 0xf, ++} DCIOCHIP_ENABLE_4BIT; ++typedef enum DCIOCHIP_MASK_5BIT { ++ DCIOCHIP_MASIK_5BIT_DISABLE = 0x0, ++ DCIOCHIP_MASIK_5BIT_ENABLE = 0x1f, ++} DCIOCHIP_MASK_5BIT; ++typedef enum DCIOCHIP_ENABLE_5BIT { ++ DCIOCHIP_5BIT_DISABLE = 0x0, ++ DCIOCHIP_5BIT_ENABLE = 0x1f, ++} DCIOCHIP_ENABLE_5BIT; ++typedef enum DCIOCHIP_MASK_2BIT { ++ DCIOCHIP_MASK_2BIT_DISABLE = 0x0, ++ DCIOCHIP_MASK_2BIT_ENABLE = 0x3, ++} DCIOCHIP_MASK_2BIT; ++typedef enum DCIOCHIP_ENABLE_2BIT { ++ DCIOCHIP_2BIT_DISABLE = 0x0, ++ DCIOCHIP_2BIT_ENABLE = 0x3, ++} DCIOCHIP_ENABLE_2BIT; ++typedef enum DCIOCHIP_REF_27_SRC_SEL { ++ DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x0, ++ DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x1, ++ DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2, ++ DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x3, ++} DCIOCHIP_REF_27_SRC_SEL; ++typedef enum DCIOCHIP_DVO_VREFPON { ++ DCIOCHIP_DVO_VREFPON_DISABLE = 0x0, ++ DCIOCHIP_DVO_VREFPON_ENABLE = 0x1, ++} DCIOCHIP_DVO_VREFPON; ++typedef enum DCIOCHIP_DVO_VREFSEL { ++ DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x0, ++ DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x1, ++} DCIOCHIP_DVO_VREFSEL; ++typedef enum DCP_GRPH_ENABLE { ++ DCP_GRPH_ENABLE_FALSE = 0x0, ++ DCP_GRPH_ENABLE_TRUE = 0x1, ++} DCP_GRPH_ENABLE; ++typedef enum DCP_GRPH_KEYER_ALPHA_SEL { ++ DCP_GRPH_KEYER_ALPHA_SEL_FALSE = 0x0, ++ DCP_GRPH_KEYER_ALPHA_SEL_TRUE = 0x1, ++} DCP_GRPH_KEYER_ALPHA_SEL; ++typedef enum DCP_GRPH_DEPTH { ++ DCP_GRPH_DEPTH_8BPP = 0x0, ++ DCP_GRPH_DEPTH_16BPP = 0x1, ++ DCP_GRPH_DEPTH_32BPP = 0x2, ++ DCP_GRPH_DEPTH_64BPP = 0x3, ++} DCP_GRPH_DEPTH; ++typedef enum DCP_GRPH_NUM_BANKS { ++ DCP_GRPH_NUM_BANKS_2BANK = 0x0, ++ DCP_GRPH_NUM_BANKS_4BANK = 0x1, ++ DCP_GRPH_NUM_BANKS_8BANK = 0x2, ++ DCP_GRPH_NUM_BANKS_16BANK = 0x3, ++} DCP_GRPH_NUM_BANKS; ++typedef enum DCP_GRPH_BANK_WIDTH { ++ DCP_GRPH_BANK_WIDTH_1 = 0x0, ++ DCP_GRPH_BANK_WIDTH_2 = 0x1, ++ DCP_GRPH_BANK_WIDTH_4 = 0x2, ++ DCP_GRPH_BANK_WIDTH_8 = 0x3, ++} DCP_GRPH_BANK_WIDTH; ++typedef enum DCP_GRPH_FORMAT { ++ DCP_GRPH_FORMAT_8BPP = 0x0, ++ DCP_GRPH_FORMAT_16BPP = 0x1, ++ DCP_GRPH_FORMAT_32BPP = 0x2, ++ DCP_GRPH_FORMAT_64BPP = 0x3, ++} DCP_GRPH_FORMAT; ++typedef enum DCP_GRPH_BANK_HEIGHT { ++ DCP_GRPH_BANK_HEIGHT_1 = 0x0, ++ DCP_GRPH_BANK_HEIGHT_2 = 0x1, ++ DCP_GRPH_BANK_HEIGHT_4 = 0x2, ++ DCP_GRPH_BANK_HEIGHT_8 = 0x3, ++} DCP_GRPH_BANK_HEIGHT; ++typedef enum DCP_GRPH_TILE_SPLIT { ++ DCP_GRPH_TILE_SPLIT_64B = 0x0, ++ DCP_GRPH_TILE_SPLIT_128B = 0x1, ++ DCP_GRPH_TILE_SPLIT_256B = 0x2, ++ DCP_GRPH_TILE_SPLIT_512B = 0x3, ++ DCP_GRPH_TILE_SPLIT_1B = 0x4, ++ DCP_GRPH_TILE_SPLIT_2B = 0x5, ++ DCP_GRPH_TILE_SPLIT_4B = 0x6, ++} DCP_GRPH_TILE_SPLIT; ++typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE { ++ DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE = 0x0, ++ DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE = 0x1, ++} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE; ++typedef enum DCP_GRPH_PRIVILEGED_ACCESS_ENABLE { ++ DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_FALSE = 0x0, ++ DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_TRUE = 0x1, ++} DCP_GRPH_PRIVILEGED_ACCESS_ENABLE; ++typedef enum DCP_GRPH_MACRO_TILE_ASPECT { ++ DCP_GRPH_MACRO_TILE_ASPECT_1 = 0x0, ++ DCP_GRPH_MACRO_TILE_ASPECT_2 = 0x1, ++ DCP_GRPH_MACRO_TILE_ASPECT_4 = 0x2, ++ DCP_GRPH_MACRO_TILE_ASPECT_8 = 0x3, ++} DCP_GRPH_MACRO_TILE_ASPECT; ++typedef enum DCP_GRPH_ARRAY_MODE { ++ DCP_GRPH_ARRAY_MODE_0 = 0x0, ++ DCP_GRPH_ARRAY_MODE_1 = 0x1, ++ DCP_GRPH_ARRAY_MODE_2 = 0x2, ++ DCP_GRPH_ARRAY_MODE_3 = 0x3, ++ DCP_GRPH_ARRAY_MODE_4 = 0x4, ++ DCP_GRPH_ARRAY_MODE_7 = 0x7, ++ DCP_GRPH_ARRAY_MODE_12 = 0xc, ++ DCP_GRPH_ARRAY_MODE_13 = 0xd, ++} DCP_GRPH_ARRAY_MODE; ++typedef enum DCP_GRPH_MICRO_TILE_MODE { ++ DCP_GRPH_MICRO_TILE_MODE_0 = 0x0, ++ DCP_GRPH_MICRO_TILE_MODE_1 = 0x1, ++ DCP_GRPH_MICRO_TILE_MODE_2 = 0x2, ++ DCP_GRPH_MICRO_TILE_MODE_3 = 0x3, ++} DCP_GRPH_MICRO_TILE_MODE; ++typedef enum DCP_GRPH_COLOR_EXPANSION_MODE { ++ DCP_GRPH_COLOR_EXPANSION_MODE_DEXP = 0x0, ++ DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP = 0x1, ++} DCP_GRPH_COLOR_EXPANSION_MODE; ++typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN { ++ DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE = 0x0, ++ DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE = 0x1, ++} DCP_GRPH_LUT_10BIT_BYPASS_EN; ++typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN { ++ DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE = 0x0, ++ DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE = 0x1, ++} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN; ++typedef enum DCP_GRPH_ENDIAN_SWAP { ++ DCP_GRPH_ENDIAN_SWAP_NONE = 0x0, ++ DCP_GRPH_ENDIAN_SWAP_8IN16 = 0x1, ++ DCP_GRPH_ENDIAN_SWAP_8IN32 = 0x2, ++ DCP_GRPH_ENDIAN_SWAP_8IN64 = 0x3, ++} DCP_GRPH_ENDIAN_SWAP; ++typedef enum DCP_GRPH_RED_CROSSBAR { ++ DCP_GRPH_RED_CROSSBAR_FROM_R = 0x0, ++ DCP_GRPH_RED_CROSSBAR_FROM_G = 0x1, ++ DCP_GRPH_RED_CROSSBAR_FROM_B = 0x2, ++ DCP_GRPH_RED_CROSSBAR_FROM_A = 0x3, ++} DCP_GRPH_RED_CROSSBAR; ++typedef enum DCP_GRPH_GREEN_CROSSBAR { ++ DCP_GRPH_GREEN_CROSSBAR_FROM_G = 0x0, ++ DCP_GRPH_GREEN_CROSSBAR_FROM_B = 0x1, ++ DCP_GRPH_GREEN_CROSSBAR_FROM_A = 0x2, ++ DCP_GRPH_GREEN_CROSSBAR_FROM_R = 0x3, ++} DCP_GRPH_GREEN_CROSSBAR; ++typedef enum DCP_GRPH_BLUE_CROSSBAR { ++ DCP_GRPH_BLUE_CROSSBAR_FROM_B = 0x0, ++ DCP_GRPH_BLUE_CROSSBAR_FROM_A = 0x1, ++ DCP_GRPH_BLUE_CROSSBAR_FROM_R = 0x2, ++ DCP_GRPH_BLUE_CROSSBAR_FROM_G = 0x3, ++} DCP_GRPH_BLUE_CROSSBAR; ++typedef enum DCP_GRPH_ALPHA_CROSSBAR { ++ DCP_GRPH_ALPHA_CROSSBAR_FROM_A = 0x0, ++ DCP_GRPH_ALPHA_CROSSBAR_FROM_R = 0x1, ++ DCP_GRPH_ALPHA_CROSSBAR_FROM_G = 0x2, ++ DCP_GRPH_ALPHA_CROSSBAR_FROM_B = 0x3, ++} DCP_GRPH_ALPHA_CROSSBAR; ++typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE { ++ DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE = 0x0, ++ DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE = 0x1, ++} DCP_GRPH_PRIMARY_DFQ_ENABLE; ++typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE { ++ DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE = 0x0, ++ DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE = 0x1, ++} DCP_GRPH_SECONDARY_DFQ_ENABLE; ++typedef enum DCP_GRPH_INPUT_GAMMA_MODE { ++ DCP_GRPH_INPUT_GAMMA_MODE_LUT = 0x0, ++ DCP_GRPH_INPUT_GAMMA_MODE_BYPASS = 0x1, ++} DCP_GRPH_INPUT_GAMMA_MODE; ++typedef enum DCP_GRPH_MODE_UPDATE_PENDING { ++ DCP_GRPH_MODE_UPDATE_PENDING_FALSE = 0x0, ++ DCP_GRPH_MODE_UPDATE_PENDING_TRUE = 0x1, ++} DCP_GRPH_MODE_UPDATE_PENDING; ++typedef enum DCP_GRPH_MODE_UPDATE_TAKEN { ++ DCP_GRPH_MODE_UPDATE_TAKEN_FALSE = 0x0, ++ DCP_GRPH_MODE_UPDATE_TAKEN_TRUE = 0x1, ++} DCP_GRPH_MODE_UPDATE_TAKEN; ++typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING { ++ DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE = 0x0, ++ DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE = 0x1, ++} DCP_GRPH_SURFACE_UPDATE_PENDING; ++typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN { ++ DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE = 0x0, ++ DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE = 0x1, ++} DCP_GRPH_SURFACE_UPDATE_TAKEN; ++typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE { ++ DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x0, ++ DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x1, ++} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE; ++typedef enum DCP_GRPH_UPDATE_LOCK { ++ DCP_GRPH_UPDATE_LOCK_FALSE = 0x0, ++ DCP_GRPH_UPDATE_LOCK_TRUE = 0x1, ++} DCP_GRPH_UPDATE_LOCK; ++typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK { ++ DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE = 0x0, ++ DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE = 0x1, ++} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK; ++typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE { ++ DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, ++ DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, ++} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE; ++typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE { ++ DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, ++ DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, ++} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE; ++typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN { ++ DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE = 0x0, ++ DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE = 0x1, ++} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN; ++typedef enum DCP_GRPH_XDMA_SUPER_AA_EN { ++ DCP_GRPH_XDMA_SUPER_AA_EN_FALSE = 0x0, ++ DCP_GRPH_XDMA_SUPER_AA_EN_TRUE = 0x1, ++} DCP_GRPH_XDMA_SUPER_AA_EN; ++typedef enum DCP_GRPH_DFQ_RESET { ++ DCP_GRPH_DFQ_RESET_FALSE = 0x0, ++ DCP_GRPH_DFQ_RESET_TRUE = 0x1, ++} DCP_GRPH_DFQ_RESET; ++typedef enum DCP_GRPH_DFQ_SIZE { ++ DCP_GRPH_DFQ_SIZE_DEEP1 = 0x0, ++ DCP_GRPH_DFQ_SIZE_DEEP2 = 0x1, ++ DCP_GRPH_DFQ_SIZE_DEEP3 = 0x2, ++ DCP_GRPH_DFQ_SIZE_DEEP4 = 0x3, ++ DCP_GRPH_DFQ_SIZE_DEEP5 = 0x4, ++ DCP_GRPH_DFQ_SIZE_DEEP6 = 0x5, ++ DCP_GRPH_DFQ_SIZE_DEEP7 = 0x6, ++ DCP_GRPH_DFQ_SIZE_DEEP8 = 0x7, ++} DCP_GRPH_DFQ_SIZE; ++typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES { ++ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1 = 0x0, ++ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2 = 0x1, ++ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3 = 0x2, ++ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4 = 0x3, ++ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5 = 0x4, ++ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6 = 0x5, ++ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7 = 0x6, ++ DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8 = 0x7, ++} DCP_GRPH_DFQ_MIN_FREE_ENTRIES; ++typedef enum DCP_GRPH_DFQ_RESET_ACK { ++ DCP_GRPH_DFQ_RESET_ACK_FALSE = 0x0, ++ DCP_GRPH_DFQ_RESET_ACK_TRUE = 0x1, ++} DCP_GRPH_DFQ_RESET_ACK; ++typedef enum DCP_GRPH_PFLIP_INT_CLEAR { ++ DCP_GRPH_PFLIP_INT_CLEAR_FALSE = 0x0, ++ DCP_GRPH_PFLIP_INT_CLEAR_TRUE = 0x1, ++} DCP_GRPH_PFLIP_INT_CLEAR; ++typedef enum DCP_GRPH_PFLIP_INT_MASK { ++ DCP_GRPH_PFLIP_INT_MASK_FALSE = 0x0, ++ DCP_GRPH_PFLIP_INT_MASK_TRUE = 0x1, ++} DCP_GRPH_PFLIP_INT_MASK; ++typedef enum DCP_GRPH_PFLIP_INT_TYPE { ++ DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL = 0x0, ++ DCP_GRPH_PFLIP_INT_TYPE_PULSE = 0x1, ++} DCP_GRPH_PFLIP_INT_TYPE; ++typedef enum DCP_GRPH_PRESCALE_SELECT { ++ DCP_GRPH_PRESCALE_SELECT_FIXED = 0x0, ++ DCP_GRPH_PRESCALE_SELECT_FLOATING = 0x1, ++} DCP_GRPH_PRESCALE_SELECT; ++typedef enum DCP_GRPH_PRESCALE_R_SIGN { ++ DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED = 0x0, ++ DCP_GRPH_PRESCALE_R_SIGN_SIGNED = 0x1, ++} DCP_GRPH_PRESCALE_R_SIGN; ++typedef enum DCP_GRPH_PRESCALE_G_SIGN { ++ DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED = 0x0, ++ DCP_GRPH_PRESCALE_G_SIGN_SIGNED = 0x1, ++} DCP_GRPH_PRESCALE_G_SIGN; ++typedef enum DCP_GRPH_PRESCALE_B_SIGN { ++ DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED = 0x0, ++ DCP_GRPH_PRESCALE_B_SIGN_SIGNED = 0x1, ++} DCP_GRPH_PRESCALE_B_SIGN; ++typedef enum DCP_GRPH_PRESCALE_BYPASS { ++ DCP_GRPH_PRESCALE_BYPASS_FALSE = 0x0, ++ DCP_GRPH_PRESCALE_BYPASS_TRUE = 0x1, ++} DCP_GRPH_PRESCALE_BYPASS; ++typedef enum DCP_INPUT_CSC_GRPH_MODE { ++ DCP_INPUT_CSC_GRPH_MODE_BYPASS = 0x0, ++ DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF = 0x1, ++ DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF = 0x2, ++ DCP_INPUT_CSC_GRPH_MODE_RESERVED = 0x3, ++} DCP_INPUT_CSC_GRPH_MODE; ++typedef enum DCP_OUTPUT_CSC_GRPH_MODE { ++ DCP_OUTPUT_CSC_GRPH_MODE_BYPASS = 0x0, ++ DCP_OUTPUT_CSC_GRPH_MODE_RGB = 0x1, ++ DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601 = 0x2, ++ DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709 = 0x3, ++ DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF = 0x4, ++ DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF = 0x5, ++ DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0 = 0x6, ++ DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1 = 0x7, ++} DCP_OUTPUT_CSC_GRPH_MODE; ++typedef enum DCP_DENORM_MODE { ++ DCP_DENORM_MODE_UNITY = 0x0, ++ DCP_DENORM_MODE_6BIT = 0x1, ++ DCP_DENORM_MODE_8BIT = 0x2, ++ DCP_DENORM_MODE_10BIT = 0x3, ++ DCP_DENORM_MODE_11BIT = 0x4, ++ DCP_DENORM_MODE_12BIT = 0x5, ++ DCP_DENORM_MODE_RESERVED0 = 0x6, ++ DCP_DENORM_MODE_RESERVED1 = 0x7, ++} DCP_DENORM_MODE; ++typedef enum DCP_DENORM_14BIT_OUT { ++ DCP_DENORM_14BIT_OUT_FALSE = 0x0, ++ DCP_DENORM_14BIT_OUT_TRUE = 0x1, ++} DCP_DENORM_14BIT_OUT; ++typedef enum DCP_OUT_ROUND_TRUNC_MODE { ++ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12 = 0x0, ++ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11 = 0x1, ++ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10 = 0x2, ++ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9 = 0x3, ++ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8 = 0x4, ++ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED = 0x5, ++ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14 = 0x6, ++ DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13 = 0x7, ++ DCP_OUT_ROUND_TRUNC_MODE_ROUND_12 = 0x8, ++ DCP_OUT_ROUND_TRUNC_MODE_ROUND_11 = 0x9, ++ DCP_OUT_ROUND_TRUNC_MODE_ROUND_10 = 0xa, ++ DCP_OUT_ROUND_TRUNC_MODE_ROUND_9 = 0xb, ++ DCP_OUT_ROUND_TRUNC_MODE_ROUND_8 = 0xc, ++ DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED = 0xd, ++ DCP_OUT_ROUND_TRUNC_MODE_ROUND_14 = 0xe, ++ DCP_OUT_ROUND_TRUNC_MODE_ROUND_13 = 0xf, ++} DCP_OUT_ROUND_TRUNC_MODE; ++typedef enum DCP_KEY_MODE { ++ DCP_KEY_MODE_ALPHA0 = 0x0, ++ DCP_KEY_MODE_ALPHA1 = 0x1, ++ DCP_KEY_MODE_IN_RANGE_ALPHA1 = 0x2, ++ DCP_KEY_MODE_IN_RANGE_ALPHA0 = 0x3, ++} DCP_KEY_MODE; ++typedef enum DCP_GRPH_DEGAMMA_MODE { ++ DCP_GRPH_DEGAMMA_MODE_BYPASS = 0x0, ++ DCP_GRPH_DEGAMMA_MODE_ROMA = 0x1, ++ DCP_GRPH_DEGAMMA_MODE_ROMB = 0x2, ++ DCP_GRPH_DEGAMMA_MODE_RESERVED = 0x3, ++} DCP_GRPH_DEGAMMA_MODE; ++typedef enum DCP_CURSOR2_DEGAMMA_MODE { ++ DCP_CURSOR2_DEGAMMA_MODE_BYPASS = 0x0, ++ DCP_CURSOR2_DEGAMMA_MODE_ROMA = 0x1, ++ DCP_CURSOR2_DEGAMMA_MODE_ROMB = 0x2, ++ DCP_CURSOR2_DEGAMMA_MODE_RESERVED = 0x3, ++} DCP_CURSOR2_DEGAMMA_MODE; ++typedef enum DCP_CURSOR_DEGAMMA_MODE { ++ DCP_CURSOR_DEGAMMA_MODE_BYPASS = 0x0, ++ DCP_CURSOR_DEGAMMA_MODE_ROMA = 0x1, ++ DCP_CURSOR_DEGAMMA_MODE_ROMB = 0x2, ++ DCP_CURSOR_DEGAMMA_MODE_RESERVED = 0x3, ++} DCP_CURSOR_DEGAMMA_MODE; ++typedef enum DCP_GRPH_GAMUT_REMAP_MODE { ++ DCP_GRPH_GAMUT_REMAP_MODE_BYPASS = 0x0, ++ DCP_GRPH_GAMUT_REMAP_MODE_ROMA = 0x1, ++ DCP_GRPH_GAMUT_REMAP_MODE_ROMB = 0x2, ++ DCP_GRPH_GAMUT_REMAP_MODE_RESERVED = 0x3, ++} DCP_GRPH_GAMUT_REMAP_MODE; ++typedef enum DCP_SPATIAL_DITHER_EN { ++ DCP_SPATIAL_DITHER_EN_FALSE = 0x0, ++ DCP_SPATIAL_DITHER_EN_TRUE = 0x1, ++} DCP_SPATIAL_DITHER_EN; ++typedef enum DCP_SPATIAL_DITHER_MODE { ++ DCP_SPATIAL_DITHER_MODE_BYPASS = 0x0, ++ DCP_SPATIAL_DITHER_MODE_ROMA = 0x1, ++ DCP_SPATIAL_DITHER_MODE_ROMB = 0x2, ++ DCP_SPATIAL_DITHER_MODE_RESERVED = 0x3, ++} DCP_SPATIAL_DITHER_MODE; ++typedef enum DCP_SPATIAL_DITHER_DEPTH { ++ DCP_SPATIAL_DITHER_DEPTH_30BPP = 0x0, ++ DCP_SPATIAL_DITHER_DEPTH_24BPP = 0x1, ++ DCP_SPATIAL_DITHER_DEPTH_36BPP = 0x2, ++ DCP_SPATIAL_DITHER_DEPTH_UNDEFINED = 0x3, ++} DCP_SPATIAL_DITHER_DEPTH; ++typedef enum DCP_FRAME_RANDOM_ENABLE { ++ DCP_FRAME_RANDOM_ENABLE_FALSE = 0x0, ++ DCP_FRAME_RANDOM_ENABLE_TRUE = 0x1, ++} DCP_FRAME_RANDOM_ENABLE; ++typedef enum DCP_RGB_RANDOM_ENABLE { ++ DCP_RGB_RANDOM_ENABLE_FALSE = 0x0, ++ DCP_RGB_RANDOM_ENABLE_TRUE = 0x1, ++} DCP_RGB_RANDOM_ENABLE; ++typedef enum DCP_HIGHPASS_RANDOM_ENABLE { ++ DCP_HIGHPASS_RANDOM_ENABLE_FALSE = 0x0, ++ DCP_HIGHPASS_RANDOM_ENABLE_TRUE = 0x1, ++} DCP_HIGHPASS_RANDOM_ENABLE; ++typedef enum DCP_CURSOR_EN { ++ DCP_CURSOR_EN_FALSE = 0x0, ++ DCP_CURSOR_EN_TRUE = 0x1, ++} DCP_CURSOR_EN; ++typedef enum DCP_CUR_INV_TRANS_CLAMP { ++ DCP_CUR_INV_TRANS_CLAMP_FALSE = 0x0, ++ DCP_CUR_INV_TRANS_CLAMP_TRUE = 0x1, ++} DCP_CUR_INV_TRANS_CLAMP; ++typedef enum DCP_CURSOR_MODE { ++ DCP_CURSOR_MODE_MONO_2BPP = 0x0, ++ DCP_CURSOR_MODE_24BPP_1BIT = 0x1, ++ DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI = 0x2, ++ DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI = 0x3, ++} DCP_CURSOR_MODE; ++typedef enum DCP_CURSOR_2X_MAGNIFY { ++ DCP_CURSOR_2X_MAGNIFY_FALSE = 0x0, ++ DCP_CURSOR_2X_MAGNIFY_TRUE = 0x1, ++} DCP_CURSOR_2X_MAGNIFY; ++typedef enum DCP_CURSOR_FORCE_MC_ON { ++ DCP_CURSOR_FORCE_MC_ON_FALSE = 0x0, ++ DCP_CURSOR_FORCE_MC_ON_TRUE = 0x1, ++} DCP_CURSOR_FORCE_MC_ON; ++typedef enum DCP_CURSOR_URGENT_CONTROL { ++ DCP_CURSOR_URGENT_CONTROL_MODE_0 = 0x0, ++ DCP_CURSOR_URGENT_CONTROL_MODE_1 = 0x1, ++ DCP_CURSOR_URGENT_CONTROL_MODE_2 = 0x2, ++ DCP_CURSOR_URGENT_CONTROL_MODE_3 = 0x3, ++ DCP_CURSOR_URGENT_CONTROL_MODE_4 = 0x4, ++} DCP_CURSOR_URGENT_CONTROL; ++typedef enum DCP_CURSOR_UPDATE_PENDING { ++ DCP_CURSOR_UPDATE_PENDING_FALSE = 0x0, ++ DCP_CURSOR_UPDATE_PENDING_TRUE = 0x1, ++} DCP_CURSOR_UPDATE_PENDING; ++typedef enum DCP_CURSOR_UPDATE_TAKEN { ++ DCP_CURSOR_UPDATE_TAKEN_FALSE = 0x0, ++ DCP_CURSOR_UPDATE_TAKEN_TRUE = 0x1, ++} DCP_CURSOR_UPDATE_TAKEN; ++typedef enum DCP_CURSOR_UPDATE_LOCK { ++ DCP_CURSOR_UPDATE_LOCK_FALSE = 0x0, ++ DCP_CURSOR_UPDATE_LOCK_TRUE = 0x1, ++} DCP_CURSOR_UPDATE_LOCK; ++typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE { ++ DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, ++ DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, ++} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE; ++typedef enum DCP_CURSOR_UPDATE_STEREO_MODE { ++ DCP_CURSOR_UPDATE_STEREO_MODE_BOTH = 0x0, ++ DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1, ++ DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED = 0x2, ++ DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3, ++} DCP_CURSOR_UPDATE_STEREO_MODE; ++typedef enum DCP_CURSOR2_EN { ++ DCP_CURSOR2_EN_FALSE = 0x0, ++ DCP_CURSOR2_EN_TRUE = 0x1, ++} DCP_CURSOR2_EN; ++typedef enum DCP_CUR2_INV_TRANS_CLAMP { ++ DCP_CUR2_INV_TRANS_CLAMP_FALSE = 0x0, ++ DCP_CUR2_INV_TRANS_CLAMP_TRUE = 0x1, ++} DCP_CUR2_INV_TRANS_CLAMP; ++typedef enum DCP_CURSOR2_MODE { ++ DCP_CURSOR2_MODE_MONO_2BPP = 0x0, ++ DCP_CURSOR2_MODE_24BPP_1BIT = 0x1, ++ DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI = 0x2, ++ DCP_CURSOR2_MODE_24BPP_8BIT_UNPREMULTI = 0x3, ++} DCP_CURSOR2_MODE; ++typedef enum DCP_CURSOR2_2X_MAGNIFY { ++ DCP_CURSOR2_2X_MAGNIFY_FALSE = 0x0, ++ DCP_CURSOR2_2X_MAGNIFY_TRUE = 0x1, ++} DCP_CURSOR2_2X_MAGNIFY; ++typedef enum DCP_CURSOR2_FORCE_MC_ON { ++ DCP_CURSOR2_FORCE_MC_ON_FALSE = 0x0, ++ DCP_CURSOR2_FORCE_MC_ON_TRUE = 0x1, ++} DCP_CURSOR2_FORCE_MC_ON; ++typedef enum DCP_CURSOR2_URGENT_CONTROL { ++ DCP_CURSOR2_URGENT_CONTROL_MODE_0 = 0x0, ++ DCP_CURSOR2_URGENT_CONTROL_MODE_1 = 0x1, ++ DCP_CURSOR2_URGENT_CONTROL_MODE_2 = 0x2, ++ DCP_CURSOR2_URGENT_CONTROL_MODE_3 = 0x3, ++ DCP_CURSOR2_URGENT_CONTROL_MODE_4 = 0x4, ++} DCP_CURSOR2_URGENT_CONTROL; ++typedef enum DCP_CURSOR2_UPDATE_PENDING { ++ DCP_CURSOR2_UPDATE_PENDING_FALSE = 0x0, ++ DCP_CURSOR2_UPDATE_PENDING_TRUE = 0x1, ++} DCP_CURSOR2_UPDATE_PENDING; ++typedef enum DCP_CURSOR2_UPDATE_TAKEN { ++ DCP_CURSOR2_UPDATE_TAKEN_FALSE = 0x0, ++ DCP_CURSOR2_UPDATE_TAKEN_TRUE = 0x1, ++} DCP_CURSOR2_UPDATE_TAKEN; ++typedef enum DCP_CURSOR2_UPDATE_LOCK { ++ DCP_CURSOR2_UPDATE_LOCK_FALSE = 0x0, ++ DCP_CURSOR2_UPDATE_LOCK_TRUE = 0x1, ++} DCP_CURSOR2_UPDATE_LOCK; ++typedef enum DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE { ++ DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_FALSE = 0x0, ++ DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_TRUE = 0x1, ++} DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE; ++typedef enum DCP_CURSOR2_UPDATE_STEREO_MODE { ++ DCP_CURSOR2_UPDATE_STEREO_MODE_BOTH = 0x0, ++ DCP_CURSOR2_UPDATE_STEREO_MODE_SECONDARY_ONLY = 0x1, ++ DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED = 0x2, ++ DCP_CURSOR2_UPDATE_STEREO_MODE_PRIMARY_ONLY = 0x3, ++} DCP_CURSOR2_UPDATE_STEREO_MODE; ++typedef enum DCP_CUR_REQUEST_FILTER_DIS { ++ DCP_CUR_REQUEST_FILTER_DIS_FALSE = 0x0, ++ DCP_CUR_REQUEST_FILTER_DIS_TRUE = 0x1, ++} DCP_CUR_REQUEST_FILTER_DIS; ++typedef enum DCP_CURSOR_STEREO_EN { ++ DCP_CURSOR_STEREO_EN_FALSE = 0x0, ++ DCP_CURSOR_STEREO_EN_TRUE = 0x1, ++} DCP_CURSOR_STEREO_EN; ++typedef enum DCP_CURSOR_STEREO_OFFSET_YNX { ++ DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION = 0x0, ++ DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION = 0x1, ++} DCP_CURSOR_STEREO_OFFSET_YNX; ++typedef enum DCP_CURSOR2_STEREO_EN { ++ DCP_CURSOR2_STEREO_EN_FALSE = 0x0, ++ DCP_CURSOR2_STEREO_EN_TRUE = 0x1, ++} DCP_CURSOR2_STEREO_EN; ++typedef enum DCP_CURSOR2_STEREO_OFFSET_YNX { ++ DCP_CURSOR2_STEREO_OFFSET_YNX_X_POSITION = 0x0, ++ DCP_CURSOR2_STEREO_OFFSET_YNX_Y_POSITION = 0x1, ++} DCP_CURSOR2_STEREO_OFFSET_YNX; ++typedef enum DCP_DC_LUT_RW_MODE { ++ DCP_DC_LUT_RW_MODE_256_ENTRY = 0x0, ++ DCP_DC_LUT_RW_MODE_PWL = 0x1, ++} DCP_DC_LUT_RW_MODE; ++typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE { ++ DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE = 0x0, ++ DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE = 0x1, ++} DCP_DC_LUT_VGA_ACCESS_ENABLE; ++typedef enum DCP_DC_LUT_AUTOFILL { ++ DCP_DC_LUT_AUTOFILL_FALSE = 0x0, ++ DCP_DC_LUT_AUTOFILL_TRUE = 0x1, ++} DCP_DC_LUT_AUTOFILL; ++typedef enum DCP_DC_LUT_AUTOFILL_DONE { ++ DCP_DC_LUT_AUTOFILL_DONE_FALSE = 0x0, ++ DCP_DC_LUT_AUTOFILL_DONE_TRUE = 0x1, ++} DCP_DC_LUT_AUTOFILL_DONE; ++typedef enum DCP_DC_LUT_INC_B { ++ DCP_DC_LUT_INC_B_NA = 0x0, ++ DCP_DC_LUT_INC_B_2 = 0x1, ++ DCP_DC_LUT_INC_B_4 = 0x2, ++ DCP_DC_LUT_INC_B_8 = 0x3, ++ DCP_DC_LUT_INC_B_16 = 0x4, ++ DCP_DC_LUT_INC_B_32 = 0x5, ++ DCP_DC_LUT_INC_B_64 = 0x6, ++ DCP_DC_LUT_INC_B_128 = 0x7, ++ DCP_DC_LUT_INC_B_256 = 0x8, ++ DCP_DC_LUT_INC_B_512 = 0x9, ++} DCP_DC_LUT_INC_B; ++typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN { ++ DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE = 0x0, ++ DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE = 0x1, ++} DCP_DC_LUT_DATA_B_SIGNED_EN; ++typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN { ++ DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE = 0x0, ++ DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE = 0x1, ++} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN; ++typedef enum DCP_DC_LUT_DATA_B_FORMAT { ++ DCP_DC_LUT_DATA_B_FORMAT_U0P10 = 0x0, ++ DCP_DC_LUT_DATA_B_FORMAT_S1P10 = 0x1, ++ DCP_DC_LUT_DATA_B_FORMAT_U1P11 = 0x2, ++ DCP_DC_LUT_DATA_B_FORMAT_U0P12 = 0x3, ++} DCP_DC_LUT_DATA_B_FORMAT; ++typedef enum DCP_DC_LUT_INC_G { ++ DCP_DC_LUT_INC_G_NA = 0x0, ++ DCP_DC_LUT_INC_G_2 = 0x1, ++ DCP_DC_LUT_INC_G_4 = 0x2, ++ DCP_DC_LUT_INC_G_8 = 0x3, ++ DCP_DC_LUT_INC_G_16 = 0x4, ++ DCP_DC_LUT_INC_G_32 = 0x5, ++ DCP_DC_LUT_INC_G_64 = 0x6, ++ DCP_DC_LUT_INC_G_128 = 0x7, ++ DCP_DC_LUT_INC_G_256 = 0x8, ++ DCP_DC_LUT_INC_G_512 = 0x9, ++} DCP_DC_LUT_INC_G; ++typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN { ++ DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE = 0x0, ++ DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE = 0x1, ++} DCP_DC_LUT_DATA_G_SIGNED_EN; ++typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN { ++ DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE = 0x0, ++ DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE = 0x1, ++} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN; ++typedef enum DCP_DC_LUT_DATA_G_FORMAT { ++ DCP_DC_LUT_DATA_G_FORMAT_U0P10 = 0x0, ++ DCP_DC_LUT_DATA_G_FORMAT_S1P10 = 0x1, ++ DCP_DC_LUT_DATA_G_FORMAT_U1P11 = 0x2, ++ DCP_DC_LUT_DATA_G_FORMAT_U0P12 = 0x3, ++} DCP_DC_LUT_DATA_G_FORMAT; ++typedef enum DCP_DC_LUT_INC_R { ++ DCP_DC_LUT_INC_R_NA = 0x0, ++ DCP_DC_LUT_INC_R_2 = 0x1, ++ DCP_DC_LUT_INC_R_4 = 0x2, ++ DCP_DC_LUT_INC_R_8 = 0x3, ++ DCP_DC_LUT_INC_R_16 = 0x4, ++ DCP_DC_LUT_INC_R_32 = 0x5, ++ DCP_DC_LUT_INC_R_64 = 0x6, ++ DCP_DC_LUT_INC_R_128 = 0x7, ++ DCP_DC_LUT_INC_R_256 = 0x8, ++ DCP_DC_LUT_INC_R_512 = 0x9, ++} DCP_DC_LUT_INC_R; ++typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN { ++ DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE = 0x0, ++ DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE = 0x1, ++} DCP_DC_LUT_DATA_R_SIGNED_EN; ++typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN { ++ DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE = 0x0, ++ DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE = 0x1, ++} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN; ++typedef enum DCP_DC_LUT_DATA_R_FORMAT { ++ DCP_DC_LUT_DATA_R_FORMAT_U0P10 = 0x0, ++ DCP_DC_LUT_DATA_R_FORMAT_S1P10 = 0x1, ++ DCP_DC_LUT_DATA_R_FORMAT_U1P11 = 0x2, ++ DCP_DC_LUT_DATA_R_FORMAT_U0P12 = 0x3, ++} DCP_DC_LUT_DATA_R_FORMAT; ++typedef enum DCP_CRC_ENABLE { ++ DCP_CRC_ENABLE_FALSE = 0x0, ++ DCP_CRC_ENABLE_TRUE = 0x1, ++} DCP_CRC_ENABLE; ++typedef enum DCP_CRC_SOURCE_SEL { ++ DCP_CRC_SOURCE_SEL_OUTPUT_PIX = 0x0, ++ DCP_CRC_SOURCE_SEL_INPUT_L32 = 0x1, ++ DCP_CRC_SOURCE_SEL_INPUT_H32 = 0x2, ++ DCP_CRC_SOURCE_SEL_OUTPUT_CNTL = 0x4, ++} DCP_CRC_SOURCE_SEL; ++typedef enum DCP_CRC_LINE_SEL { ++ DCP_CRC_LINE_SEL_RESERVED = 0x0, ++ DCP_CRC_LINE_SEL_EVEN = 0x1, ++ DCP_CRC_LINE_SEL_ODD = 0x2, ++ DCP_CRC_LINE_SEL_BOTH = 0x3, ++} DCP_CRC_LINE_SEL; ++typedef enum DCP_GRPH_FLIP_RATE { ++ DCP_GRPH_FLIP_RATE_1FRAME = 0x0, ++ DCP_GRPH_FLIP_RATE_2FRAME = 0x1, ++ DCP_GRPH_FLIP_RATE_3FRAME = 0x2, ++ DCP_GRPH_FLIP_RATE_4FRAME = 0x3, ++ DCP_GRPH_FLIP_RATE_5FRAME = 0x4, ++ DCP_GRPH_FLIP_RATE_6FRAME = 0x5, ++ DCP_GRPH_FLIP_RATE_7FRAME = 0x6, ++ DCP_GRPH_FLIP_RATE_8FRAME = 0x7, ++} DCP_GRPH_FLIP_RATE; ++typedef enum DCP_GRPH_FLIP_RATE_ENABLE { ++ DCP_GRPH_FLIP_RATE_ENABLE_FALSE = 0x0, ++ DCP_GRPH_FLIP_RATE_ENABLE_TRUE = 0x1, ++} DCP_GRPH_FLIP_RATE_ENABLE; ++typedef enum DCP_GSL0_EN { ++ DCP_GSL0_EN_FALSE = 0x0, ++ DCP_GSL0_EN_TRUE = 0x1, ++} DCP_GSL0_EN; ++typedef enum DCP_GSL1_EN { ++ DCP_GSL1_EN_FALSE = 0x0, ++ DCP_GSL1_EN_TRUE = 0x1, ++} DCP_GSL1_EN; ++typedef enum DCP_GSL2_EN { ++ DCP_GSL2_EN_FALSE = 0x0, ++ DCP_GSL2_EN_TRUE = 0x1, ++} DCP_GSL2_EN; ++typedef enum DCP_GSL_MASTER_EN { ++ DCP_GSL_MASTER_EN_FALSE = 0x0, ++ DCP_GSL_MASTER_EN_TRUE = 0x1, ++} DCP_GSL_MASTER_EN; ++typedef enum DCP_GSL_XDMA_GROUP { ++ DCP_GSL_XDMA_GROUP_VSYNC = 0x0, ++ DCP_GSL_XDMA_GROUP_HSYNC0 = 0x1, ++ DCP_GSL_XDMA_GROUP_HSYNC1 = 0x2, ++ DCP_GSL_XDMA_GROUP_HSYNC2 = 0x3, ++} DCP_GSL_XDMA_GROUP; ++typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN { ++ DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE = 0x0, ++ DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE = 0x1, ++} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN; ++typedef enum DCP_GSL_SYNC_SOURCE { ++ DCP_GSL_SYNC_SOURCE_FLIP = 0x0, ++ DCP_GSL_SYNC_SOURCE_PHASE0 = 0x1, ++ DCP_GSL_SYNC_SOURCE_RESET = 0x2, ++ DCP_GSL_SYNC_SOURCE_PHASE1 = 0x3, ++} DCP_GSL_SYNC_SOURCE; ++typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING { ++ DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE = 0x0, ++ DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE = 0x1, ++} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING; ++typedef enum DCP_TEST_DEBUG_WRITE_EN { ++ DCP_TEST_DEBUG_WRITE_EN_FALSE = 0x0, ++ DCP_TEST_DEBUG_WRITE_EN_TRUE = 0x1, ++} DCP_TEST_DEBUG_WRITE_EN; ++typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN { ++ DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE = 0x0, ++ DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE = 0x1, ++} DCP_GRPH_STEREOSYNC_FLIP_EN; ++typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE { ++ DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP = 0x0, ++ DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0 = 0x1, ++ DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET = 0x2, ++ DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1 = 0x3, ++} DCP_GRPH_STEREOSYNC_FLIP_MODE; ++typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE { ++ DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE = 0x0, ++ DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE = 0x1, ++} DCP_GRPH_STEREOSYNC_SELECT_DISABLE; ++typedef enum DCP_GRPH_ROTATION_ANGLE { ++ DCP_GRPH_ROTATION_ANGLE_0 = 0x0, ++ DCP_GRPH_ROTATION_ANGLE_90 = 0x1, ++ DCP_GRPH_ROTATION_ANGLE_180 = 0x2, ++ DCP_GRPH_ROTATION_ANGLE_270 = 0x3, ++} DCP_GRPH_ROTATION_ANGLE; ++typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN { ++ DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE = 0x0, ++ DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE = 0x1, ++} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN; ++typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE { ++ DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM = 0x0, ++ DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE= 0x1, ++} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE; ++typedef enum DCP_GRPH_REGAMMA_MODE { ++ DCP_GRPH_REGAMMA_MODE_BYPASS = 0x0, ++ DCP_GRPH_REGAMMA_MODE_SRGB = 0x1, ++ DCP_GRPH_REGAMMA_MODE_XVYCC = 0x2, ++ DCP_GRPH_REGAMMA_MODE_PROGA = 0x3, ++ DCP_GRPH_REGAMMA_MODE_PROGB = 0x4, ++} DCP_GRPH_REGAMMA_MODE; ++typedef enum DCP_ALPHA_ROUND_TRUNC_MODE { ++ DCP_ALPHA_ROUND_TRUNC_MODE_ROUND = 0x0, ++ DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC = 0x1, ++} DCP_ALPHA_ROUND_TRUNC_MODE; ++typedef enum DCP_CURSOR_ALPHA_BLND_ENA { ++ DCP_CURSOR_ALPHA_BLND_ENA_FALSE = 0x0, ++ DCP_CURSOR_ALPHA_BLND_ENA_TRUE = 0x1, ++} DCP_CURSOR_ALPHA_BLND_ENA; ++typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK { ++ DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE = 0x0, ++ DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE = 0x1, ++} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK; ++typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK { ++ DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x0, ++ DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE = 0x1, ++} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK; ++typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK { ++ DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE = 0x0, ++ DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE = 0x1, ++} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK; ++typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK { ++ DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x0, ++ DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE = 0x1, ++} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK; ++typedef enum DCP_GRPH_SURFACE_COUNTER_EN { ++ DCP_GRPH_SURFACE_COUNTER_EN_DISABLE = 0x0, ++ DCP_GRPH_SURFACE_COUNTER_EN_ENABLE = 0x1, ++} DCP_GRPH_SURFACE_COUNTER_EN; ++typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT { ++ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0 = 0x0, ++ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1 = 0x1, ++ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2 = 0x2, ++ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3 = 0x3, ++ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4 = 0x4, ++ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5 = 0x5, ++ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6 = 0x6, ++ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7 = 0x7, ++ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8 = 0x8, ++ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9 = 0x9, ++ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10 = 0xa, ++ DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11 = 0xb, ++} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT; ++typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED { ++ DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO = 0x0, ++ DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES = 0x1, ++} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED; ++typedef enum HDMI_KEEPOUT_MODE { ++ HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x0, ++ HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x1, ++} HDMI_KEEPOUT_MODE; ++typedef enum HDMI_CLOCK_CHANNEL_RATE { ++ HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x0, ++ HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x1, ++} HDMI_CLOCK_CHANNEL_RATE; ++typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED { ++ HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x0, ++ HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x1, ++} HDMI_NO_EXTRA_NULL_PACKET_FILLED; ++typedef enum HDMI_PACKET_GEN_VERSION { ++ HDMI_PACKET_GEN_VERSION_OLD = 0x0, ++ HDMI_PACKET_GEN_VERSION_NEW = 0x1, ++} HDMI_PACKET_GEN_VERSION; ++typedef enum HDMI_ERROR_ACK { ++ HDMI_ERROR_ACK_INT = 0x0, ++ HDMI_ERROR_NOT_ACK = 0x1, ++} HDMI_ERROR_ACK; ++typedef enum HDMI_ERROR_MASK { ++ HDMI_ERROR_MASK_INT = 0x0, ++ HDMI_ERROR_NOT_MASK = 0x1, ++} HDMI_ERROR_MASK; ++typedef enum HDMI_DEEP_COLOR_DEPTH { ++ HDMI_DEEP_COLOR_DEPTH_24BPP = 0x0, ++ HDMI_DEEP_COLOR_DEPTH_30BPP = 0x1, ++ HDMI_DEEP_COLOR_DEPTH_36BPP = 0x2, ++ HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x3, ++} HDMI_DEEP_COLOR_DEPTH; ++typedef enum HDMI_AUDIO_DELAY_EN { ++ HDMI_AUDIO_DELAY_DISABLE = 0x0, ++ HDMI_AUDIO_DELAY_58CLK = 0x1, ++ HDMI_AUDIO_DELAY_56CLK = 0x2, ++ HDMI_AUDIO_DELAY_RESERVED = 0x3, ++} HDMI_AUDIO_DELAY_EN; ++typedef enum HDMI_AUDIO_SEND_MAX_PACKETS { ++ HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x0, ++ HDMI_SEND_MAX_AUDIO_PACKETS = 0x1, ++} HDMI_AUDIO_SEND_MAX_PACKETS; ++typedef enum HDMI_ACR_SEND { ++ HDMI_ACR_NOT_SEND = 0x0, ++ HDMI_ACR_PKT_SEND = 0x1, ++} HDMI_ACR_SEND; ++typedef enum HDMI_ACR_CONT { ++ HDMI_ACR_CONT_DISABLE = 0x0, ++ HDMI_ACR_CONT_ENABLE = 0x1, ++} HDMI_ACR_CONT; ++typedef enum HDMI_ACR_SELECT { ++ HDMI_ACR_SELECT_HW = 0x0, ++ HDMI_ACR_SELECT_32K = 0x1, ++ HDMI_ACR_SELECT_44K = 0x2, ++ HDMI_ACR_SELECT_48K = 0x3, ++} HDMI_ACR_SELECT; ++typedef enum HDMI_ACR_SOURCE { ++ HDMI_ACR_SOURCE_HW = 0x0, ++ HDMI_ACR_SOURCE_SW = 0x1, ++} HDMI_ACR_SOURCE; ++typedef enum HDMI_ACR_N_MULTIPLE { ++ HDMI_ACR_0_MULTIPLE_RESERVED = 0x0, ++ HDMI_ACR_1_MULTIPLE = 0x1, ++ HDMI_ACR_2_MULTIPLE = 0x2, ++ HDMI_ACR_3_MULTIPLE_RESERVED = 0x3, ++ HDMI_ACR_4_MULTIPLE = 0x4, ++ HDMI_ACR_5_MULTIPLE_RESERVED = 0x5, ++ HDMI_ACR_6_MULTIPLE_RESERVED = 0x6, ++ HDMI_ACR_7_MULTIPLE_RESERVED = 0x7, ++} HDMI_ACR_N_MULTIPLE; ++typedef enum HDMI_ACR_AUDIO_PRIORITY { ++ HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x0, ++ HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x1, ++} HDMI_ACR_AUDIO_PRIORITY; ++typedef enum HDMI_NULL_SEND { ++ HDMI_NULL_NOT_SEND = 0x0, ++ HDMI_NULL_PKT_SEND = 0x1, ++} HDMI_NULL_SEND; ++typedef enum HDMI_GC_SEND { ++ HDMI_GC_NOT_SEND = 0x0, ++ HDMI_GC_PKT_SEND = 0x1, ++} HDMI_GC_SEND; ++typedef enum HDMI_GC_CONT { ++ HDMI_GC_CONT_DISABLE = 0x0, ++ HDMI_GC_CONT_ENABLE = 0x1, ++} HDMI_GC_CONT; ++typedef enum HDMI_ISRC_SEND { ++ HDMI_ISRC_NOT_SEND = 0x0, ++ HDMI_ISRC_PKT_SEND = 0x1, ++} HDMI_ISRC_SEND; ++typedef enum HDMI_ISRC_CONT { ++ HDMI_ISRC_CONT_DISABLE = 0x0, ++ HDMI_ISRC_CONT_ENABLE = 0x1, ++} HDMI_ISRC_CONT; ++typedef enum HDMI_AVI_INFO_SEND { ++ HDMI_AVI_INFO_NOT_SEND = 0x0, ++ HDMI_AVI_INFO_PKT_SEND = 0x1, ++} HDMI_AVI_INFO_SEND; ++typedef enum HDMI_AVI_INFO_CONT { ++ HDMI_AVI_INFO_CONT_DISABLE = 0x0, ++ HDMI_AVI_INFO_CONT_ENABLE = 0x1, ++} HDMI_AVI_INFO_CONT; ++typedef enum HDMI_AUDIO_INFO_SEND { ++ HDMI_AUDIO_INFO_NOT_SEND = 0x0, ++ HDMI_AUDIO_INFO_PKT_SEND = 0x1, ++} HDMI_AUDIO_INFO_SEND; ++typedef enum HDMI_AUDIO_INFO_CONT { ++ HDMI_AUDIO_INFO_CONT_DISABLE = 0x0, ++ HDMI_AUDIO_INFO_CONT_ENABLE = 0x1, ++} HDMI_AUDIO_INFO_CONT; ++typedef enum HDMI_MPEG_INFO_SEND { ++ HDMI_MPEG_INFO_NOT_SEND = 0x0, ++ HDMI_MPEG_INFO_PKT_SEND = 0x1, ++} HDMI_MPEG_INFO_SEND; ++typedef enum HDMI_MPEG_INFO_CONT { ++ HDMI_MPEG_INFO_CONT_DISABLE = 0x0, ++ HDMI_MPEG_INFO_CONT_ENABLE = 0x1, ++} HDMI_MPEG_INFO_CONT; ++typedef enum HDMI_GENERIC0_SEND { ++ HDMI_GENERIC0_NOT_SEND = 0x0, ++ HDMI_GENERIC0_PKT_SEND = 0x1, ++} HDMI_GENERIC0_SEND; ++typedef enum HDMI_GENERIC0_CONT { ++ HDMI_GENERIC0_CONT_DISABLE = 0x0, ++ HDMI_GENERIC0_CONT_ENABLE = 0x1, ++} HDMI_GENERIC0_CONT; ++typedef enum HDMI_GENERIC1_SEND { ++ HDMI_GENERIC1_NOT_SEND = 0x0, ++ HDMI_GENERIC1_PKT_SEND = 0x1, ++} HDMI_GENERIC1_SEND; ++typedef enum HDMI_GENERIC1_CONT { ++ HDMI_GENERIC1_CONT_DISABLE = 0x0, ++ HDMI_GENERIC1_CONT_ENABLE = 0x1, ++} HDMI_GENERIC1_CONT; ++typedef enum HDMI_GC_AVMUTE_CONT { ++ HDMI_GC_AVMUTE_CONT_DISABLE = 0x0, ++ HDMI_GC_AVMUTE_CONT_ENABLE = 0x1, ++} HDMI_GC_AVMUTE_CONT; ++typedef enum HDMI_PACKING_PHASE_OVERRIDE { ++ HDMI_PACKING_PHASE_SET_BY_HW = 0x0, ++ HDMI_PACKING_PHASE_SET_BY_SW = 0x1, ++} HDMI_PACKING_PHASE_OVERRIDE; ++typedef enum HDMI_GENERIC2_SEND { ++ HDMI_GENERIC2_NOT_SEND = 0x0, ++ HDMI_GENERIC2_PKT_SEND = 0x1, ++} HDMI_GENERIC2_SEND; ++typedef enum HDMI_GENERIC2_CONT { ++ HDMI_GENERIC2_CONT_DISABLE = 0x0, ++ HDMI_GENERIC2_CONT_ENABLE = 0x1, ++} HDMI_GENERIC2_CONT; ++typedef enum HDMI_GENERIC3_SEND { ++ HDMI_GENERIC3_NOT_SEND = 0x0, ++ HDMI_GENERIC3_PKT_SEND = 0x1, ++} HDMI_GENERIC3_SEND; ++typedef enum HDMI_GENERIC3_CONT { ++ HDMI_GENERIC3_CONT_DISABLE = 0x0, ++ HDMI_GENERIC3_CONT_ENABLE = 0x1, ++} HDMI_GENERIC3_CONT; ++typedef enum TMDS_PIXEL_ENCODING { ++ TMDS_PIXEL_ENCODING_444 = 0x0, ++ TMDS_PIXEL_ENCODING_422 = 0x1, ++} TMDS_PIXEL_ENCODING; ++typedef enum TMDS_COLOR_FORMAT { ++ TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP= 0x0, ++ TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x1, ++ TMDS_COLOR_FORMAT_DUAL30BPP = 0x2, ++ TMDS_COLOR_FORMAT_RESERVED = 0x3, ++} TMDS_COLOR_FORMAT; ++typedef enum TMDS_STEREOSYNC_CTL_SEL_REG { ++ TMDS_STEREOSYNC_CTL0 = 0x0, ++ TMDS_STEREOSYNC_CTL1 = 0x1, ++ TMDS_STEREOSYNC_CTL2 = 0x2, ++ TMDS_STEREOSYNC_CTL3 = 0x3, ++} TMDS_STEREOSYNC_CTL_SEL_REG; ++typedef enum TMDS_CTL0_DATA_SEL { ++ TMDS_CTL0_DATA_SEL0_RESERVED = 0x0, ++ TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x1, ++ TMDS_CTL0_DATA_SEL2_VSYNC = 0x2, ++ TMDS_CTL0_DATA_SEL3_RESERVED = 0x3, ++ TMDS_CTL0_DATA_SEL4_HSYNC = 0x4, ++ TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x5, ++ TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x6, ++ TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x7, ++} TMDS_CTL0_DATA_SEL; ++typedef enum TMDS_CTL0_DATA_DELAY { ++ TMDS_CTL0_DATA_DELAY_0PIX = 0x0, ++ TMDS_CTL0_DATA_DELAY_1PIX = 0x1, ++ TMDS_CTL0_DATA_DELAY_2PIX = 0x2, ++ TMDS_CTL0_DATA_DELAY_3PIX = 0x3, ++ TMDS_CTL0_DATA_DELAY_4PIX = 0x4, ++ TMDS_CTL0_DATA_DELAY_5PIX = 0x5, ++ TMDS_CTL0_DATA_DELAY_6PIX = 0x6, ++ TMDS_CTL0_DATA_DELAY_7PIX = 0x7, ++} TMDS_CTL0_DATA_DELAY; ++typedef enum TMDS_CTL0_DATA_INVERT { ++ TMDS_CTL0_DATA_NORMAL = 0x0, ++ TMDS_CTL0_DATA_INVERT_EN = 0x1, ++} TMDS_CTL0_DATA_INVERT; ++typedef enum TMDS_CTL0_DATA_MODULATION { ++ TMDS_CTL0_DATA_MODULATION_DISABLE = 0x0, ++ TMDS_CTL0_DATA_MODULATION_BIT0 = 0x1, ++ TMDS_CTL0_DATA_MODULATION_BIT1 = 0x2, ++ TMDS_CTL0_DATA_MODULATION_BIT2 = 0x3, ++} TMDS_CTL0_DATA_MODULATION; ++typedef enum TMDS_CTL0_PATTERN_OUT_EN { ++ TMDS_CTL0_PATTERN_OUT_DISABLE = 0x0, ++ TMDS_CTL0_PATTERN_OUT_ENABLE = 0x1, ++} TMDS_CTL0_PATTERN_OUT_EN; ++typedef enum TMDS_CTL1_DATA_SEL { ++ TMDS_CTL1_DATA_SEL0_RESERVED = 0x0, ++ TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x1, ++ TMDS_CTL1_DATA_SEL2_VSYNC = 0x2, ++ TMDS_CTL1_DATA_SEL3_RESERVED = 0x3, ++ TMDS_CTL1_DATA_SEL4_HSYNC = 0x4, ++ TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x5, ++ TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x6, ++ TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x7, ++} TMDS_CTL1_DATA_SEL; ++typedef enum TMDS_CTL1_DATA_DELAY { ++ TMDS_CTL1_DATA_DELAY_0PIX = 0x0, ++ TMDS_CTL1_DATA_DELAY_1PIX = 0x1, ++ TMDS_CTL1_DATA_DELAY_2PIX = 0x2, ++ TMDS_CTL1_DATA_DELAY_3PIX = 0x3, ++ TMDS_CTL1_DATA_DELAY_4PIX = 0x4, ++ TMDS_CTL1_DATA_DELAY_5PIX = 0x5, ++ TMDS_CTL1_DATA_DELAY_6PIX = 0x6, ++ TMDS_CTL1_DATA_DELAY_7PIX = 0x7, ++} TMDS_CTL1_DATA_DELAY; ++typedef enum TMDS_CTL1_DATA_INVERT { ++ TMDS_CTL1_DATA_NORMAL = 0x0, ++ TMDS_CTL1_DATA_INVERT_EN = 0x1, ++} TMDS_CTL1_DATA_INVERT; ++typedef enum TMDS_CTL1_DATA_MODULATION { ++ TMDS_CTL1_DATA_MODULATION_DISABLE = 0x0, ++ TMDS_CTL1_DATA_MODULATION_BIT0 = 0x1, ++ TMDS_CTL1_DATA_MODULATION_BIT1 = 0x2, ++ TMDS_CTL1_DATA_MODULATION_BIT2 = 0x3, ++} TMDS_CTL1_DATA_MODULATION; ++typedef enum TMDS_CTL1_PATTERN_OUT_EN { ++ TMDS_CTL1_PATTERN_OUT_DISABLE = 0x0, ++ TMDS_CTL1_PATTERN_OUT_ENABLE = 0x1, ++} TMDS_CTL1_PATTERN_OUT_EN; ++typedef enum TMDS_CTL2_DATA_SEL { ++ TMDS_CTL2_DATA_SEL0_RESERVED = 0x0, ++ TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x1, ++ TMDS_CTL2_DATA_SEL2_VSYNC = 0x2, ++ TMDS_CTL2_DATA_SEL3_RESERVED = 0x3, ++ TMDS_CTL2_DATA_SEL4_HSYNC = 0x4, ++ TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x5, ++ TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x6, ++ TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x7, ++} TMDS_CTL2_DATA_SEL; ++typedef enum TMDS_CTL2_DATA_DELAY { ++ TMDS_CTL2_DATA_DELAY_0PIX = 0x0, ++ TMDS_CTL2_DATA_DELAY_1PIX = 0x1, ++ TMDS_CTL2_DATA_DELAY_2PIX = 0x2, ++ TMDS_CTL2_DATA_DELAY_3PIX = 0x3, ++ TMDS_CTL2_DATA_DELAY_4PIX = 0x4, ++ TMDS_CTL2_DATA_DELAY_5PIX = 0x5, ++ TMDS_CTL2_DATA_DELAY_6PIX = 0x6, ++ TMDS_CTL2_DATA_DELAY_7PIX = 0x7, ++} TMDS_CTL2_DATA_DELAY; ++typedef enum TMDS_CTL2_DATA_INVERT { ++ TMDS_CTL2_DATA_NORMAL = 0x0, ++ TMDS_CTL2_DATA_INVERT_EN = 0x1, ++} TMDS_CTL2_DATA_INVERT; ++typedef enum TMDS_CTL2_DATA_MODULATION { ++ TMDS_CTL2_DATA_MODULATION_DISABLE = 0x0, ++ TMDS_CTL2_DATA_MODULATION_BIT0 = 0x1, ++ TMDS_CTL2_DATA_MODULATION_BIT1 = 0x2, ++ TMDS_CTL2_DATA_MODULATION_BIT2 = 0x3, ++} TMDS_CTL2_DATA_MODULATION; ++typedef enum TMDS_CTL2_PATTERN_OUT_EN { ++ TMDS_CTL2_PATTERN_OUT_DISABLE = 0x0, ++ TMDS_CTL2_PATTERN_OUT_ENABLE = 0x1, ++} TMDS_CTL2_PATTERN_OUT_EN; ++typedef enum TMDS_CTL3_DATA_DELAY { ++ TMDS_CTL3_DATA_DELAY_0PIX = 0x0, ++ TMDS_CTL3_DATA_DELAY_1PIX = 0x1, ++ TMDS_CTL3_DATA_DELAY_2PIX = 0x2, ++ TMDS_CTL3_DATA_DELAY_3PIX = 0x3, ++ TMDS_CTL3_DATA_DELAY_4PIX = 0x4, ++ TMDS_CTL3_DATA_DELAY_5PIX = 0x5, ++ TMDS_CTL3_DATA_DELAY_6PIX = 0x6, ++ TMDS_CTL3_DATA_DELAY_7PIX = 0x7, ++} TMDS_CTL3_DATA_DELAY; ++typedef enum TMDS_CTL3_DATA_INVERT { ++ TMDS_CTL3_DATA_NORMAL = 0x0, ++ TMDS_CTL3_DATA_INVERT_EN = 0x1, ++} TMDS_CTL3_DATA_INVERT; ++typedef enum TMDS_CTL3_DATA_MODULATION { ++ TMDS_CTL3_DATA_MODULATION_DISABLE = 0x0, ++ TMDS_CTL3_DATA_MODULATION_BIT0 = 0x1, ++ TMDS_CTL3_DATA_MODULATION_BIT1 = 0x2, ++ TMDS_CTL3_DATA_MODULATION_BIT2 = 0x3, ++} TMDS_CTL3_DATA_MODULATION; ++typedef enum TMDS_CTL3_PATTERN_OUT_EN { ++ TMDS_CTL3_PATTERN_OUT_DISABLE = 0x0, ++ TMDS_CTL3_PATTERN_OUT_ENABLE = 0x1, ++} TMDS_CTL3_PATTERN_OUT_EN; ++typedef enum TMDS_CTL3_DATA_SEL { ++ TMDS_CTL3_DATA_SEL0_RESERVED = 0x0, ++ TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x1, ++ TMDS_CTL3_DATA_SEL2_VSYNC = 0x2, ++ TMDS_CTL3_DATA_SEL3_RESERVED = 0x3, ++ TMDS_CTL3_DATA_SEL4_HSYNC = 0x4, ++ TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x5, ++ TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x6, ++ TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x7, ++} TMDS_CTL3_DATA_SEL; ++typedef enum DIG_FE_CNTL_SOURCE_SELECT { ++ DIG_FE_SOURCE_FROM_FMT0 = 0x0, ++ DIG_FE_SOURCE_FROM_FMT1 = 0x1, ++ DIG_FE_SOURCE_FROM_FMT2 = 0x2, ++ DIG_FE_SOURCE_FROM_FMT3 = 0x3, ++} DIG_FE_CNTL_SOURCE_SELECT; ++typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT { ++ DIG_FE_STEREOSYNC_FROM_FMT0 = 0x0, ++ DIG_FE_STEREOSYNC_FROM_FMT1 = 0x1, ++ DIG_FE_STEREOSYNC_FROM_FMT2 = 0x2, ++ DIG_FE_STEREOSYNC_FROM_FMT3 = 0x3, ++} DIG_FE_CNTL_STEREOSYNC_SELECT; ++typedef enum DIG_FIFO_READ_CLOCK_SRC { ++ DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x0, ++ DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x1, ++} DIG_FIFO_READ_CLOCK_SRC; ++typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL { ++ DIG_OUTPUT_CRC_ON_LINK0 = 0x0, ++ DIG_OUTPUT_CRC_ON_LINK1 = 0x1, ++} DIG_OUTPUT_CRC_CNTL_LINK_SEL; ++typedef enum DIG_OUTPUT_CRC_DATA_SEL { ++ DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x0, ++ DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x1, ++ DIG_OUTPUT_CRC_FOR_VBI = 0x2, ++ DIG_OUTPUT_CRC_FOR_AUDIO = 0x3, ++} DIG_OUTPUT_CRC_DATA_SEL; ++typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN { ++ DIG_IN_NORMAL_OPERATION = 0x0, ++ DIG_IN_DEBUG_MODE = 0x1, ++} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN; ++typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL { ++ DIG_10BIT_TEST_PATTERN = 0x0, ++ DIG_ALTERNATING_TEST_PATTERN = 0x1, ++} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL; ++typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN { ++ DIG_TEST_PATTERN_NORMAL = 0x0, ++ DIG_TEST_PATTERN_RANDOM = 0x1, ++} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN; ++typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET { ++ DIG_RANDOM_PATTERN_ENABLED = 0x0, ++ DIG_RANDOM_PATTERN_RESETED = 0x1, ++} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET; ++typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN { ++ DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x0, ++ DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x1, ++} DIG_TEST_PATTERN_EXTERNAL_RESET_EN; ++typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT { ++ DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x0, ++ DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x1, ++} DIG_RANDOM_PATTERN_SEED_RAN_PAT; ++typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL { ++ DIG_FIFO_USE_OVERWRITE_LEVEL = 0x0, ++ DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x1, ++} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL; ++typedef enum DIG_FIFO_ERROR_ACK { ++ DIG_FIFO_ERROR_ACK_INT = 0x0, ++ DIG_FIFO_ERROR_NOT_ACK = 0x1, ++} DIG_FIFO_ERROR_ACK; ++typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE { ++ DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x0, ++ DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x1, ++} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE; ++typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX { ++ DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x0, ++ DIG_FIFO_FORCE_RECOMP_MINMAX = 0x1, ++} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX; ++typedef enum DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT { ++ DIG_DISPCLK_SWITCH_AT_EARLY_VBLANK = 0x0, ++ DIG_DISPCLK_SWITCH_AT_FIRST_HSYNC = 0x1, ++} DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT; ++typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK { ++ DIG_DISPCLK_SWITCH_ALLOWED_ACK_INT = 0x0, ++ DIG_DISPCLK_SWITCH_ALLOWED_INT_NOT_ACK = 0x1, ++} DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK; ++typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK { ++ DIG_DISPCLK_SWITCH_ALLOWED_MASK_INT = 0x0, ++ DIG_DISPCLK_SWITCH_ALLOWED_INT_UNMASK = 0x1, ++} DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK; ++typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK { ++ AFMT_INTERRUPT_DISABLE = 0x0, ++ AFMT_INTERRUPT_ENABLE = 0x1, ++} AFMT_INTERRUPT_STATUS_CHG_MASK; ++typedef enum HDMI_GC_AVMUTE { ++ HDMI_GC_AVMUTE_SET = 0x0, ++ HDMI_GC_AVMUTE_UNSET = 0x1, ++} HDMI_GC_AVMUTE; ++typedef enum HDMI_DEFAULT_PAHSE { ++ HDMI_DEFAULT_PHASE_IS_0 = 0x0, ++ HDMI_DEFAULT_PHASE_IS_1 = 0x1, ++} HDMI_DEFAULT_PAHSE; ++typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD { ++ AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS= 0x0, ++ AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x1, ++} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD; ++typedef enum AUDIO_LAYOUT_SELECT { ++ AUDIO_LAYOUT_0 = 0x0, ++ AUDIO_LAYOUT_1 = 0x1, ++} AUDIO_LAYOUT_SELECT; ++typedef enum AFMT_AUDIO_CRC_CONTROL_CONT { ++ AFMT_AUDIO_CRC_ONESHOT = 0x0, ++ AFMT_AUDIO_CRC_AUTO_RESTART = 0x1, ++} AFMT_AUDIO_CRC_CONTROL_CONT; ++typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE { ++ AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x0, ++ AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x1, ++} AFMT_AUDIO_CRC_CONTROL_SOURCE; ++typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL { ++ AFMT_AUDIO_CRC_CH0_SIG = 0x0, ++ AFMT_AUDIO_CRC_CH1_SIG = 0x1, ++ AFMT_AUDIO_CRC_CH2_SIG = 0x2, ++ AFMT_AUDIO_CRC_CH3_SIG = 0x3, ++ AFMT_AUDIO_CRC_CH4_SIG = 0x4, ++ AFMT_AUDIO_CRC_CH5_SIG = 0x5, ++ AFMT_AUDIO_CRC_CH6_SIG = 0x6, ++ AFMT_AUDIO_CRC_CH7_SIG = 0x7, ++ AFMT_AUDIO_CRC_RESERVED = 0x8, ++ AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x9, ++} AFMT_AUDIO_CRC_CONTROL_CH_SEL; ++typedef enum AFMT_RAMP_CONTROL0_SIGN { ++ AFMT_RAMP_SIGNED = 0x0, ++ AFMT_RAMP_UNSIGNED = 0x1, ++} AFMT_RAMP_CONTROL0_SIGN; ++typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND { ++ AFMT_AUDIO_PACKET_SENT_DISABLED = 0x0, ++ AFMT_AUDIO_PACKET_SENT_ENABLED = 0x1, ++} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND; ++typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS { ++ AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED= 0x0, ++ AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x1, ++} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS; ++typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE { ++ AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x0, ++ AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x1, ++} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE; ++typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT { ++ AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x0, ++ AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x1, ++ AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x2, ++ AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x3, ++ AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x4, ++ AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x5, ++ AFMT_AUDIO_SRC_RESERVED = 0x6, ++} AFMT_AUDIO_SRC_CONTROL_SELECT; ++typedef enum DIG_BE_CNTL_MODE { ++ DIG_BE_DP_SST_MODE = 0x0, ++ DIG_BE_RESERVED1 = 0x1, ++ DIG_BE_TMDS_DVI_MODE = 0x2, ++ DIG_BE_TMDS_HDMI_MODE = 0x3, ++ DIG_BE_SDVO_RESERVED = 0x4, ++ DIG_BE_DP_MST_MODE = 0x5, ++ DIG_BE_RESERVED2 = 0x6, ++ DIG_BE_RESERVED3 = 0x7, ++} DIG_BE_CNTL_MODE; ++typedef enum DIG_BE_CNTL_HPD_SELECT { ++ DIG_BE_CNTL_HPD1 = 0x0, ++ DIG_BE_CNTL_HPD2 = 0x1, ++ DIG_BE_CNTL_HPD3 = 0x2, ++ DIG_BE_CNTL_HPD4 = 0x3, ++ DIG_BE_CNTL_HPD5 = 0x4, ++ DIG_BE_CNTL_HPD6 = 0x5, ++} DIG_BE_CNTL_HPD_SELECT; ++typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT { ++ LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x0, ++ LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x1, ++} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT; ++typedef enum TMDS_SYNC_PHASE { ++ TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x0, ++ TMDS_SYNC_PHASE_ON_FRAME_START = 0x1, ++} TMDS_SYNC_PHASE; ++typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL { ++ TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x0, ++ TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x1, ++} TMDS_DATA_SYNCHRONIZATION_DSINTSEL; ++typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK { ++ TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x0, ++ TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x1, ++} TMDS_TRANSMITTER_ENABLE_HPD_MASK; ++typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK { ++ TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x0, ++ TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x1, ++} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK; ++typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK { ++ TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x0, ++ TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x1, ++} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK; ++typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK { ++ TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x0, ++ TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON= 0x1, ++ TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x2, ++ TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x3, ++} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK; ++typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA { ++ TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x0, ++ TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x1, ++} TMDS_TRANSMITTER_CONTROL_IDSCKSELA; ++typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB { ++ TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x0, ++ TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x1, ++} TMDS_TRANSMITTER_CONTROL_IDSCKSELB; ++typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN { ++ TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x0, ++ TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x1, ++} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN; ++typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK { ++ TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x0, ++ TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x1, ++} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK; ++typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS { ++ TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x0, ++ TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x1, ++} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS; ++typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS { ++ TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x0, ++ TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x1, ++} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS; ++typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN { ++ TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x0, ++ TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x1, ++} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN; ++typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA { ++ TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x0, ++ TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x1, ++} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA; ++typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB { ++ TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x0, ++ TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x1, ++} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB; ++typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA { ++ TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x0, ++ TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x1, ++ TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x2, ++ TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x3, ++} TMDS_REG_TEST_OUTPUTA_CNTLA; ++typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB { ++ TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x0, ++ TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x1, ++ TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x2, ++ TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x3, ++} TMDS_REG_TEST_OUTPUTB_CNTLB; ++typedef enum DP_LINK_TRAINING_COMPLETE { ++ DP_LINK_TRAINING_NOT_COMPLETE = 0x0, ++ DP_LINK_TRAINING_ALREADY_COMPLETE = 0x1, ++} DP_LINK_TRAINING_COMPLETE; ++typedef enum DP_EMBEDDED_PANEL_MODE { ++ DP_EXTERNAL_PANEL = 0x0, ++ DP_EMBEDDED_PANEL = 0x1, ++} DP_EMBEDDED_PANEL_MODE; ++typedef enum DP_PIXEL_ENCODING { ++ DP_PIXEL_ENCODING_RGB444 = 0x0, ++ DP_PIXEL_ENCODING_YCBCR422 = 0x1, ++ DP_PIXEL_ENCODING_YCBCR444 = 0x2, ++ DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x3, ++ DP_PIXEL_ENCODING_Y_ONLY = 0x4, ++ DP_PIXEL_ENCODING_RESERVED = 0x5, ++} DP_PIXEL_ENCODING; ++typedef enum DP_DYN_RANGE { ++ DP_DYN_VESA_RANGE = 0x0, ++ DP_DYN_CEA_RANGE = 0x1, ++} DP_DYN_RANGE; ++typedef enum DP_YCBCR_RANGE { ++ DP_YCBCR_RANGE_BT601_5 = 0x0, ++ DP_YCBCR_RANGE_BT709_5 = 0x1, ++} DP_YCBCR_RANGE; ++typedef enum DP_COMPONENT_DEPTH { ++ DP_COMPONENT_DEPTH_6BPC = 0x0, ++ DP_COMPONENT_DEPTH_8BPC = 0x1, ++ DP_COMPONENT_DEPTH_10BPC = 0x2, ++ DP_COMPONENT_DEPTH_12BPC = 0x3, ++ DP_COMPONENT_DEPTH_16BPC = 0x4, ++ DP_COMPONENT_DEPTH_RESERVED = 0x5, ++} DP_COMPONENT_DEPTH; ++typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE { ++ MSA_MISC0_OVERRIDE_DISABLE = 0x0, ++ MSA_MISC0_OVERRIDE_ENABLE = 0x1, ++} DP_MSA_MISC0_OVERRIDE_ENABLE; ++typedef enum DP_UDI_LANES { ++ DP_UDI_1_LANE = 0x0, ++ DP_UDI_2_LANES = 0x1, ++ DP_UDI_LANES_RESERVED = 0x2, ++ DP_UDI_4_LANES = 0x3, ++} DP_UDI_LANES; ++typedef enum DP_VID_STREAM_DIS_DEFER { ++ DP_VID_STREAM_DIS_NO_DEFER = 0x0, ++ DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x1, ++ DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x2, ++} DP_VID_STREAM_DIS_DEFER; ++typedef enum DP_STEER_OVERFLOW_ACK { ++ DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x0, ++ DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x1, ++} DP_STEER_OVERFLOW_ACK; ++typedef enum DP_STEER_OVERFLOW_MASK { ++ DP_STEER_OVERFLOW_MASKED = 0x0, ++ DP_STEER_OVERFLOW_UNMASK = 0x1, ++} DP_STEER_OVERFLOW_MASK; ++typedef enum DP_TU_OVERFLOW_ACK { ++ DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x0, ++ DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x1, ++} DP_TU_OVERFLOW_ACK; ++typedef enum DP_VID_TIMING_MODE { ++ DP_VID_TIMING_MODE_ASYNC = 0x0, ++ DP_VID_TIMING_MODE_SYNC = 0x1, ++} DP_VID_TIMING_MODE; ++typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE { ++ DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x0, ++ DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x1, ++} DP_VID_M_N_DOUBLE_BUFFER_MODE; ++typedef enum DP_VID_M_N_GEN_EN { ++ DP_VID_M_N_PROGRAMMED_VIA_REG = 0x0, ++ DP_VID_M_N_CALC_AUTO = 0x1, ++} DP_VID_M_N_GEN_EN; ++typedef enum DP_VID_ENHANCED_FRAME_MODE { ++ VID_NORMAL_FRAME_MODE = 0x0, ++ VID_ENHANCED_MODE = 0x1, ++} DP_VID_ENHANCED_FRAME_MODE; ++typedef enum DP_VID_MSA_TOP_FIELD_MODE { ++ DP_TOP_FIELD_ONLY = 0x0, ++ DP_TOP_PLUS_BOTTOM_FIELD = 0x1, ++} DP_VID_MSA_TOP_FIELD_MODE; ++typedef enum DP_VID_VBID_FIELD_POL { ++ DP_VID_VBID_FIELD_POL_NORMAL = 0x0, ++ DP_VID_VBID_FIELD_POL_INV = 0x1, ++} DP_VID_VBID_FIELD_POL; ++typedef enum DP_VID_STREAM_DISABLE_ACK { ++ ID_STREAM_DISABLE_NO_ACK = 0x0, ++ ID_STREAM_DISABLE_ACKED = 0x1, ++} DP_VID_STREAM_DISABLE_ACK; ++typedef enum DP_VID_STREAM_DISABLE_MASK { ++ VID_STREAM_DISABLE_MASKED = 0x0, ++ VID_STREAM_DISABLE_UNMASK = 0x1, ++} DP_VID_STREAM_DISABLE_MASK; ++typedef enum DPHY_ATEST_SEL_LANE0 { ++ DPHY_ATEST_LANE0_PRBS_PATTERN = 0x0, ++ DPHY_ATEST_LANE0_REG_PATTERN = 0x1, ++} DPHY_ATEST_SEL_LANE0; ++typedef enum DPHY_ATEST_SEL_LANE1 { ++ DPHY_ATEST_LANE1_PRBS_PATTERN = 0x0, ++ DPHY_ATEST_LANE1_REG_PATTERN = 0x1, ++} DPHY_ATEST_SEL_LANE1; ++typedef enum DPHY_ATEST_SEL_LANE2 { ++ DPHY_ATEST_LANE2_PRBS_PATTERN = 0x0, ++ DPHY_ATEST_LANE2_REG_PATTERN = 0x1, ++} DPHY_ATEST_SEL_LANE2; ++typedef enum DPHY_ATEST_SEL_LANE3 { ++ DPHY_ATEST_LANE3_PRBS_PATTERN = 0x0, ++ DPHY_ATEST_LANE3_REG_PATTERN = 0x1, ++} DPHY_ATEST_SEL_LANE3; ++typedef enum DPHY_BYPASS { ++ DPHY_8B10B_OUTPUT = 0x0, ++ DPHY_DBG_OUTPUT = 0x1, ++} DPHY_BYPASS; ++typedef enum DPHY_SKEW_BYPASS { ++ DPHY_WITH_SKEW = 0x0, ++ DPHY_NO_SKEW = 0x1, ++} DPHY_SKEW_BYPASS; ++typedef enum DPHY_TRAINING_PATTERN_SEL { ++ DPHY_TRAINING_PATTERN_1 = 0x0, ++ DPHY_TRAINING_PATTERN_2 = 0x1, ++ DPHY_TRAINING_PATTERN_3 = 0x2, ++} DPHY_TRAINING_PATTERN_SEL; ++typedef enum DPHY_8B10B_RESET { ++ DPHY_8B10B_NOT_RESET = 0x0, ++ DPHY_8B10B_RESETET = 0x1, ++} DPHY_8B10B_RESET; ++typedef enum DP_DPHY_8B10B_EXT_DISP { ++ DP_DPHY_8B10B_EXT_DISP_ZERO = 0x0, ++ DP_DPHY_8B10B_EXT_DISP_ONE = 0x1, ++} DP_DPHY_8B10B_EXT_DISP; ++typedef enum DPHY_8B10B_CUR_DISP { ++ DPHY_8B10B_CUR_DISP_ZERO = 0x0, ++ DPHY_8B10B_CUR_DISP_ONE = 0x1, ++} DPHY_8B10B_CUR_DISP; ++typedef enum DPHY_PRBS_EN { ++ DPHY_PRBS_DISABLE = 0x0, ++ DPHY_PRBS_ENABLE = 0x1, ++} DPHY_PRBS_EN; ++typedef enum DPHY_PRBS_SEL { ++ DPHY_PRBS7_SELECTED = 0x0, ++ DPHY_PRBS23_SELECTED = 0x1, ++ DPHY_PRBS11_SELECTED = 0x2, ++} DPHY_PRBS_SEL; ++typedef enum DPHY_LOAD_BS_COUNT_START { ++ DPHY_LOAD_BS_COUNT_STARTED = 0x0, ++ DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x1, ++} DPHY_LOAD_BS_COUNT_START; ++typedef enum DPHY_CRC_EN { ++ DPHY_CRC_DISABLED = 0x0, ++ DPHY_CRC_ENABLED = 0x1, ++} DPHY_CRC_EN; ++typedef enum DPHY_CRC_CONT_EN { ++ DPHY_CRC_ONE_SHOT = 0x0, ++ DPHY_CRC_CONTINUOUS = 0x1, ++} DPHY_CRC_CONT_EN; ++typedef enum DPHY_CRC_FIELD { ++ DPHY_CRC_START_FROM_TOP_FIELD = 0x0, ++ DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x1, ++} DPHY_CRC_FIELD; ++typedef enum DPHY_CRC_SEL { ++ DPHY_CRC_LANE0_SELECTED = 0x0, ++ DPHY_CRC_LANE1_SELECTED = 0x1, ++ DPHY_CRC_LANE2_SELECTED = 0x2, ++ DPHY_CRC_LANE3_SELECTED = 0x3, ++} DPHY_CRC_SEL; ++typedef enum DPHY_RX_FAST_TRAINING_CAPABLE { ++ DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x0, ++ DPHY_FAST_TRAINING_CAPABLE = 0x1, ++} DPHY_RX_FAST_TRAINING_CAPABLE; ++typedef enum DP_SEC_COLLISION_ACK { ++ DP_SEC_COLLISION_ACK_NO_EFFECT = 0x0, ++ DP_SEC_COLLISION_ACK_CLR_FLAG = 0x1, ++} DP_SEC_COLLISION_ACK; ++typedef enum DP_SEC_AUDIO_MUTE { ++ DP_SEC_AUDIO_MUTE_HW_CTRL = 0x0, ++ DP_SEC_AUDIO_MUTE_SW_CTRL = 0x1, ++} DP_SEC_AUDIO_MUTE; ++typedef enum DP_SEC_TIMESTAMP_MODE { ++ DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x0, ++ DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x1, ++} DP_SEC_TIMESTAMP_MODE; ++typedef enum DP_SEC_ASP_PRIORITY { ++ DP_SEC_ASP_LOW_PRIORITY = 0x0, ++ DP_SEC_ASP_HIGH_PRIORITY = 0x1, ++} DP_SEC_ASP_PRIORITY; ++typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE { ++ DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x0, ++ DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x1, ++} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE; ++typedef enum DP_MSE_SAT_UPDATE_ACT { ++ DP_MSE_SAT_UPDATE_NO_ACTION = 0x0, ++ DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x1, ++ DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x2, ++} DP_MSE_SAT_UPDATE_ACT; ++typedef enum DP_MSE_LINK_LINE { ++ DP_MSE_LINK_LINE_32_MTP_LONG = 0x0, ++ DP_MSE_LINK_LINE_64_MTP_LONG = 0x1, ++ DP_MSE_LINK_LINE_128_MTP_LONG = 0x2, ++ DP_MSE_LINK_LINE_256_MTP_LONG = 0x3, ++} DP_MSE_LINK_LINE; ++typedef enum DP_MSE_BLANK_CODE { ++ DP_MSE_BLANK_CODE_SF_FILLED = 0x0, ++ DP_MSE_BLANK_CODE_ZERO_FILLED = 0x1, ++} DP_MSE_BLANK_CODE; ++typedef enum DP_MSE_TIMESTAMP_MODE { ++ DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x0, ++ DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x1, ++} DP_MSE_TIMESTAMP_MODE; ++typedef enum DP_MSE_ZERO_ENCODER { ++ DP_MSE_NOT_ZERO_FE_ENCODER = 0x0, ++ DP_MSE_ZERO_FE_ENCODER = 0x1, ++} DP_MSE_ZERO_ENCODER; ++typedef enum DP_MSE_OUTPUT_DPDBG_DATA { ++ DP_MSE_OUTPUT_DPDBG_DATA_DIS = 0x0, ++ DP_MSE_OUTPUT_DPDBG_DATA_EN = 0x1, ++} DP_MSE_OUTPUT_DPDBG_DATA; ++typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE { ++ DP_DPHY_HBR2_PASS_THROUGH = 0x0, ++ DP_DPHY_HBR2_PATTERN_1 = 0x1, ++ DP_DPHY_HBR2_PATTERN_2_NEG = 0x2, ++ DP_DPHY_HBR2_PATTERN_3 = 0x3, ++ DP_DPHY_HBR2_PATTERN_2_POS = 0x6, ++} DP_DPHY_HBR2_PATTERN_CONTROL_MODE; ++typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK { ++ DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x0, ++ DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x1, ++} DPHY_CRC_MST_PHASE_ERROR_ACK; ++typedef enum DPHY_SW_FAST_TRAINING_START { ++ DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x0, ++ DPHY_SW_FAST_TRAINING_STARTED = 0x1, ++} DPHY_SW_FAST_TRAINING_START; ++typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN { ++ DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED= 0x0, ++ DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x1, ++} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN; ++typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK { ++ DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x0, ++ DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x1, ++} DP_DPHY_FAST_TRAINING_COMPLETE_MASK; ++typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK { ++ DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x0, ++ DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x1, ++} DP_DPHY_FAST_TRAINING_COMPLETE_ACK; ++typedef enum DP_MSA_V_TIMING_OVERRIDE_EN { ++ MSA_V_TIMING_OVERRIDE_DISABLED = 0x0, ++ MSA_V_TIMING_OVERRIDE_ENABLED = 0x1, ++} DP_MSA_V_TIMING_OVERRIDE_EN; ++typedef enum DP_SEC_GSP0_PRIORITY { ++ SEC_GSP0_PRIORITY_LOW = 0x0, ++ SEC_GSP0_PRIORITY_HIGH = 0x1, ++} DP_SEC_GSP0_PRIORITY; ++typedef enum DP_SEC_GSP0_SEND { ++ NOT_SENT = 0x0, ++ FORCE_SENT = 0x1, ++} DP_SEC_GSP0_SEND; ++typedef enum DP_AUX_CONTROL_HPD_SEL { ++ DP_AUX_CONTROL_HPD1_SELECTED = 0x0, ++ DP_AUX_CONTROL_HPD2_SELECTED = 0x1, ++ DP_AUX_CONTROL_HPD3_SELECTED = 0x2, ++ DP_AUX_CONTROL_HPD4_SELECTED = 0x3, ++ DP_AUX_CONTROL_HPD5_SELECTED = 0x4, ++ DP_AUX_CONTROL_HPD6_SELECTED = 0x5, ++} DP_AUX_CONTROL_HPD_SEL; ++typedef enum DP_AUX_CONTROL_TEST_MODE { ++ DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x0, ++ DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x1, ++} DP_AUX_CONTROL_TEST_MODE; ++typedef enum DP_AUX_SW_CONTROL_SW_GO { ++ DP_AUX_SW_CONTROL_SW__NOT_GO = 0x0, ++ DP_AUX_SW_CONTROL_SW__GO = 0x1, ++} DP_AUX_SW_CONTROL_SW_GO; ++typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG { ++ DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x0, ++ DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x1, ++} DP_AUX_SW_CONTROL_LS_READ_TRIG; ++typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY { ++ DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x0, ++ DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x1, ++ DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x2, ++ DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x3, ++} DP_AUX_ARB_CONTROL_ARB_PRIORITY; ++typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ { ++ DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x0, ++ DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x1, ++} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ; ++typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG { ++ DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x0, ++ DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x1, ++} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG; ++typedef enum DP_AUX_INT_ACK { ++ DP_AUX_INT__NOT_ACK = 0x0, ++ DP_AUX_INT__ACK = 0x1, ++} DP_AUX_INT_ACK; ++typedef enum DP_AUX_LS_UPDATE_ACK { ++ DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x0, ++ DP_AUX_INT_LS_UPDATE_ACK = 0x1, ++} DP_AUX_LS_UPDATE_ACK; ++typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL { ++ DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK= 0x0, ++ DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF= 0x1, ++} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL; ++typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE { ++ DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x0, ++ DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x1, ++ DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x2, ++ DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x3, ++} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE; ++typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN { ++ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x0, ++ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x1, ++ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x2, ++ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x3, ++ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x4, ++ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x5, ++ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x6, ++ DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x7, ++} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN; ++typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY { ++ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x0, ++ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US= 0x1, ++ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US= 0x2, ++ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US= 0x3, ++ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US= 0x4, ++ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US= 0x5, ++} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY; ++typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW { ++ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x0, ++ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x1, ++ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x2, ++ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD= 0x3, ++ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD= 0x4, ++ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD= 0x5, ++ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD= 0x6, ++ DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD= 0x7, ++} DP_AUX_DPHY_RX_CONTROL_START_WINDOW; ++typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW { ++ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD= 0x0, ++ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD= 0x1, ++ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD= 0x2, ++ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD= 0x3, ++ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD= 0x4, ++ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD= 0x5, ++ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD= 0x6, ++ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD= 0x7, ++} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW; ++typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN { ++ DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES= 0x0, ++ DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES= 0x1, ++ DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES= 0x2, ++ DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED= 0x3, ++} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN; ++typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT { ++ DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x0, ++ DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x1, ++} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; ++typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START { ++ DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START= 0x0, ++ DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START= 0x1, ++} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START; ++typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP { ++ DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP= 0x0, ++ DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP= 0x1, ++} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP; ++typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN { ++ DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS= 0x0, ++ DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS= 0x1, ++ DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS= 0x2, ++ DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS= 0x3, ++} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN; ++typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN { ++ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x0, ++ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x1, ++ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x2, ++ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x3, ++ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x4, ++ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x5, ++ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x6, ++ DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x7, ++} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN; ++typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD { ++ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x0, ++ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x1, ++ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x2, ++ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x3, ++ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x4, ++ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x5, ++ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x6, ++ DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x7, ++} DP_AUX_DPHY_RX_DETECTION_THRESHOLD; ++typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ { ++ DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX= 0x0, ++ DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX= 0x1, ++} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ; ++typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW { ++ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US= 0x0, ++ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US= 0x1, ++ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US= 0x2, ++ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US= 0x3, ++} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW; ++typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT { ++ DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS= 0x0, ++ DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS= 0x1, ++ DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS= 0x2, ++ DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED= 0x3, ++} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT; ++typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN { ++ DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0= 0x0, ++ DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64= 0x1, ++ DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128= 0x2, ++ DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256= 0x3, ++} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN; ++typedef enum DP_AUX_ERR_OCCURRED_ACK { ++ DP_AUX_ERR_OCCURRED__NOT_ACK = 0x0, ++ DP_AUX_ERR_OCCURRED__ACK = 0x1, ++} DP_AUX_ERR_OCCURRED_ACK; ++typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK { ++ DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x0, ++ DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x1, ++} DP_AUX_POTENTIAL_ERR_REACHED_ACK; ++typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK { ++ ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x0, ++ ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x1, ++} DP_AUX_DEFINITE_ERR_REACHED_ACK; ++typedef enum DP_AUX_RESET { ++ DP_AUX_RESET_DEASSERTED = 0x0, ++ DP_AUX_RESET_ASSERTED = 0x1, ++} DP_AUX_RESET; ++typedef enum DP_AUX_RESET_DONE { ++ DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x0, ++ DP_AUX_RESET_SEQUENCE_DONE = 0x1, ++} DP_AUX_RESET_DONE; ++typedef enum FMT_CONTROL_PIXEL_ENCODING { ++ FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x0, ++ FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x1, ++} FMT_CONTROL_PIXEL_ENCODING; ++typedef enum FMT_CONTROL_SUBSAMPLING_MODE { ++ FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x0, ++ FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x1, ++} FMT_CONTROL_SUBSAMPLING_MODE; ++typedef enum FMT_CONTROL_SUBSAMPLING_ORDER { ++ FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x0, ++ FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x1, ++} FMT_CONTROL_SUBSAMPLING_ORDER; ++typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE { ++ FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x0, ++ FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x1, ++} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE; ++typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH { ++ FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x0, ++ FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x1, ++ FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x2, ++} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH; ++typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH { ++ FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x0, ++ FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x1, ++ FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x2, ++} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH; ++typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH { ++ FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP= 0x0, ++ FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP= 0x1, ++ FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP= 0x2, ++} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH; ++typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL { ++ FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x0, ++ FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x1, ++} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL; ++typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL { ++ FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x0, ++ FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x1, ++ FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x2, ++ FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x3, ++} FMT_BIT_DEPTH_CONTROL_25FRC_SEL; ++typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL { ++ FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x0, ++ FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x1, ++ FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x2, ++ FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x3, ++} FMT_BIT_DEPTH_CONTROL_50FRC_SEL; ++typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL { ++ FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x0, ++ FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x1, ++ FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x2, ++ FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x3, ++} FMT_BIT_DEPTH_CONTROL_75FRC_SEL; ++typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT { ++ FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN= 0x0, ++ FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN= 0x1, ++} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT; ++typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 { ++ FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR= 0x0, ++ FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB= 0x1, ++} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0; ++typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT { ++ FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x0, ++ FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x1, ++ FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x2, ++ FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED0 = 0x3, ++ FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x4, ++ FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x5, ++ FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x6, ++ FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x7, ++} FMT_CLAMP_CNTL_COLOR_FORMAT; ++typedef enum FMT_CRC_CNTL_CONT_EN { ++ FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0x0, ++ FMT_CRC_CNTL_CONT_EN_CONT = 0x1, ++} FMT_CRC_CNTL_CONT_EN; ++typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN { ++ FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0x0, ++ FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 0x1, ++} FMT_CRC_CNTL_INCLUDE_OVERSCAN; ++typedef enum FMT_CRC_CNTL_ONLY_BLANKB { ++ FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0x0, ++ FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 0x1, ++} FMT_CRC_CNTL_ONLY_BLANKB; ++typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE { ++ FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0x0, ++ FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 0x1, ++} FMT_CRC_CNTL_PSR_MODE_ENABLE; ++typedef enum FMT_CRC_CNTL_INTERLACE_MODE { ++ FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0x0, ++ FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 0x1, ++ FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x2, ++ FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 0x3, ++} FMT_CRC_CNTL_INTERLACE_MODE; ++typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE { ++ FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0x0, ++ FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 0x1, ++} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE; ++typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT { ++ FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0x0, ++ FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 0x1, ++} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT; ++typedef enum FMT_DEBUG_CNTL_COLOR_SELECT { ++ FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x0, ++ FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x1, ++ FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x2, ++ FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x3, ++} FMT_DEBUG_CNTL_COLOR_SELECT; ++typedef enum FMT_SPATIAL_DITHER_MODE { ++ FMT_SPATIAL_DITHER_MODE_0 = 0x0, ++ FMT_SPATIAL_DITHER_MODE_1 = 0x1, ++ FMT_SPATIAL_DITHER_MODE_2 = 0x2, ++ FMT_SPATIAL_DITHER_MODE_3 = 0x3, ++} FMT_SPATIAL_DITHER_MODE; ++typedef enum FMT_STEREOSYNC_OVR_POL { ++ FMT_STEREOSYNC_OVR_POL_INVERTED = 0x0, ++ FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 0x1, ++} FMT_STEREOSYNC_OVR_POL; ++typedef enum FMT_DYNAMIC_EXP_MODE { ++ FMT_DYNAMIC_EXP_MODE_10to12 = 0x0, ++ FMT_DYNAMIC_EXP_MODE_8to12 = 0x1, ++} FMT_DYNAMIC_EXP_MODE; ++typedef enum LB_DATA_FORMAT_PIXEL_DEPTH { ++ LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0x0, ++ LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 0x1, ++ LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x2, ++ LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 0x3, ++} LB_DATA_FORMAT_PIXEL_DEPTH; ++typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE { ++ LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION= 0x0, ++ LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION= 0x1, ++} LB_DATA_FORMAT_PIXEL_EXPAN_MODE; ++typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE { ++ LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x0, ++ LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x1, ++} LB_DATA_FORMAT_PIXEL_REDUCE_MODE; ++typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH { ++ LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x0, ++ LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x1, ++} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH; ++typedef enum LB_DATA_FORMAT_INTERLEAVE_EN { ++ LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0x0, ++ LB_DATA_FORMAT_INTERLEAVE_ENABLE = 0x1, ++} LB_DATA_FORMAT_INTERLEAVE_EN; ++typedef enum LB_DATA_FORMAT_REQUEST_MODE { ++ LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0x0, ++ LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 0x1, ++} LB_DATA_FORMAT_REQUEST_MODE; ++typedef enum LB_DATA_FORMAT_ALPHA_EN { ++ LB_DATA_FORMAT_ALPHA_DISABLE = 0x0, ++ LB_DATA_FORMAT_ALPHA_ENABLE = 0x1, ++} LB_DATA_FORMAT_ALPHA_EN; ++typedef enum LB_VLINE_START_END_VLINE_INV { ++ LB_VLINE_START_END_VLINE_NORMAL = 0x0, ++ LB_VLINE_START_END_VLINE_INVERSE = 0x1, ++} LB_VLINE_START_END_VLINE_INV; ++typedef enum LB_VLINE2_START_END_VLINE2_INV { ++ LB_VLINE2_START_END_VLINE2_NORMAL = 0x0, ++ LB_VLINE2_START_END_VLINE2_INVERSE = 0x1, ++} LB_VLINE2_START_END_VLINE2_INV; ++typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK { ++ LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x0, ++ LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x1, ++} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK; ++typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK { ++ LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x0, ++ LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x1, ++} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK; ++typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK { ++ LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x0, ++ LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x1, ++} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK; ++typedef enum LB_VLINE_STATUS_VLINE_ACK { ++ LB_VLINE_STATUS_VLINE_NORMAL = 0x0, ++ LB_VLINE_STATUS_VLINE_CLEAR = 0x1, ++} LB_VLINE_STATUS_VLINE_ACK; ++typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE { ++ LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x0, ++ LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x1, ++} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE; ++typedef enum LB_VLINE2_STATUS_VLINE2_ACK { ++ LB_VLINE2_STATUS_VLINE2_NORMAL = 0x0, ++ LB_VLINE2_STATUS_VLINE2_CLEAR = 0x1, ++} LB_VLINE2_STATUS_VLINE2_ACK; ++typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE { ++ LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED= 0x0, ++ LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED= 0x1, ++} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE; ++typedef enum LB_VBLANK_STATUS_VBLANK_ACK { ++ LB_VBLANK_STATUS_VBLANK_NORMAL = 0x0, ++ LB_VBLANK_STATUS_VBLANK_CLEAR = 0x1, ++} LB_VBLANK_STATUS_VBLANK_ACK; ++typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE { ++ LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED= 0x0, ++ LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED= 0x1, ++} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE; ++typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL { ++ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0x0, ++ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK= 0x1, ++ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET= 0x2, ++ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET= 0x3, ++} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL; ++typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 { ++ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0x0, ++ LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 0x1, ++} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2; ++typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION { ++ LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x0, ++ LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x1, ++ LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x2, ++ LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x3, ++} LB_SYNC_RESET_SEL_LB_SYNC_DURATION; ++typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN { ++ LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x0, ++ LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x1, ++} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN; ++typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN { ++ LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE= 0x0, ++ LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE= 0x1, ++} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN; ++typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK { ++ LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0x0, ++ LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 0x1, ++} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK; ++typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK { ++ LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0x0, ++ LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 0x1, ++} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK; ++typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE { ++ LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x2, ++ LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP= 0x3, ++} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE; ++typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET { ++ LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL= 0x0, ++ LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE= 0x1, ++} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET; ++typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK { ++ LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0= 0x0, ++ LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1= 0x1, ++} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK; ++typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE { ++ LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT= 0x0, ++ LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG= 0x1, ++ LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE= 0x2, ++} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE; ++typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE { ++ LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE= 0x0, ++ LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 0x1, ++} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE; ++typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE { ++ ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER= 0x1, ++ ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE= 0x2, ++} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE; ++typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL { ++ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0= 0x0, ++ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1= 0x1, ++} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL; ++typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE { ++ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE= 0x0, ++ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE= 0x1, ++} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE; ++typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO { ++ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO= 0x0, ++ LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO= 0x1, ++} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO; ++typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN { ++ LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0= 0x0, ++ LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1= 0x1, ++} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN; ++typedef enum LBV_PIXEL_DEPTH { ++ PIXEL_DEPTH_30BPP = 0x0, ++ PIXEL_DEPTH_24BPP = 0x1, ++ PIXEL_DEPTH_18BPP = 0x2, ++ PIXEL_DEPTH_38BPP = 0x3, ++} LBV_PIXEL_DEPTH; ++typedef enum LBV_PIXEL_EXPAN_MODE { ++ PIXEL_EXPAN_MODE_ZERO_EXP = 0x0, ++ PIXEL_EXPAN_MODE_DYN_EXP = 0x1, ++} LBV_PIXEL_EXPAN_MODE; ++typedef enum LBV_INTERLEAVE_EN { ++ INTERLEAVE_DIS = 0x0, ++ INTERLEAVE_EN = 0x1, ++} LBV_INTERLEAVE_EN; ++typedef enum LBV_PIXEL_REDUCE_MODE { ++ PIXEL_REDUCE_MODE_TRUNCATION = 0x0, ++ PIXEL_REDUCE_MODE_ROUNDING = 0x1, ++} LBV_PIXEL_REDUCE_MODE; ++typedef enum LBV_DYNAMIC_PIXEL_DEPTH { ++ DYNAMIC_PIXEL_DEPTH_36BPP = 0x0, ++ DYNAMIC_PIXEL_DEPTH_30BPP = 0x1, ++} LBV_DYNAMIC_PIXEL_DEPTH; ++typedef enum LBV_DITHER_EN { ++ DITHER_DIS = 0x0, ++ DITHER_EN = 0x1, ++} LBV_DITHER_EN; ++typedef enum LBV_DOWNSCALE_PREFETCH_EN { ++ DOWNSCALE_PREFETCH_DIS = 0x0, ++ DOWNSCALE_PREFETCH_EN = 0x1, ++} LBV_DOWNSCALE_PREFETCH_EN; ++typedef enum LBV_MEMORY_CONFIG { ++ MEMORY_CONFIG_0 = 0x0, ++ MEMORY_CONFIG_1 = 0x1, ++ MEMORY_CONFIG_2 = 0x2, ++ MEMORY_CONFIG_3 = 0x3, ++} LBV_MEMORY_CONFIG; ++typedef enum LBV_SYNC_RESET_SEL2 { ++ SYNC_RESET_SEL2_VBLANK = 0x0, ++ SYNC_RESET_SEL2_VSYNC = 0x1, ++} LBV_SYNC_RESET_SEL2; ++typedef enum LBV_SYNC_DURATION { ++ SYNC_DURATION_16 = 0x0, ++ SYNC_DURATION_32 = 0x1, ++ SYNC_DURATION_64 = 0x2, ++ SYNC_DURATION_128 = 0x3, ++} LBV_SYNC_DURATION; ++typedef enum SCL_C_RAM_TAP_PAIR_IDX { ++ SCL_C_RAM_TAP_PAIR_ID0 = 0x0, ++ SCL_C_RAM_TAP_PAIR_ID1 = 0x1, ++ SCL_C_RAM_TAP_PAIR_ID2 = 0x2, ++ SCL_C_RAM_TAP_PAIR_ID3 = 0x3, ++ SCL_C_RAM_TAP_PAIR_ID4 = 0x4, ++} SCL_C_RAM_TAP_PAIR_IDX; ++typedef enum SCL_C_RAM_PHASE { ++ SCL_C_RAM_PHASE_0 = 0x0, ++ SCL_C_RAM_PHASE_1 = 0x1, ++ SCL_C_RAM_PHASE_2 = 0x2, ++ SCL_C_RAM_PHASE_3 = 0x3, ++ SCL_C_RAM_PHASE_4 = 0x4, ++ SCL_C_RAM_PHASE_5 = 0x5, ++ SCL_C_RAM_PHASE_6 = 0x6, ++ SCL_C_RAM_PHASE_7 = 0x7, ++ SCL_C_RAM_PHASE_8 = 0x8, ++} SCL_C_RAM_PHASE; ++typedef enum SCL_C_RAM_FILTER_TYPE { ++ SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT = 0x0, ++ SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT = 0x1, ++ SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT = 0x2, ++ SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT = 0x3, ++ SCL_C_RAM_FILTER_TYPE_VERT_ALPHA_LUT = 0x4, ++ SCL_C_RAM_FILTER_TYPE_HORI_ALPHA_LUT = 0x5, ++} SCL_C_RAM_FILTER_TYPE; ++typedef enum SCL_MODE_SEL { ++ SCL_MODE_SCL_BYPASS = 0x0, ++ SCL_MODE_RGB_SCALING = 0x1, ++ SCL_MODE_YCBCR_SCALING = 0x2, ++} SCL_MODE_SEL; ++typedef enum SCL_PSCL_EN { ++ SCL_PSCL_DISABLE = 0x0, ++ SCL_PSCL_ENANBLE = 0x1, ++} SCL_PSCL_EN; ++typedef enum SCL_V_NUM_OF_TAPS { ++ SCL_V_NUM_OF_TAPS_1 = 0x0, ++ SCL_V_NUM_OF_TAPS_2 = 0x1, ++ SCL_V_NUM_OF_TAPS_3 = 0x2, ++ SCL_V_NUM_OF_TAPS_4 = 0x3, ++ SCL_V_NUM_OF_TAPS_5 = 0x4, ++ SCL_V_NUM_OF_TAPS_6 = 0x5, ++} SCL_V_NUM_OF_TAPS; ++typedef enum SCL_H_NUM_OF_TAPS { ++ SCL_H_NUM_OF_TAPS_1 = 0x0, ++ SCL_H_NUM_OF_TAPS_2 = 0x1, ++ SCL_H_NUM_OF_TAPS_4 = 0x3, ++ SCL_H_NUM_OF_TAPS_6 = 0x5, ++ SCL_H_NUM_OF_TAPS_8 = 0x7, ++ SCL_H_NUM_OF_TAPS_10 = 0x9, ++} SCL_H_NUM_OF_TAPS; ++typedef enum SCL_BOUNDARY_MODE { ++ SCL_BOUNDARY_MODE_BLACK = 0x0, ++ SCL_BOUNDARY_MODE_EDGE = 0x1, ++} SCL_BOUNDARY_MODE; ++typedef enum SCL_EARLY_EOL_MOD { ++ SCL_EARLY_EOL_MODE_CRTC = 0x0, ++ SCL_EARLY_EOL_MODE_INTERNAL = 0x1, ++} SCL_EARLY_EOL_MOD; ++typedef enum SCL_BYPASS_MODE { ++ SCL_BYPASS_MODE_MC_MR = 0x0, ++ SCL_BYPASS_MODE_AC_NR = 0x1, ++ SCL_BYPASS_MODE_AC_AR = 0x2, ++ SCL_BYPASS_MODE_RESERVED = 0x3, ++} SCL_BYPASS_MODE; ++typedef enum SCL_V_MANUAL_REPLICATE_FACTOR { ++ SCL_V_MANUAL_REPLICATE_FACTOR_1 = 0x0, ++ SCL_V_MANUAL_REPLICATE_FACTOR_2 = 0x1, ++ SCL_V_MANUAL_REPLICATE_FACTOR_3 = 0x2, ++ SCL_V_MANUAL_REPLICATE_FACTOR_4 = 0x3, ++ SCL_V_MANUAL_REPLICATE_FACTOR_5 = 0x4, ++ SCL_V_MANUAL_REPLICATE_FACTOR_6 = 0x5, ++ SCL_V_MANUAL_REPLICATE_FACTOR_7 = 0x6, ++ SCL_V_MANUAL_REPLICATE_FACTOR_8 = 0x7, ++ SCL_V_MANUAL_REPLICATE_FACTOR_9 = 0x8, ++ SCL_V_MANUAL_REPLICATE_FACTOR_10 = 0x9, ++ SCL_V_MANUAL_REPLICATE_FACTOR_11 = 0xa, ++ SCL_V_MANUAL_REPLICATE_FACTOR_12 = 0xb, ++ SCL_V_MANUAL_REPLICATE_FACTOR_13 = 0xc, ++ SCL_V_MANUAL_REPLICATE_FACTOR_14 = 0xd, ++ SCL_V_MANUAL_REPLICATE_FACTOR_15 = 0xe, ++ SCL_V_MANUAL_REPLICATE_FACTOR_16 = 0xf, ++} SCL_V_MANUAL_REPLICATE_FACTOR; ++typedef enum SCL_H_MANUAL_REPLICATE_FACTOR { ++ SCL_H_MANUAL_REPLICATE_FACTOR_1 = 0x0, ++ SCL_H_MANUAL_REPLICATE_FACTOR_2 = 0x1, ++ SCL_H_MANUAL_REPLICATE_FACTOR_3 = 0x2, ++ SCL_H_MANUAL_REPLICATE_FACTOR_4 = 0x3, ++ SCL_H_MANUAL_REPLICATE_FACTOR_5 = 0x4, ++ SCL_H_MANUAL_REPLICATE_FACTOR_6 = 0x5, ++ SCL_H_MANUAL_REPLICATE_FACTOR_7 = 0x6, ++ SCL_H_MANUAL_REPLICATE_FACTOR_8 = 0x7, ++ SCL_H_MANUAL_REPLICATE_FACTOR_9 = 0x8, ++ SCL_H_MANUAL_REPLICATE_FACTOR_10 = 0x9, ++ SCL_H_MANUAL_REPLICATE_FACTOR_11 = 0xa, ++ SCL_H_MANUAL_REPLICATE_FACTOR_12 = 0xb, ++ SCL_H_MANUAL_REPLICATE_FACTOR_13 = 0xc, ++ SCL_H_MANUAL_REPLICATE_FACTOR_14 = 0xd, ++ SCL_H_MANUAL_REPLICATE_FACTOR_15 = 0xe, ++ SCL_H_MANUAL_REPLICATE_FACTOR_16 = 0xf, ++} SCL_H_MANUAL_REPLICATE_FACTOR; ++typedef enum SCL_V_CALC_AUTO_RATIO_EN { ++ SCL_V_CALC_AUTO_RATIO_DISABLE = 0x0, ++ SCL_V_CALC_AUTO_RATIO_ENABLE = 0x1, ++} SCL_V_CALC_AUTO_RATIO_EN; ++typedef enum SCL_H_CALC_AUTO_RATIO_EN { ++ SCL_H_CALC_AUTO_RATIO_DISABLE = 0x0, ++ SCL_H_CALC_AUTO_RATIO_ENABLE = 0x1, ++} SCL_H_CALC_AUTO_RATIO_EN; ++typedef enum SCL_H_FILTER_PICK_NEAREST { ++ SCL_H_FILTER_PICK_NEAREST_DISABLE = 0x0, ++ SCL_H_FILTER_PICK_NEAREST_ENABLE = 0x1, ++} SCL_H_FILTER_PICK_NEAREST; ++typedef enum SCL_H_2TAP_HARDCODE_COEF_EN { ++ SCL_H_2TAP_HARDCODE_COEF_DISABLE = 0x0, ++ SCL_H_2TAP_HARDCODE_COEF_ENABLE = 0x1, ++} SCL_H_2TAP_HARDCODE_COEF_EN; ++typedef enum SCL_V_FILTER_PICK_NEAREST { ++ SCL_V_FILTER_PICK_NEAREST_DISABLE = 0x0, ++ SCL_V_FILTER_PICK_NEAREST_ENABLE = 0x1, ++} SCL_V_FILTER_PICK_NEAREST; ++typedef enum SCL_V_2TAP_HARDCODE_COEF_EN { ++ SCL_V_2TAP_HARDCODE_COEF_DISABLE = 0x0, ++ SCL_V_2TAP_HARDCODE_COEF_ENABLE = 0x1, ++} SCL_V_2TAP_HARDCODE_COEF_EN; ++typedef enum SCL_UPDATE_TAKEN { ++ SCL_UPDATE_TAKEN_NO = 0x0, ++ SCL_UPDATE_TAKEN_YES = 0x1, ++} SCL_UPDATE_TAKEN; ++typedef enum SCL_UPDATE_LOCK { ++ SCL_UPDATE_UNLOCKED = 0x0, ++ SCL_UPDATE_LOCKED = 0x1, ++} SCL_UPDATE_LOCK; ++typedef enum SCL_COEF_UPDATE_COMPLETE { ++ SCL_COEF_UPDATE_NOT_COMPLETED = 0x0, ++ SCL_COEF_UPDATE_COMPLETED = 0x1, ++} SCL_COEF_UPDATE_COMPLETE; ++typedef enum SCL_HF_SHARP_SCALE_FACTOR { ++ SCL_HF_SHARP_SCALE_FACTOR_0 = 0x0, ++ SCL_HF_SHARP_SCALE_FACTOR_1 = 0x1, ++ SCL_HF_SHARP_SCALE_FACTOR_2 = 0x2, ++ SCL_HF_SHARP_SCALE_FACTOR_3 = 0x3, ++ SCL_HF_SHARP_SCALE_FACTOR_4 = 0x4, ++ SCL_HF_SHARP_SCALE_FACTOR_5 = 0x5, ++ SCL_HF_SHARP_SCALE_FACTOR_6 = 0x6, ++ SCL_HF_SHARP_SCALE_FACTOR_7 = 0x7, ++} SCL_HF_SHARP_SCALE_FACTOR; ++typedef enum SCL_HF_SHARP_EN { ++ SCL_HF_SHARP_DISABLE = 0x0, ++ SCL_HF_SHARP_ENABLE = 0x1, ++} SCL_HF_SHARP_EN; ++typedef enum SCL_VF_SHARP_SCALE_FACTOR { ++ SCL_VF_SHARP_SCALE_FACTOR_0 = 0x0, ++ SCL_VF_SHARP_SCALE_FACTOR_1 = 0x1, ++ SCL_VF_SHARP_SCALE_FACTOR_2 = 0x2, ++ SCL_VF_SHARP_SCALE_FACTOR_3 = 0x3, ++ SCL_VF_SHARP_SCALE_FACTOR_4 = 0x4, ++ SCL_VF_SHARP_SCALE_FACTOR_5 = 0x5, ++ SCL_VF_SHARP_SCALE_FACTOR_6 = 0x6, ++ SCL_VF_SHARP_SCALE_FACTOR_7 = 0x7, ++} SCL_VF_SHARP_SCALE_FACTOR; ++typedef enum SCL_VF_SHARP_EN { ++ SCL_VF_SHARP_DISABLE = 0x0, ++ SCL_VF_SHARP_ENABLE = 0x1, ++} SCL_VF_SHARP_EN; ++typedef enum SCL_ALU_DISABLE { ++ SCL_ALU_ENABLED = 0x0, ++ SCL_ALU_DISABLED = 0x1, ++} SCL_ALU_DISABLE; ++typedef enum SCL_HOST_CONFLICT_MASK { ++ SCL_HOST_CONFLICT_DISABLE_INTERRUPT = 0x0, ++ SCL_HOST_CONFLICT_ENABLE_INTERRUPT = 0x1, ++} SCL_HOST_CONFLICT_MASK; ++typedef enum SCL_SCL_MODE_CHANGE_MASK { ++ SCL_MODE_CHANGE_DISABLE_INTERRUPT = 0x0, ++ SCL_MODE_CHANGE_ENABLE_INTERRUPT = 0x1, ++} SCL_SCL_MODE_CHANGE_MASK; ++typedef enum SCLV_INTERLACE_SOURCE { ++ INTERLACE_SOURCE_PROGRESSIVE = 0x0, ++ INTERLACE_SOURCE_INTERLEAVE = 0x1, ++ INTERLACE_SOURCE_STACK = 0x2, ++} SCLV_INTERLACE_SOURCE; ++typedef enum SCLV_UPDATE_LOCK { ++ UPDATE_UNLOCKED = 0x0, ++ UPDATE_LOCKED = 0x1, ++} SCLV_UPDATE_LOCK; ++typedef enum SCLV_COEF_UPDATE_COMPLETE { ++ COEF_UPDATE_NOT_COMPLETE = 0x0, ++ COEF_UPDATE_COMPLETE = 0x1, ++} SCLV_COEF_UPDATE_COMPLETE; ++typedef enum COL_MAN_UPDATE_LOCK { ++ COL_MAN_UPDATE_UNLOCKED = 0x0, ++ COL_MAN_UPDATE_LOCKED = 0x1, ++} COL_MAN_UPDATE_LOCK; ++typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE { ++ COL_MAN_MULTIPLE_UPDATE = 0x0, ++ COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x1, ++} COL_MAN_DISABLE_MULTIPLE_UPDATE; ++typedef enum COL_MAN_INPUTCSC_MODE { ++ INPUTCSC_MODE_BYPASS = 0x0, ++ INPUTCSC_MODE_A = 0x1, ++ INPUTCSC_MODE_B = 0x2, ++ INPUTCSC_MODE_UNITY = 0x3, ++} COL_MAN_INPUTCSC_MODE; ++typedef enum COL_MAN_INPUTCSC_TYPE { ++ INPUTCSC_TYPE_12_0 = 0x0, ++ INPUTCSC_TYPE_10_2 = 0x1, ++ INPUTCSC_TYPE_8_4 = 0x2, ++} COL_MAN_INPUTCSC_TYPE; ++typedef enum COL_MAN_INPUTCSC_CONVERT { ++ INPUTCSC_ROUND = 0x0, ++ INPUTCSC_TRUNCATE = 0x1, ++} COL_MAN_INPUTCSC_CONVERT; ++typedef enum COL_MAN_PRESCALE_MODE { ++ PRESCALE_MODE_BYPASS = 0x0, ++ PRESCALE_MODE_PROGRAM = 0x1, ++ PRESCALE_MODE_UNITY = 0x2, ++} COL_MAN_PRESCALE_MODE; ++typedef enum COL_MAN_INPUT_GAMMA_MODE { ++ INGAMMA_MODE_BYPASS = 0x0, ++ INGAMMA_MODE_FIX = 0x1, ++ INGAMMA_MODE_FLOAT = 0x2, ++} COL_MAN_INPUT_GAMMA_MODE; ++typedef enum COL_MAN_OUTPUT_CSC_MODE { ++ COL_MAN_OUTPUT_CSC_BYPASS = 0x0, ++ COL_MAN_OUTPUT_CSC_RGB = 0x1, ++ COL_MAN_OUTPUT_CSC_YCrCb601 = 0x2, ++ COL_MAN_OUTPUT_CSC_YCrCb709 = 0x3, ++ COL_MAN_OUTPUT_CSC_A = 0x4, ++ COL_MAN_OUTPUT_CSC_B = 0x5, ++ COL_MAN_OUTPUT_CSC_UNITY = 0x6, ++} COL_MAN_OUTPUT_CSC_MODE; ++typedef enum COL_MAN_DENORM_CLAMP_CONTROL { ++ DENORM_CLAMP_MODE_UNITY = 0x0, ++ DENORM_CLAMP_MODE_8 = 0x1, ++ DENORM_CLAMP_MODE_10 = 0x2, ++ DENORM_CLAMP_MODE_12 = 0x3, ++} COL_MAN_DENORM_CLAMP_CONTROL; ++typedef enum COL_MAN_GAMMA_CORR_CONTROL { ++ GAMMA_CORR_MODE_BYPASS = 0x0, ++ GAMMA_CORR_MODE_A = 0x1, ++ GAMMA_CORR_MODE_B = 0x2, ++} COL_MAN_GAMMA_CORR_CONTROL; ++typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE { ++ CM_GLOBAL_PASSTHROUGH_DISBALE = 0x0, ++ CM_GLOBAL_PASSTHROUGH_ENABLE = 0x1, ++} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE; ++typedef enum UNP_GRPH_EN { ++ UNP_GRPH_DISABLED = 0x0, ++ UNP_GRPH_ENABLED = 0x1, ++} UNP_GRPH_EN; ++typedef enum UNP_GRPH_DEPTH { ++ UNP_GRPH_8BPP = 0x0, ++ UNP_GRPH_16BPP = 0x1, ++ UNP_GRPH_32BPP = 0x2, ++} UNP_GRPH_DEPTH; ++typedef enum UNP_GRPH_NUM_BANKS { ++ UNP_GRPH_ADDR_SURF_2_BANK = 0x0, ++ UNP_GRPH_ADDR_SURF_4_BANK = 0x1, ++ UNP_GRPH_ADDR_SURF_8_BANK = 0x2, ++ UNP_GRPH_ADDR_SURF_16_BANK = 0x3, ++} UNP_GRPH_NUM_BANKS; ++typedef enum UNP_GRPH_BANK_WIDTH { ++ UNP_GRPH_ADDR_SURF_BANK_WIDTH_1 = 0x0, ++ UNP_GRPH_ADDR_SURF_BANK_WIDTH_2 = 0x1, ++ UNP_GRPH_ADDR_SURF_BANK_WIDTH_4 = 0x2, ++ UNP_GRPH_ADDR_SURF_BANK_WIDTH_8 = 0x3, ++} UNP_GRPH_BANK_WIDTH; ++typedef enum UNP_GRPH_BANK_HEIGHT { ++ UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1 = 0x0, ++ UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2 = 0x1, ++ UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4 = 0x2, ++ UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8 = 0x3, ++} UNP_GRPH_BANK_HEIGHT; ++typedef enum UNP_GRPH_TILE_SPLIT { ++ UNP_ADDR_SURF_TILE_SPLIT_64B = 0x0, ++ UNP_ADDR_SURF_TILE_SPLIT_128B = 0x1, ++ UNP_ADDR_SURF_TILE_SPLIT_256B = 0x2, ++ UNP_ADDR_SURF_TILE_SPLIT_512B = 0x3, ++ UNP_ADDR_SURF_TILE_SPLIT_1KB = 0x4, ++ UNP_ADDR_SURF_TILE_SPLIT_2KB = 0x5, ++ UNP_ADDR_SURF_TILE_SPLIT_4KB = 0x6, ++} UNP_GRPH_TILE_SPLIT; ++typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE { ++ UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0 = 0x0, ++ UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1 = 0x1, ++} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE; ++typedef enum UNP_GRPH_PRIVILEGED_ACCESS_ENABLE { ++ UNP_GRPH_PRIVILEGED_ACCESS_DIS = 0x0, ++ UNP_GRPH_PRIVILEGED_ACCESS_EN = 0x1, ++} UNP_GRPH_PRIVILEGED_ACCESS_ENABLE; ++typedef enum UNP_GRPH_MACRO_TILE_ASPECT { ++ UNP_ADDR_SURF_MACRO_ASPECT_1 = 0x0, ++ UNP_ADDR_SURF_MACRO_ASPECT_2 = 0x1, ++ UNP_ADDR_SURF_MACRO_ASPECT_4 = 0x2, ++ UNP_ADDR_SURF_MACRO_ASPECT_8 = 0x3, ++} UNP_GRPH_MACRO_TILE_ASPECT; ++typedef enum UNP_GRPH_COLOR_EXPANSION_MODE { ++ UNP_GRPH_DYNAMIC_EXPANSION = 0x0, ++ UNP_GRPH_ZERO_EXPANSION = 0x1, ++} UNP_GRPH_COLOR_EXPANSION_MODE; ++typedef enum UNP_VIDEO_FORMAT { ++ UNP_VIDEO_FORMAT0 = 0x0, ++ UNP_VIDEO_FORMAT1 = 0x1, ++ UNP_VIDEO_FORMAT_YUV420_YCbCr = 0x2, ++ UNP_VIDEO_FORMAT_YUV420_YCrCb = 0x3, ++ UNP_VIDEO_FORMAT_YUV422_YCb = 0x4, ++ UNP_VIDEO_FORMAT_YUV422_YCr = 0x5, ++ UNP_VIDEO_FORMAT_YUV422_CbY = 0x6, ++ UNP_VIDEO_FORMAT_YUV422_CrY = 0x7, ++} UNP_VIDEO_FORMAT; ++typedef enum UNP_GRPH_ENDIAN_SWAP { ++ UNP_GRPH_ENDIAN_SWAP_NONE = 0x0, ++ UNP_GRPH_ENDIAN_SWAP_8IN16 = 0x1, ++ UNP_GRPH_ENDIAN_SWAP_8IN32 = 0x2, ++ UNP_GRPH_ENDIAN_SWAP_8IN43 = 0x3, ++} UNP_GRPH_ENDIAN_SWAP; ++typedef enum UNP_GRPH_RED_CROSSBAR { ++ UNP_GRPH_RED_CROSSBAR_R_Cr = 0x0, ++ UNP_GRPH_RED_CROSSBAR_G_Y = 0x1, ++ UNP_GRPH_RED_CROSSBAR_B_Cb = 0x2, ++ UNP_GRPH_RED_CROSSBAR_A = 0x3, ++} UNP_GRPH_RED_CROSSBAR; ++typedef enum UNP_GRPH_GREEN_CROSSBAR { ++ UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y = 0x0, ++ UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C = 0x1, ++ UNP_UNP_GRPH_GREEN_CROSSBAR_A = 0x2, ++ UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr = 0x3, ++} UNP_GRPH_GREEN_CROSSBAR; ++typedef enum UNP_GRPH_BLUE_CROSSBAR { ++ UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C = 0x0, ++ UNP_GRPH_BLUE_CROSSBAR_A = 0x1, ++ UNP_GRPH_BLUE_CROSSBAR_R_Cr = 0x2, ++ UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y = 0x3, ++} UNP_GRPH_BLUE_CROSSBAR; ++typedef enum UNP_GRPH_MODE_UPDATE_LOCKG { ++ UNP_GRPH_UPDATE_LOCK_0 = 0x0, ++ UNP_GRPH_UPDATE_LOCK_1 = 0x1, ++} UNP_GRPH_MODE_UPDATE_LOCKG; ++typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK { ++ UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0 = 0x0, ++ UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1 = 0x1, ++} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK; ++typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE { ++ UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0 = 0x0, ++ UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1 = 0x1, ++} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE; ++typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE { ++ UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0 = 0x0, ++ UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1 = 0x1, ++} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE; ++typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN { ++ UNP_GRPH_STEREOSYNC_FLIP_DISABLE = 0x0, ++ UNP_GRPH_STEREOSYNC_FLIP_ENABLE = 0x1, ++} UNP_GRPH_STEREOSYNC_FLIP_EN; ++typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE { ++ UNP_GRPH_STEREOSYNC_FLIP_MODE_0 = 0x0, ++ UNP_GRPH_STEREOSYNC_FLIP_MODE_1 = 0x1, ++ UNP_GRPH_STEREOSYNC_FLIP_MODE_2 = 0x2, ++ UNP_GRPH_STEREOSYNC_FLIP_MODE_3 = 0x3, ++} UNP_GRPH_STEREOSYNC_FLIP_MODE; ++typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN { ++ UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE = 0x0, ++ UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE = 0x1, ++} UNP_GRPH_STACK_INTERLACE_FLIP_EN; ++typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE { ++ UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0 = 0x0, ++ UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1 = 0x1, ++ UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2 = 0x2, ++ UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3 = 0x3, ++} UNP_GRPH_STACK_INTERLACE_FLIP_MODE; ++typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE { ++ UNP_GRPH_STEREOSYNC_SELECT_EN = 0x0, ++ UNP_GRPH_STEREOSYNC_SELECT_DIS = 0x1, ++} UNP_GRPH_STEREOSYNC_SELECT_DISABLE; ++typedef enum UNP_CRC_SOURCE_SEL { ++ UNP_CRC_SOURCE_SEL_NP_TO_LBV = 0x0, ++ UNP_CRC_SOURCE_SEL_LOWER32 = 0x1, ++ UNP_CRC_SOURCE_SEL_RESERVED = 0x2, ++ UNP_CRC_SOURCE_SEL_LOWER16 = 0x3, ++ UNP_CRC_SOURCE_SEL_UNP_TO_LBV = 0x4, ++} UNP_CRC_SOURCE_SEL; ++typedef enum UNP_CRC_LINE_SEL { ++ UNP_CRC_LINE_SEL_RESERVED = 0x0, ++ UNP_CRC_LINE_SEL_EVEN_ONLY = 0x1, ++ UNP_CRC_LINE_SEL_ODD_ONLY = 0x2, ++ UNP_CRC_LINE_SEL_ODD_EVEN = 0x3, ++} UNP_CRC_LINE_SEL; ++typedef enum UNP_ROTATION_ANGLE { ++ UNP_ROTATION_ANGLE_0 = 0x0, ++ UNP_ROTATION_ANGLE_90 = 0x1, ++ UNP_ROTATION_ANGLE_180 = 0x2, ++ UNP_ROTATION_ANGLE_270 = 0x3, ++ UNP_ROTATION_ANGLE_0m = 0x4, ++ UNP_ROTATION_ANGLE_90m = 0x5, ++ UNP_ROTATION_ANGLE_180m = 0x6, ++ UNP_ROTATION_ANGLE_270m = 0x7, ++} UNP_ROTATION_ANGLE; ++typedef enum UNP_PIXEL_DROP { ++ UNP_PIXEL_NO_DROP = 0x0, ++ UNP_PIXEL_DROPPING = 0x1, ++} UNP_PIXEL_DROP; ++typedef enum UNP_BUFFER_MODE { ++ UNP_BUFFER_MODE_LUMA = 0x0, ++ UNP_BUFFER_MODE_LUMA_CHROMA = 0x1, ++} UNP_BUFFER_MODE; ++typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET { ++ AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET= 0x0, ++ AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET= 0x1, ++} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET; ++typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY { ++ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL= 0x0, ++ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6= 0x1, ++ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5= 0x2, ++ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4= 0x3, ++ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3= 0x4, ++ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2= 0x5, ++ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1= 0x6, ++ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0= 0x7, ++} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY; ++typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY { ++ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL= 0x0, ++ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6= 0x1, ++ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5= 0x2, ++ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4= 0x3, ++ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3= 0x4, ++ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2= 0x5, ++ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1= 0x6, ++ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0= 0x7, ++} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY; ++typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL { ++ GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x0, ++ GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x1, ++} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL; ++typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED { ++ GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x0, ++ GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x1, ++} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED; ++typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS { ++ GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x0, ++ GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x1, ++} GENERIC_AZ_CONTROLLER_REGISTER_STATUS; ++typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED { ++ GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED= 0x0, ++ GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED= 0x1, ++} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED; ++typedef enum AZ_GLOBAL_CAPABILITIES { ++ AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED= 0x0, ++ AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED= 0x1, ++} AZ_GLOBAL_CAPABILITIES; ++typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE { ++ ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x0, ++ ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x1, ++} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE; ++typedef enum GLOBAL_CONTROL_FLUSH_CONTROL { ++ FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x0, ++ FLUSH_CONTROL_FLUSH_STARTED = 0x1, ++} GLOBAL_CONTROL_FLUSH_CONTROL; ++typedef enum GLOBAL_CONTROL_CONTROLLER_RESET { ++ CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x0, ++ CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x1, ++} GLOBAL_CONTROL_CONTROLLER_RESET; ++typedef enum AZ_STATE_CHANGE_STATUS { ++ AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x0, ++ AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x1, ++} AZ_STATE_CHANGE_STATUS; ++typedef enum GLOBAL_STATUS_FLUSH_STATUS { ++ GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x0, ++ GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x1, ++} GLOBAL_STATUS_FLUSH_STATUS; ++typedef enum STREAM_0_SYNCHRONIZATION { ++ STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, ++ STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x1, ++} STREAM_0_SYNCHRONIZATION; ++typedef enum STREAM_1_SYNCHRONIZATION { ++ STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, ++ STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x1, ++} STREAM_1_SYNCHRONIZATION; ++typedef enum STREAM_2_SYNCHRONIZATION { ++ STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x0, ++ STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x1, ++} STREAM_2_SYNCHRONIZATION; ++typedef enum STREAM_3_SYNCHRONIZATION { ++ STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, ++ STREAM_3_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, ++} STREAM_3_SYNCHRONIZATION; ++typedef enum STREAM_4_SYNCHRONIZATION { ++ STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, ++ STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, ++} STREAM_4_SYNCHRONIZATION; ++typedef enum STREAM_5_SYNCHRONIZATION { ++ STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, ++ STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, ++} STREAM_5_SYNCHRONIZATION; ++typedef enum STREAM_6_SYNCHRONIZATION { ++ STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, ++ STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, ++} STREAM_6_SYNCHRONIZATION; ++typedef enum STREAM_7_SYNCHRONIZATION { ++ STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, ++ STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, ++} STREAM_7_SYNCHRONIZATION; ++typedef enum STREAM_8_SYNCHRONIZATION { ++ STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, ++ STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, ++} STREAM_8_SYNCHRONIZATION; ++typedef enum STREAM_9_SYNCHRONIZATION { ++ STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, ++ STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, ++} STREAM_9_SYNCHRONIZATION; ++typedef enum STREAM_10_SYNCHRONIZATION { ++ STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, ++ STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, ++} STREAM_10_SYNCHRONIZATION; ++typedef enum STREAM_11_SYNCHRONIZATION { ++ STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, ++ STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, ++} STREAM_11_SYNCHRONIZATION; ++typedef enum STREAM_12_SYNCHRONIZATION { ++ STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, ++ STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, ++} STREAM_12_SYNCHRONIZATION; ++typedef enum STREAM_13_SYNCHRONIZATION { ++ STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, ++ STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, ++} STREAM_13_SYNCHRONIZATION; ++typedef enum STREAM_14_SYNCHRONIZATION { ++ STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, ++ STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, ++} STREAM_14_SYNCHRONIZATION; ++typedef enum STREAM_15_SYNCHRONIZATION { ++ STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0, ++ STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1, ++} STREAM_15_SYNCHRONIZATION; ++typedef enum CORB_READ_POINTER_RESET { ++ CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x0, ++ CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x1, ++} CORB_READ_POINTER_RESET; ++typedef enum AZ_CORB_SIZE { ++ AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x0, ++ AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x1, ++ AZ_CORB_SIZE_256ENTRIES = 0x2, ++ AZ_CORB_SIZE_RESERVED = 0x3, ++} AZ_CORB_SIZE; ++typedef enum AZ_RIRB_WRITE_POINTER_RESET { ++ AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x0, ++ AZ_RIRB_WRITE_POINTER_DO_RESET = 0x1, ++} AZ_RIRB_WRITE_POINTER_RESET; ++typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL { ++ RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0, ++ RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1, ++} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL; ++typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL { ++ RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0, ++ RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1, ++} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL; ++typedef enum AZ_RIRB_SIZE { ++ AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x0, ++ AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x1, ++ AZ_RIRB_SIZE_256ENTRIES = 0x2, ++ AZ_RIRB_SIZE_UNDEFINED = 0x3, ++} AZ_RIRB_SIZE; ++typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID { ++ IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID= 0x0, ++ IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID= 0x1, ++} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID; ++typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY { ++ IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY= 0x0, ++ IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY= 0x1, ++} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY; ++typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE { ++ DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE= 0x0, ++ DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE= 0x1, ++} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR { ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET= 0x1, ++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR { ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET= 0x1, ++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS { ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET= 0x1, ++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY { ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY= 0x1, ++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE { ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED= 0x1, ++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE { ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED= 0x1, ++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE { ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED= 0x1, ++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN { ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN= 0x1, ++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET { ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET= 0x1, ++} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE { ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1, ++} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE { ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4, ++} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR { ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7, ++} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE { ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16= 0x1, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20= 0x2, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24= 0x3, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5, ++} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE; ++typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS { ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1= 0x0, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2= 0x1, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3= 0x2, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4= 0x3, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5= 0x4, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6= 0x5, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7= 0x6, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8= 0x7, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED= 0x8, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED= 0x9, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED= 0xa, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED= 0xb, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED= 0xc, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED= 0xd, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED= 0xe, ++ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED= 0xf, ++} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET= 0x1, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET= 0x1, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET= 0x1, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET= 0x1, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET= 0x1, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON= 0x1, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE= 0x1, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; ++typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE { ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE= 0x0, ++ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE= 0x1, ++} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE; ++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE { ++ AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF= 0x0, ++ AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN= 0x1, ++} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE; ++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { ++ AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0, ++ AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1, ++} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; ++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT { ++ AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED= 0x0, ++ AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x1, ++} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT; ++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE { ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED= 0x1, ++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE; ++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE { ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED= 0x1, ++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE; ++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE { ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED= 0x1, ++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE; ++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE { ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED= 0x1, ++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE; ++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1, ++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; ++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1, ++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; ++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1, ++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; ++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1, ++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; ++typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0, ++ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1, ++} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; ++typedef enum AZ_LATENCY_COUNTER_CONTROL { ++ AZ_LATENCY_COUNTER_NO_RESET = 0x0, ++ AZ_LATENCY_COUNTER_RESET_DONE = 0x1, ++} AZ_LATENCY_COUNTER_CONTROL; ++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, ++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; ++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; ++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; ++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1, ++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; ++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, ++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; ++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; ++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1, ++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; ++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, ++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; ++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE= 0x1, ++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; ++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1, ++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; ++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, ++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; ++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, ++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; ++typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0, ++ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1, ++} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, ++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; ++typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; ++typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE { ++ AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0, ++ AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1, ++} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; ++typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { ++ AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY= 0x0, ++ AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY= 0x1, ++} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; ++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, ++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; ++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; ++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; ++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG= 0x0, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL= 0x1, ++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; ++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, ++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; ++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; ++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES= 0x0, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES= 0x1, ++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; ++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING= 0x0, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, ++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; ++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE { ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE= 0x1, ++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; ++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER= 0x1, ++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; ++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, ++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; ++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, ++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; ++typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES { ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0, ++ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1, ++} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE { ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; ++typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE { ++ AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY= 0x0, ++ AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY= 0x1, ++} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; ++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE { ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1, ++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; ++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE { ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1, ++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; ++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE { ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4, ++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; ++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR { ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7, ++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; ++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE { ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5, ++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; ++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS { ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8, ++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; ++typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN { ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0, ++ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1, ++} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; ++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE { ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF= 0x0, ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN= 0x1, ++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE; ++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE { ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0, ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1, ++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; ++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE { ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED= 0x1, ++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE; ++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE { ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1, ++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; ++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE { ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED= 0x1, ++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE; ++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE { ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1, ++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; ++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE { ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED= 0x1, ++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE; ++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE { ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1, ++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; ++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE { ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED= 0x1, ++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE; ++typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE { ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0, ++ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1, ++} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; ++typedef enum BLND_CONTROL_BLND_MODE { ++ BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0, ++ BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1, ++ BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2, ++ BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3, ++} BLND_CONTROL_BLND_MODE; ++typedef enum BLND_CONTROL_BLND_STEREO_TYPE { ++ BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0, ++ BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1, ++ BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2, ++ BLND_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3, ++} BLND_CONTROL_BLND_STEREO_TYPE; ++typedef enum BLND_CONTROL_BLND_STEREO_POLARITY { ++ BLND_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0, ++ BLND_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1, ++} BLND_CONTROL_BLND_STEREO_POLARITY; ++typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN { ++ BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0, ++ BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1, ++} BLND_CONTROL_BLND_FEEDTHROUGH_EN; ++typedef enum BLND_CONTROL_BLND_ALPHA_MODE { ++ BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x0, ++ BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1, ++ BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2, ++ BLND_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3, ++} BLND_CONTROL_BLND_ALPHA_MODE; ++typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE { ++ BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0, ++ BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1, ++} BLND_CONTROL_BLND_MULTIPLIED_MODE; ++typedef enum BLND_SM_CONTROL2_SM_MODE { ++ BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0, ++ BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2, ++ BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4, ++ BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6, ++} BLND_SM_CONTROL2_SM_MODE; ++typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE { ++ BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0, ++ BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1, ++} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE; ++typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE { ++ BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0, ++ BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1, ++} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE; ++typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL { ++ BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0, ++ BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1, ++ BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2, ++ BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3, ++} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL; ++typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL { ++ BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0, ++ BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1, ++ BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x2, ++ BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3, ++} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL; ++typedef enum BLND_CONTROL2_PTI_ENABLE { ++ BLND_CONTROL2_PTI_ENABLE_FALSE = 0x0, ++ BLND_CONTROL2_PTI_ENABLE_TRUE = 0x1, ++} BLND_CONTROL2_PTI_ENABLE; ++typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN { ++ BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0, ++ BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1, ++} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN; ++typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN { ++ BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0, ++ BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1, ++} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN; ++typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK { ++ BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0, ++ BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1, ++} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK; ++typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK { ++ BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0, ++ BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1, ++} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK; ++typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK { ++ BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0, ++ BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1, ++} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK; ++typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK { ++ BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0, ++ BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1, ++} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; ++typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK { ++ BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0, ++ BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1, ++} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK; ++typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK { ++ BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0, ++ BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1, ++} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK; ++typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK { ++ BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0, ++ BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1, ++} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK; ++typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK { ++ BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x0, ++ BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1, ++} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK; ++typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE { ++ BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x0, ++ BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1, ++} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE; ++typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT { ++ BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0, ++ BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1, ++} BLND_DEBUG_BLND_CNV_MUX_SELECT; ++typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN { ++ BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0, ++ BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1, ++} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN; ++typedef enum DebugBlockId { ++ DBG_BLOCK_ID_RESERVED = 0x0, ++ DBG_BLOCK_ID_DBG = 0x1, ++ DBG_BLOCK_ID_VMC = 0x2, ++ DBG_BLOCK_ID_PDMA = 0x3, ++ DBG_BLOCK_ID_CG = 0x4, ++ DBG_BLOCK_ID_SRBM = 0x5, ++ DBG_BLOCK_ID_GRBM = 0x6, ++ DBG_BLOCK_ID_RLC = 0x7, ++ DBG_BLOCK_ID_CSC = 0x8, ++ DBG_BLOCK_ID_SEM = 0x9, ++ DBG_BLOCK_ID_IH = 0xa, ++ DBG_BLOCK_ID_SC = 0xb, ++ DBG_BLOCK_ID_SQ = 0xc, ++ DBG_BLOCK_ID_UVDU = 0xd, ++ DBG_BLOCK_ID_SQA = 0xe, ++ DBG_BLOCK_ID_SDMA0 = 0xf, ++ DBG_BLOCK_ID_SDMA1 = 0x10, ++ DBG_BLOCK_ID_SPIM = 0x11, ++ DBG_BLOCK_ID_GDS = 0x12, ++ DBG_BLOCK_ID_VC0 = 0x13, ++ DBG_BLOCK_ID_VC1 = 0x14, ++ DBG_BLOCK_ID_PA0 = 0x15, ++ DBG_BLOCK_ID_PA1 = 0x16, ++ DBG_BLOCK_ID_CP0 = 0x17, ++ DBG_BLOCK_ID_CP1 = 0x18, ++ DBG_BLOCK_ID_CP2 = 0x19, ++ DBG_BLOCK_ID_XBR = 0x1a, ++ DBG_BLOCK_ID_UVDM = 0x1b, ++ DBG_BLOCK_ID_VGT0 = 0x1c, ++ DBG_BLOCK_ID_VGT1 = 0x1d, ++ DBG_BLOCK_ID_IA = 0x1e, ++ DBG_BLOCK_ID_SXM0 = 0x1f, ++ DBG_BLOCK_ID_SXM1 = 0x20, ++ DBG_BLOCK_ID_SCT0 = 0x21, ++ DBG_BLOCK_ID_SCT1 = 0x22, ++ DBG_BLOCK_ID_SPM0 = 0x23, ++ DBG_BLOCK_ID_SPM1 = 0x24, ++ DBG_BLOCK_ID_UNUSED0 = 0x25, ++ DBG_BLOCK_ID_UNUSED1 = 0x26, ++ DBG_BLOCK_ID_TCAA = 0x27, ++ DBG_BLOCK_ID_TCAB = 0x28, ++ DBG_BLOCK_ID_TCCA = 0x29, ++ DBG_BLOCK_ID_TCCB = 0x2a, ++ DBG_BLOCK_ID_MCC0 = 0x2b, ++ DBG_BLOCK_ID_MCC1 = 0x2c, ++ DBG_BLOCK_ID_MCC2 = 0x2d, ++ DBG_BLOCK_ID_MCC3 = 0x2e, ++ DBG_BLOCK_ID_SXS0 = 0x2f, ++ DBG_BLOCK_ID_SXS1 = 0x30, ++ DBG_BLOCK_ID_SXS2 = 0x31, ++ DBG_BLOCK_ID_SXS3 = 0x32, ++ DBG_BLOCK_ID_SXS4 = 0x33, ++ DBG_BLOCK_ID_SXS5 = 0x34, ++ DBG_BLOCK_ID_SXS6 = 0x35, ++ DBG_BLOCK_ID_SXS7 = 0x36, ++ DBG_BLOCK_ID_SXS8 = 0x37, ++ DBG_BLOCK_ID_SXS9 = 0x38, ++ DBG_BLOCK_ID_BCI0 = 0x39, ++ DBG_BLOCK_ID_BCI1 = 0x3a, ++ DBG_BLOCK_ID_BCI2 = 0x3b, ++ DBG_BLOCK_ID_BCI3 = 0x3c, ++ DBG_BLOCK_ID_MCB = 0x3d, ++ DBG_BLOCK_ID_UNUSED6 = 0x3e, ++ DBG_BLOCK_ID_SQA00 = 0x3f, ++ DBG_BLOCK_ID_SQA01 = 0x40, ++ DBG_BLOCK_ID_SQA02 = 0x41, ++ DBG_BLOCK_ID_SQA10 = 0x42, ++ DBG_BLOCK_ID_SQA11 = 0x43, ++ DBG_BLOCK_ID_SQA12 = 0x44, ++ DBG_BLOCK_ID_UNUSED7 = 0x45, ++ DBG_BLOCK_ID_UNUSED8 = 0x46, ++ DBG_BLOCK_ID_SQB00 = 0x47, ++ DBG_BLOCK_ID_SQB01 = 0x48, ++ DBG_BLOCK_ID_SQB10 = 0x49, ++ DBG_BLOCK_ID_SQB11 = 0x4a, ++ DBG_BLOCK_ID_SQ00 = 0x4b, ++ DBG_BLOCK_ID_SQ01 = 0x4c, ++ DBG_BLOCK_ID_SQ10 = 0x4d, ++ DBG_BLOCK_ID_SQ11 = 0x4e, ++ DBG_BLOCK_ID_CB00 = 0x4f, ++ DBG_BLOCK_ID_CB01 = 0x50, ++ DBG_BLOCK_ID_CB02 = 0x51, ++ DBG_BLOCK_ID_CB03 = 0x52, ++ DBG_BLOCK_ID_CB04 = 0x53, ++ DBG_BLOCK_ID_UNUSED9 = 0x54, ++ DBG_BLOCK_ID_UNUSED10 = 0x55, ++ DBG_BLOCK_ID_UNUSED11 = 0x56, ++ DBG_BLOCK_ID_CB10 = 0x57, ++ DBG_BLOCK_ID_CB11 = 0x58, ++ DBG_BLOCK_ID_CB12 = 0x59, ++ DBG_BLOCK_ID_CB13 = 0x5a, ++ DBG_BLOCK_ID_CB14 = 0x5b, ++ DBG_BLOCK_ID_UNUSED12 = 0x5c, ++ DBG_BLOCK_ID_UNUSED13 = 0x5d, ++ DBG_BLOCK_ID_UNUSED14 = 0x5e, ++ DBG_BLOCK_ID_TCP0 = 0x5f, ++ DBG_BLOCK_ID_TCP1 = 0x60, ++ DBG_BLOCK_ID_TCP2 = 0x61, ++ DBG_BLOCK_ID_TCP3 = 0x62, ++ DBG_BLOCK_ID_TCP4 = 0x63, ++ DBG_BLOCK_ID_TCP5 = 0x64, ++ DBG_BLOCK_ID_TCP6 = 0x65, ++ DBG_BLOCK_ID_TCP7 = 0x66, ++ DBG_BLOCK_ID_TCP8 = 0x67, ++ DBG_BLOCK_ID_TCP9 = 0x68, ++ DBG_BLOCK_ID_TCP10 = 0x69, ++ DBG_BLOCK_ID_TCP11 = 0x6a, ++ DBG_BLOCK_ID_TCP12 = 0x6b, ++ DBG_BLOCK_ID_TCP13 = 0x6c, ++ DBG_BLOCK_ID_TCP14 = 0x6d, ++ DBG_BLOCK_ID_TCP15 = 0x6e, ++ DBG_BLOCK_ID_TCP16 = 0x6f, ++ DBG_BLOCK_ID_TCP17 = 0x70, ++ DBG_BLOCK_ID_TCP18 = 0x71, ++ DBG_BLOCK_ID_TCP19 = 0x72, ++ DBG_BLOCK_ID_TCP20 = 0x73, ++ DBG_BLOCK_ID_TCP21 = 0x74, ++ DBG_BLOCK_ID_TCP22 = 0x75, ++ DBG_BLOCK_ID_TCP23 = 0x76, ++ DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, ++ DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, ++ DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, ++ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, ++ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, ++ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, ++ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, ++ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, ++ DBG_BLOCK_ID_DB00 = 0x7f, ++ DBG_BLOCK_ID_DB01 = 0x80, ++ DBG_BLOCK_ID_DB02 = 0x81, ++ DBG_BLOCK_ID_DB03 = 0x82, ++ DBG_BLOCK_ID_DB04 = 0x83, ++ DBG_BLOCK_ID_UNUSED15 = 0x84, ++ DBG_BLOCK_ID_UNUSED16 = 0x85, ++ DBG_BLOCK_ID_UNUSED17 = 0x86, ++ DBG_BLOCK_ID_DB10 = 0x87, ++ DBG_BLOCK_ID_DB11 = 0x88, ++ DBG_BLOCK_ID_DB12 = 0x89, ++ DBG_BLOCK_ID_DB13 = 0x8a, ++ DBG_BLOCK_ID_DB14 = 0x8b, ++ DBG_BLOCK_ID_UNUSED18 = 0x8c, ++ DBG_BLOCK_ID_UNUSED19 = 0x8d, ++ DBG_BLOCK_ID_UNUSED20 = 0x8e, ++ DBG_BLOCK_ID_TCC0 = 0x8f, ++ DBG_BLOCK_ID_TCC1 = 0x90, ++ DBG_BLOCK_ID_TCC2 = 0x91, ++ DBG_BLOCK_ID_TCC3 = 0x92, ++ DBG_BLOCK_ID_TCC4 = 0x93, ++ DBG_BLOCK_ID_TCC5 = 0x94, ++ DBG_BLOCK_ID_TCC6 = 0x95, ++ DBG_BLOCK_ID_TCC7 = 0x96, ++ DBG_BLOCK_ID_SPS00 = 0x97, ++ DBG_BLOCK_ID_SPS01 = 0x98, ++ DBG_BLOCK_ID_SPS02 = 0x99, ++ DBG_BLOCK_ID_SPS10 = 0x9a, ++ DBG_BLOCK_ID_SPS11 = 0x9b, ++ DBG_BLOCK_ID_SPS12 = 0x9c, ++ DBG_BLOCK_ID_UNUSED21 = 0x9d, ++ DBG_BLOCK_ID_UNUSED22 = 0x9e, ++ DBG_BLOCK_ID_TA00 = 0x9f, ++ DBG_BLOCK_ID_TA01 = 0xa0, ++ DBG_BLOCK_ID_TA02 = 0xa1, ++ DBG_BLOCK_ID_TA03 = 0xa2, ++ DBG_BLOCK_ID_TA04 = 0xa3, ++ DBG_BLOCK_ID_TA05 = 0xa4, ++ DBG_BLOCK_ID_TA06 = 0xa5, ++ DBG_BLOCK_ID_TA07 = 0xa6, ++ DBG_BLOCK_ID_TA08 = 0xa7, ++ DBG_BLOCK_ID_TA09 = 0xa8, ++ DBG_BLOCK_ID_TA0A = 0xa9, ++ DBG_BLOCK_ID_TA0B = 0xaa, ++ DBG_BLOCK_ID_UNUSED23 = 0xab, ++ DBG_BLOCK_ID_UNUSED24 = 0xac, ++ DBG_BLOCK_ID_UNUSED25 = 0xad, ++ DBG_BLOCK_ID_UNUSED26 = 0xae, ++ DBG_BLOCK_ID_TA10 = 0xaf, ++ DBG_BLOCK_ID_TA11 = 0xb0, ++ DBG_BLOCK_ID_TA12 = 0xb1, ++ DBG_BLOCK_ID_TA13 = 0xb2, ++ DBG_BLOCK_ID_TA14 = 0xb3, ++ DBG_BLOCK_ID_TA15 = 0xb4, ++ DBG_BLOCK_ID_TA16 = 0xb5, ++ DBG_BLOCK_ID_TA17 = 0xb6, ++ DBG_BLOCK_ID_TA18 = 0xb7, ++ DBG_BLOCK_ID_TA19 = 0xb8, ++ DBG_BLOCK_ID_TA1A = 0xb9, ++ DBG_BLOCK_ID_TA1B = 0xba, ++ DBG_BLOCK_ID_UNUSED27 = 0xbb, ++ DBG_BLOCK_ID_UNUSED28 = 0xbc, ++ DBG_BLOCK_ID_UNUSED29 = 0xbd, ++ DBG_BLOCK_ID_UNUSED30 = 0xbe, ++ DBG_BLOCK_ID_TD00 = 0xbf, ++ DBG_BLOCK_ID_TD01 = 0xc0, ++ DBG_BLOCK_ID_TD02 = 0xc1, ++ DBG_BLOCK_ID_TD03 = 0xc2, ++ DBG_BLOCK_ID_TD04 = 0xc3, ++ DBG_BLOCK_ID_TD05 = 0xc4, ++ DBG_BLOCK_ID_TD06 = 0xc5, ++ DBG_BLOCK_ID_TD07 = 0xc6, ++ DBG_BLOCK_ID_TD08 = 0xc7, ++ DBG_BLOCK_ID_TD09 = 0xc8, ++ DBG_BLOCK_ID_TD0A = 0xc9, ++ DBG_BLOCK_ID_TD0B = 0xca, ++ DBG_BLOCK_ID_UNUSED31 = 0xcb, ++ DBG_BLOCK_ID_UNUSED32 = 0xcc, ++ DBG_BLOCK_ID_UNUSED33 = 0xcd, ++ DBG_BLOCK_ID_UNUSED34 = 0xce, ++ DBG_BLOCK_ID_TD10 = 0xcf, ++ DBG_BLOCK_ID_TD11 = 0xd0, ++ DBG_BLOCK_ID_TD12 = 0xd1, ++ DBG_BLOCK_ID_TD13 = 0xd2, ++ DBG_BLOCK_ID_TD14 = 0xd3, ++ DBG_BLOCK_ID_TD15 = 0xd4, ++ DBG_BLOCK_ID_TD16 = 0xd5, ++ DBG_BLOCK_ID_TD17 = 0xd6, ++ DBG_BLOCK_ID_TD18 = 0xd7, ++ DBG_BLOCK_ID_TD19 = 0xd8, ++ DBG_BLOCK_ID_TD1A = 0xd9, ++ DBG_BLOCK_ID_TD1B = 0xda, ++ DBG_BLOCK_ID_UNUSED35 = 0xdb, ++ DBG_BLOCK_ID_UNUSED36 = 0xdc, ++ DBG_BLOCK_ID_UNUSED37 = 0xdd, ++ DBG_BLOCK_ID_UNUSED38 = 0xde, ++ DBG_BLOCK_ID_LDS00 = 0xdf, ++ DBG_BLOCK_ID_LDS01 = 0xe0, ++ DBG_BLOCK_ID_LDS02 = 0xe1, ++ DBG_BLOCK_ID_LDS03 = 0xe2, ++ DBG_BLOCK_ID_LDS04 = 0xe3, ++ DBG_BLOCK_ID_LDS05 = 0xe4, ++ DBG_BLOCK_ID_LDS06 = 0xe5, ++ DBG_BLOCK_ID_LDS07 = 0xe6, ++ DBG_BLOCK_ID_LDS08 = 0xe7, ++ DBG_BLOCK_ID_LDS09 = 0xe8, ++ DBG_BLOCK_ID_LDS0A = 0xe9, ++ DBG_BLOCK_ID_LDS0B = 0xea, ++ DBG_BLOCK_ID_UNUSED39 = 0xeb, ++ DBG_BLOCK_ID_UNUSED40 = 0xec, ++ DBG_BLOCK_ID_UNUSED41 = 0xed, ++ DBG_BLOCK_ID_UNUSED42 = 0xee, ++ DBG_BLOCK_ID_LDS10 = 0xef, ++ DBG_BLOCK_ID_LDS11 = 0xf0, ++ DBG_BLOCK_ID_LDS12 = 0xf1, ++ DBG_BLOCK_ID_LDS13 = 0xf2, ++ DBG_BLOCK_ID_LDS14 = 0xf3, ++ DBG_BLOCK_ID_LDS15 = 0xf4, ++ DBG_BLOCK_ID_LDS16 = 0xf5, ++ DBG_BLOCK_ID_LDS17 = 0xf6, ++ DBG_BLOCK_ID_LDS18 = 0xf7, ++ DBG_BLOCK_ID_LDS19 = 0xf8, ++ DBG_BLOCK_ID_LDS1A = 0xf9, ++ DBG_BLOCK_ID_LDS1B = 0xfa, ++ DBG_BLOCK_ID_UNUSED43 = 0xfb, ++ DBG_BLOCK_ID_UNUSED44 = 0xfc, ++ DBG_BLOCK_ID_UNUSED45 = 0xfd, ++ DBG_BLOCK_ID_UNUSED46 = 0xfe, ++} DebugBlockId; ++typedef enum DebugBlockId_BY2 { ++ DBG_BLOCK_ID_RESERVED_BY2 = 0x0, ++ DBG_BLOCK_ID_VMC_BY2 = 0x1, ++ DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, ++ DBG_BLOCK_ID_GRBM_BY2 = 0x3, ++ DBG_BLOCK_ID_CSC_BY2 = 0x4, ++ DBG_BLOCK_ID_IH_BY2 = 0x5, ++ DBG_BLOCK_ID_SQ_BY2 = 0x6, ++ DBG_BLOCK_ID_UVD_BY2 = 0x7, ++ DBG_BLOCK_ID_SDMA0_BY2 = 0x8, ++ DBG_BLOCK_ID_SPIM_BY2 = 0x9, ++ DBG_BLOCK_ID_VC0_BY2 = 0xa, ++ DBG_BLOCK_ID_PA_BY2 = 0xb, ++ DBG_BLOCK_ID_CP0_BY2 = 0xc, ++ DBG_BLOCK_ID_CP2_BY2 = 0xd, ++ DBG_BLOCK_ID_PC0_BY2 = 0xe, ++ DBG_BLOCK_ID_BCI0_BY2 = 0xf, ++ DBG_BLOCK_ID_SXM0_BY2 = 0x10, ++ DBG_BLOCK_ID_SCT0_BY2 = 0x11, ++ DBG_BLOCK_ID_SPM0_BY2 = 0x12, ++ DBG_BLOCK_ID_BCI2_BY2 = 0x13, ++ DBG_BLOCK_ID_TCA_BY2 = 0x14, ++ DBG_BLOCK_ID_TCCA_BY2 = 0x15, ++ DBG_BLOCK_ID_MCC_BY2 = 0x16, ++ DBG_BLOCK_ID_MCC2_BY2 = 0x17, ++ DBG_BLOCK_ID_MCD_BY2 = 0x18, ++ DBG_BLOCK_ID_MCD2_BY2 = 0x19, ++ DBG_BLOCK_ID_MCD4_BY2 = 0x1a, ++ DBG_BLOCK_ID_MCB_BY2 = 0x1b, ++ DBG_BLOCK_ID_SQA_BY2 = 0x1c, ++ DBG_BLOCK_ID_SQA02_BY2 = 0x1d, ++ DBG_BLOCK_ID_SQA11_BY2 = 0x1e, ++ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, ++ DBG_BLOCK_ID_SQB_BY2 = 0x20, ++ DBG_BLOCK_ID_SQB10_BY2 = 0x21, ++ DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, ++ DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, ++ DBG_BLOCK_ID_CB_BY2 = 0x24, ++ DBG_BLOCK_ID_CB02_BY2 = 0x25, ++ DBG_BLOCK_ID_CB10_BY2 = 0x26, ++ DBG_BLOCK_ID_CB12_BY2 = 0x27, ++ DBG_BLOCK_ID_SXS_BY2 = 0x28, ++ DBG_BLOCK_ID_SXS2_BY2 = 0x29, ++ DBG_BLOCK_ID_SXS4_BY2 = 0x2a, ++ DBG_BLOCK_ID_SXS6_BY2 = 0x2b, ++ DBG_BLOCK_ID_DB_BY2 = 0x2c, ++ DBG_BLOCK_ID_DB02_BY2 = 0x2d, ++ DBG_BLOCK_ID_DB10_BY2 = 0x2e, ++ DBG_BLOCK_ID_DB12_BY2 = 0x2f, ++ DBG_BLOCK_ID_TCP_BY2 = 0x30, ++ DBG_BLOCK_ID_TCP2_BY2 = 0x31, ++ DBG_BLOCK_ID_TCP4_BY2 = 0x32, ++ DBG_BLOCK_ID_TCP6_BY2 = 0x33, ++ DBG_BLOCK_ID_TCP8_BY2 = 0x34, ++ DBG_BLOCK_ID_TCP10_BY2 = 0x35, ++ DBG_BLOCK_ID_TCP12_BY2 = 0x36, ++ DBG_BLOCK_ID_TCP14_BY2 = 0x37, ++ DBG_BLOCK_ID_TCP16_BY2 = 0x38, ++ DBG_BLOCK_ID_TCP18_BY2 = 0x39, ++ DBG_BLOCK_ID_TCP20_BY2 = 0x3a, ++ DBG_BLOCK_ID_TCP22_BY2 = 0x3b, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, ++ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, ++ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, ++ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, ++ DBG_BLOCK_ID_TCC_BY2 = 0x40, ++ DBG_BLOCK_ID_TCC2_BY2 = 0x41, ++ DBG_BLOCK_ID_TCC4_BY2 = 0x42, ++ DBG_BLOCK_ID_TCC6_BY2 = 0x43, ++ DBG_BLOCK_ID_SPS_BY2 = 0x44, ++ DBG_BLOCK_ID_SPS02_BY2 = 0x45, ++ DBG_BLOCK_ID_SPS11_BY2 = 0x46, ++ DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, ++ DBG_BLOCK_ID_TA_BY2 = 0x48, ++ DBG_BLOCK_ID_TA02_BY2 = 0x49, ++ DBG_BLOCK_ID_TA04_BY2 = 0x4a, ++ DBG_BLOCK_ID_TA06_BY2 = 0x4b, ++ DBG_BLOCK_ID_TA08_BY2 = 0x4c, ++ DBG_BLOCK_ID_TA0A_BY2 = 0x4d, ++ DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, ++ DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, ++ DBG_BLOCK_ID_TA10_BY2 = 0x50, ++ DBG_BLOCK_ID_TA12_BY2 = 0x51, ++ DBG_BLOCK_ID_TA14_BY2 = 0x52, ++ DBG_BLOCK_ID_TA16_BY2 = 0x53, ++ DBG_BLOCK_ID_TA18_BY2 = 0x54, ++ DBG_BLOCK_ID_TA1A_BY2 = 0x55, ++ DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, ++ DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, ++ DBG_BLOCK_ID_TD_BY2 = 0x58, ++ DBG_BLOCK_ID_TD02_BY2 = 0x59, ++ DBG_BLOCK_ID_TD04_BY2 = 0x5a, ++ DBG_BLOCK_ID_TD06_BY2 = 0x5b, ++ DBG_BLOCK_ID_TD08_BY2 = 0x5c, ++ DBG_BLOCK_ID_TD0A_BY2 = 0x5d, ++ DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, ++ DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, ++ DBG_BLOCK_ID_TD10_BY2 = 0x60, ++ DBG_BLOCK_ID_TD12_BY2 = 0x61, ++ DBG_BLOCK_ID_TD14_BY2 = 0x62, ++ DBG_BLOCK_ID_TD16_BY2 = 0x63, ++ DBG_BLOCK_ID_TD18_BY2 = 0x64, ++ DBG_BLOCK_ID_TD1A_BY2 = 0x65, ++ DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, ++ DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, ++ DBG_BLOCK_ID_LDS_BY2 = 0x68, ++ DBG_BLOCK_ID_LDS02_BY2 = 0x69, ++ DBG_BLOCK_ID_LDS04_BY2 = 0x6a, ++ DBG_BLOCK_ID_LDS06_BY2 = 0x6b, ++ DBG_BLOCK_ID_LDS08_BY2 = 0x6c, ++ DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, ++ DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, ++ DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, ++ DBG_BLOCK_ID_LDS10_BY2 = 0x70, ++ DBG_BLOCK_ID_LDS12_BY2 = 0x71, ++ DBG_BLOCK_ID_LDS14_BY2 = 0x72, ++ DBG_BLOCK_ID_LDS16_BY2 = 0x73, ++ DBG_BLOCK_ID_LDS18_BY2 = 0x74, ++ DBG_BLOCK_ID_LDS1A_BY2 = 0x75, ++ DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, ++ DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, ++} DebugBlockId_BY2; ++typedef enum DebugBlockId_BY4 { ++ DBG_BLOCK_ID_RESERVED_BY4 = 0x0, ++ DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, ++ DBG_BLOCK_ID_CSC_BY4 = 0x2, ++ DBG_BLOCK_ID_SQ_BY4 = 0x3, ++ DBG_BLOCK_ID_SDMA0_BY4 = 0x4, ++ DBG_BLOCK_ID_VC0_BY4 = 0x5, ++ DBG_BLOCK_ID_CP0_BY4 = 0x6, ++ DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, ++ DBG_BLOCK_ID_SXM0_BY4 = 0x8, ++ DBG_BLOCK_ID_SPM0_BY4 = 0x9, ++ DBG_BLOCK_ID_TCAA_BY4 = 0xa, ++ DBG_BLOCK_ID_MCC_BY4 = 0xb, ++ DBG_BLOCK_ID_MCD_BY4 = 0xc, ++ DBG_BLOCK_ID_MCD4_BY4 = 0xd, ++ DBG_BLOCK_ID_SQA_BY4 = 0xe, ++ DBG_BLOCK_ID_SQA11_BY4 = 0xf, ++ DBG_BLOCK_ID_SQB_BY4 = 0x10, ++ DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, ++ DBG_BLOCK_ID_CB_BY4 = 0x12, ++ DBG_BLOCK_ID_CB10_BY4 = 0x13, ++ DBG_BLOCK_ID_SXS_BY4 = 0x14, ++ DBG_BLOCK_ID_SXS4_BY4 = 0x15, ++ DBG_BLOCK_ID_DB_BY4 = 0x16, ++ DBG_BLOCK_ID_DB10_BY4 = 0x17, ++ DBG_BLOCK_ID_TCP_BY4 = 0x18, ++ DBG_BLOCK_ID_TCP4_BY4 = 0x19, ++ DBG_BLOCK_ID_TCP8_BY4 = 0x1a, ++ DBG_BLOCK_ID_TCP12_BY4 = 0x1b, ++ DBG_BLOCK_ID_TCP16_BY4 = 0x1c, ++ DBG_BLOCK_ID_TCP20_BY4 = 0x1d, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, ++ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, ++ DBG_BLOCK_ID_TCC_BY4 = 0x20, ++ DBG_BLOCK_ID_TCC4_BY4 = 0x21, ++ DBG_BLOCK_ID_SPS_BY4 = 0x22, ++ DBG_BLOCK_ID_SPS11_BY4 = 0x23, ++ DBG_BLOCK_ID_TA_BY4 = 0x24, ++ DBG_BLOCK_ID_TA04_BY4 = 0x25, ++ DBG_BLOCK_ID_TA08_BY4 = 0x26, ++ DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, ++ DBG_BLOCK_ID_TA10_BY4 = 0x28, ++ DBG_BLOCK_ID_TA14_BY4 = 0x29, ++ DBG_BLOCK_ID_TA18_BY4 = 0x2a, ++ DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, ++ DBG_BLOCK_ID_TD_BY4 = 0x2c, ++ DBG_BLOCK_ID_TD04_BY4 = 0x2d, ++ DBG_BLOCK_ID_TD08_BY4 = 0x2e, ++ DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, ++ DBG_BLOCK_ID_TD10_BY4 = 0x30, ++ DBG_BLOCK_ID_TD14_BY4 = 0x31, ++ DBG_BLOCK_ID_TD18_BY4 = 0x32, ++ DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, ++ DBG_BLOCK_ID_LDS_BY4 = 0x34, ++ DBG_BLOCK_ID_LDS04_BY4 = 0x35, ++ DBG_BLOCK_ID_LDS08_BY4 = 0x36, ++ DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, ++ DBG_BLOCK_ID_LDS10_BY4 = 0x38, ++ DBG_BLOCK_ID_LDS14_BY4 = 0x39, ++ DBG_BLOCK_ID_LDS18_BY4 = 0x3a, ++ DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, ++} DebugBlockId_BY4; ++typedef enum DebugBlockId_BY8 { ++ DBG_BLOCK_ID_RESERVED_BY8 = 0x0, ++ DBG_BLOCK_ID_CSC_BY8 = 0x1, ++ DBG_BLOCK_ID_SDMA0_BY8 = 0x2, ++ DBG_BLOCK_ID_CP0_BY8 = 0x3, ++ DBG_BLOCK_ID_SXM0_BY8 = 0x4, ++ DBG_BLOCK_ID_TCA_BY8 = 0x5, ++ DBG_BLOCK_ID_MCD_BY8 = 0x6, ++ DBG_BLOCK_ID_SQA_BY8 = 0x7, ++ DBG_BLOCK_ID_SQB_BY8 = 0x8, ++ DBG_BLOCK_ID_CB_BY8 = 0x9, ++ DBG_BLOCK_ID_SXS_BY8 = 0xa, ++ DBG_BLOCK_ID_DB_BY8 = 0xb, ++ DBG_BLOCK_ID_TCP_BY8 = 0xc, ++ DBG_BLOCK_ID_TCP8_BY8 = 0xd, ++ DBG_BLOCK_ID_TCP16_BY8 = 0xe, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, ++ DBG_BLOCK_ID_TCC_BY8 = 0x10, ++ DBG_BLOCK_ID_SPS_BY8 = 0x11, ++ DBG_BLOCK_ID_TA_BY8 = 0x12, ++ DBG_BLOCK_ID_TA08_BY8 = 0x13, ++ DBG_BLOCK_ID_TA10_BY8 = 0x14, ++ DBG_BLOCK_ID_TA18_BY8 = 0x15, ++ DBG_BLOCK_ID_TD_BY8 = 0x16, ++ DBG_BLOCK_ID_TD08_BY8 = 0x17, ++ DBG_BLOCK_ID_TD10_BY8 = 0x18, ++ DBG_BLOCK_ID_TD18_BY8 = 0x19, ++ DBG_BLOCK_ID_LDS_BY8 = 0x1a, ++ DBG_BLOCK_ID_LDS08_BY8 = 0x1b, ++ DBG_BLOCK_ID_LDS10_BY8 = 0x1c, ++ DBG_BLOCK_ID_LDS18_BY8 = 0x1d, ++} DebugBlockId_BY8; ++typedef enum DebugBlockId_BY16 { ++ DBG_BLOCK_ID_RESERVED_BY16 = 0x0, ++ DBG_BLOCK_ID_SDMA0_BY16 = 0x1, ++ DBG_BLOCK_ID_SXM_BY16 = 0x2, ++ DBG_BLOCK_ID_MCD_BY16 = 0x3, ++ DBG_BLOCK_ID_SQB_BY16 = 0x4, ++ DBG_BLOCK_ID_SXS_BY16 = 0x5, ++ DBG_BLOCK_ID_TCP_BY16 = 0x6, ++ DBG_BLOCK_ID_TCP16_BY16 = 0x7, ++ DBG_BLOCK_ID_TCC_BY16 = 0x8, ++ DBG_BLOCK_ID_TA_BY16 = 0x9, ++ DBG_BLOCK_ID_TA10_BY16 = 0xa, ++ DBG_BLOCK_ID_TD_BY16 = 0xb, ++ DBG_BLOCK_ID_TD10_BY16 = 0xc, ++ DBG_BLOCK_ID_LDS_BY16 = 0xd, ++ DBG_BLOCK_ID_LDS10_BY16 = 0xe, ++} DebugBlockId_BY16; ++typedef enum SurfaceEndian { ++ ENDIAN_NONE = 0x0, ++ ENDIAN_8IN16 = 0x1, ++ ENDIAN_8IN32 = 0x2, ++ ENDIAN_8IN64 = 0x3, ++} SurfaceEndian; ++typedef enum ArrayMode { ++ ARRAY_LINEAR_GENERAL = 0x0, ++ ARRAY_LINEAR_ALIGNED = 0x1, ++ ARRAY_1D_TILED_THIN1 = 0x2, ++ ARRAY_1D_TILED_THICK = 0x3, ++ ARRAY_2D_TILED_THIN1 = 0x4, ++ ARRAY_PRT_TILED_THIN1 = 0x5, ++ ARRAY_PRT_2D_TILED_THIN1 = 0x6, ++ ARRAY_2D_TILED_THICK = 0x7, ++ ARRAY_2D_TILED_XTHICK = 0x8, ++ ARRAY_PRT_TILED_THICK = 0x9, ++ ARRAY_PRT_2D_TILED_THICK = 0xa, ++ ARRAY_PRT_3D_TILED_THIN1 = 0xb, ++ ARRAY_3D_TILED_THIN1 = 0xc, ++ ARRAY_3D_TILED_THICK = 0xd, ++ ARRAY_3D_TILED_XTHICK = 0xe, ++ ARRAY_PRT_3D_TILED_THICK = 0xf, ++} ArrayMode; ++typedef enum PipeTiling { ++ CONFIG_1_PIPE = 0x0, ++ CONFIG_2_PIPE = 0x1, ++ CONFIG_4_PIPE = 0x2, ++ CONFIG_8_PIPE = 0x3, ++} PipeTiling; ++typedef enum BankTiling { ++ CONFIG_4_BANK = 0x0, ++ CONFIG_8_BANK = 0x1, ++} BankTiling; ++typedef enum GroupInterleave { ++ CONFIG_256B_GROUP = 0x0, ++ CONFIG_512B_GROUP = 0x1, ++} GroupInterleave; ++typedef enum RowTiling { ++ CONFIG_1KB_ROW = 0x0, ++ CONFIG_2KB_ROW = 0x1, ++ CONFIG_4KB_ROW = 0x2, ++ CONFIG_8KB_ROW = 0x3, ++ CONFIG_1KB_ROW_OPT = 0x4, ++ CONFIG_2KB_ROW_OPT = 0x5, ++ CONFIG_4KB_ROW_OPT = 0x6, ++ CONFIG_8KB_ROW_OPT = 0x7, ++} RowTiling; ++typedef enum BankSwapBytes { ++ CONFIG_128B_SWAPS = 0x0, ++ CONFIG_256B_SWAPS = 0x1, ++ CONFIG_512B_SWAPS = 0x2, ++ CONFIG_1KB_SWAPS = 0x3, ++} BankSwapBytes; ++typedef enum SampleSplitBytes { ++ CONFIG_1KB_SPLIT = 0x0, ++ CONFIG_2KB_SPLIT = 0x1, ++ CONFIG_4KB_SPLIT = 0x2, ++ CONFIG_8KB_SPLIT = 0x3, ++} SampleSplitBytes; ++typedef enum NumPipes { ++ ADDR_CONFIG_1_PIPE = 0x0, ++ ADDR_CONFIG_2_PIPE = 0x1, ++ ADDR_CONFIG_4_PIPE = 0x2, ++ ADDR_CONFIG_8_PIPE = 0x3, ++} NumPipes; ++typedef enum PipeInterleaveSize { ++ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, ++ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, ++} PipeInterleaveSize; ++typedef enum BankInterleaveSize { ++ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, ++ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, ++ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, ++ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, ++} BankInterleaveSize; ++typedef enum NumShaderEngines { ++ ADDR_CONFIG_1_SHADER_ENGINE = 0x0, ++ ADDR_CONFIG_2_SHADER_ENGINE = 0x1, ++} NumShaderEngines; ++typedef enum ShaderEngineTileSize { ++ ADDR_CONFIG_SE_TILE_16 = 0x0, ++ ADDR_CONFIG_SE_TILE_32 = 0x1, ++} ShaderEngineTileSize; ++typedef enum NumGPUs { ++ ADDR_CONFIG_1_GPU = 0x0, ++ ADDR_CONFIG_2_GPU = 0x1, ++ ADDR_CONFIG_4_GPU = 0x2, ++} NumGPUs; ++typedef enum MultiGPUTileSize { ++ ADDR_CONFIG_GPU_TILE_16 = 0x0, ++ ADDR_CONFIG_GPU_TILE_32 = 0x1, ++ ADDR_CONFIG_GPU_TILE_64 = 0x2, ++ ADDR_CONFIG_GPU_TILE_128 = 0x3, ++} MultiGPUTileSize; ++typedef enum RowSize { ++ ADDR_CONFIG_1KB_ROW = 0x0, ++ ADDR_CONFIG_2KB_ROW = 0x1, ++ ADDR_CONFIG_4KB_ROW = 0x2, ++} RowSize; ++typedef enum NumLowerPipes { ++ ADDR_CONFIG_1_LOWER_PIPES = 0x0, ++ ADDR_CONFIG_2_LOWER_PIPES = 0x1, ++} NumLowerPipes; ++typedef enum ColorTransform { ++ DCC_CT_AUTO = 0x0, ++ DCC_CT_NONE = 0x1, ++ ABGR_TO_A_BG_G_RB = 0x2, ++ BGRA_TO_BG_G_RB_A = 0x3, ++} ColorTransform; ++typedef enum CompareRef { ++ REF_NEVER = 0x0, ++ REF_LESS = 0x1, ++ REF_EQUAL = 0x2, ++ REF_LEQUAL = 0x3, ++ REF_GREATER = 0x4, ++ REF_NOTEQUAL = 0x5, ++ REF_GEQUAL = 0x6, ++ REF_ALWAYS = 0x7, ++} CompareRef; ++typedef enum ReadSize { ++ READ_256_BITS = 0x0, ++ READ_512_BITS = 0x1, ++} ReadSize; ++typedef enum DepthFormat { ++ DEPTH_INVALID = 0x0, ++ DEPTH_16 = 0x1, ++ DEPTH_X8_24 = 0x2, ++ DEPTH_8_24 = 0x3, ++ DEPTH_X8_24_FLOAT = 0x4, ++ DEPTH_8_24_FLOAT = 0x5, ++ DEPTH_32_FLOAT = 0x6, ++ DEPTH_X24_8_32_FLOAT = 0x7, ++} DepthFormat; ++typedef enum ZFormat { ++ Z_INVALID = 0x0, ++ Z_16 = 0x1, ++ Z_24 = 0x2, ++ Z_32_FLOAT = 0x3, ++} ZFormat; ++typedef enum StencilFormat { ++ STENCIL_INVALID = 0x0, ++ STENCIL_8 = 0x1, ++} StencilFormat; ++typedef enum CmaskMode { ++ CMASK_CLEAR_NONE = 0x0, ++ CMASK_CLEAR_ONE = 0x1, ++ CMASK_CLEAR_ALL = 0x2, ++ CMASK_ANY_EXPANDED = 0x3, ++ CMASK_ALPHA0_FRAG1 = 0x4, ++ CMASK_ALPHA0_FRAG2 = 0x5, ++ CMASK_ALPHA0_FRAG4 = 0x6, ++ CMASK_ALPHA0_FRAGS = 0x7, ++ CMASK_ALPHA1_FRAG1 = 0x8, ++ CMASK_ALPHA1_FRAG2 = 0x9, ++ CMASK_ALPHA1_FRAG4 = 0xa, ++ CMASK_ALPHA1_FRAGS = 0xb, ++ CMASK_ALPHAX_FRAG1 = 0xc, ++ CMASK_ALPHAX_FRAG2 = 0xd, ++ CMASK_ALPHAX_FRAG4 = 0xe, ++ CMASK_ALPHAX_FRAGS = 0xf, ++} CmaskMode; ++typedef enum QuadExportFormat { ++ EXPORT_UNUSED = 0x0, ++ EXPORT_32_R = 0x1, ++ EXPORT_32_GR = 0x2, ++ EXPORT_32_AR = 0x3, ++ EXPORT_FP16_ABGR = 0x4, ++ EXPORT_UNSIGNED16_ABGR = 0x5, ++ EXPORT_SIGNED16_ABGR = 0x6, ++ EXPORT_32_ABGR = 0x7, ++} QuadExportFormat; ++typedef enum QuadExportFormatOld { ++ EXPORT_4P_32BPC_ABGR = 0x0, ++ EXPORT_4P_16BPC_ABGR = 0x1, ++ EXPORT_4P_32BPC_GR = 0x2, ++ EXPORT_4P_32BPC_AR = 0x3, ++ EXPORT_2P_32BPC_ABGR = 0x4, ++ EXPORT_8P_32BPC_R = 0x5, ++} QuadExportFormatOld; ++typedef enum ColorFormat { ++ COLOR_INVALID = 0x0, ++ COLOR_8 = 0x1, ++ COLOR_16 = 0x2, ++ COLOR_8_8 = 0x3, ++ COLOR_32 = 0x4, ++ COLOR_16_16 = 0x5, ++ COLOR_10_11_11 = 0x6, ++ COLOR_11_11_10 = 0x7, ++ COLOR_10_10_10_2 = 0x8, ++ COLOR_2_10_10_10 = 0x9, ++ COLOR_8_8_8_8 = 0xa, ++ COLOR_32_32 = 0xb, ++ COLOR_16_16_16_16 = 0xc, ++ COLOR_RESERVED_13 = 0xd, ++ COLOR_32_32_32_32 = 0xe, ++ COLOR_RESERVED_15 = 0xf, ++ COLOR_5_6_5 = 0x10, ++ COLOR_1_5_5_5 = 0x11, ++ COLOR_5_5_5_1 = 0x12, ++ COLOR_4_4_4_4 = 0x13, ++ COLOR_8_24 = 0x14, ++ COLOR_24_8 = 0x15, ++ COLOR_X24_8_32_FLOAT = 0x16, ++ COLOR_RESERVED_23 = 0x17, ++} ColorFormat; ++typedef enum SurfaceFormat { ++ FMT_INVALID = 0x0, ++ FMT_8 = 0x1, ++ FMT_16 = 0x2, ++ FMT_8_8 = 0x3, ++ FMT_32 = 0x4, ++ FMT_16_16 = 0x5, ++ FMT_10_11_11 = 0x6, ++ FMT_11_11_10 = 0x7, ++ FMT_10_10_10_2 = 0x8, ++ FMT_2_10_10_10 = 0x9, ++ FMT_8_8_8_8 = 0xa, ++ FMT_32_32 = 0xb, ++ FMT_16_16_16_16 = 0xc, ++ FMT_32_32_32 = 0xd, ++ FMT_32_32_32_32 = 0xe, ++ FMT_RESERVED_4 = 0xf, ++ FMT_5_6_5 = 0x10, ++ FMT_1_5_5_5 = 0x11, ++ FMT_5_5_5_1 = 0x12, ++ FMT_4_4_4_4 = 0x13, ++ FMT_8_24 = 0x14, ++ FMT_24_8 = 0x15, ++ FMT_X24_8_32_FLOAT = 0x16, ++ FMT_RESERVED_33 = 0x17, ++ FMT_11_11_10_FLOAT = 0x18, ++ FMT_16_FLOAT = 0x19, ++ FMT_32_FLOAT = 0x1a, ++ FMT_16_16_FLOAT = 0x1b, ++ FMT_8_24_FLOAT = 0x1c, ++ FMT_24_8_FLOAT = 0x1d, ++ FMT_32_32_FLOAT = 0x1e, ++ FMT_10_11_11_FLOAT = 0x1f, ++ FMT_16_16_16_16_FLOAT = 0x20, ++ FMT_3_3_2 = 0x21, ++ FMT_6_5_5 = 0x22, ++ FMT_32_32_32_32_FLOAT = 0x23, ++ FMT_RESERVED_36 = 0x24, ++ FMT_1 = 0x25, ++ FMT_1_REVERSED = 0x26, ++ FMT_GB_GR = 0x27, ++ FMT_BG_RG = 0x28, ++ FMT_32_AS_8 = 0x29, ++ FMT_32_AS_8_8 = 0x2a, ++ FMT_5_9_9_9_SHAREDEXP = 0x2b, ++ FMT_8_8_8 = 0x2c, ++ FMT_16_16_16 = 0x2d, ++ FMT_16_16_16_FLOAT = 0x2e, ++ FMT_4_4 = 0x2f, ++ FMT_32_32_32_FLOAT = 0x30, ++ FMT_BC1 = 0x31, ++ FMT_BC2 = 0x32, ++ FMT_BC3 = 0x33, ++ FMT_BC4 = 0x34, ++ FMT_BC5 = 0x35, ++ FMT_BC6 = 0x36, ++ FMT_BC7 = 0x37, ++ FMT_32_AS_32_32_32_32 = 0x38, ++ FMT_APC3 = 0x39, ++ FMT_APC4 = 0x3a, ++ FMT_APC5 = 0x3b, ++ FMT_APC6 = 0x3c, ++ FMT_APC7 = 0x3d, ++ FMT_CTX1 = 0x3e, ++ FMT_RESERVED_63 = 0x3f, ++} SurfaceFormat; ++typedef enum BUF_DATA_FORMAT { ++ BUF_DATA_FORMAT_INVALID = 0x0, ++ BUF_DATA_FORMAT_8 = 0x1, ++ BUF_DATA_FORMAT_16 = 0x2, ++ BUF_DATA_FORMAT_8_8 = 0x3, ++ BUF_DATA_FORMAT_32 = 0x4, ++ BUF_DATA_FORMAT_16_16 = 0x5, ++ BUF_DATA_FORMAT_10_11_11 = 0x6, ++ BUF_DATA_FORMAT_11_11_10 = 0x7, ++ BUF_DATA_FORMAT_10_10_10_2 = 0x8, ++ BUF_DATA_FORMAT_2_10_10_10 = 0x9, ++ BUF_DATA_FORMAT_8_8_8_8 = 0xa, ++ BUF_DATA_FORMAT_32_32 = 0xb, ++ BUF_DATA_FORMAT_16_16_16_16 = 0xc, ++ BUF_DATA_FORMAT_32_32_32 = 0xd, ++ BUF_DATA_FORMAT_32_32_32_32 = 0xe, ++ BUF_DATA_FORMAT_RESERVED_15 = 0xf, ++} BUF_DATA_FORMAT; ++typedef enum IMG_DATA_FORMAT { ++ IMG_DATA_FORMAT_INVALID = 0x0, ++ IMG_DATA_FORMAT_8 = 0x1, ++ IMG_DATA_FORMAT_16 = 0x2, ++ IMG_DATA_FORMAT_8_8 = 0x3, ++ IMG_DATA_FORMAT_32 = 0x4, ++ IMG_DATA_FORMAT_16_16 = 0x5, ++ IMG_DATA_FORMAT_10_11_11 = 0x6, ++ IMG_DATA_FORMAT_11_11_10 = 0x7, ++ IMG_DATA_FORMAT_10_10_10_2 = 0x8, ++ IMG_DATA_FORMAT_2_10_10_10 = 0x9, ++ IMG_DATA_FORMAT_8_8_8_8 = 0xa, ++ IMG_DATA_FORMAT_32_32 = 0xb, ++ IMG_DATA_FORMAT_16_16_16_16 = 0xc, ++ IMG_DATA_FORMAT_32_32_32 = 0xd, ++ IMG_DATA_FORMAT_32_32_32_32 = 0xe, ++ IMG_DATA_FORMAT_RESERVED_15 = 0xf, ++ IMG_DATA_FORMAT_5_6_5 = 0x10, ++ IMG_DATA_FORMAT_1_5_5_5 = 0x11, ++ IMG_DATA_FORMAT_5_5_5_1 = 0x12, ++ IMG_DATA_FORMAT_4_4_4_4 = 0x13, ++ IMG_DATA_FORMAT_8_24 = 0x14, ++ IMG_DATA_FORMAT_24_8 = 0x15, ++ IMG_DATA_FORMAT_X24_8_32 = 0x16, ++ IMG_DATA_FORMAT_RESERVED_23 = 0x17, ++ IMG_DATA_FORMAT_RESERVED_24 = 0x18, ++ IMG_DATA_FORMAT_RESERVED_25 = 0x19, ++ IMG_DATA_FORMAT_RESERVED_26 = 0x1a, ++ IMG_DATA_FORMAT_RESERVED_27 = 0x1b, ++ IMG_DATA_FORMAT_RESERVED_28 = 0x1c, ++ IMG_DATA_FORMAT_RESERVED_29 = 0x1d, ++ IMG_DATA_FORMAT_RESERVED_30 = 0x1e, ++ IMG_DATA_FORMAT_RESERVED_31 = 0x1f, ++ IMG_DATA_FORMAT_GB_GR = 0x20, ++ IMG_DATA_FORMAT_BG_RG = 0x21, ++ IMG_DATA_FORMAT_5_9_9_9 = 0x22, ++ IMG_DATA_FORMAT_BC1 = 0x23, ++ IMG_DATA_FORMAT_BC2 = 0x24, ++ IMG_DATA_FORMAT_BC3 = 0x25, ++ IMG_DATA_FORMAT_BC4 = 0x26, ++ IMG_DATA_FORMAT_BC5 = 0x27, ++ IMG_DATA_FORMAT_BC6 = 0x28, ++ IMG_DATA_FORMAT_BC7 = 0x29, ++ IMG_DATA_FORMAT_RESERVED_42 = 0x2a, ++ IMG_DATA_FORMAT_RESERVED_43 = 0x2b, ++ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, ++ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, ++ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, ++ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, ++ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, ++ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, ++ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, ++ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, ++ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, ++ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, ++ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, ++ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, ++ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, ++ IMG_DATA_FORMAT_4_4 = 0x39, ++ IMG_DATA_FORMAT_6_5_5 = 0x3a, ++ IMG_DATA_FORMAT_1 = 0x3b, ++ IMG_DATA_FORMAT_1_REVERSED = 0x3c, ++ IMG_DATA_FORMAT_32_AS_8 = 0x3d, ++ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, ++ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, ++} IMG_DATA_FORMAT; ++typedef enum BUF_NUM_FORMAT { ++ BUF_NUM_FORMAT_UNORM = 0x0, ++ BUF_NUM_FORMAT_SNORM = 0x1, ++ BUF_NUM_FORMAT_USCALED = 0x2, ++ BUF_NUM_FORMAT_SSCALED = 0x3, ++ BUF_NUM_FORMAT_UINT = 0x4, ++ BUF_NUM_FORMAT_SINT = 0x5, ++ BUF_NUM_FORMAT_RESERVED_6 = 0x6, ++ BUF_NUM_FORMAT_FLOAT = 0x7, ++} BUF_NUM_FORMAT; ++typedef enum IMG_NUM_FORMAT { ++ IMG_NUM_FORMAT_UNORM = 0x0, ++ IMG_NUM_FORMAT_SNORM = 0x1, ++ IMG_NUM_FORMAT_USCALED = 0x2, ++ IMG_NUM_FORMAT_SSCALED = 0x3, ++ IMG_NUM_FORMAT_UINT = 0x4, ++ IMG_NUM_FORMAT_SINT = 0x5, ++ IMG_NUM_FORMAT_RESERVED_6 = 0x6, ++ IMG_NUM_FORMAT_FLOAT = 0x7, ++ IMG_NUM_FORMAT_RESERVED_8 = 0x8, ++ IMG_NUM_FORMAT_SRGB = 0x9, ++ IMG_NUM_FORMAT_RESERVED_10 = 0xa, ++ IMG_NUM_FORMAT_RESERVED_11 = 0xb, ++ IMG_NUM_FORMAT_RESERVED_12 = 0xc, ++ IMG_NUM_FORMAT_RESERVED_13 = 0xd, ++ IMG_NUM_FORMAT_RESERVED_14 = 0xe, ++ IMG_NUM_FORMAT_RESERVED_15 = 0xf, ++} IMG_NUM_FORMAT; ++typedef enum TileType { ++ ARRAY_COLOR_TILE = 0x0, ++ ARRAY_DEPTH_TILE = 0x1, ++} TileType; ++typedef enum NonDispTilingOrder { ++ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, ++ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, ++} NonDispTilingOrder; ++typedef enum MicroTileMode { ++ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, ++ ADDR_SURF_THIN_MICRO_TILING = 0x1, ++ ADDR_SURF_DEPTH_MICRO_TILING = 0x2, ++ ADDR_SURF_ROTATED_MICRO_TILING = 0x3, ++ ADDR_SURF_THICK_MICRO_TILING = 0x4, ++} MicroTileMode; ++typedef enum TileSplit { ++ ADDR_SURF_TILE_SPLIT_64B = 0x0, ++ ADDR_SURF_TILE_SPLIT_128B = 0x1, ++ ADDR_SURF_TILE_SPLIT_256B = 0x2, ++ ADDR_SURF_TILE_SPLIT_512B = 0x3, ++ ADDR_SURF_TILE_SPLIT_1KB = 0x4, ++ ADDR_SURF_TILE_SPLIT_2KB = 0x5, ++ ADDR_SURF_TILE_SPLIT_4KB = 0x6, ++} TileSplit; ++typedef enum SampleSplit { ++ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, ++ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, ++ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, ++ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, ++} SampleSplit; ++typedef enum PipeConfig { ++ ADDR_SURF_P2 = 0x0, ++ ADDR_SURF_P2_RESERVED0 = 0x1, ++ ADDR_SURF_P2_RESERVED1 = 0x2, ++ ADDR_SURF_P2_RESERVED2 = 0x3, ++ ADDR_SURF_P4_8x16 = 0x4, ++ ADDR_SURF_P4_16x16 = 0x5, ++ ADDR_SURF_P4_16x32 = 0x6, ++ ADDR_SURF_P4_32x32 = 0x7, ++ ADDR_SURF_P8_16x16_8x16 = 0x8, ++ ADDR_SURF_P8_16x32_8x16 = 0x9, ++ ADDR_SURF_P8_32x32_8x16 = 0xa, ++ ADDR_SURF_P8_16x32_16x16 = 0xb, ++ ADDR_SURF_P8_32x32_16x16 = 0xc, ++ ADDR_SURF_P8_32x32_16x32 = 0xd, ++ ADDR_SURF_P8_32x64_32x32 = 0xe, ++ ADDR_SURF_P8_RESERVED0 = 0xf, ++ ADDR_SURF_P16_32x32_8x16 = 0x10, ++ ADDR_SURF_P16_32x32_16x16 = 0x11, ++} PipeConfig; ++typedef enum NumBanks { ++ ADDR_SURF_2_BANK = 0x0, ++ ADDR_SURF_4_BANK = 0x1, ++ ADDR_SURF_8_BANK = 0x2, ++ ADDR_SURF_16_BANK = 0x3, ++} NumBanks; ++typedef enum BankWidth { ++ ADDR_SURF_BANK_WIDTH_1 = 0x0, ++ ADDR_SURF_BANK_WIDTH_2 = 0x1, ++ ADDR_SURF_BANK_WIDTH_4 = 0x2, ++ ADDR_SURF_BANK_WIDTH_8 = 0x3, ++} BankWidth; ++typedef enum BankHeight { ++ ADDR_SURF_BANK_HEIGHT_1 = 0x0, ++ ADDR_SURF_BANK_HEIGHT_2 = 0x1, ++ ADDR_SURF_BANK_HEIGHT_4 = 0x2, ++ ADDR_SURF_BANK_HEIGHT_8 = 0x3, ++} BankHeight; ++typedef enum BankWidthHeight { ++ ADDR_SURF_BANK_WH_1 = 0x0, ++ ADDR_SURF_BANK_WH_2 = 0x1, ++ ADDR_SURF_BANK_WH_4 = 0x2, ++ ADDR_SURF_BANK_WH_8 = 0x3, ++} BankWidthHeight; ++typedef enum MacroTileAspect { ++ ADDR_SURF_MACRO_ASPECT_1 = 0x0, ++ ADDR_SURF_MACRO_ASPECT_2 = 0x1, ++ ADDR_SURF_MACRO_ASPECT_4 = 0x2, ++ ADDR_SURF_MACRO_ASPECT_8 = 0x3, ++} MacroTileAspect; ++typedef enum GATCL1RequestType { ++ GATCL1_TYPE_NORMAL = 0x0, ++ GATCL1_TYPE_SHOOTDOWN = 0x1, ++ GATCL1_TYPE_BYPASS = 0x2, ++} GATCL1RequestType; ++typedef enum TCC_CACHE_POLICIES { ++ TCC_CACHE_POLICY_LRU = 0x0, ++ TCC_CACHE_POLICY_STREAM = 0x1, ++} TCC_CACHE_POLICIES; ++typedef enum MTYPE { ++ MTYPE_NC_NV = 0x0, ++ MTYPE_NC = 0x1, ++ MTYPE_CC = 0x2, ++ MTYPE_UC = 0x3, ++} MTYPE; ++typedef enum PERFMON_COUNTER_MODE { ++ PERFMON_COUNTER_MODE_ACCUM = 0x0, ++ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, ++ PERFMON_COUNTER_MODE_MAX = 0x2, ++ PERFMON_COUNTER_MODE_DIRTY = 0x3, ++ PERFMON_COUNTER_MODE_SAMPLE = 0x4, ++ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, ++ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, ++ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, ++ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, ++ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, ++ PERFMON_COUNTER_MODE_RESERVED = 0xf, ++} PERFMON_COUNTER_MODE; ++typedef enum PERFMON_SPM_MODE { ++ PERFMON_SPM_MODE_OFF = 0x0, ++ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, ++ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, ++ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, ++ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, ++ PERFMON_SPM_MODE_RESERVED_5 = 0x5, ++ PERFMON_SPM_MODE_RESERVED_6 = 0x6, ++ PERFMON_SPM_MODE_RESERVED_7 = 0x7, ++ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, ++ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, ++ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, ++} PERFMON_SPM_MODE; ++typedef enum SurfaceTiling { ++ ARRAY_LINEAR = 0x0, ++ ARRAY_TILED = 0x1, ++} SurfaceTiling; ++typedef enum SurfaceArray { ++ ARRAY_1D = 0x0, ++ ARRAY_2D = 0x1, ++ ARRAY_3D = 0x2, ++ ARRAY_3D_SLICE = 0x3, ++} SurfaceArray; ++typedef enum ColorArray { ++ ARRAY_2D_ALT_COLOR = 0x0, ++ ARRAY_2D_COLOR = 0x1, ++ ARRAY_3D_SLICE_COLOR = 0x3, ++} ColorArray; ++typedef enum DepthArray { ++ ARRAY_2D_ALT_DEPTH = 0x0, ++ ARRAY_2D_DEPTH = 0x1, ++} DepthArray; ++typedef enum ENUM_NUM_SIMD_PER_CU { ++ NUM_SIMD_PER_CU = 0x4, ++} ENUM_NUM_SIMD_PER_CU; ++typedef enum MEM_PWR_FORCE_CTRL { ++ NO_FORCE_REQUEST = 0x0, ++ FORCE_LIGHT_SLEEP_REQUEST = 0x1, ++ FORCE_DEEP_SLEEP_REQUEST = 0x2, ++ FORCE_SHUT_DOWN_REQUEST = 0x3, ++} MEM_PWR_FORCE_CTRL; ++typedef enum MEM_PWR_FORCE_CTRL2 { ++ NO_FORCE_REQ = 0x0, ++ FORCE_LIGHT_SLEEP_REQ = 0x1, ++} MEM_PWR_FORCE_CTRL2; ++typedef enum MEM_PWR_DIS_CTRL { ++ ENABLE_MEM_PWR_CTRL = 0x0, ++ DISABLE_MEM_PWR_CTRL = 0x1, ++} MEM_PWR_DIS_CTRL; ++typedef enum MEM_PWR_SEL_CTRL { ++ DYNAMIC_SHUT_DOWN_ENABLE = 0x0, ++ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, ++ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, ++} MEM_PWR_SEL_CTRL; ++typedef enum MEM_PWR_SEL_CTRL2 { ++ DYNAMIC_DEEP_SLEEP_EN = 0x0, ++ DYNAMIC_LIGHT_SLEEP_EN = 0x1, ++} MEM_PWR_SEL_CTRL2; ++typedef enum HPD_INT_CONTROL_ACK { ++ HPD_INT_CONTROL_ACK_0 = 0x0, ++ HPD_INT_CONTROL_ACK_1 = 0x1, ++} HPD_INT_CONTROL_ACK; ++typedef enum HPD_INT_CONTROL_POLARITY { ++ HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x0, ++ HPD_INT_CONTROL_GEN_INT_ON_CON = 0x1, ++} HPD_INT_CONTROL_POLARITY; ++typedef enum HPD_INT_CONTROL_RX_INT_ACK { ++ HPD_INT_CONTROL_RX_INT_ACK_0 = 0x0, ++ HPD_INT_CONTROL_RX_INT_ACK_1 = 0x1, ++} HPD_INT_CONTROL_RX_INT_ACK; ++typedef enum DPDBG_EN { ++ DPDBG_DISABLE = 0x0, ++ DPDBG_ENABLE = 0x1, ++} DPDBG_EN; ++typedef enum DPDBG_INPUT_EN { ++ DPDBG_INPUT_DISABLE = 0x0, ++ DPDBG_INPUT_ENABLE = 0x1, ++} DPDBG_INPUT_EN; ++typedef enum DPDBG_ERROR_DETECTION_MODE { ++ DPDBG_ERROR_DETECTION_MODE_CSC = 0x0, ++ DPDBG_ERROR_DETECTION_MODE_RS_ENCODING = 0x1, ++} DPDBG_ERROR_DETECTION_MODE; ++typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK { ++ DPDBG_FIFO_OVERFLOW_INT_DISABLE = 0x0, ++ DPDBG_FIFO_OVERFLOW_INT_ENABLE = 0x1, ++} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK; ++typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE { ++ DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED = 0x0, ++ DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED = 0x1, ++} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE; ++typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK { ++ DPDBG_FIFO_OVERFLOW_INT_NO_ACK = 0x0, ++ DPDBG_FIFO_OVERFLOW_INT_CLEAR = 0x1, ++} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK; ++typedef enum PM_ASSERT_RESET { ++ PM_ASSERT_RESET_0 = 0x0, ++ PM_ASSERT_RESET_1 = 0x1, ++} PM_ASSERT_RESET; ++typedef enum DAC_MUX_SELECT { ++ DAC_MUX_SELECT_DACA = 0x0, ++ DAC_MUX_SELECT_DACB = 0x1, ++} DAC_MUX_SELECT; ++typedef enum TMDS_DVO_MUX_SELECT { ++ TMDS_DVO_MUX_SELECT_B = 0x0, ++ TMDS_DVO_MUX_SELECT_G = 0x1, ++ TMDS_DVO_MUX_SELECT_R = 0x2, ++ TMDS_DVO_MUX_SELECT_RESERVED = 0x3, ++} TMDS_DVO_MUX_SELECT; ++typedef enum DACA_SOFT_RESET { ++ DACA_SOFT_RESET_0 = 0x0, ++ DACA_SOFT_RESET_1 = 0x1, ++} DACA_SOFT_RESET; ++typedef enum I2S0_SPDIF0_SOFT_RESET { ++ I2S0_SPDIF0_SOFT_RESET_0 = 0x0, ++ I2S0_SPDIF0_SOFT_RESET_1 = 0x1, ++} I2S0_SPDIF0_SOFT_RESET; ++typedef enum I2S1_SOFT_RESET { ++ I2S1_SOFT_RESET_0 = 0x0, ++ I2S1_SOFT_RESET_1 = 0x1, ++} I2S1_SOFT_RESET; ++typedef enum SPDIF1_SOFT_RESET { ++ SPDIF1_SOFT_RESET_0 = 0x0, ++ SPDIF1_SOFT_RESET_1 = 0x1, ++} SPDIF1_SOFT_RESET; ++typedef enum DB_CLK_SOFT_RESET { ++ DB_CLK_SOFT_RESET_0 = 0x0, ++ DB_CLK_SOFT_RESET_1 = 0x1, ++} DB_CLK_SOFT_RESET; ++typedef enum FMT0_SOFT_RESET { ++ FMT0_SOFT_RESET_0 = 0x0, ++ FMT0_SOFT_RESET_1 = 0x1, ++} FMT0_SOFT_RESET; ++typedef enum FMT1_SOFT_RESET { ++ FMT1_SOFT_RESET_0 = 0x0, ++ FMT1_SOFT_RESET_1 = 0x1, ++} FMT1_SOFT_RESET; ++typedef enum FMT2_SOFT_RESET { ++ FMT2_SOFT_RESET_0 = 0x0, ++ FMT2_SOFT_RESET_1 = 0x1, ++} FMT2_SOFT_RESET; ++typedef enum FMT3_SOFT_RESET { ++ FMT3_SOFT_RESET_0 = 0x0, ++ FMT3_SOFT_RESET_1 = 0x1, ++} FMT3_SOFT_RESET; ++typedef enum FMT4_SOFT_RESET { ++ FMT4_SOFT_RESET_0 = 0x0, ++ FMT4_SOFT_RESET_1 = 0x1, ++} FMT4_SOFT_RESET; ++typedef enum FMT5_SOFT_RESET { ++ FMT5_SOFT_RESET_0 = 0x0, ++ FMT5_SOFT_RESET_1 = 0x1, ++} FMT5_SOFT_RESET; ++typedef enum MVP_SOFT_RESET { ++ MVP_SOFT_RESET_0 = 0x0, ++ MVP_SOFT_RESET_1 = 0x1, ++} MVP_SOFT_RESET; ++typedef enum ABM_SOFT_RESET { ++ ABM_SOFT_RESET_0 = 0x0, ++ ABM_SOFT_RESET_1 = 0x1, ++} ABM_SOFT_RESET; ++typedef enum DVO_SOFT_RESET { ++ DVO_SOFT_RESET_0 = 0x0, ++ DVO_SOFT_RESET_1 = 0x1, ++} DVO_SOFT_RESET; ++typedef enum DIGA_FE_SOFT_RESET { ++ DIGA_FE_SOFT_RESET_0 = 0x0, ++ DIGA_FE_SOFT_RESET_1 = 0x1, ++} DIGA_FE_SOFT_RESET; ++typedef enum DIGA_BE_SOFT_RESET { ++ DIGA_BE_SOFT_RESET_0 = 0x0, ++ DIGA_BE_SOFT_RESET_1 = 0x1, ++} DIGA_BE_SOFT_RESET; ++typedef enum DIGB_FE_SOFT_RESET { ++ DIGB_FE_SOFT_RESET_0 = 0x0, ++ DIGB_FE_SOFT_RESET_1 = 0x1, ++} DIGB_FE_SOFT_RESET; ++typedef enum DIGB_BE_SOFT_RESET { ++ DIGB_BE_SOFT_RESET_0 = 0x0, ++ DIGB_BE_SOFT_RESET_1 = 0x1, ++} DIGB_BE_SOFT_RESET; ++typedef enum DIGC_FE_SOFT_RESET { ++ DIGC_FE_SOFT_RESET_0 = 0x0, ++ DIGC_FE_SOFT_RESET_1 = 0x1, ++} DIGC_FE_SOFT_RESET; ++typedef enum DIGC_BE_SOFT_RESET { ++ DIGC_BE_SOFT_RESET_0 = 0x0, ++ DIGC_BE_SOFT_RESET_1 = 0x1, ++} DIGC_BE_SOFT_RESET; ++typedef enum DIGD_FE_SOFT_RESET { ++ DIGD_FE_SOFT_RESET_0 = 0x0, ++ DIGD_FE_SOFT_RESET_1 = 0x1, ++} DIGD_FE_SOFT_RESET; ++typedef enum DIGD_BE_SOFT_RESET { ++ DIGD_BE_SOFT_RESET_0 = 0x0, ++ DIGD_BE_SOFT_RESET_1 = 0x1, ++} DIGD_BE_SOFT_RESET; ++typedef enum DIGE_FE_SOFT_RESET { ++ DIGE_FE_SOFT_RESET_0 = 0x0, ++ DIGE_FE_SOFT_RESET_1 = 0x1, ++} DIGE_FE_SOFT_RESET; ++typedef enum DIGE_BE_SOFT_RESET { ++ DIGE_BE_SOFT_RESET_0 = 0x0, ++ DIGE_BE_SOFT_RESET_1 = 0x1, ++} DIGE_BE_SOFT_RESET; ++typedef enum DIGF_FE_SOFT_RESET { ++ DIGF_FE_SOFT_RESET_0 = 0x0, ++ DIGF_FE_SOFT_RESET_1 = 0x1, ++} DIGF_FE_SOFT_RESET; ++typedef enum DIGF_BE_SOFT_RESET { ++ DIGF_BE_SOFT_RESET_0 = 0x0, ++ DIGF_BE_SOFT_RESET_1 = 0x1, ++} DIGF_BE_SOFT_RESET; ++typedef enum DIGG_FE_SOFT_RESET { ++ DIGG_FE_SOFT_RESET_0 = 0x0, ++ DIGG_FE_SOFT_RESET_1 = 0x1, ++} DIGG_FE_SOFT_RESET; ++typedef enum DIGG_BE_SOFT_RESET { ++ DIGG_BE_SOFT_RESET_0 = 0x0, ++ DIGG_BE_SOFT_RESET_1 = 0x1, ++} DIGG_BE_SOFT_RESET; ++typedef enum DPDBG_SOFT_RESET { ++ DPDBG_SOFT_RESET_0 = 0x0, ++ DPDBG_SOFT_RESET_1 = 0x1, ++} DPDBG_SOFT_RESET; ++typedef enum DIGLPA_FE_SOFT_RESET { ++ DIGLPA_FE_SOFT_RESET_0 = 0x0, ++ DIGLPA_FE_SOFT_RESET_1 = 0x1, ++} DIGLPA_FE_SOFT_RESET; ++typedef enum DIGLPA_BE_SOFT_RESET { ++ DIGLPA_BE_SOFT_RESET_0 = 0x0, ++ DIGLPA_BE_SOFT_RESET_1 = 0x1, ++} DIGLPA_BE_SOFT_RESET; ++typedef enum DIGLPB_FE_SOFT_RESET { ++ DIGLPB_FE_SOFT_RESET_0 = 0x0, ++ DIGLPB_FE_SOFT_RESET_1 = 0x1, ++} DIGLPB_FE_SOFT_RESET; ++typedef enum DIGLPB_BE_SOFT_RESET { ++ DIGLPB_BE_SOFT_RESET_0 = 0x0, ++ DIGLPB_BE_SOFT_RESET_1 = 0x1, ++} DIGLPB_BE_SOFT_RESET; ++typedef enum GENERICA_STEREOSYNC_SEL { ++ GENERICA_STEREOSYNC_SEL_D1 = 0x0, ++ GENERICA_STEREOSYNC_SEL_D2 = 0x1, ++ GENERICA_STEREOSYNC_SEL_D3 = 0x2, ++ GENERICA_STEREOSYNC_SEL_D4 = 0x3, ++ GENERICA_STEREOSYNC_SEL_D5 = 0x4, ++ GENERICA_STEREOSYNC_SEL_D6 = 0x5, ++ GENERICA_STEREOSYNC_SEL_RESERVED = 0x6, ++} GENERICA_STEREOSYNC_SEL; ++typedef enum GENERICB_STEREOSYNC_SEL { ++ GENERICB_STEREOSYNC_SEL_D1 = 0x0, ++ GENERICB_STEREOSYNC_SEL_D2 = 0x1, ++ GENERICB_STEREOSYNC_SEL_D3 = 0x2, ++ GENERICB_STEREOSYNC_SEL_D4 = 0x3, ++ GENERICB_STEREOSYNC_SEL_D5 = 0x4, ++ GENERICB_STEREOSYNC_SEL_D6 = 0x5, ++ GENERICB_STEREOSYNC_SEL_RESERVED = 0x6, ++} GENERICB_STEREOSYNC_SEL; ++typedef enum DCO_DBG_BLOCK_SEL { ++ DCO_DBG_BLOCK_SEL_DCO = 0x0, ++ DCO_DBG_BLOCK_SEL_ABM = 0x1, ++ DCO_DBG_BLOCK_SEL_DVO = 0x2, ++ DCO_DBG_BLOCK_SEL_DAC = 0x3, ++ DCO_DBG_BLOCK_SEL_MVP = 0x4, ++ DCO_DBG_BLOCK_SEL_FMT0 = 0x5, ++ DCO_DBG_BLOCK_SEL_FMT1 = 0x6, ++ DCO_DBG_BLOCK_SEL_FMT2 = 0x7, ++ DCO_DBG_BLOCK_SEL_FMT3 = 0x8, ++ DCO_DBG_BLOCK_SEL_FMT4 = 0x9, ++ DCO_DBG_BLOCK_SEL_FMT5 = 0xa, ++ DCO_DBG_BLOCK_SEL_DIGFE_A = 0xb, ++ DCO_DBG_BLOCK_SEL_DIGFE_B = 0xc, ++ DCO_DBG_BLOCK_SEL_DIGFE_C = 0xd, ++ DCO_DBG_BLOCK_SEL_DIGFE_D = 0xe, ++ DCO_DBG_BLOCK_SEL_DIGFE_E = 0xf, ++ DCO_DBG_BLOCK_SEL_DIGFE_F = 0x10, ++ DCO_DBG_BLOCK_SEL_DIGFE_G = 0x11, ++ DCO_DBG_BLOCK_SEL_DIGA = 0x12, ++ DCO_DBG_BLOCK_SEL_DIGB = 0x13, ++ DCO_DBG_BLOCK_SEL_DIGC = 0x14, ++ DCO_DBG_BLOCK_SEL_DIGD = 0x15, ++ DCO_DBG_BLOCK_SEL_DIGE = 0x16, ++ DCO_DBG_BLOCK_SEL_DIGF = 0x17, ++ DCO_DBG_BLOCK_SEL_DIGG = 0x18, ++ DCO_DBG_BLOCK_SEL_DPFE_A = 0x19, ++ DCO_DBG_BLOCK_SEL_DPFE_B = 0x1a, ++ DCO_DBG_BLOCK_SEL_DPFE_C = 0x1b, ++ DCO_DBG_BLOCK_SEL_DPFE_D = 0x1c, ++ DCO_DBG_BLOCK_SEL_DPFE_E = 0x1d, ++ DCO_DBG_BLOCK_SEL_DPFE_F = 0x1e, ++ DCO_DBG_BLOCK_SEL_DPFE_G = 0x1f, ++ DCO_DBG_BLOCK_SEL_DPA = 0x20, ++ DCO_DBG_BLOCK_SEL_DPB = 0x21, ++ DCO_DBG_BLOCK_SEL_DPC = 0x22, ++ DCO_DBG_BLOCK_SEL_DPD = 0x23, ++ DCO_DBG_BLOCK_SEL_DPE = 0x24, ++ DCO_DBG_BLOCK_SEL_DPF = 0x25, ++ DCO_DBG_BLOCK_SEL_DPG = 0x26, ++ DCO_DBG_BLOCK_SEL_AUX0 = 0x27, ++ DCO_DBG_BLOCK_SEL_AUX1 = 0x28, ++ DCO_DBG_BLOCK_SEL_AUX2 = 0x29, ++ DCO_DBG_BLOCK_SEL_AUX3 = 0x2a, ++ DCO_DBG_BLOCK_SEL_AUX4 = 0x2b, ++ DCO_DBG_BLOCK_SEL_AUX5 = 0x2c, ++ DCO_DBG_BLOCK_SEL_PERFMON_DCO = 0x2d, ++ DCO_DBG_BLOCK_SEL_AUDIO_OUT = 0x2e, ++ DCO_DBG_BLOCK_SEL_DIGLPFEA = 0x2f, ++ DCO_DBG_BLOCK_SEL_DIGLPFEB = 0x30, ++ DCO_DBG_BLOCK_SEL_DIGLPA = 0x31, ++ DCO_DBG_BLOCK_SEL_DIGLPB = 0x32, ++ DCO_DBG_BLOCK_SEL_DPLPFEA = 0x33, ++ DCO_DBG_BLOCK_SEL_DPLPFEB = 0x34, ++ DCO_DBG_BLOCK_SEL_DPLPA = 0x35, ++ DCO_DBG_BLOCK_SEL_DPLPB = 0x36, ++} DCO_DBG_BLOCK_SEL; ++typedef enum DCO_DBG_CLOCK_SEL { ++ DCO_DBG_CLOCK_SEL_DISPCLK = 0x0, ++ DCO_DBG_CLOCK_SEL_SCLK = 0x1, ++ DCO_DBG_CLOCK_SEL_MVPCLK = 0x2, ++ DCO_DBG_CLOCK_SEL_DVOCLK = 0x3, ++ DCO_DBG_CLOCK_SEL_DACCLK = 0x4, ++ DCO_DBG_CLOCK_SEL_REFCLK = 0x5, ++ DCO_DBG_CLOCK_SEL_SYMCLKA = 0x6, ++ DCO_DBG_CLOCK_SEL_SYMCLKB = 0x7, ++ DCO_DBG_CLOCK_SEL_SYMCLKC = 0x8, ++ DCO_DBG_CLOCK_SEL_SYMCLKD = 0x9, ++ DCO_DBG_CLOCK_SEL_SYMCLKE = 0xa, ++ DCO_DBG_CLOCK_SEL_SYMCLKF = 0xb, ++ DCO_DBG_CLOCK_SEL_SYMCLKG = 0xc, ++ DCO_DBG_CLOCK_SEL_RESERVED = 0xd, ++ DCO_DBG_CLOCK_SEL_AM0CLK = 0xe, ++ DCO_DBG_CLOCK_SEL_AM1CLK = 0xf, ++ DCO_DBG_CLOCK_SEL_AM2CLK = 0x10, ++ DCO_DBG_CLOCK_SEL_SYMCLKLPA = 0x11, ++ DCO_DBG_CLOCK_SEL_SYMCLKLPB = 0x12, ++} DCO_DBG_CLOCK_SEL; ++typedef enum DOUT_I2C_CONTROL_GO { ++ DOUT_I2C_CONTROL_STOP_TRANSFER = 0x0, ++ DOUT_I2C_CONTROL_START_TRANSFER = 0x1, ++} DOUT_I2C_CONTROL_GO; ++typedef enum DOUT_I2C_CONTROL_SOFT_RESET { ++ DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x0, ++ DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x1, ++} DOUT_I2C_CONTROL_SOFT_RESET; ++typedef enum DOUT_I2C_CONTROL_SEND_RESET { ++ DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x0, ++ DOUT_I2C_CONTROL__SEND_RESET = 0x1, ++} DOUT_I2C_CONTROL_SEND_RESET; ++typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET { ++ DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x0, ++ DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x1, ++} DOUT_I2C_CONTROL_SW_STATUS_RESET; ++typedef enum DOUT_I2C_CONTROL_DDC_SELECT { ++ DOUT_I2C_CONTROL_SELECT_DDC1 = 0x0, ++ DOUT_I2C_CONTROL_SELECT_DDC2 = 0x1, ++ DOUT_I2C_CONTROL_SELECT_DDC3 = 0x2, ++ DOUT_I2C_CONTROL_SELECT_DDC4 = 0x3, ++ DOUT_I2C_CONTROL_SELECT_DDC5 = 0x4, ++ DOUT_I2C_CONTROL_SELECT_DDC6 = 0x5, ++ DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x6, ++} DOUT_I2C_CONTROL_DDC_SELECT; ++typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT { ++ DOUT_I2C_CONTROL_TRANS0 = 0x0, ++ DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x1, ++ DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x2, ++ DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x3, ++} DOUT_I2C_CONTROL_TRANSACTION_COUNT; ++typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL { ++ DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x0, ++ DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x1, ++} DOUT_I2C_CONTROL_DBG_REF_SEL; ++typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY { ++ DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x0, ++ DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x1, ++ DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x2, ++ DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x3, ++} DOUT_I2C_ARBITRATION_SW_PRIORITY; ++typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO { ++ DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x0, ++ DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x1, ++} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO; ++typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER { ++ DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x0, ++ DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x1, ++} DOUT_I2C_ARBITRATION_ABORT_XFER; ++typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ { ++ DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x0, ++ DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x1, ++} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ; ++typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG { ++ DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x0, ++ DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x1, ++} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG; ++typedef enum DOUT_I2C_ACK { ++ DOUT_I2C_NO_ACK = 0x0, ++ DOUT_I2C_ACK_TO_CLEAN = 0x1, ++} DOUT_I2C_ACK; ++typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD { ++ DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x0, ++ DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE= 0x1, ++ DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE= 0x2, ++ DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE= 0x3, ++} DOUT_I2C_DDC_SPEED_THRESHOLD; ++typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN { ++ DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR= 0x0, ++ DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x1, ++} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN; ++typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL { ++ DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x0, ++ DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x1, ++} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL; ++typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE { ++ DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x0, ++ DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x1, ++} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE; ++typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN { ++ DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR= 0x0, ++ DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x1, ++} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN; ++typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK { ++ DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x0, ++ DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x1, ++} DOUT_I2C_TRANSACTION_STOP_ON_NACK; ++typedef enum DOUT_I2C_DATA_INDEX_WRITE { ++ DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x0, ++ DOUT_I2C_DATA__INDEX_WRITE = 0x1, ++} DOUT_I2C_DATA_INDEX_WRITE; ++typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET { ++ DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x0, ++ DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x1, ++} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET; ++typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE { ++ DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x0, ++ DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x1, ++} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE; ++typedef enum BLNDV_CONTROL_BLND_MODE { ++ BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x0, ++ BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x1, ++ BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x2, ++ BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x3, ++} BLNDV_CONTROL_BLND_MODE; ++typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE { ++ BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0, ++ BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1, ++ BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2, ++ BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x3, ++} BLNDV_CONTROL_BLND_STEREO_TYPE; ++typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY { ++ BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0x0, ++ BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x1, ++} BLNDV_CONTROL_BLND_STEREO_POLARITY; ++typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN { ++ BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x0, ++ BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x1, ++} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN; ++typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE { ++ BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA= 0x0, ++ BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1, ++ BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x2, ++ BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x3, ++} BLNDV_CONTROL_BLND_ALPHA_MODE; ++typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE { ++ BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x0, ++ BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x1, ++} BLNDV_CONTROL_BLND_MULTIPLIED_MODE; ++typedef enum BLNDV_SM_CONTROL2_SM_MODE { ++ BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x0, ++ BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x2, ++ BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x4, ++ BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6, ++} BLNDV_SM_CONTROL2_SM_MODE; ++typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE { ++ BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x0, ++ BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x1, ++} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE; ++typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE { ++ BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x0, ++ BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x1, ++} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE; ++typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL { ++ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0, ++ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1, ++ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2, ++ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3, ++} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL; ++typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL { ++ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0, ++ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1, ++ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW= 0x2, ++ BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3, ++} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL; ++typedef enum BLNDV_CONTROL2_PTI_ENABLE { ++ BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0x0, ++ BLNDV_CONTROL2_PTI_ENABLE_TRUE = 0x1, ++} BLNDV_CONTROL2_PTI_ENABLE; ++typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN { ++ BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x0, ++ BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x1, ++} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN; ++typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN { ++ BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x0, ++ BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x1, ++} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN; ++typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK { ++ BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0, ++ BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1, ++} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK; ++typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK { ++ BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0, ++ BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1, ++} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK; ++typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK { ++ BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0, ++ BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1, ++} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK; ++typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK { ++ BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0, ++ BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1, ++} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; ++typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK { ++ BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0, ++ BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1, ++} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK; ++typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK { ++ BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0, ++ BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1, ++} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK; ++typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK { ++ BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0, ++ BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x1, ++} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK; ++typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK { ++ BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE= 0x0, ++ BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1, ++} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK; ++typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE { ++ BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE= 0x0, ++ BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1, ++} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE; ++typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT { ++ BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x0, ++ BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x1, ++} BLNDV_DEBUG_BLND_CNV_MUX_SELECT; ++typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN { ++ BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0, ++ BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1, ++} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN; ++ ++#endif /* DCE_11_0_ENUM_H */ +diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h +new file mode 100644 +index 0000000..a438c2b +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h +@@ -0,0 +1,17557 @@ ++/* ++ * DCE_11_0 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef DCE_11_0_SH_MASK_H ++#define DCE_11_0_SH_MASK_H ++ ++#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1 ++#define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0 ++#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1 ++#define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0 ++#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff ++#define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0 ++#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000 ++#define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18 ++#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 ++#define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c ++#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000 ++#define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d ++#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000 ++#define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e ++#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1 ++#define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0 ++#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1 ++#define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0 ++#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff ++#define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0 ++#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000 ++#define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18 ++#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000 ++#define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c ++#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000 ++#define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d ++#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000 ++#define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e ++#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1 ++#define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0 ++#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1 ++#define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0 ++#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff ++#define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0 ++#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000 ++#define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18 ++#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000 ++#define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c ++#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000 ++#define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d ++#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000 ++#define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e ++#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON_MASK 0x1 ++#define DCFEV0_PG_CONFIG__DCFEV0_POWER_FORCEON__SHIFT 0x0 ++#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE_MASK 0x1 ++#define DCFEV0_PG_ENABLE__DCFEV0_POWER_GATE__SHIFT 0x0 ++#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_READ_DATA_MASK 0xffffff ++#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_READ_DATA__SHIFT 0x0 ++#define DCFEV0_PG_STATUS__DCFEV0_DEBUG_PWR_STATUS_MASK 0x3000000 ++#define DCFEV0_PG_STATUS__DCFEV0_DEBUG_PWR_STATUS__SHIFT 0x18 ++#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE_MASK 0x10000000 ++#define DCFEV0_PG_STATUS__DCFEV0_DESIRED_PWR_STATE__SHIFT 0x1c ++#define DCFEV0_PG_STATUS__DCFEV0_REQUESTED_PWR_STATE_MASK 0x20000000 ++#define DCFEV0_PG_STATUS__DCFEV0_REQUESTED_PWR_STATE__SHIFT 0x1d ++#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS_MASK 0xc0000000 ++#define DCFEV0_PG_STATUS__DCFEV0_PGFSM_PWR_STATUS__SHIFT 0x1e ++#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1 ++#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0 ++#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x2 ++#define DCPG_INTERRUPT_STATUS__DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 ++#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED_MASK 0x4 ++#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x2 ++#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x8 ++#define DCPG_INTERRUPT_STATUS__DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 ++#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED_MASK 0x10 ++#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x4 ++#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x20 ++#define DCPG_INTERRUPT_STATUS__DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 ++#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED_MASK 0x40 ++#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x6 ++#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x80 ++#define DCPG_INTERRUPT_STATUS__DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 ++#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED_MASK 0x100 ++#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x8 ++#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x200 ++#define DCPG_INTERRUPT_STATUS__DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 ++#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED_MASK 0x400 ++#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0xa ++#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800 ++#define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb ++#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x1000 ++#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0xc ++#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x2000 ++#define DCPG_INTERRUPT_STATUS__DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0xd ++#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED_MASK 0x4000 ++#define DCPG_INTERRUPT_STATUS__DSI_POWER_UP_INT_OCCURRED__SHIFT 0xe ++#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED_MASK 0x8000 ++#define DCPG_INTERRUPT_STATUS__DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0xf ++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK_MASK 0x1 ++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_MASK__SHIFT 0x0 ++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR_MASK 0x2 ++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x1 ++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK_MASK 0x4 ++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x2 ++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x8 ++#define DCPG_INTERRUPT_CONTROL__DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x3 ++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK_MASK 0x10 ++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK__SHIFT 0x4 ++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR_MASK 0x20 ++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x5 ++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK_MASK 0x40 ++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x6 ++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80 ++#define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x7 ++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK_MASK 0x100 ++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_MASK__SHIFT 0x8 ++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR_MASK 0x200 ++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x9 ++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK_MASK 0x400 ++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_MASK__SHIFT 0xa ++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x800 ++#define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0xb ++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK_MASK 0x1000 ++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_MASK__SHIFT 0xc ++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR_MASK 0x2000 ++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xd ++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK_MASK 0x4000 ++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_MASK__SHIFT 0xe ++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x8000 ++#define DCPG_INTERRUPT_CONTROL__DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0xf ++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK_MASK 0x10000 ++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK__SHIFT 0x10 ++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR_MASK 0x20000 ++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x11 ++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK_MASK 0x40000 ++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x12 ++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x80000 ++#define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x13 ++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK_MASK 0x100000 ++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_MASK__SHIFT 0x14 ++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR_MASK 0x200000 ++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x15 ++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK_MASK 0x400000 ++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x16 ++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000 ++#define DCPG_INTERRUPT_CONTROL__DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 ++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK_MASK 0x1000000 ++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_MASK__SHIFT 0x18 ++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR_MASK 0x2000000 ++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x19 ++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK_MASK 0x4000000 ++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_MASK__SHIFT 0x1a ++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x8000000 ++#define DCPG_INTERRUPT_CONTROL__DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x1b ++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK_MASK 0x10000000 ++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_MASK__SHIFT 0x1c ++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR_MASK 0x20000000 ++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_UP_INT_CLEAR__SHIFT 0x1d ++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK_MASK 0x40000000 ++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_MASK__SHIFT 0x1e ++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR_MASK 0x80000000 ++#define DCPG_INTERRUPT_CONTROL__DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x1f ++#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1 ++#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 ++#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff ++#define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0 ++#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff ++#define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0 ++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1 ++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0 ++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2 ++#define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1 ++#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4 ++#define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2 ++#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000 ++#define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10 ++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff ++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0 ++#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff ++#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 ++#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff ++#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 ++#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff ++#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 ++#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff ++#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 ++#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff ++#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 ++#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff ++#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 ++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1 ++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 ++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2 ++#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 ++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4 ++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 ++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8 ++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 ++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000 ++#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 ++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1 ++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 ++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 ++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 ++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 ++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 ++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 ++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 ++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 ++#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f ++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1 ++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 ++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100 ++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 ++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000 ++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 ++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000 ++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 ++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 ++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 ++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 ++#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f ++#define DC_ABM1_CNTL__ABM1_EN_MASK 0x1 ++#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 ++#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700 ++#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 ++#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000 ++#define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f ++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf ++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 ++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00 ++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 ++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000 ++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 ++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 ++#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f ++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff ++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 ++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000 ++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 ++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000 ++#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f ++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff ++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 ++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000 ++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 ++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000 ++#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f ++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff ++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 ++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000 ++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 ++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000 ++#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f ++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff ++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 ++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000 ++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 ++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000 ++#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f ++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff ++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 ++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000 ++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 ++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000 ++#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f ++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff ++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 ++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000 ++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 ++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000 ++#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f ++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff ++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 ++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000 ++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 ++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000 ++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c ++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000 ++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d ++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000 ++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e ++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000 ++#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f ++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1 ++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 ++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100 ++#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 ++#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1 ++#define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0 ++#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100 ++#define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8 ++#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000 ++#define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000 ++#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f ++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc ++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c ++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d ++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e ++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 ++#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f ++#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff ++#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 ++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff ++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 ++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000 ++#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 ++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff ++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 ++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000 ++#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 ++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff ++#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 ++#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff ++#define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0 ++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff ++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 ++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000 ++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 ++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000 ++#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f ++#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff ++#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 ++#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff ++#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 ++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1 ++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 ++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 ++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 ++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 ++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 ++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 ++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 ++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 ++#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f ++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1 ++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 ++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 ++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 ++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 ++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 ++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 ++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 ++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 ++#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f ++#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff ++#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 ++#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff ++#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 ++#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff ++#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 ++#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff ++#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 ++#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff ++#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 ++#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff ++#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 ++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff ++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0 ++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00 ++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa ++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000 ++#define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14 ++#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000 ++#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f ++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff ++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff ++#define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0 ++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff ++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0 ++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000 ++#define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10 ++#define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff ++#define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0 ++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff ++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0 ++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000 ++#define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10 ++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff ++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0 ++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000 ++#define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10 ++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1 ++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0 ++#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000 ++#define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10 ++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000 ++#define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11 ++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff ++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0 ++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000 ++#define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10 ++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1 ++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0 ++#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000 ++#define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10 ++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000 ++#define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11 ++#define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x3fff ++#define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0 ++#define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000 ++#define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10 ++#define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff ++#define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0 ++#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff ++#define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0 ++#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff ++#define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0 ++#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000 ++#define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10 ++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1 ++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0 ++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10 ++#define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4 ++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100 ++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8 ++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000 ++#define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc ++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000 ++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf ++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000 ++#define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 ++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1 ++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 ++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10 ++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 ++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100 ++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 ++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000 ++#define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc ++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1 ++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0 ++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10 ++#define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 ++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff ++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0 ++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000 ++#define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10 ++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff ++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0 ++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000 ++#define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10 ++#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1 ++#define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0 ++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff ++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0 ++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000 ++#define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10 ++#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1 ++#define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0 ++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1 ++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0 ++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e ++#define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1 ++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff ++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0 ++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000 ++#define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000 ++#define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f ++#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1 ++#define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000 ++#define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f ++#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1 ++#define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0 ++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3 ++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0 ++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10 ++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 ++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100 ++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 ++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000 ++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 ++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000 ++#define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 ++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f ++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 ++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100 ++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8 ++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000 ++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 ++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000 ++#define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 ++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3 ++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 ++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00 ++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8 ++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000 ++#define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10 ++#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff ++#define CRTC_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0 ++#define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1 ++#define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0 ++#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10 ++#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4 ++#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300 ++#define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8 ++#define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000 ++#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc ++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000 ++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd ++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000 ++#define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe ++#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000 ++#define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10 ++#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000 ++#define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14 ++#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000 ++#define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 ++#define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000 ++#define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d ++#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000 ++#define CRTC_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e ++#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000 ++#define CRTC_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f ++#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1 ++#define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0 ++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100 ++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8 ++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000 ++#define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10 ++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1 ++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0 ++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000 ++#define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 ++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1 ++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0 ++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2 ++#define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1 ++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1 ++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 ++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2 ++#define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1 ++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff ++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0 ++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000 ++#define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10 ++#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff ++#define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0 ++#define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1 ++#define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0 ++#define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2 ++#define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1 ++#define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4 ++#define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2 ++#define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8 ++#define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3 ++#define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10 ++#define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4 ++#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20 ++#define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5 ++#define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000 ++#define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10 ++#define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000 ++#define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11 ++#define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000 ++#define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12 ++#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff ++#define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0 ++#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000 ++#define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10 ++#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff ++#define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0 ++#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff ++#define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0 ++#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff ++#define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0 ++#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff ++#define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0 ++#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1 ++#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0 ++#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e ++#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1 ++#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1 ++#define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0 ++#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1 ++#define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 ++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1 ++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 ++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100 ++#define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 ++#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000 ++#define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 ++#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1 ++#define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0 ++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100 ++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8 ++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000 ++#define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10 ++#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000 ++#define CRTC_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14 ++#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000 ++#define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 ++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff ++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 ++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000 ++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf ++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000 ++#define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10 ++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000 ++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 ++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000 ++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 ++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000 ++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13 ++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000 ++#define CRTC_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 ++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000 ++#define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18 ++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1 ++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0 ++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2 ++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1 ++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4 ++#define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 ++#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3 ++#define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 ++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff ++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0 ++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000 ++#define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 ++#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff ++#define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 ++#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1 ++#define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0 ++#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x2 ++#define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1 ++#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x4 ++#define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2 ++#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100 ++#define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8 ++#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000 ++#define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc ++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1 ++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0 ++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2 ++#define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1 ++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10 ++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4 ++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20 ++#define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5 ++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100 ++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 ++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200 ++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 ++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000 ++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 ++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000 ++#define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 ++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000 ++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18 ++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000 ++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19 ++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000 ++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a ++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000 ++#define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b ++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000 ++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c ++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000 ++#define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d ++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000 ++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e ++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000 ++#define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f ++#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1 ++#define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0 ++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1 ++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0 ++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100 ++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8 ++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000 ++#define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 ++#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1 ++#define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0 ++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1 ++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0 ++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700 ++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8 ++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000 ++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 ++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000 ++#define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 ++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf ++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0 ++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0 ++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4 ++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00 ++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8 ++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000 ++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc ++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000 ++#define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 ++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff ++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0 ++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000 ++#define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10 ++#define CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1 ++#define CRTC_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0 ++#define CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100 ++#define CRTC_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8 ++#define CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x10000 ++#define CRTC_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10 ++#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7 ++#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0 ++#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000 ++#define CRTC_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10 ++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3 ++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0 ++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00 ++#define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8 ++#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff ++#define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0 ++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1 ++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0 ++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10 ++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4 ++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000 ++#define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10 ++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000 ++#define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14 ++#define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1 ++#define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0 ++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff ++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0 ++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000 ++#define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10 ++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1 ++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0 ++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100 ++#define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8 ++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff ++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0 ++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00 ++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa ++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000 ++#define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14 ++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3 ++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0 ++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300 ++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8 ++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000 ++#define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10 ++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff ++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 ++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00 ++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa ++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000 ++#define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 ++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3 ++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 ++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300 ++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 ++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000 ++#define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 ++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff ++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0 ++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00 ++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa ++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000 ++#define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14 ++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3 ++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 ++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300 ++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 ++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000 ++#define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 ++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff ++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 ++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000 ++#define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 ++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10 ++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 ++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100 ++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 ++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000 ++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc ++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000 ++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 ++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000 ++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 ++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000 ++#define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 ++#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff ++#define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 ++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100 ++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 ++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000 ++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc ++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000 ++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 ++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000 ++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 ++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000 ++#define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 ++#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff ++#define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 ++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100 ++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 ++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000 ++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc ++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000 ++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 ++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000 ++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 ++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000 ++#define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 ++#define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1 ++#define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0 ++#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10 ++#define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4 ++#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300 ++#define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8 ++#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000 ++#define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc ++#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 ++#define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 ++#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000 ++#define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14 ++#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000 ++#define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18 ++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff ++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0 ++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000 ++#define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10 ++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff ++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0 ++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000 ++#define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10 ++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff ++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0 ++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000 ++#define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10 ++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff ++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0 ++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000 ++#define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10 ++#define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff ++#define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 ++#define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000 ++#define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 ++#define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff ++#define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 ++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff ++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0 ++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000 ++#define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10 ++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff ++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0 ++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000 ++#define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10 ++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff ++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0 ++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000 ++#define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10 ++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff ++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0 ++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000 ++#define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10 ++#define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff ++#define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 ++#define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000 ++#define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 ++#define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff ++#define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000 ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000 ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18 ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000 ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19 ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000 ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000 ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000 ++#define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1 ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0 ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10 ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4 ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300 ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000 ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000 ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000 ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000 ++#define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000 ++#define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18 ++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff ++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0 ++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000 ++#define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10 ++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff ++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0 ++#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000 ++#define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10 ++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000 ++#define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c ++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff ++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff ++#define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0 ++#define DAC_ENABLE__DAC_ENABLE_MASK 0x1 ++#define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0 ++#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2 ++#define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1 ++#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc ++#define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2 ++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10 ++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4 ++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20 ++#define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5 ++#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100 ++#define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8 ++#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7 ++#define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0 ++#define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8 ++#define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3 ++#define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1 ++#define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0 ++#define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000 ++#define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10 ++#define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1 ++#define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0 ++#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB_MASK 0x100 ++#define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKB__SHIFT 0x8 ++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff ++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0 ++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00 ++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa ++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000 ++#define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14 ++#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f ++#define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0 ++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff ++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0 ++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00 ++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa ++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000 ++#define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14 ++#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f ++#define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0 ++#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1 ++#define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0 ++#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100 ++#define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8 ++#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000 ++#define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10 ++#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7 ++#define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0 ++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3 ++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0 ++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00 ++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8 ++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000 ++#define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10 ++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff ++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0 ++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100 ++#define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8 ++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff ++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0 ++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00 ++#define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8 ++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1 ++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0 ++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10 ++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4 ++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300 ++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8 ++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000 ++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10 ++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000 ++#define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18 ++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1 ++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0 ++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000 ++#define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10 ++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1 ++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0 ++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700 ++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8 ++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY_MASK 0x1000000 ++#define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKB_ONLY__SHIFT 0x18 ++#define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff ++#define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0 ++#define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1 ++#define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0 ++#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100 ++#define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8 ++#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000 ++#define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10 ++#define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000 ++#define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18 ++#define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1 ++#define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0 ++#define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100 ++#define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8 ++#define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000 ++#define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10 ++#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1 ++#define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0 ++#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100 ++#define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8 ++#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000 ++#define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10 ++#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000 ++#define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11 ++#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000 ++#define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12 ++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1 ++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0 ++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2 ++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1 ++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4 ++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2 ++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8 ++#define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3 ++#define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3 ++#define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0 ++#define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000 ++#define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10 ++#define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff ++#define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0 ++#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 ++#define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 ++#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc ++#define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 ++#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 ++#define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa ++#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 ++#define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 ++#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 ++#define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16 ++#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000 ++#define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d ++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 ++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e ++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 ++#define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f ++#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX_MASK 0xff ++#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DAC_TEST_DEBUG_INDEX__DAC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DAC_TEST_DEBUG_DATA__DAC_TEST_DEBUG_DATA__SHIFT 0x0 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff ++#define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0xe00 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc ++#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe ++#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf ++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK 0x4000000 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT 0x1a ++#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x8000000 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x1b ++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000 ++#define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3 ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30 ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300 ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000 ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000 ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000 ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000 ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000 ++#define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000 ++#define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e ++#define PERFMON_CNTL__PERFMON_STATE_MASK 0x3 ++#define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 ++#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xfc ++#define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x2 ++#define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00 ++#define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 ++#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000 ++#define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c ++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000 ++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d ++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000 ++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e ++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000 ++#define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f ++#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x1 ++#define PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 ++#define PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x2 ++#define PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000 ++#define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf ++#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000 ++#define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 ++#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff ++#define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 ++#define PERFMON_HI__PERFMON_HI_MASK 0xffff ++#define PERFMON_HI__PERFMON_HI__SHIFT 0x0 ++#define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000 ++#define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d ++#define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff ++#define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 ++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff ++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff ++#define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0 ++#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x1 ++#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0 ++#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x2 ++#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1 ++#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY_MASK 0xf ++#define DCCG_CBUS_WRCMD_DELAY__CBUS_PLL_WRCMD_DELAY__SHIFT 0x0 ++#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7 ++#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 ++#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE_MASK 0x100 ++#define DPREFCLK_CNTL__UNB_DB_CLK_ENABLE__SHIFT 0x8 ++#define DCE_VERSION__MAJOR_VERSION_MASK 0xff ++#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0 ++#define DCE_VERSION__MINOR_VERSION_MASK 0xff00 ++#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8 ++#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE_MASK 0xffffffff ++#define AVSYNC_COUNTER_WRITE__AVSYNC_COUNTER_WRVALUE__SHIFT 0x0 ++#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE_MASK 0x1 ++#define AVSYNC_COUNTER_CONTROL__AVSYNC_COUNTER_ENABLE__SHIFT 0x0 ++#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE_MASK 0xffffffff ++#define AVSYNC_COUNTER_READ__AVSYNC_COUNTER_RDVALUE__SHIFT 0x0 ++#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1 ++#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 ++#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff ++#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 ++#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff ++#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 ++#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff ++#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 ++#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff ++#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 ++#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff ++#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 ++#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1 ++#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 ++#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100 ++#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 ++#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200 ++#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 ++#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000 ++#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 ++#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000 ++#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 ++#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000 ++#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 ++#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff ++#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000 ++#define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18 ++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1 ++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 ++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000 ++#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 ++#define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1 ++#define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0 ++#define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2 ++#define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1 ++#define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4 ++#define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2 ++#define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8 ++#define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3 ++#define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10 ++#define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4 ++#define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20 ++#define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5 ++#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI_MASK 0x40 ++#define SMU_CONTROL__DISPLAY_V0_FORCE_VBI__SHIFT 0x6 ++#define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000 ++#define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10 ++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1 ++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 ++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10 ++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 ++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 ++#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 ++#define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1 ++#define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0 ++#define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10 ++#define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4 ++#define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1 ++#define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0 ++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1 ++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 ++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2 ++#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 ++#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4 ++#define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2 ++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8 ++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 ++#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10 ++#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 ++#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20 ++#define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5 ++#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40 ++#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 ++#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE_MASK 0x80 ++#define DCCG_GATE_DISABLE_CNTL__DPDBG_CLK_GATE_DISABLE__SHIFT 0x7 ++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x100 ++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 ++#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000 ++#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 ++#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000 ++#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 ++#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000 ++#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 ++#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000 ++#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15 ++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000 ++#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 ++#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE_MASK 0x800000 ++#define DCCG_GATE_DISABLE_CNTL__UNB_DB_CLK_GATE_DISABLE__SHIFT 0x17 ++#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x4000000 ++#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a ++#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x8000000 ++#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b ++#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000 ++#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c ++#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000 ++#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d ++#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000 ++#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x1 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x2 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x4 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x8 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x10 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x20 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x40 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE_MASK 0x100 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_FE_GATE_DISABLE__SHIFT 0x8 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE_MASK 0x200 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_FE_GATE_DISABLE__SHIFT 0x9 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x10000 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x20000 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x40000 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x80000 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x100000 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x200000 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x400000 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE_MASK 0x1000000 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPA_GATE_DISABLE__SHIFT 0x18 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE_MASK 0x2000000 ++#define DCCG_GATE_DISABLE_CNTL2__SYMCLKLPB_GATE_DISABLE__SHIFT 0x19 ++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf ++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 ++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0 ++#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 ++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf ++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0 ++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0 ++#define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4 ++#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000 ++#define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc ++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0xf ++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 ++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0xff0 ++#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 ++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0xf ++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 ++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0xff0 ++#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 ++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0xf ++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0 ++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0xff0 ++#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4 ++#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff ++#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 ++#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1 ++#define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0 ++#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30 ++#define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4 ++#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1 ++#define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0 ++#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30 ++#define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4 ++#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1 ++#define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0 ++#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30 ++#define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4 ++#define PHYPLL_PIXCLK_CNTL__PHYPLL_PIXCLK_RESYNC_ENABLE_MASK 0x1 ++#define PHYPLL_PIXCLK_CNTL__PHYPLL_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 ++#define PHYPLL_PIXCLK_CNTL__DCCG_DEEP_COLOR_CNTL_PHYPLL_PIXCLK_MASK 0x30 ++#define PHYPLL_PIXCLK_CNTL__DCCG_DEEP_COLOR_CNTL_PHYPLL_PIXCLK__SHIFT 0x4 ++#define PHYPLL_PIXCLK_CNTL__PIXEL_RATE_PHYPLL_SEL_MASK 0x100 ++#define PHYPLL_PIXCLK_CNTL__PIXEL_RATE_PHYPLL_SEL__SHIFT 0x8 ++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f ++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 ++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00 ++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 ++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000 ++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 ++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000 ++#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 ++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 ++#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 ++#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100 ++#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 ++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff ++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 ++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 ++#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 ++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff ++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 ++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000 ++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 ++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000 ++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 ++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000 ++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 ++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000 ++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c ++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000 ++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d ++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000 ++#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e ++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000 ++#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f ++#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x1 ++#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800 ++#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb ++#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x1 ++#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 ++#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x2 ++#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 ++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3 ++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0 ++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10 ++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 ++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20 ++#define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 ++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100 ++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8 ++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200 ++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9 ++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000 ++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe ++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000 ++#define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10 ++#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff ++#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 ++#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff ++#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 ++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3 ++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0 ++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10 ++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 ++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20 ++#define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 ++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100 ++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8 ++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200 ++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9 ++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000 ++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe ++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000 ++#define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10 ++#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff ++#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 ++#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff ++#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 ++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3 ++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0 ++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10 ++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 ++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20 ++#define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 ++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100 ++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8 ++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200 ++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9 ++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000 ++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe ++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000 ++#define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10 ++#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff ++#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 ++#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff ++#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 ++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3 ++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0 ++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10 ++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 ++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20 ++#define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 ++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100 ++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8 ++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200 ++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9 ++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000 ++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe ++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000 ++#define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10 ++#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff ++#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 ++#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff ++#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 ++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3 ++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0 ++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10 ++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4 ++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20 ++#define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5 ++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100 ++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8 ++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200 ++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9 ++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000 ++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe ++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000 ++#define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10 ++#define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff ++#define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0 ++#define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff ++#define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0 ++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3 ++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0 ++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10 ++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4 ++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20 ++#define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5 ++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100 ++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8 ++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200 ++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9 ++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000 ++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe ++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000 ++#define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10 ++#define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff ++#define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0 ++#define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff ++#define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0 ++#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE_MASK 0x3 ++#define DCFEV0_CRTC_PIXEL_RATE_CNTL__DCFEV0_CRTC_PIXEL_RATE_SOURCE__SHIFT 0x0 ++#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1 ++#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 ++#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x2 ++#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1 ++#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4 ++#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 ++#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8 ++#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 ++#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10 ++#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 ++#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100 ++#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 ++#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000 ++#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc ++#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000 ++#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd ++#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x4000 ++#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe ++#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x8000 ++#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf ++#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x10000 ++#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 ++#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x20000 ++#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 ++#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x40000 ++#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 ++#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x80000 ++#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 ++#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x100000 ++#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 ++#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x200000 ++#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 ++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1 ++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 ++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10 ++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 ++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700 ++#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 ++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1 ++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 ++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10 ++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 ++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700 ++#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 ++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1 ++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 ++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10 ++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 ++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700 ++#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 ++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1 ++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 ++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10 ++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 ++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700 ++#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 ++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1 ++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 ++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10 ++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 ++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700 ++#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 ++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1 ++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0 ++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10 ++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4 ++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700 ++#define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8 ++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x1 ++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0 ++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x10 ++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4 ++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x700 ++#define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8 ++#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN_MASK 0x10 ++#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_EN__SHIFT 0x4 ++#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC_MASK 0x700 ++#define DPDBG_CLK_FORCE_CONTROL__DPDBG_CLK_FORCE_SRC__SHIFT 0x8 ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7 ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30 ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000 ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000 ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10 ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000 ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000 ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000 ++#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c ++#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff ++#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 ++#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff ++#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 ++#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff ++#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 ++#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff ++#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 ++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff ++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0 ++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff ++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 ++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000 ++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc ++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000 ++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 ++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000 ++#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c ++#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define CPLL_MACRO_CNTL_RESERVED0__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define CPLL_MACRO_CNTL_RESERVED1__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define CPLL_MACRO_CNTL_RESERVED2__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define CPLL_MACRO_CNTL_RESERVED3__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define CPLL_MACRO_CNTL_RESERVED4__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define CPLL_MACRO_CNTL_RESERVED5__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define CPLL_MACRO_CNTL_RESERVED6__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define CPLL_MACRO_CNTL_RESERVED7__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define CPLL_MACRO_CNTL_RESERVED8__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define CPLL_MACRO_CNTL_RESERVED9__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define CPLL_MACRO_CNTL_RESERVED10__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define CPLL_MACRO_CNTL_RESERVED11__CPLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f ++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf ++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000 ++#define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18 ++#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff ++#define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0 ++#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff ++#define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0 ++#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff ++#define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0 ++#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff ++#define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0 ++#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL_MASK 0xffffffff ++#define DCDEBUG_BUS_CLK5_SEL__DCDEBUG_BUS_CLK5_SEL__SHIFT 0x0 ++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x1f ++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0 ++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x3e0 ++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x5 ++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000 ++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc ++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf8000 ++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0xf ++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000 ++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14 ++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000 ++#define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c ++#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f ++#define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0 ++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x800000 ++#define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x17 ++#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL_MASK 0x1f000000 ++#define DCDEBUG_OUT_CNTL__DCDEBUG_CLK_SEL__SHIFT 0x18 ++#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff ++#define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0 ++#define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 ++#define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 ++#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 ++#define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 ++#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 ++#define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 ++#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 ++#define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc ++#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 ++#define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 ++#define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 ++#define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c ++#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 ++#define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e ++#define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3 ++#define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0 ++#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4 ++#define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2 ++#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10 ++#define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4 ++#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700 ++#define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8 ++#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800 ++#define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN__SHIFT 0xb ++#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000 ++#define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc ++#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000 ++#define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10 ++#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000 ++#define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18 ++#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000 ++#define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d ++#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0xff ++#define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0 ++#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0xff00 ++#define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8 ++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000 ++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10 ++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000 ++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11 ++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0xf00000 ++#define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14 ++#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0xf000000 ++#define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18 ++#define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000 ++#define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c ++#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT_MASK 0x60000000 ++#define DMIF_STATUS__DMIF_MC_LATENCY_TAP_POINT__SHIFT 0x1d ++#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE_MASK 0x80000000 ++#define DMIF_STATUS__DMIF_MC_LATENCY_REQ_TYPE__SHIFT 0x1f ++#define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff ++#define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0 ++#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff ++#define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0 ++#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000 ++#define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10 ++#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff ++#define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 ++#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff ++#define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 ++#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff ++#define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 ++#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff ++#define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 ++#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff ++#define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 ++#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff ++#define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 ++#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff ++#define PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 ++#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff ++#define PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 ++#define DMIF_P_VMID__P_VMID_PIPE0_MASK 0xf ++#define DMIF_P_VMID__P_VMID_PIPE0__SHIFT 0x0 ++#define DMIF_P_VMID__P_VMID_PIPE1_MASK 0xf0 ++#define DMIF_P_VMID__P_VMID_PIPE1__SHIFT 0x4 ++#define DMIF_P_VMID__P_VMID_PIPE2_MASK 0xf00 ++#define DMIF_P_VMID__P_VMID_PIPE2__SHIFT 0x8 ++#define DMIF_P_VMID__P_VMID_PIPE3_MASK 0xf000 ++#define DMIF_P_VMID__P_VMID_PIPE3__SHIFT 0xc ++#define DMIF_P_VMID__P_VMID_PIPE4_MASK 0xf0000 ++#define DMIF_P_VMID__P_VMID_PIPE4__SHIFT 0x10 ++#define DMIF_P_VMID__P_VMID_PIPE5_MASK 0xf00000 ++#define DMIF_P_VMID__P_VMID_PIPE5__SHIFT 0x14 ++#define DMIF_P_VMID__P_VMID_PIPE6_MASK 0xf000000 ++#define DMIF_P_VMID__P_VMID_PIPE6__SHIFT 0x18 ++#define DMIF_P_VMID__P_VMID_PIPE7_MASK 0xf0000000 ++#define DMIF_P_VMID__P_VMID_PIPE7__SHIFT 0x1c ++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN_MASK 0x1 ++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_EN__SHIFT 0x0 ++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL_MASK 0xf0 ++#define DMIF_URG_OVERRIDE__DMIF_URG_OVERRIDE_LEVEL__SHIFT 0x4 ++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff ++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0 ++#define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff ++#define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0 ++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000 ++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10 ++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000 ++#define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11 ++#define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff ++#define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0 ++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000 ++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10 ++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000 ++#define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11 ++#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70 ++#define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4 ++#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000 ++#define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c ++#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1 ++#define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0 ++#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2 ++#define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1 ++#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4 ++#define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2 ++#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8 ++#define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3 ++#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10 ++#define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4 ++#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20 ++#define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5 ++#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100 ++#define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8 ++#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200 ++#define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9 ++#define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff ++#define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 ++#define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff ++#define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 ++#define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff ++#define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 ++#define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff ++#define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 ++#define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff ++#define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 ++#define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff ++#define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 ++#define PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff ++#define PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 ++#define PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff ++#define PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 ++#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS_MASK 0x1 ++#define DVMM_REG_RD_STATUS__DVMM_REG_RD_STATUS__SHIFT 0x0 ++#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA_MASK 0xffffffff ++#define DVMM_REG_RD_DATA__DVMM_REG_RD_DATA__SHIFT 0x0 ++#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE_MASK 0xff ++#define DVMM_PTE_REQ__MAX_PTEREQ_TO_ISSUE__SHIFT 0x0 ++#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT_MASK 0xff00 ++#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_INT__SHIFT 0x8 ++#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER_MASK 0x3f0000 ++#define DVMM_PTE_REQ__HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER__SHIFT 0x10 ++#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL_MASK 0x3 ++#define DVMM_CNTL__PDE_CACHE_INVALIDATE_CNTL__SHIFT 0x0 ++#define DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE_MASK 0x30 ++#define DVMM_CNTL__DEBUG_SYSTEM_ACCESS_MODE__SHIFT 0x4 ++#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE_MASK 0x80 ++#define DVMM_CNTL__FORCE_SYSTEM_ACCESS_MODE__SHIFT 0x7 ++#define DVMM_CNTL__DBG_DCE_VMID_MASK 0xf00 ++#define DVMM_CNTL__DBG_DCE_VMID__SHIFT 0x8 ++#define DVMM_CNTL__FORCE_DBG_DCE_VMID_MASK 0x8000 ++#define DVMM_CNTL__FORCE_DBG_DCE_VMID__SHIFT 0xf ++#define DVMM_CNTL__OVERRIDE_SNOOP_MASK 0x20000 ++#define DVMM_CNTL__OVERRIDE_SNOOP__SHIFT 0x11 ++#define DVMM_CNTL__ENABLE_PDE_INVALIDATE_MASK 0x40000 ++#define DVMM_CNTL__ENABLE_PDE_INVALIDATE__SHIFT 0x12 ++#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS_MASK 0xffffffff ++#define DVMM_FAULT_STATUS__DVMM_FAULT_STATUS__SHIFT 0x0 ++#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR_MASK 0xffffffff ++#define DVMM_FAULT_ADDR__DVMM_FAULT_ADDR__SHIFT 0x0 ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1 ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0 ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18 ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3 ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0 ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5 ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700 ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8 ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800 ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000 ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000 ++#define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10 ++#define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3 ++#define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0 ++#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10 ++#define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4 ++#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100 ++#define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8 ++#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000 ++#define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc ++#define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000 ++#define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10 ++#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000 ++#define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18 ++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000 ++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e ++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000 ++#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f ++#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff ++#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 ++#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00 ++#define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8 ++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff ++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff ++#define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0 ++#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff ++#define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 ++#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff ++#define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0 ++#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff ++#define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0 ++#define MCIF_VMID__MCIF_WR_VMID_MASK 0xf ++#define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0 ++#define MCIF_VMID__VIP_WR_VMID_MASK 0xf0 ++#define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4 ++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1 ++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0 ++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30 ++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4 ++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00 ++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8 ++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000 ++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10 ++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000 ++#define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13 ++#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e ++#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1 ++#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS_MASK 0x3f0000 ++#define CC_DC_PIPE_DIS__DC_UNDERLAY_PIPE_DIS__SHIFT 0x10 ++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1 ++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0 ++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10 ++#define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4 ++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100 ++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8 ++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000 ++#define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc ++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000 ++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10 ++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000 ++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14 ++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000 ++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18 ++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000 ++#define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c ++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0xfffff ++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 ++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xfff00000 ++#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14 ++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0x7fff ++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 ++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000 ++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c ++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000 ++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d ++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000 ++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e ++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000 ++#define RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f ++#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x1 ++#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 ++#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x2 ++#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 ++#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x4 ++#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 ++#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x8 ++#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 ++#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x10 ++#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 ++#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x20 ++#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 ++#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x40 ++#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 ++#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x80 ++#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 ++#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x100 ++#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 ++#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x200 ++#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 ++#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x400 ++#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa ++#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800 ++#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb ++#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x1000 ++#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc ++#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x2000 ++#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd ++#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x4000 ++#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe ++#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x3 ++#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 ++#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x10 ++#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 ++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x20 ++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 ++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x40 ++#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 ++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE_MASK 0x3 ++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM1_PWR_STATE__SHIFT 0x0 ++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE_MASK 0xc ++#define DCI_MEM_PWR_STATUS__DMIF_RDREQ_MEM2_PWR_STATE__SHIFT 0x2 ++#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE_MASK 0x10 ++#define DCI_MEM_PWR_STATUS__MCIF_RDREQ_MEM_PWR_STATE__SHIFT 0x4 ++#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE_MASK 0x40 ++#define DCI_MEM_PWR_STATUS__MCIF_WRREQ_MEM_PWR_STATE__SHIFT 0x6 ++#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x100 ++#define DCI_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x8 ++#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE_MASK 0x600 ++#define DCI_MEM_PWR_STATUS__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x9 ++#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800 ++#define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xb ++#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE_MASK 0x3000 ++#define DCI_MEM_PWR_STATUS__FBC_MEM_PWR_STATE__SHIFT 0xc ++#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE_MASK 0xc000 ++#define DCI_MEM_PWR_STATUS__MCIF_MEM_PWR_STATE__SHIFT 0xe ++#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE_MASK 0x30000 ++#define DCI_MEM_PWR_STATUS__MCIF_DWB_MEM_PWR_STATE__SHIFT 0x10 ++#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE_MASK 0xc0000 ++#define DCI_MEM_PWR_STATUS__MCIF_CWB0_MEM_PWR_STATE__SHIFT 0x12 ++#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK 0x300000 ++#define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE__SHIFT 0x14 ++#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE_MASK 0x400000 ++#define DCI_MEM_PWR_STATUS__VIP_MEM_PWR_STATE__SHIFT 0x16 ++#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000000 ++#define DCI_MEM_PWR_STATUS__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x18 ++#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE_MASK 0xc000000 ++#define DCI_MEM_PWR_STATUS__DMIF0_DATA_MEM_PWR_STATE__SHIFT 0x1a ++#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE_MASK 0x10000000 ++#define DCI_MEM_PWR_STATUS__DMIF0_CHUNK_MEM_PWR_STATE__SHIFT 0x1c ++#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x3 ++#define DCI_MEM_PWR_STATUS2__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0 ++#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE_MASK 0xc ++#define DCI_MEM_PWR_STATUS2__DMIF1_DATA_MEM_PWR_STATE__SHIFT 0x2 ++#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE_MASK 0x10 ++#define DCI_MEM_PWR_STATUS2__DMIF1_CHUNK_MEM_PWR_STATE__SHIFT 0x4 ++#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x60 ++#define DCI_MEM_PWR_STATUS2__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x5 ++#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE_MASK 0x180 ++#define DCI_MEM_PWR_STATUS2__DMIF2_DATA_MEM_PWR_STATE__SHIFT 0x7 ++#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE_MASK 0x200 ++#define DCI_MEM_PWR_STATUS2__DMIF2_CHUNK_MEM_PWR_STATE__SHIFT 0x9 ++#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc00 ++#define DCI_MEM_PWR_STATUS2__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0xa ++#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE_MASK 0x3000 ++#define DCI_MEM_PWR_STATUS2__DMIF3_DATA_MEM_PWR_STATE__SHIFT 0xc ++#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE_MASK 0x4000 ++#define DCI_MEM_PWR_STATUS2__DMIF3_CHUNK_MEM_PWR_STATE__SHIFT 0xe ++#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x18000 ++#define DCI_MEM_PWR_STATUS2__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0xf ++#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE_MASK 0x60000 ++#define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11 ++#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE_MASK 0x80000 ++#define DCI_MEM_PWR_STATUS2__DMIF4_CHUNK_MEM_PWR_STATE__SHIFT 0x13 ++#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x300000 ++#define DCI_MEM_PWR_STATUS2__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x14 ++#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE_MASK 0xc00000 ++#define DCI_MEM_PWR_STATUS2__DMIF5_DATA_MEM_PWR_STATE__SHIFT 0x16 ++#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE_MASK 0x1000000 ++#define DCI_MEM_PWR_STATUS2__DMIF5_CHUNK_MEM_PWR_STATE__SHIFT 0x18 ++#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f ++#define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0 ++#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20 ++#define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5 ++#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40 ++#define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6 ++#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80 ++#define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7 ++#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100 ++#define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 ++#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200 ++#define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9 ++#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800 ++#define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb ++#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000 ++#define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd ++#define DCI_CLK_CNTL__VPCLK_POL_MASK 0x4000 ++#define DCI_CLK_CNTL__VPCLK_POL__SHIFT 0xe ++#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000 ++#define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf ++#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15 ++#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000 ++#define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16 ++#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000 ++#define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17 ++#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000 ++#define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS_MASK 0x2000000 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_L_GATE_DIS__SHIFT 0x19 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS_MASK 0x4000000 ++#define DCI_CLK_CNTL__DISPCLK_G_DMIFV_C_GATE_DIS__SHIFT 0x1a ++#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000 ++#define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b ++#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS_MASK 0x1 ++#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x0 ++#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS_MASK 0x2 ++#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_DWB_GATE_DIS__SHIFT 0x1 ++#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x4 ++#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x2 ++#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS_MASK 0x8 ++#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB0_GATE_DIS__SHIFT 0x3 ++#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x10 ++#define DCI_CLK_RAMP_CNTL__DISPCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x4 ++#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS_MASK 0x80000000 ++#define DCI_CLK_RAMP_CNTL__SCLK_G_MCIF_CWB1_GATE_DIS__SHIFT 0x1f ++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE_MASK 0x3 ++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x0 ++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS_MASK 0x4 ++#define DCI_MEM_PWR_CNTL__DMIF_RDREQ_MEM_PWR_DIS__SHIFT 0x2 ++#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE_MASK 0x8 ++#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_FORCE__SHIFT 0x3 ++#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS_MASK 0x10 ++#define DCI_MEM_PWR_CNTL__MCIF_RDREQ_MEM_PWR_DIS__SHIFT 0x4 ++#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE_MASK 0x20 ++#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_FORCE__SHIFT 0x5 ++#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS_MASK 0x40 ++#define DCI_MEM_PWR_CNTL__MCIF_WRREQ_MEM_PWR_DIS__SHIFT 0x6 ++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x80 ++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x7 ++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x100 ++#define DCI_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x8 ++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x600 ++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x9 ++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x800 ++#define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0xb ++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x1000 ++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0xc ++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x2000 ++#define DCI_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0xd ++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE_MASK 0xc000 ++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_FORCE__SHIFT 0xe ++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS_MASK 0x10000 ++#define DCI_MEM_PWR_CNTL__FBC_MEM_PWR_DIS__SHIFT 0x10 ++#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE_MASK 0x60000 ++#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_FORCE__SHIFT 0x11 ++#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS_MASK 0x80000 ++#define DCI_MEM_PWR_CNTL__MCIF_MEM_PWR_DIS__SHIFT 0x13 ++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE_MASK 0x300000 ++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_FORCE__SHIFT 0x14 ++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS_MASK 0x400000 ++#define DCI_MEM_PWR_CNTL__MCIF_DWB_MEM_PWR_DIS__SHIFT 0x16 ++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE_MASK 0x1800000 ++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_FORCE__SHIFT 0x17 ++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS_MASK 0x2000000 ++#define DCI_MEM_PWR_CNTL__MCIF_CWB0_MEM_PWR_DIS__SHIFT 0x19 ++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE_MASK 0xc000000 ++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_FORCE__SHIFT 0x1a ++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS_MASK 0x10000000 ++#define DCI_MEM_PWR_CNTL__MCIF_CWB1_MEM_PWR_DIS__SHIFT 0x1c ++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE_MASK 0x20000000 ++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_FORCE__SHIFT 0x1d ++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS_MASK 0x40000000 ++#define DCI_MEM_PWR_CNTL__VIP_MEM_PWR_DIS__SHIFT 0x1e ++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE_MASK 0x3 ++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_FORCE__SHIFT 0x0 ++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS_MASK 0x4 ++#define DCI_MEM_PWR_CNTL2__DMIF0_ASYNC_MEM_PWR_DIS__SHIFT 0x2 ++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE_MASK 0x18 ++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_FORCE__SHIFT 0x3 ++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS_MASK 0x20 ++#define DCI_MEM_PWR_CNTL2__DMIF0_DATA_MEM_PWR_DIS__SHIFT 0x5 ++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE_MASK 0x40 ++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_FORCE__SHIFT 0x6 ++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS_MASK 0x80 ++#define DCI_MEM_PWR_CNTL2__DMIF0_CHUNK_MEM_PWR_DIS__SHIFT 0x7 ++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE_MASK 0x300 ++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_FORCE__SHIFT 0x8 ++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS_MASK 0x400 ++#define DCI_MEM_PWR_CNTL2__DMIF1_ASYNC_MEM_PWR_DIS__SHIFT 0xa ++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE_MASK 0x1800 ++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_FORCE__SHIFT 0xb ++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS_MASK 0x2000 ++#define DCI_MEM_PWR_CNTL2__DMIF1_DATA_MEM_PWR_DIS__SHIFT 0xd ++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE_MASK 0x4000 ++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_FORCE__SHIFT 0xe ++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS_MASK 0x8000 ++#define DCI_MEM_PWR_CNTL2__DMIF1_CHUNK_MEM_PWR_DIS__SHIFT 0xf ++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE_MASK 0x30000 ++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_FORCE__SHIFT 0x10 ++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS_MASK 0x40000 ++#define DCI_MEM_PWR_CNTL2__DMIF2_ASYNC_MEM_PWR_DIS__SHIFT 0x12 ++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE_MASK 0x180000 ++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_FORCE__SHIFT 0x13 ++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS_MASK 0x200000 ++#define DCI_MEM_PWR_CNTL2__DMIF2_DATA_MEM_PWR_DIS__SHIFT 0x15 ++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE_MASK 0x400000 ++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_FORCE__SHIFT 0x16 ++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS_MASK 0x800000 ++#define DCI_MEM_PWR_CNTL2__DMIF2_CHUNK_MEM_PWR_DIS__SHIFT 0x17 ++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE_MASK 0x3000000 ++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_FORCE__SHIFT 0x18 ++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS_MASK 0x4000000 ++#define DCI_MEM_PWR_CNTL2__DMIF3_ASYNC_MEM_PWR_DIS__SHIFT 0x1a ++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE_MASK 0x18000000 ++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_FORCE__SHIFT 0x1b ++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS_MASK 0x20000000 ++#define DCI_MEM_PWR_CNTL2__DMIF3_DATA_MEM_PWR_DIS__SHIFT 0x1d ++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE_MASK 0x40000000 ++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_FORCE__SHIFT 0x1e ++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS_MASK 0x80000000 ++#define DCI_MEM_PWR_CNTL2__DMIF3_CHUNK_MEM_PWR_DIS__SHIFT 0x1f ++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE_MASK 0x3 ++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_FORCE__SHIFT 0x0 ++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS_MASK 0x4 ++#define DCI_MEM_PWR_CNTL3__DMIF4_ASYNC_MEM_PWR_DIS__SHIFT 0x2 ++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE_MASK 0x18 ++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_FORCE__SHIFT 0x3 ++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS_MASK 0x20 ++#define DCI_MEM_PWR_CNTL3__DMIF4_DATA_MEM_PWR_DIS__SHIFT 0x5 ++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE_MASK 0x40 ++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_FORCE__SHIFT 0x6 ++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS_MASK 0x80 ++#define DCI_MEM_PWR_CNTL3__DMIF4_CHUNK_MEM_PWR_DIS__SHIFT 0x7 ++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE_MASK 0x300 ++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_FORCE__SHIFT 0x8 ++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS_MASK 0x400 ++#define DCI_MEM_PWR_CNTL3__DMIF5_ASYNC_MEM_PWR_DIS__SHIFT 0xa ++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE_MASK 0x1800 ++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_FORCE__SHIFT 0xb ++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS_MASK 0x2000 ++#define DCI_MEM_PWR_CNTL3__DMIF5_DATA_MEM_PWR_DIS__SHIFT 0xd ++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE_MASK 0x4000 ++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_FORCE__SHIFT 0xe ++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS_MASK 0x8000 ++#define DCI_MEM_PWR_CNTL3__DMIF5_CHUNK_MEM_PWR_DIS__SHIFT 0xf ++#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL_MASK 0x30000 ++#define DCI_MEM_PWR_CNTL3__DMIF_RDREQ_MEM_PWR_MODE_SEL__SHIFT 0x10 ++#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL_MASK 0xc0000 ++#define DCI_MEM_PWR_CNTL3__DMIF_ASYNC_MEM_PWR_MODE_SEL__SHIFT 0x12 ++#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL_MASK 0x300000 ++#define DCI_MEM_PWR_CNTL3__DMIF_DATA_MEM_PWR_MODE_SEL__SHIFT 0x14 ++#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x400000 ++#define DCI_MEM_PWR_CNTL3__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x16 ++#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL_MASK 0x1800000 ++#define DCI_MEM_PWR_CNTL3__FBC_MEM_PWR_MODE_SEL__SHIFT 0x17 ++#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL_MASK 0x6000000 ++#define DCI_MEM_PWR_CNTL3__MCIF_CWB0_MEM_PWR_MODE_SEL__SHIFT 0x19 ++#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL_MASK 0x18000000 ++#define DCI_MEM_PWR_CNTL3__MCIF_CWB1_MEM_PWR_MODE_SEL__SHIFT 0x1b ++#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL_MASK 0x60000000 ++#define DCI_MEM_PWR_CNTL3__MCIF_DWB_MEM_PWR_MODE_SEL__SHIFT 0x1d ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE_MASK 0x3 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_FORCE__SHIFT 0x0 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS_MASK 0x4 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE0_MEM_PWR_DIS__SHIFT 0x2 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE_MASK 0x18 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_FORCE__SHIFT 0x3 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS_MASK 0x20 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE1_MEM_PWR_DIS__SHIFT 0x5 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE_MASK 0xc0 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_FORCE__SHIFT 0x6 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS_MASK 0x100 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE2_MEM_PWR_DIS__SHIFT 0x8 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE_MASK 0x600 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_FORCE__SHIFT 0x9 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS_MASK 0x800 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE3_MEM_PWR_DIS__SHIFT 0xb ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE_MASK 0x3000 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_FORCE__SHIFT 0xc ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS_MASK 0x4000 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE4_MEM_PWR_DIS__SHIFT 0xe ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE_MASK 0x18000 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_FORCE__SHIFT 0xf ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS_MASK 0x20000 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE5_MEM_PWR_DIS__SHIFT 0x11 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE_MASK 0xc0000 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_FORCE__SHIFT 0x12 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS_MASK 0x100000 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE6_MEM_PWR_DIS__SHIFT 0x14 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE_MASK 0x600000 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_FORCE__SHIFT 0x15 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS_MASK 0x800000 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE7_MEM_PWR_DIS__SHIFT 0x17 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL_MASK 0x3000000 ++#define DVMM_PTE_PGMEM_CONTROL__DVMM_PTE_MEM_PWR_MODE_SEL__SHIFT 0x18 ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE_MASK 0x3 ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE0_PTE_PGMEM_STATE__SHIFT 0x0 ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE_MASK 0xc ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE1_PTE_PGMEM_STATE__SHIFT 0x2 ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE_MASK 0x30 ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE2_PTE_PGMEM_STATE__SHIFT 0x4 ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE_MASK 0xc0 ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE3_PTE_PGMEM_STATE__SHIFT 0x6 ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE_MASK 0x300 ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE4_PTE_PGMEM_STATE__SHIFT 0x8 ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE_MASK 0xc00 ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE5_PTE_PGMEM_STATE__SHIFT 0xa ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE_MASK 0x3000 ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE6_PTE_PGMEM_STATE__SHIFT 0xc ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE_MASK 0xc000 ++#define DVMM_PTE_PGMEM_STATE__DVMM_PIPE7_PTE_PGMEM_STATE__SHIFT 0xe ++#define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1 ++#define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 ++#define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2 ++#define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1 ++#define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4 ++#define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2 ++#define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8 ++#define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3 ++#define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10 ++#define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4 ++#define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20 ++#define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5 ++#define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40 ++#define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6 ++#define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80 ++#define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7 ++#define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100 ++#define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8 ++#define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200 ++#define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9 ++#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET_MASK 0x400 ++#define DCI_SOFT_RESET__DCFEV0_L_SOFT_RESET__SHIFT 0xa ++#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET_MASK 0x800 ++#define DCI_SOFT_RESET__DCFEV0_C_SOFT_RESET__SHIFT 0xb ++#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000 ++#define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc ++#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET_MASK 0x10000 ++#define DCI_SOFT_RESET__MCIF_DWB_SOFT_RESET__SHIFT 0x10 ++#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET_MASK 0x20000 ++#define DCI_SOFT_RESET__MCIF_CWB0_SOFT_RESET__SHIFT 0x11 ++#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET_MASK 0x40000 ++#define DCI_SOFT_RESET__MCIF_CWB1_SOFT_RESET__SHIFT 0x12 ++#define DCI_MISC__MCIF_WB_URG_OVRD_MASK 0x1 ++#define DCI_MISC__MCIF_WB_URG_OVRD__SHIFT 0x0 ++#define DCI_MISC__MCIF_WB_URG_LVL_MASK 0x1e ++#define DCI_MISC__MCIF_WB_URG_LVL__SHIFT 0x1 ++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff ++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0 ++#define DCI_DEBUG_CONFIG__DCI_DBG_EN_MASK 0x1 ++#define DCI_DEBUG_CONFIG__DCI_DBG_EN__SHIFT 0x0 ++#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL_MASK 0xf0 ++#define DCI_DEBUG_CONFIG__DCI_DBG_BLOCK_SEL__SHIFT 0x4 ++#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL_MASK 0xf00 ++#define DCI_DEBUG_CONFIG__DCI_DBG_CLOCK_SEL__SHIFT 0x8 ++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 ++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 ++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 ++#define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 ++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 ++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 ++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 ++#define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 ++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 ++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 ++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 ++#define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 ++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 ++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 ++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 ++#define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 ++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 ++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 ++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 ++#define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 ++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 ++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 ++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 ++#define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 ++#define DC_GENERICA__GENERICA_EN_MASK 0x1 ++#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 ++#define DC_GENERICA__GENERICA_SEL_MASK 0xf80 ++#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 ++#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0xf000 ++#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc ++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0xf0000 ++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 ++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0xf00000 ++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 ++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0xf000000 ++#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 ++#define DC_GENERICB__GENERICB_EN_MASK 0x1 ++#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 ++#define DC_GENERICB__GENERICB_SEL_MASK 0xf00 ++#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 ++#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0xf000 ++#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc ++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0xf0000 ++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 ++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0xf00000 ++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 ++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0xf000000 ++#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 ++#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf ++#define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0 ++#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30 ++#define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4 ++#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3 ++#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 ++#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300 ++#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 ++#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1 ++#define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0 ++#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300 ++#define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8 ++#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000 ++#define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10 ++#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000 ++#define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11 ++#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE_MASK 0x80000000 ++#define DC_GPIO_DEBUG__DPRX_LOOPBACK_ENABLE__SHIFT 0x1f ++#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 ++#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 ++#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 ++#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 ++#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 ++#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 ++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 ++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc ++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 ++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd ++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 ++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe ++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 ++#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf ++#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 ++#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 ++#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 ++#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 ++#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 ++#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 ++#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 ++#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 ++#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 ++#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 ++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 ++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc ++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 ++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd ++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 ++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe ++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 ++#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf ++#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 ++#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 ++#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 ++#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 ++#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 ++#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 ++#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 ++#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 ++#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 ++#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 ++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 ++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc ++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 ++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd ++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 ++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe ++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 ++#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf ++#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 ++#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 ++#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 ++#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 ++#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 ++#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 ++#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 ++#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 ++#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 ++#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 ++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 ++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc ++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 ++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd ++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 ++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe ++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 ++#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf ++#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 ++#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 ++#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 ++#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 ++#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 ++#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 ++#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 ++#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 ++#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 ++#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 ++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 ++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc ++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 ++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd ++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 ++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe ++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 ++#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf ++#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 ++#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 ++#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 ++#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 ++#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 ++#define UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 ++#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 ++#define UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 ++#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 ++#define UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 ++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 ++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc ++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 ++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd ++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 ++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe ++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 ++#define UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf ++#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 ++#define UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 ++#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 ++#define UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 ++#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 ++#define UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 ++#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 ++#define UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 ++#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 ++#define UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 ++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 ++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc ++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 ++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd ++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 ++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe ++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 ++#define UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf ++#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 ++#define UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 ++#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x3000000 ++#define UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 ++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 ++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 ++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 ++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 ++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 ++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 ++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 ++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 ++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 ++#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c ++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 ++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 ++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 ++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 ++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 ++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 ++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 ++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 ++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 ++#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c ++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 ++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 ++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 ++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 ++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 ++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 ++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 ++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 ++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 ++#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c ++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 ++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 ++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 ++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 ++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 ++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 ++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 ++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 ++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 ++#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c ++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 ++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 ++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 ++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 ++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 ++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 ++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 ++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 ++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 ++#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c ++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 ++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 ++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 ++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 ++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 ++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 ++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 ++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 ++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 ++#define UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c ++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 ++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 ++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 ++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 ++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 ++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 ++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 ++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 ++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000 ++#define UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x1 ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0 ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x10 ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4 ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x1000 ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x2000 ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x4000 ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x8000 ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x700000 ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14 ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x3000000 ++#define UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK 0x1 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT 0x0 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK 0x10 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT 0x4 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK 0x1000 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT 0xc ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK 0x2000 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT 0xd ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK 0x4000 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT 0xe ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK 0x8000 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT 0xf ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK 0x700000 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT 0x14 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK 0x3000000 ++#define UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT 0x18 ++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x3 ++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 ++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x300 ++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 ++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x30000 ++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 ++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 ++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 ++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000 ++#define UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c ++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK 0x3 ++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 ++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK 0x300 ++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 ++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK 0x30000 ++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 ++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 ++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 ++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK 0x10000000 ++#define UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT 0x1c ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000 ++#define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000 ++#define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000 ++#define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000 ++#define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000 ++#define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000 ++#define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e ++#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff ++#define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0 ++#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1 ++#define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0 ++#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100 ++#define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8 ++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200 ++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9 ++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400 ++#define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa ++#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000 ++#define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10 ++#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000 ++#define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14 ++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000 ++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18 ++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 ++#define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c ++#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1 ++#define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0 ++#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100 ++#define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8 ++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200 ++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9 ++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400 ++#define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa ++#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000 ++#define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10 ++#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000 ++#define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14 ++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000 ++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18 ++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 ++#define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c ++#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE_MASK 0xf ++#define DCIO_IMPCAL_CNTL__CALR_CNTL_OVERRIDE__SHIFT 0x0 ++#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET_MASK 0x20 ++#define DCIO_IMPCAL_CNTL__IMPCAL_SOFT_RESET__SHIFT 0x5 ++#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS_MASK 0x300 ++#define DCIO_IMPCAL_CNTL__IMPCAL_STATUS__SHIFT 0x8 ++#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE_MASK 0x7000 ++#define DCIO_IMPCAL_CNTL__IMPCAL_ARB_STATE__SHIFT 0xc ++#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL_MASK 0x78000 ++#define DCIO_IMPCAL_CNTL__AUX_IMPCAL_INTERVAL__SHIFT 0xf ++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff ++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0 ++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000 ++#define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10 ++#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf ++#define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0 ++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20 ++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5 ++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300 ++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8 ++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000 ++#define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc ++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff ++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0 ++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000 ++#define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10 ++#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf ++#define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0 ++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20 ++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5 ++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300 ++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8 ++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000 ++#define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc ++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff ++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0 ++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000 ++#define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10 ++#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xf ++#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x0 ++#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0xf0 ++#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4 ++#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0xf00 ++#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8 ++#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0xf000 ++#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc ++#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400 ++#define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa ++#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000 ++#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd ++#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000 ++#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe ++#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000 ++#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 ++#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0xe0000 ++#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11 ++#define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000 ++#define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13 ++#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000 ++#define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14 ++#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000 ++#define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa ++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000 ++#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a ++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1 ++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 ++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2 ++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 ++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4 ++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 ++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8 ++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 ++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10 ++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 ++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00 ++#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 ++#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff ++#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 ++#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 ++#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 ++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff ++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 ++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00 ++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 ++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000 ++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 ++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000 ++#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 ++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff ++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 ++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00 ++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 ++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000 ++#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 ++#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000 ++#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 ++#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff ++#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 ++#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000 ++#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e ++#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000 ++#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f ++#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff ++#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 ++#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000 ++#define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c ++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000 ++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e ++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000 ++#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f ++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff ++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 ++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000 ++#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 ++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1 ++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 ++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100 ++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 ++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000 ++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 ++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000 ++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 ++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 ++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 ++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 ++#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f ++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3 ++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0 ++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30 ++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4 ++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300 ++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 ++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000 ++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10 ++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000 ++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14 ++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000 ++#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 ++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3 ++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0 ++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30 ++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4 ++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300 ++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 ++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000 ++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10 ++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000 ++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14 ++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000 ++#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 ++#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7 ++#define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0 ++#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700 ++#define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8 ++#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000 ++#define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10 ++#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7 ++#define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0 ++#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700 ++#define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8 ++#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000 ++#define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10 ++#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7 ++#define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0 ++#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700 ++#define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8 ++#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000 ++#define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10 ++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7 ++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 ++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70 ++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 ++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700 ++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 ++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000 ++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc ++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000 ++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 ++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000 ++#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7 ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0 ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70 ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4 ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700 ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8 ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000 ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000 ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10 ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000 ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14 ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV_P_FLIP_MASK 0x3800000 ++#define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_DCFEV_P_FLIP__SHIFT 0x17 ++#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff ++#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700 ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800 ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000 ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000 ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000 ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000 ++#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 ++#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x1f ++#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 ++#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x20 ++#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 ++#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff ++#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000 ++#define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f ++#define DBG_OUT_CNTL__DBG_OUT_PIN_EN_MASK 0x1 ++#define DBG_OUT_CNTL__DBG_OUT_PIN_EN__SHIFT 0x0 ++#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL_MASK 0x10 ++#define DBG_OUT_CNTL__DBG_OUT_PIN_SEL__SHIFT 0x4 ++#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL_MASK 0x300 ++#define DBG_OUT_CNTL__DBG_OUT_12BIT_SEL__SHIFT 0x8 ++#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA_MASK 0xfff000 ++#define DBG_OUT_CNTL__DBG_OUT_TEST_DATA__SHIFT 0xc ++#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x1 ++#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0 ++#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x1 ++#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 ++#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x2 ++#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1 ++#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x4 ++#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2 ++#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x8 ++#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3 ++#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x10 ++#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4 ++#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x20 ++#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5 ++#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x40 ++#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6 ++#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x80 ++#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7 ++#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x100 ++#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8 ++#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x200 ++#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9 ++#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x400 ++#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa ++#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x800 ++#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb ++#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x1000 ++#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc ++#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x2000 ++#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd ++#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x10000 ++#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10 ++#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x100000 ++#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14 ++#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x1000000 ++#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18 ++#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET_MASK 0x10000000 ++#define DCIO_SOFT_RESET__UNIPHYLPA_SOFT_RESET__SHIFT 0x1c ++#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET_MASK 0x20000000 ++#define DCIO_SOFT_RESET__DSYNCLPA_SOFT_RESET__SHIFT 0x1d ++#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET_MASK 0x40000000 ++#define DCIO_SOFT_RESET__UNIPHYLPB_SOFT_RESET__SHIFT 0x1e ++#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET_MASK 0x80000000 ++#define DCIO_SOFT_RESET__DSYNCLPB_SOFT_RESET__SHIFT 0x1f ++#define DCIO_DPHY_SEL__DPHY_LANE0_SEL_MASK 0x3 ++#define DCIO_DPHY_SEL__DPHY_LANE0_SEL__SHIFT 0x0 ++#define DCIO_DPHY_SEL__DPHY_LANE1_SEL_MASK 0xc ++#define DCIO_DPHY_SEL__DPHY_LANE1_SEL__SHIFT 0x2 ++#define DCIO_DPHY_SEL__DPHY_LANE2_SEL_MASK 0x30 ++#define DCIO_DPHY_SEL__DPHY_LANE2_SEL__SHIFT 0x4 ++#define DCIO_DPHY_SEL__DPHY_LANE3_SEL_MASK 0xc0 ++#define DCIO_DPHY_SEL__DPHY_LANE3_SEL__SHIFT 0x6 ++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff ++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0 ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3 ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0 ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2 ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30 ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4 ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0_MASK 0xc0 ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6 ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300 ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8 ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN_MASK 0xc00 ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C_MASK 0x1000 ++#define DCIO_DEBUG1__DCO_DCIO_MVP_DVOCLK_C__SHIFT 0xc ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG_MASK 0x2000 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0_MASK 0x8000 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_A0__SHIFT 0xf ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG_MASK 0x10000 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10 ++#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000 ++#define DCIO_DEBUG1__DCO_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11 ++#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE_MASK 0x40000 ++#define DCIO_DEBUG1__DCO_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN_MASK 0x100000 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_EN__SHIFT 0x14 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX_MASK 0x200000 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MUX__SHIFT 0x15 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16 ++#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE_MASK 0x800000 ++#define DCIO_DEBUG1__DCO_DCIO_DVO_ENABLE__SHIFT 0x17 ++#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000 ++#define DCIO_DEBUG1__DCO_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18 ++#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL_MASK 0x2000000 ++#define DCIO_DEBUG1__DCO_DCIO_DVO_RATE_SEL__SHIFT 0x19 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0_MASK 0x8000000 ++#define DCIO_DEBUG1__DCO_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b ++#define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff ++#define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0 ++#define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff ++#define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0 ++#define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff ++#define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0 ++#define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff ++#define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0 ++#define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff ++#define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0 ++#define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff ++#define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0 ++#define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff ++#define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0 ++#define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff ++#define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0 ++#define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff ++#define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0 ++#define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff ++#define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0 ++#define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff ++#define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0 ++#define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff ++#define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0 ++#define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff ++#define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0 ++#define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff ++#define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0 ++#define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff ++#define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0 ++#define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff ++#define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0 ++#define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff ++#define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0 ++#define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff ++#define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0 ++#define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff ++#define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0 ++#define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff ++#define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0 ++#define DCIO_DEBUG16__DCIO_DEBUG16_MASK 0xffffffff ++#define DCIO_DEBUG16__DCIO_DEBUG16__SHIFT 0x0 ++#define DCIO_DEBUG17__DCIO_DEBUG17_MASK 0xffffffff ++#define DCIO_DEBUG17__DCIO_DEBUG17__SHIFT 0x0 ++#define DCIO_DEBUG18__DCIO_DEBUG18_MASK 0xffffffff ++#define DCIO_DEBUG18__DCIO_DEBUG18__SHIFT 0x0 ++#define DCIO_DEBUG19__DCIO_DIGLPA_DEBUG_MASK 0xffffffff ++#define DCIO_DEBUG19__DCIO_DIGLPA_DEBUG__SHIFT 0x0 ++#define DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG_MASK 0xffffffff ++#define DCIO_DEBUG1A__DCIO_DIGLPB_DEBUG__SHIFT 0x0 ++#define DCIO_DEBUG1B__DCIO_DEBUGHPD_MASK 0xffffffff ++#define DCIO_DEBUG1B__DCIO_DEBUGHPD__SHIFT 0x0 ++#define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff ++#define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000 ++#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1 ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100 ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000 ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000 ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000 ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000 ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000 ++#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000 ++#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000 ++#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 ++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff ++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0 ++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000 ++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18 ++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000 ++#define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d ++#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000 ++#define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e ++#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff ++#define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0 ++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000 ++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18 ++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000 ++#define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d ++#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000 ++#define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e ++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff ++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0 ++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000 ++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18 ++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000 ++#define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d ++#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000 ++#define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e ++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff ++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0 ++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000 ++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18 ++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000 ++#define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d ++#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000 ++#define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe ++#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000 ++#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 ++#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000 ++#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 ++#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000 ++#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000 ++#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c ++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1 ++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 ++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100 ++#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 ++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1 ++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 ++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100 ++#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 ++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1 ++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 ++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100 ++#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe ++#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000 ++#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 ++#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000 ++#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 ++#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000 ++#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000 ++#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c ++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1 ++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 ++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100 ++#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 ++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1 ++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 ++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100 ++#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 ++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1 ++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 ++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100 ++#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe ++#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000 ++#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 ++#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000 ++#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 ++#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000 ++#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000 ++#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c ++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1 ++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 ++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100 ++#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 ++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1 ++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 ++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100 ++#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 ++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1 ++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 ++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100 ++#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe ++#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000 ++#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 ++#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000 ++#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 ++#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000 ++#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000 ++#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c ++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1 ++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 ++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100 ++#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 ++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1 ++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 ++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100 ++#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 ++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1 ++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 ++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100 ++#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe ++#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000 ++#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 ++#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000 ++#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 ++#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000 ++#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000 ++#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c ++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1 ++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 ++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100 ++#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 ++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1 ++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 ++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100 ++#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 ++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1 ++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 ++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100 ++#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe ++#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000 ++#define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10 ++#define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000 ++#define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14 ++#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000 ++#define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000 ++#define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c ++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1 ++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0 ++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100 ++#define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8 ++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1 ++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0 ++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100 ++#define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8 ++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1 ++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0 ++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100 ++#define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8 ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1 ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40 ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100 ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000 ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000 ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe ++#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000 ++#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 ++#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000 ++#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 ++#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000 ++#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000 ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000 ++#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c ++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1 ++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 ++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100 ++#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 ++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1 ++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 ++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100 ++#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 ++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1 ++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 ++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100 ++#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000 ++#define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c ++#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1 ++#define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0 ++#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100 ++#define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8 ++#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1 ++#define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0 ++#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100 ++#define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8 ++#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1 ++#define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0 ++#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100 ++#define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000 ++#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b ++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1 ++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 ++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100 ++#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 ++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000 ++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 ++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000 ++#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 ++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1 ++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 ++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100 ++#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 ++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000 ++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 ++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000 ++#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 ++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1 ++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 ++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100 ++#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 ++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000 ++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 ++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000 ++#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 ++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x2 ++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1 ++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x4 ++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2 ++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x8 ++#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000 ++#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e ++#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1 ++#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 ++#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100 ++#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 ++#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000 ++#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 ++#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000 ++#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 ++#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000 ++#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a ++#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000 ++#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c ++#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1 ++#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 ++#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x2 ++#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 ++#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x4 ++#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 ++#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x8 ++#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3 ++#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x10 ++#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4 ++#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x20 ++#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5 ++#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x40 ++#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 ++#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x80 ++#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7 ++#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100 ++#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 ++#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x200 ++#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9 ++#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x400 ++#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa ++#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000 ++#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 ++#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x20000 ++#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11 ++#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x40000 ++#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12 ++#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x100000 ++#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14 ++#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x200000 ++#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15 ++#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x400000 ++#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16 ++#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x1000000 ++#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18 ++#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x2000000 ++#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19 ++#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x4000000 ++#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a ++#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000 ++#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c ++#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000 ++#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d ++#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000 ++#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e ++#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1 ++#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 ++#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100 ++#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 ++#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000 ++#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 ++#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000 ++#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 ++#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000 ++#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a ++#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000 ++#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000 ++#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e ++#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1 ++#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 ++#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100 ++#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 ++#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000 ++#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 ++#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000 ++#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 ++#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000 ++#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f ++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1 ++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 ++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2 ++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 ++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100 ++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 ++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000 ++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 ++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000 ++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 ++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000 ++#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f ++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1 ++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 ++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100 ++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 ++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000 ++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 ++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000 ++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 ++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000 ++#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f ++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf ++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 ++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0 ++#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 ++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0xf00 ++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8 ++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0xf000 ++#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc ++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0xf0000 ++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10 ++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0xf00000 ++#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14 ++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000 ++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 ++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000 ++#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c ++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf ++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 ++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0 ++#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 ++#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700 ++#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 ++#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000 ++#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc ++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000 ++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 ++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000 ++#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 ++#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000 ++#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e ++#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x1 ++#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0 ++#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x2 ++#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1 ++#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x4 ++#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 ++#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x8 ++#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3 ++#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x10 ++#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4 ++#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x20 ++#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5 ++#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x40 ++#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6 ++#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x80 ++#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7 ++#define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000 ++#define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc ++#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x2000 ++#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0xd ++#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000 ++#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe ++#define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000 ++#define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x1 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x0 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x2 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x1 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x4 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x2 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x10 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x4 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x20 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x5 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x40 ++#define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x6 ++#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1 ++#define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0 ++#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2 ++#define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1 ++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1 ++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0 ++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2 ++#define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1 ++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1 ++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0 ++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2 ++#define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1 ++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf ++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0 ++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0 ++#define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4 ++#define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1 ++#define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0 ++#define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2 ++#define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1 ++#define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0 ++#define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4 ++#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff ++#define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0 ++#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED0__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED1__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED2__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED3__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED4__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED5__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED6__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED7__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED8__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED9__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED10__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED11__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED12__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED13__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED14__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED15__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED16__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED17__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED18__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED19__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED20__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED21__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED22__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED23__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED24__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED25__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED26__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED27__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED28__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED29__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED30__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED31__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED32__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED33__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED34__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED35__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED36__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED37__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED38__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED39__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED40__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED41__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED42__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED43__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED44__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED45__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED46__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED47__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED48__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED49__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED50__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED51__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED52__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED53__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED54__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED55__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED56__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED57__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED58__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED59__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED60__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED61__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED62__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED63__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED64__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED65__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED66__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED67__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED68__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED69__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED70__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED71__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED72__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED73__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED74__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED75__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED76__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED77__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED78__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED79__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED80__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED81__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED82__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED83__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED84__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED85__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED86__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED87__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED88__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED89__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED90__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED91__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED92__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED93__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED94__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED95__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED96__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED97__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED98__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED99__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED100__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED101__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED102__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED103__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED104__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED105__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED106__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED107__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED108__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED109__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED110__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED111__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED112__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED113__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED114__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED115__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED116__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED117__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED118__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED119__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED120__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED121__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED122__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED123__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED124__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED125__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED126__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED127__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED128__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED129__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED130__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED131__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED132__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED133__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED134__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED135__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED136__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED137__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED138__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED139__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED140__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED141__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED142__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED143__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED144__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED145__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED146__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED147__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED148__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED149__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED150__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED151__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED152__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED153__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED154__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED155__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED156__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED157__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED158__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED159__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED160__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED161__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED162__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED163__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED164__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED165__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED166__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED167__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED168__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED169__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED170__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED171__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED172__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED173__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED174__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED175__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED176__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED177__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED178__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED179__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED180__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED181__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED182__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED183__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED184__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED185__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED186__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED187__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED188__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED189__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED190__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED191__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED192__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED193__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED194__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED195__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED196__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED197__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED198__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED199__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED200__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED201__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED202__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED203__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED204__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED205__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED206__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED207__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED208__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED209__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED210__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED211__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED212__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED213__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED214__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED215__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED216__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED217__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED218__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED219__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED220__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED221__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED222__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED223__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED224__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED225__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED226__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED227__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED228__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED229__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED230__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED231__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED232__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED233__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED234__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED235__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED236__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED237__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED238__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED239__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED240__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED241__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED242__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED243__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED244__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED245__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED246__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED247__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED248__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED249__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED250__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED251__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED252__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED253__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED254__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED255__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED256__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED257__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED258__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED259__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED260__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED261__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED262__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED263__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED264__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED265__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED266__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED267__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED268__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED269__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED270__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED271__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED272__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED273__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED274__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED275__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED276__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED277__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED278__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED279__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED280__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED281__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED282__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED283__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED284__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED285__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED286__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED287__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED288__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED289__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED290__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED291__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED292__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED293__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED294__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED295__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED296__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED297__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED298__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED299__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED300__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED301__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED302__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED303__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED304__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED305__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED306__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED307__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED308__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED309__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED310__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED311__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED312__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED313__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED314__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED315__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED316__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED317__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED318__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED319__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED320__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED321__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED322__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED323__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED324__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED325__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED326__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED327__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED328__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED329__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED330__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED331__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED332__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED333__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED334__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED335__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED336__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED337__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED338__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED339__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED340__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED341__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED342__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED343__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED344__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED345__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED346__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED347__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED348__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED349__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED350__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED351__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED352__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED353__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED354__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED355__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED356__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED357__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED358__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED359__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED360__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED361__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED362__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED363__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED364__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED365__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED366__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED367__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED368__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED369__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED370__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED371__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED372__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED373__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED374__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED375__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED376__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED377__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED378__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DCRX_PHY_MACRO_CNTL_RESERVED379__DCRX_PHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED0__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED1__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED2__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED3__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED4__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED5__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED6__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED7__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED8__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED9__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED10__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED11__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED12__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED13__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED14__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED15__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED16__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED17__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED18__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED19__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED20__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED21__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED22__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED23__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED24__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED25__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED26__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED27__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED28__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED29__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED30__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED31__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED32__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED33__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED34__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED35__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED36__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED37__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED38__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED39__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED40__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED41__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED42__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED43__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED44__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED45__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED46__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED47__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED48__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED49__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED50__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED51__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED52__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED53__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED54__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED55__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED56__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED57__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED58__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED59__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED60__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED61__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED62__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED_MASK 0xffffffff ++#define DPHY_MACRO_CNTL_RESERVED63__DPHY_MACRO_CNTL_RESERVED__SHIFT 0x0 ++#define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1 ++#define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0 ++#define GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK 0x2 ++#define GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT 0x1 ++#define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3 ++#define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0 ++#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc ++#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2 ++#define GRPH_CONTROL__GRPH_Z_MASK 0x30 ++#define GRPH_CONTROL__GRPH_Z__SHIFT 0x4 ++#define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0 ++#define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6 ++#define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700 ++#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8 ++#define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800 ++#define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb ++#define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000 ++#define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd ++#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 ++#define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 ++#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 ++#define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 ++#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000 ++#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12 ++#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000 ++#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14 ++#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000 ++#define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18 ++#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000 ++#define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d ++#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000 ++#define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f ++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100 ++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8 ++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000 ++#define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10 ++#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3 ++#define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0 ++#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30 ++#define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4 ++#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0 ++#define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6 ++#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300 ++#define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8 ++#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00 ++#define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa ++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1 ++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0 ++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00 ++#define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8 ++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1 ++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0 ++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00 ++#define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8 ++#define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff ++#define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0 ++#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff ++#define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 ++#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff ++#define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 ++#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff ++#define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0 ++#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff ++#define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0 ++#define GRPH_X_START__GRPH_X_START_MASK 0x3fff ++#define GRPH_X_START__GRPH_X_START__SHIFT 0x0 ++#define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff ++#define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0 ++#define GRPH_X_END__GRPH_X_END_MASK 0x7fff ++#define GRPH_X_END__GRPH_X_END__SHIFT 0x0 ++#define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff ++#define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0 ++#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x1 ++#define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0 ++#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1 ++#define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0 ++#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2 ++#define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1 ++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4 ++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2 ++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8 ++#define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3 ++#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100 ++#define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8 ++#define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000 ++#define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10 ++#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000 ++#define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14 ++#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 ++#define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 ++#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000 ++#define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c ++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1 ++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0 ++#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK 0x2 ++#define GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT 0x1 ++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK 0x10 ++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT 0x4 ++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x20 ++#define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x5 ++#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00 ++#define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8 ++#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1 ++#define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0 ++#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70 ++#define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4 ++#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700 ++#define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 ++#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf ++#define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0 ++#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 ++#define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 ++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100 ++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8 ++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200 ++#define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9 ++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 ++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0 ++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 ++#define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8 ++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 ++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0 ++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100 ++#define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8 ++#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff ++#define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0 ++#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00 ++#define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8 ++#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0 ++#define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6 ++#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff ++#define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0 ++#define GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK 0xff ++#define GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT 0x0 ++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1 ++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0 ++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2 ++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1 ++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4 ++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2 ++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8 ++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3 ++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10 ++#define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4 ++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff ++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0 ++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000 ++#define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10 ++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff ++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0 ++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000 ++#define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10 ++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff ++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0 ++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000 ++#define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10 ++#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3 ++#define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0 ++#define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff ++#define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0 ++#define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000 ++#define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10 ++#define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff ++#define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0 ++#define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000 ++#define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10 ++#define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff ++#define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0 ++#define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000 ++#define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10 ++#define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff ++#define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0 ++#define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000 ++#define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10 ++#define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff ++#define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0 ++#define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000 ++#define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10 ++#define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff ++#define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0 ++#define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000 ++#define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10 ++#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7 ++#define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0 ++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff ++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0 ++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000 ++#define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10 ++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff ++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0 ++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000 ++#define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10 ++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff ++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0 ++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000 ++#define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10 ++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff ++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0 ++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000 ++#define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10 ++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff ++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0 ++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000 ++#define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10 ++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff ++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0 ++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000 ++#define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10 ++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff ++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0 ++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000 ++#define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10 ++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff ++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0 ++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000 ++#define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10 ++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff ++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0 ++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000 ++#define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10 ++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff ++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0 ++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000 ++#define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10 ++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff ++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0 ++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000 ++#define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10 ++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff ++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0 ++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000 ++#define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10 ++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff ++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0 ++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000 ++#define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10 ++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff ++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0 ++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000 ++#define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10 ++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff ++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0 ++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000 ++#define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10 ++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff ++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0 ++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000 ++#define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10 ++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff ++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0 ++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000 ++#define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10 ++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff ++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0 ++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000 ++#define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10 ++#define DENORM_CONTROL__DENORM_MODE_MASK 0x7 ++#define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0 ++#define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10 ++#define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4 ++#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf ++#define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0 ++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff ++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0 ++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000 ++#define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10 ++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff ++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0 ++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000 ++#define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10 ++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff ++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0 ++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000 ++#define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10 ++#define KEY_CONTROL__KEY_MODE_MASK 0x6 ++#define KEY_CONTROL__KEY_MODE__SHIFT 0x1 ++#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff ++#define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0 ++#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000 ++#define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10 ++#define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff ++#define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0 ++#define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000 ++#define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10 ++#define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff ++#define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0 ++#define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000 ++#define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10 ++#define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff ++#define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0 ++#define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000 ++#define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10 ++#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3 ++#define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0 ++#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300 ++#define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8 ++#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000 ++#define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc ++#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3 ++#define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0 ++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff ++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0 ++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000 ++#define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10 ++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff ++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0 ++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000 ++#define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10 ++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff ++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0 ++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000 ++#define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10 ++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff ++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0 ++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000 ++#define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10 ++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff ++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0 ++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000 ++#define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10 ++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff ++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0 ++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000 ++#define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10 ++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1 ++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0 ++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30 ++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4 ++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0 ++#define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6 ++#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100 ++#define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8 ++#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200 ++#define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9 ++#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400 ++#define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa ++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff ++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0 ++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000 ++#define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14 ++#define CUR_CONTROL__CURSOR_EN_MASK 0x1 ++#define CUR_CONTROL__CURSOR_EN__SHIFT 0x0 ++#define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10 ++#define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4 ++#define CUR_CONTROL__CURSOR_MODE_MASK 0x300 ++#define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8 ++#define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000 ++#define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10 ++#define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000 ++#define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14 ++#define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000 ++#define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18 ++#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff ++#define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 ++#define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f ++#define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 ++#define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000 ++#define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10 ++#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff ++#define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 ++#define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff ++#define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 ++#define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000 ++#define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 ++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f ++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 ++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000 ++#define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 ++#define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff ++#define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0 ++#define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00 ++#define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8 ++#define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000 ++#define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10 ++#define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff ++#define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0 ++#define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00 ++#define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8 ++#define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000 ++#define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10 ++#define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1 ++#define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0 ++#define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2 ++#define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1 ++#define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000 ++#define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10 ++#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 ++#define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 ++#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000 ++#define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19 ++#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1 ++#define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0 ++#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1 ++#define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 ++#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2 ++#define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1 ++#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0 ++#define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 ++#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000 ++#define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10 ++#define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1 ++#define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0 ++#define DC_LUT_RW_MODE__DC_LUT_ERROR_MASK 0x10000 ++#define DC_LUT_RW_MODE__DC_LUT_ERROR__SHIFT 0x10 ++#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST_MASK 0x20000 ++#define DC_LUT_RW_MODE__DC_LUT_ERROR_RST__SHIFT 0x11 ++#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff ++#define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0 ++#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff ++#define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0 ++#define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff ++#define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0 ++#define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000 ++#define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10 ++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff ++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0 ++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00 ++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa ++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000 ++#define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14 ++#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1 ++#define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0 ++#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7 ++#define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0 ++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1 ++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0 ++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2 ++#define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1 ++#define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf ++#define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0 ++#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10 ++#define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4 ++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20 ++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5 ++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0 ++#define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6 ++#define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00 ++#define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8 ++#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000 ++#define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc ++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000 ++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd ++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000 ++#define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe ++#define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000 ++#define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10 ++#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000 ++#define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14 ++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000 ++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15 ++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000 ++#define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16 ++#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff ++#define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 ++#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff ++#define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 ++#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff ++#define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0 ++#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff ++#define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0 ++#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff ++#define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0 ++#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff ++#define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0 ++#define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1 ++#define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0 ++#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c ++#define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2 ++#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300 ++#define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8 ++#define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff ++#define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0 ++#define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff ++#define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0 ++#define DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x1 ++#define DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0 ++#define DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x1e ++#define DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1 ++#define DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x1e0 ++#define DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5 ++#define DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x7fe00 ++#define DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9 ++#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x100000 ++#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14 ++#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x200000 ++#define DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15 ++#define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff ++#define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0 ++#define DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x3f ++#define DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0 ++#define DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0xff00 ++#define DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8 ++#define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff ++#define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0 ++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7 ++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0 ++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8 ++#define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3 ++#define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1 ++#define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0 ++#define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2 ++#define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1 ++#define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4 ++#define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2 ++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000 ++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc ++#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000 ++#define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10 ++#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_MASK 0x60000 ++#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP__SHIFT 0x11 ++#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_MASK 0x80000 ++#define DCP_GSL_CONTROL__DCP_GSL_XDMA_GROUP_UNDERFLOW_EN__SHIFT 0x13 ++#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000 ++#define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18 ++#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000 ++#define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b ++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000 ++#define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c ++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf ++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0 ++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x1f0 ++#define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4 ++#define DCP_DEBUG_SG__DCP_DEBUG_SG_MASK 0xffffffff ++#define DCP_DEBUG_SG__DCP_DEBUG_SG__SHIFT 0x0 ++#define DCP_DEBUG_SG2__DCP_DEBUG_SG2_MASK 0xffffffff ++#define DCP_DEBUG_SG2__DCP_DEBUG_SG2__SHIFT 0x0 ++#define DCP_DVMM_DEBUG__DCP_DVMM_DEBUG_MASK 0xffffffff ++#define DCP_DVMM_DEBUG__DCP_DVMM_DEBUG__SHIFT 0x0 ++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff ++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0 ++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1 ++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0 ++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300 ++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8 ++#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000 ++#define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10 ++#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000 ++#define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11 ++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 ++#define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c ++#define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff ++#define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0 ++#define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7 ++#define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4 ++#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7 ++#define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0 ++#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff ++#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0 ++#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff ++#define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0 ++#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7 ++#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0 ++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff ++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0 ++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000 ++#define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14 ++#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff ++#define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 ++#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff ++#define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0 ++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff ++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0 ++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000 ++#define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10 ++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff ++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0 ++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000 ++#define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14 ++#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff ++#define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 ++#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff ++#define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0 ++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff ++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0 ++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000 ++#define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10 ++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c ++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff ++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 ++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 ++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc ++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 ++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 ++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 ++#define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c ++#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1 ++#define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0 ++#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2 ++#define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1 ++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00 ++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8 ++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff ++#define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000 ++#define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e ++#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK 0x1 ++#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT 0x0 ++#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK 0x1e ++#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT 0x1 ++#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK 0x200 ++#define GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT 0x9 ++#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK 0xffff ++#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT 0x0 ++#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK 0xffff0000 ++#define GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT 0x10 ++#define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7 ++#define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 ++#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70 ++#define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 ++#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100 ++#define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 ++#define DIG_FE_CNTL__DIG_START_MASK 0x400 ++#define DIG_FE_CNTL__DIG_START__SHIFT 0xa ++#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000 ++#define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 ++#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000 ++#define DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c ++#define DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xc0000000 ++#define DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e ++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1 ++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 ++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10 ++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 ++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300 ++#define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 ++#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff ++#define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 ++#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff ++#define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 ++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1 ++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 ++#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2 ++#define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 ++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10 ++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 ++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20 ++#define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 ++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40 ++#define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 ++#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000 ++#define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 ++#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff ++#define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 ++#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000 ++#define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 ++#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1 ++#define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 ++#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 ++#define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 ++#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc ++#define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 ++#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100 ++#define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 ++#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 ++#define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa ++#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000 ++#define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 ++#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 ++#define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 ++#define DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x4000000 ++#define DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a ++#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000 ++#define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d ++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 ++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e ++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 ++#define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f ++#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1 ++#define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0 ++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1 ++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0 ++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10 ++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4 ++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100 ++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8 ++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000 ++#define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc ++#define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1 ++#define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 ++#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x4 ++#define HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 ++#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x8 ++#define HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 ++#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10 ++#define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 ++#define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100 ++#define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 ++#define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200 ++#define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 ++#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000 ++#define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 ++#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000 ++#define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c ++#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1 ++#define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 ++#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000 ++#define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 ++#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000 ++#define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 ++#define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000 ++#define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b ++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30 ++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 ++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100 ++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 ++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000 ++#define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1 ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2 ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30 ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100 ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000 ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000 ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000 ++#define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f ++#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1 ++#define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 ++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10 ++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 ++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20 ++#define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 ++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100 ++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 ++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200 ++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 ++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000 ++#define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 ++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1 ++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0 ++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2 ++#define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1 ++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10 ++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 ++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20 ++#define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 ++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100 ++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 ++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200 ++#define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 ++#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f ++#define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0 ++#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00 ++#define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 ++#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000 ++#define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 ++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1 ++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 ++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2 ++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 ++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10 ++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 ++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20 ++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 ++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000 ++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 ++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000 ++#define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 ++#define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1 ++#define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 ++#define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4 ++#define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 ++#define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10 ++#define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 ++#define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00 ++#define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 ++#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000 ++#define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc ++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1 ++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 ++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2 ++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 ++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00 ++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 ++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000 ++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 ++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000 ++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 ++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000 ++#define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c ++#define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7 ++#define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 ++#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40 ++#define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 ++#define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80 ++#define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 ++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff ++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 ++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00 ++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 ++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000 ++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 ++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000 ++#define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 ++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff ++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 ++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00 ++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 ++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000 ++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 ++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000 ++#define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 ++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff ++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 ++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00 ++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 ++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000 ++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 ++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000 ++#define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 ++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff ++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 ++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00 ++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 ++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000 ++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 ++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000 ++#define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 ++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff ++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 ++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00 ++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 ++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000 ++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 ++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000 ++#define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 ++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff ++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 ++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00 ++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 ++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000 ++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 ++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000 ++#define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 ++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff ++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 ++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00 ++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 ++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000 ++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 ++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000 ++#define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 ++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff ++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 ++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00 ++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 ++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000 ++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 ++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000 ++#define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x6000 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x8000 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0xf ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000 ++#define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f ++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x7f ++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0 ++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x80 ++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x7 ++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00 ++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8 ++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000 ++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc ++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000 ++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe ++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000 ++#define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10 ++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff ++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0 ++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000 ++#define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10 ++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff ++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0 ++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000 ++#define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18 ++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff ++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 ++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00 ++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 ++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000 ++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 ++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000 ++#define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 ++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff ++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 ++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300 ++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 ++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000 ++#define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc ++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff ++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 ++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00 ++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 ++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000 ++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 ++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000 ++#define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 ++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff ++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 ++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00 ++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 ++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000 ++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 ++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000 ++#define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 ++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff ++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 ++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00 ++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 ++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000 ++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 ++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000 ++#define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 ++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff ++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 ++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00 ++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 ++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000 ++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 ++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000 ++#define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 ++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff ++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 ++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00 ++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 ++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000 ++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 ++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000 ++#define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 ++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff ++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 ++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00 ++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 ++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000 ++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 ++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000 ++#define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 ++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff ++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 ++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00 ++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 ++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000 ++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 ++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000 ++#define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 ++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff ++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 ++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00 ++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 ++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000 ++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 ++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000 ++#define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 ++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff ++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 ++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00 ++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 ++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000 ++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 ++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000 ++#define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 ++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1 ++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 ++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2 ++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 ++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10 ++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 ++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20 ++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 ++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000 ++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 ++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000 ++#define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 ++#define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000 ++#define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc ++#define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff ++#define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 ++#define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000 ++#define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc ++#define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff ++#define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 ++#define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000 ++#define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc ++#define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff ++#define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 ++#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000 ++#define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc ++#define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff ++#define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 ++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff ++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 ++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700 ++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 ++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800 ++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb ++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000 ++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 ++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000 ++#define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 ++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff ++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 ++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800 ++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb ++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000 ++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf ++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000 ++#define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 ++#define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1 ++#define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 ++#define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2 ++#define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 ++#define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4 ++#define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 ++#define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38 ++#define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 ++#define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0 ++#define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 ++#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00 ++#define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 ++#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000 ++#define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 ++#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000 ++#define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 ++#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000 ++#define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 ++#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000 ++#define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c ++#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf ++#define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 ++#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0 ++#define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 ++#define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000 ++#define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 ++#define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000 ++#define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 ++#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000 ++#define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 ++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1 ++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 ++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10 ++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 ++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100 ++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 ++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000 ++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc ++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000 ++#define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 ++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff ++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 ++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000 ++#define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f ++#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff ++#define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 ++#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000 ++#define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 ++#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff ++#define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 ++#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff ++#define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 ++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf ++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 ++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 ++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 ++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00 ++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 ++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000 ++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc ++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000 ++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 ++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000 ++#define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 ++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1 ++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 ++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00 ++#define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 ++#define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10 ++#define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 ++#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100 ++#define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 ++#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000 ++#define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 ++#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000 ++#define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1 ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800 ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000 ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000 ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000 ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000 ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000 ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000 ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000 ++#define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f ++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4 ++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2 ++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8 ++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3 ++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000 ++#define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e ++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40 ++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 ++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80 ++#define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 ++#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400 ++#define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa ++#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7 ++#define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 ++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7 ++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 ++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100 ++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 ++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000 ++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc ++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000 ++#define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 ++#define AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x1 ++#define AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 ++#define AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x100 ++#define AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 ++#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x1 ++#define DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 ++#define DIG_BE_CNTL__DIG_SWAP_MASK 0x2 ++#define DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 ++#define DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x4 ++#define DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 ++#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00 ++#define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 ++#define DIG_BE_CNTL__DIG_MODE_MASK 0x70000 ++#define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 ++#define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000 ++#define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c ++#define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1 ++#define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 ++#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100 ++#define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 ++#define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1 ++#define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 ++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1 ++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 ++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2 ++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 ++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4 ++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 ++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8 ++#define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 ++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3 ++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 ++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300 ++#define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 ++#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3 ++#define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 ++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff ++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 ++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000 ++#define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 ++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff ++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 ++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000 ++#define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 ++#define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1 ++#define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0 ++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100 ++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8 ++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200 ++#define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9 ++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000 ++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10 ++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000 ++#define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11 ++#define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000 ++#define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18 ++#define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000 ++#define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19 ++#define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1 ++#define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 ++#define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100 ++#define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 ++#define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000 ++#define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 ++#define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000 ++#define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 ++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1 ++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 ++#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70 ++#define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 ++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100 ++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 ++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000 ++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 ++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000 ++#define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000 ++#define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000 ++#define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c ++#define DIG_VERSION__DIG_TYPE_MASK 0x1 ++#define DIG_VERSION__DIG_TYPE__SHIFT 0x0 ++#define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1 ++#define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 ++#define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2 ++#define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 ++#define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4 ++#define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 ++#define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8 ++#define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 ++#define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100 ++#define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 ++#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX_MASK 0xff ++#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DIG_TEST_DEBUG_INDEX__DIG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DIG_TEST_DEBUG_DATA__DIG_TEST_DEBUG_DATA__SHIFT 0x0 ++#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX_MASK 0xff ++#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DIG_FE_TEST_DEBUG_INDEX__DIG_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DIG_FE_TEST_DEBUG_DATA__DIG_FE_TEST_DEBUG_DATA__SHIFT 0x0 ++#define DMCU_CTRL__RESET_UC_MASK 0x1 ++#define DMCU_CTRL__RESET_UC__SHIFT 0x0 ++#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2 ++#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 ++#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4 ++#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 ++#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8 ++#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 ++#define DMCU_CTRL__DMCU_ENABLE_MASK 0x10 ++#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 ++#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x100 ++#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8 ++#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffff0000 ++#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10 ++#define DMCU_STATUS__UC_IN_RESET_MASK 0x1 ++#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 ++#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2 ++#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 ++#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4 ++#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 ++#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff ++#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 ++#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00 ++#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 ++#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff ++#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 ++#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00 ++#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 ++#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff ++#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 ++#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00 ++#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 ++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff ++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 ++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00 ++#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 ++#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff ++#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 ++#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff ++#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 ++#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1 ++#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 ++#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2 ++#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 ++#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4 ++#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 ++#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8 ++#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 ++#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10 ++#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 ++#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20 ++#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 ++#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff ++#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 ++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000 ++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 ++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000 ++#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 ++#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff ++#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 ++#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff ++#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 ++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000 ++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 ++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000 ++#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 ++#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff ++#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 ++#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff ++#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 ++#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff ++#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 ++#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff ++#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 ++#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff ++#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 ++#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1 ++#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 ++#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000 ++#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 ++#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000 ++#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000 ++#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000 ++#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 ++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1 ++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 ++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1 ++#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 ++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2 ++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 ++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2 ++#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 ++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4 ++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 ++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4 ++#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 ++#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8 ++#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED_MASK 0x10 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_OCCURRED__SHIFT 0x4 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR_MASK 0x10 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_UP_INT_CLEAR__SHIFT 0x4 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED_MASK 0x20 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR_MASK 0x20 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR__SHIFT 0x5 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED_MASK 0x40 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED__SHIFT 0x6 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR_MASK 0x40 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR__SHIFT 0x6 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED_MASK 0x80 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR_MASK 0x80 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR__SHIFT 0x7 ++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100 ++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 ++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100 ++#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 ++#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200 ++#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 ++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400 ++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa ++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400 ++#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa ++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800 ++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb ++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800 ++#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000 ++#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 ++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 ++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 ++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000 ++#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 ++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000 ++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 ++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000 ++#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 ++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000 ++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a ++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 ++#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a ++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000 ++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b ++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000 ++#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b ++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000 ++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c ++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000 ++#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c ++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000 ++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d ++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000 ++#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d ++#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_OCCURRED_MASK 0x40000000 ++#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_OCCURRED__SHIFT 0x1e ++#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_CLEAR_MASK 0x40000000 ++#define DMCU_INTERRUPT_STATUS__DCFEV0_VBLANK_INT_CLEAR__SHIFT 0x1e ++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1 ++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0 ++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2 ++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1 ++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4 ++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2 ++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200 ++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 ++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400 ++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa ++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800 ++#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN_MASK 0x10 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN__SHIFT 0x4 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN_MASK 0x20 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x5 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x40 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x80 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x200 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x400 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x800 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCFEV0_VBLANK_INT_TO_UC_EN_MASK 0x80000000 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCFEV0_VBLANK_INT_TO_UC_EN__SHIFT 0x1f ++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN_MASK 0x1 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN_MASK 0x2 ++#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x1 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x20 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x5 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x200 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x400 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x800 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL_MASK 0x80000000 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL__SHIFT 0x1f ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x2 ++#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x1 ++#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff ++#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 ++#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff ++#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 ++#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00 ++#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 ++#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000 ++#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 ++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3 ++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 ++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc ++#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 ++#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7 ++#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 ++#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700 ++#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 ++#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000 ++#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 ++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff ++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 ++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00 ++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 ++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000 ++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 ++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000 ++#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 ++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff ++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 ++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00 ++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 ++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000 ++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 ++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000 ++#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 ++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff ++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 ++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00 ++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 ++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000 ++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 ++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000 ++#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 ++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff ++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 ++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00 ++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 ++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000 ++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 ++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000 ++#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 ++#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 ++#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 ++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff ++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 ++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00 ++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 ++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000 ++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 ++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000 ++#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 ++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff ++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 ++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00 ++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 ++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000 ++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 ++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000 ++#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 ++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff ++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 ++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00 ++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 ++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000 ++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 ++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000 ++#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 ++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff ++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 ++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00 ++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 ++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000 ++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 ++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000 ++#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 ++#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1 ++#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 ++#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100 ++#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 ++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff ++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__WB_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_STATUS4__DCRX_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x100 ++#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x8 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x1 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x1 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x2 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x2 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x4 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x4 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x8 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x8 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x10 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x10 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x20 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x20 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x40 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x40 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x80 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x80 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x100 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x100 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x200 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x200 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x400 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x400 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x800 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x800 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x1000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x1000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x2000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x2000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x4000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x4000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x8000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x8000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x10000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x10000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x20000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x20000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x40000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x40000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x80000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x80000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x100000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x100000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x200000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x200000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x400000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x400000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x800000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x800000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x1000000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x1000000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x2000000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x2000000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x4000000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x4000000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x8000000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x8000000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000 ++#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x1 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x2 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x4 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x8 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x10 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x20 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x40 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x80 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x100 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x200 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x400 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x800 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x1000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x2000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x4000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x8000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x10000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x20000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x40000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x80000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x100000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x200000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x400000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x800000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x1000000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x2000000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x4000000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x8000000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x1 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x2 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x4 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x8 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x10 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x20 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x40 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x80 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x100 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x200 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x400 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x800 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x1000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x2000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x4000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x8000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x10000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x20000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x40000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x80000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x100000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x200000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x400000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x800000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x1000000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x2000000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x4000000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x8000000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000 ++#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c ++#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10 ++#define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 ++#define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100 ++#define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 ++#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000 ++#define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 ++#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7 ++#define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 ++#define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100 ++#define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8 ++#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000 ++#define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10 ++#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000 ++#define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 ++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff ++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0 ++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100 ++#define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8 ++#define DP_CONFIG__DP_UDI_LANES_MASK 0x3 ++#define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 ++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1 ++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 ++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300 ++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 ++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000 ++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 ++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000 ++#define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 ++#define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1 ++#define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 ++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10 ++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 ++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20 ++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 ++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40 ++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 ++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80 ++#define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 ++#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100 ++#define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 ++#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000 ++#define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc ++#define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78 ++#define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3 ++#define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00 ++#define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 ++#define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000 ++#define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 ++#define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000 ++#define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 ++#define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1 ++#define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0 ++#define DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x10 ++#define DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 ++#define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100 ++#define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 ++#define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000 ++#define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 ++#define DP_VID_N__DP_VID_N_MASK 0xffffff ++#define DP_VID_N__DP_VID_N__SHIFT 0x0 ++#define DP_VID_M__DP_VID_M_MASK 0xffffff ++#define DP_VID_M__DP_VID_M__SHIFT 0x0 ++#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff ++#define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 ++#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000 ++#define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 ++#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000 ++#define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c ++#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1 ++#define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 ++#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff ++#define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 ++#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000 ++#define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10 ++#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000 ++#define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 ++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1 ++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 ++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2 ++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 ++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4 ++#define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 ++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1 ++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 ++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2 ++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 ++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4 ++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 ++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8 ++#define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 ++#define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000 ++#define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 ++#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000 ++#define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 ++#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3 ++#define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 ++#define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff ++#define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 ++#define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00 ++#define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa ++#define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000 ++#define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 ++#define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff ++#define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 ++#define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00 ++#define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa ++#define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000 ++#define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 ++#define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff ++#define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 ++#define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00 ++#define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa ++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100 ++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 ++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000 ++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 ++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000 ++#define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 ++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1 ++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 ++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30 ++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 ++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00 ++#define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 ++#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x3ff ++#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 ++#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x8000 ++#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf ++#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x10000 ++#define DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 ++#define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1 ++#define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 ++#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10 ++#define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 ++#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100 ++#define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 ++#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1 ++#define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 ++#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30 ++#define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 ++#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000 ++#define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 ++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff ++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 ++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00 ++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 ++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000 ++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 ++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000 ++#define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 ++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f ++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 ++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00 ++#define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 ++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1 ++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 ++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100 ++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 ++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000 ++#define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 ++#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1 ++#define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 ++#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2 ++#define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 ++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4 ++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 ++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00 ++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 ++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000 ++#define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 ++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7 ++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 ++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10 ++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 ++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100 ++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 ++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000 ++#define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc ++#define DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x7 ++#define DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 ++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1 ++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0 ++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x3fff0 ++#define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4 ++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x3fff ++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0 ++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x3fff0000 ++#define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10 ++#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1 ++#define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 ++#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10 ++#define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 ++#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100 ++#define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 ++#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000 ++#define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc ++#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000 ++#define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 ++#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000 ++#define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 ++#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000 ++#define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 ++#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000 ++#define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 ++#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000 ++#define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 ++#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000 ++#define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18 ++#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000 ++#define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c ++#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1 ++#define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 ++#define DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x10 ++#define DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 ++#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x20 ++#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 ++#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x40 ++#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 ++#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x80 ++#define DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 ++#define DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xffff0000 ++#define DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 ++#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff ++#define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 ++#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 ++#define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 ++#define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff ++#define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 ++#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 ++#define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 ++#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff ++#define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 ++#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000 ++#define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 ++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000 ++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 ++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000 ++#define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 ++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000 ++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c ++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000 ++#define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d ++#define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff ++#define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 ++#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff ++#define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 ++#define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff ++#define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 ++#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff ++#define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 ++#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1 ++#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 ++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe ++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 ++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10 ++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 ++#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00 ++#define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 ++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000 ++#define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 ++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff ++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 ++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000 ++#define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a ++#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1 ++#define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 ++#define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7 ++#define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 ++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00 ++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 ++#define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000 ++#define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 ++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000 ++#define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 ++#define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7 ++#define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 ++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00 ++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 ++#define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000 ++#define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 ++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000 ++#define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 ++#define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7 ++#define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 ++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00 ++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 ++#define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000 ++#define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 ++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000 ++#define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 ++#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3 ++#define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 ++#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100 ++#define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 ++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff ++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 ++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000 ++#define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 ++#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1 ++#define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 ++#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10 ++#define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 ++#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100 ++#define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 ++#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA_MASK 0x10000 ++#define DP_MSE_MISC_CNTL__DP_MSE_OUTPUT_DPDBG_DATA__SHIFT 0x10 ++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff ++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0 ++#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX_MASK 0xff ++#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DP_FE_TEST_DEBUG_INDEX__DP_FE_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DP_FE_TEST_DEBUG_DATA__DP_FE_TEST_DEBUG_DATA__SHIFT 0x0 ++#define AUX_CONTROL__AUX_EN_MASK 0x1 ++#define AUX_CONTROL__AUX_EN__SHIFT 0x0 ++#define AUX_CONTROL__AUX_RESET_MASK 0x10 ++#define AUX_CONTROL__AUX_RESET__SHIFT 0x4 ++#define AUX_CONTROL__AUX_RESET_DONE_MASK 0x20 ++#define AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 ++#define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100 ++#define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 ++#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000 ++#define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc ++#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000 ++#define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 ++#define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000 ++#define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 ++#define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000 ++#define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 ++#define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000 ++#define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 ++#define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000 ++#define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c ++#define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000 ++#define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d ++#define AUX_CONTROL__SPARE_0_MASK 0x40000000 ++#define AUX_CONTROL__SPARE_0__SHIFT 0x1e ++#define AUX_CONTROL__SPARE_1_MASK 0x80000000 ++#define AUX_CONTROL__SPARE_1__SHIFT 0x1f ++#define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1 ++#define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 ++#define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4 ++#define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 ++#define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0 ++#define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 ++#define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000 ++#define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 ++#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3 ++#define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 ++#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc ++#define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 ++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100 ++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 ++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400 ++#define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa ++#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000 ++#define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 ++#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000 ++#define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 ++#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000 ++#define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 ++#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000 ++#define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 ++#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000 ++#define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 ++#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000 ++#define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 ++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1 ++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 ++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2 ++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 ++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4 ++#define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 ++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10 ++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 ++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20 ++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 ++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40 ++#define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 ++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100 ++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 ++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200 ++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 ++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400 ++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa ++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000 ++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc ++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000 ++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd ++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000 ++#define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe ++#define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1 ++#define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 ++#define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2 ++#define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 ++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70 ++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 ++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80 ++#define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 ++#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100 ++#define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 ++#define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200 ++#define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 ++#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400 ++#define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa ++#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800 ++#define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb ++#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000 ++#define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc ++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000 ++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe ++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000 ++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 ++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000 ++#define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 ++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000 ++#define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 ++#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000 ++#define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 ++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000 ++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 ++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000 ++#define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 ++#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000 ++#define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 ++#define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000 ++#define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e ++#define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1 ++#define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 ++#define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2 ++#define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 ++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70 ++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 ++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80 ++#define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 ++#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100 ++#define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 ++#define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200 ++#define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 ++#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400 ++#define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa ++#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800 ++#define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb ++#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000 ++#define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc ++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000 ++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe ++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000 ++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 ++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000 ++#define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 ++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000 ++#define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 ++#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000 ++#define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 ++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000 ++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 ++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000 ++#define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 ++#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000 ++#define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 ++#define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000 ++#define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d ++#define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000 ++#define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e ++#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000 ++#define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f ++#define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1 ++#define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 ++#define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00 ++#define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 ++#define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000 ++#define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 ++#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000 ++#define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f ++#define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00 ++#define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 ++#define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000 ++#define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 ++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1 ++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 ++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30 ++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 ++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000 ++#define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 ++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7 ++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 ++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00 ++#define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 ++#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000 ++#define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000 ++#define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c ++#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff ++#define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 ++#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1 ++#define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 ++#define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70 ++#define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 ++#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000 ++#define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 ++#define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7 ++#define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 ++#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00 ++#define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 ++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000 ++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 ++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000 ++#define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x1 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x10 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0xf00 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0xf000 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x70000 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x100000 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0xc00000 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x3000000 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xf0000000 ++#define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c ++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f ++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 ++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00 ++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 ++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000 ++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 ++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000 ++#define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000 ++#define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000 ++#define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e ++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK 0x1 ++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT 0x0 ++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK 0xff00 ++#define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT 0x8 ++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK 0x3f0000 ++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT 0x10 ++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK 0x80000000 ++#define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT 0x1f ++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK 0x1 ++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT 0x0 ++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK 0xffff0 ++#define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT 0x4 ++#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX_MASK 0xff ++#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define AUX_TEST_DEBUG_INDEX__AUX_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA_MASK 0xffffffff ++#define AUX_TEST_DEBUG_DATA__AUX_TEST_DEBUG_DATA__SHIFT 0x0 ++#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xffffffff ++#define DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 ++#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xffffffff ++#define DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 ++#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xffffffff ++#define DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 ++#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xffffffff ++#define DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 ++#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xffffffff ++#define DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 ++#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xffffffff ++#define DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 ++#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xffffffff ++#define DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 ++#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xffffffff ++#define DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 ++#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xffffffff ++#define DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 ++#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xffffffff ++#define DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 ++#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K_MASK 0xffffffff ++#define DP_AUX_DEBUG_K__DP_AUX_DEBUG_K__SHIFT 0x0 ++#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L_MASK 0xffffffff ++#define DP_AUX_DEBUG_L__DP_AUX_DEBUG_L__SHIFT 0x0 ++#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M_MASK 0xffffffff ++#define DP_AUX_DEBUG_M__DP_AUX_DEBUG_M__SHIFT 0x0 ++#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N_MASK 0xffffffff ++#define DP_AUX_DEBUG_N__DP_AUX_DEBUG_N__SHIFT 0x0 ++#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O_MASK 0xffffffff ++#define DP_AUX_DEBUG_O__DP_AUX_DEBUG_O__SHIFT 0x0 ++#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P_MASK 0xffffffff ++#define DP_AUX_DEBUG_P__DP_AUX_DEBUG_P__SHIFT 0x0 ++#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q_MASK 0xffffffff ++#define DP_AUX_DEBUG_Q__DP_AUX_DEBUG_Q__SHIFT 0x0 ++#define DVO_ENABLE__DVO_ENABLE_MASK 0x1 ++#define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0 ++#define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30 ++#define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4 ++#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7 ++#define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0 ++#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000 ++#define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10 ++#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3 ++#define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0 ++#define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100 ++#define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8 ++#define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1 ++#define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0 ++#define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2 ++#define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1 ++#define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30 ++#define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4 ++#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100 ++#define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8 ++#define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000 ++#define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10 ++#define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000 ++#define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11 ++#define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000 ++#define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12 ++#define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000 ++#define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14 ++#define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000 ++#define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15 ++#define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000 ++#define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16 ++#define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000 ++#define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18 ++#define DVO_CONTROL__DVO_CTL3_MASK 0x80000000 ++#define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f ++#define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000 ++#define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10 ++#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff ++#define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0 ++#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff ++#define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 ++#define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f ++#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX_MASK 0xff ++#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DVO_TEST_DEBUG_INDEX__DVO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DVO_TEST_DEBUG_DATA__DVO_TEST_DEBUG_DATA__SHIFT 0x0 ++#define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1 ++#define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0 ++#define FBC_CNTL__FBC_SRC_SEL_MASK 0xe ++#define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1 ++#define FBC_CNTL__FBC_COMP_CLK_GATE_EN_MASK 0x100 ++#define FBC_CNTL__FBC_COMP_CLK_GATE_EN__SHIFT 0x8 ++#define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000 ++#define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10 ++#define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000 ++#define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19 ++#define FBC_CNTL__FBC_EN_MASK 0x80000000 ++#define FBC_CNTL__FBC_EN__SHIFT 0x1f ++#define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffff ++#define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x0 ++#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff ++#define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0 ++#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f ++#define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0 ++#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80 ++#define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7 ++#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00 ++#define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8 ++#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf ++#define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0 ++#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000 ++#define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10 ++#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000 ++#define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11 ++#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000 ++#define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12 ++#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000 ++#define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13 ++#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000 ++#define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14 ++#define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1 ++#define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0 ++#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100 ++#define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8 ++#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200 ++#define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9 ++#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400 ++#define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa ++#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800 ++#define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb ++#define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000 ++#define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10 ++#define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff ++#define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0 ++#define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00 ++#define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8 ++#define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000 ++#define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10 ++#define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000 ++#define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11 ++#define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000 ++#define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18 ++#define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff ++#define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0 ++#define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff ++#define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0 ++#define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffff ++#define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0 ++#define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffff ++#define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0 ++#define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffff ++#define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0 ++#define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffff ++#define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0 ++#define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffff ++#define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0 ++#define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffff ++#define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0 ++#define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffff ++#define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0 ++#define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffff ++#define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0 ++#define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffff ++#define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0 ++#define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffff ++#define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0 ++#define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffff ++#define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0 ++#define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffff ++#define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0 ++#define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffff ++#define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0 ++#define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffff ++#define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0 ++#define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffff ++#define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0 ++#define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffff ++#define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0 ++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0xfff ++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0 ++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0xfff0000 ++#define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10 ++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0xfff ++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0 ++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0xfff0000 ++#define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10 ++#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000 ++#define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10 ++#define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3 ++#define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0 ++#define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8 ++#define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3 ++#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0 ++#define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4 ++#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300 ++#define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8 ++#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400 ++#define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa ++#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800 ++#define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb ++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0xfff ++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0 ++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000 ++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10 ++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000 ++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11 ++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000 ++#define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f ++#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff ++#define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0 ++#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff ++#define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0 ++#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff ++#define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0 ++#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff ++#define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0 ++#define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3 ++#define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0 ++#define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4 ++#define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2 ++#define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8 ++#define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3 ++#define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0 ++#define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4 ++#define FBC_MISC__FBC_DIVIDE_X_MASK 0x300 ++#define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8 ++#define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400 ++#define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa ++#define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800 ++#define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb ++#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000 ++#define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc ++#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT_MASK 0x2000 ++#define FBC_MISC__FBC_STOP_ON_HFLIP_EVENT__SHIFT 0xd ++#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000 ++#define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10 ++#define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000 ++#define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14 ++#define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000 ++#define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15 ++#define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0x1f000000 ++#define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x18 ++#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN_MASK 0x80000000 ++#define FBC_MISC__FBC_FORCE_DECOMPRESSOR_EN__SHIFT 0x1f ++#define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1 ++#define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0 ++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff ++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff ++#define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0 ++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff ++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 ++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000 ++#define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 ++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff ++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 ++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000 ++#define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 ++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff ++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 ++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000 ++#define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 ++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1 ++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 ++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10 ++#define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 ++#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1 ++#define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 ++#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10 ++#define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4 ++#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0xf00 ++#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 ++#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x3000 ++#define FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc ++#define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x10000 ++#define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 ++#define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x20000 ++#define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x11 ++#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x40000 ++#define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x12 ++#define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000 ++#define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 ++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100 ++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 ++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600 ++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 ++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800 ++#define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb ++#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000 ++#define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd ++#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000 ++#define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe ++#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000 ++#define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf ++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000 ++#define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 ++#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000 ++#define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a ++#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000 ++#define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c ++#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000 ++#define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e ++#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff ++#define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 ++#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000 ++#define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 ++#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff ++#define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 ++#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000 ++#define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 ++#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff ++#define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 ++#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000 ++#define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 ++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x1 ++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x0 ++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x10 ++#define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x4 ++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffff ++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x0 ++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffff ++#define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x0 ++#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1 ++#define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 ++#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000 ++#define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 ++#define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1 ++#define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0 ++#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2 ++#define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1 ++#define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10 ++#define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4 ++#define FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING_MASK 0x20 ++#define FMT_CRC_CNTL__FMT_ONE_SHOT_CRC_PENDING__SHIFT 0x5 ++#define FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN_MASK 0x40 ++#define FMT_CRC_CNTL__FMT_CRC_INCLUDE_OVERSCAN__SHIFT 0x6 ++#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB_MASK 0x100 ++#define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKB__SHIFT 0x8 ++#define FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE_MASK 0x200 ++#define FMT_CRC_CNTL__FMT_CRC_PSR_MODE_ENABLE__SHIFT 0x9 ++#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000 ++#define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc ++#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 ++#define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 ++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000 ++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14 ++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000 ++#define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18 ++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff ++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0 ++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000 ++#define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10 ++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff ++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0 ++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000 ++#define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10 ++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff ++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0 ++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000 ++#define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10 ++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff ++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0 ++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000 ++#define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10 ++#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3 ++#define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0 ++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff ++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff ++#define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0 ++#define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff ++#define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0 ++#define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff ++#define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0 ++#define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff ++#define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0 ++#define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff ++#define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0 ++#define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3 ++#define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 ++#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4 ++#define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2 ++#define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8 ++#define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3 ++#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10 ++#define LB_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4 ++#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20 ++#define LB_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5 ++#define LB_DATA_FORMAT__PREFETCH_MASK 0x1000 ++#define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc ++#define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000 ++#define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18 ++#define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000 ++#define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f ++#define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff ++#define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0 ++#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000 ++#define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 ++#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000 ++#define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14 ++#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff ++#define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0 ++#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff ++#define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0 ++#define LB_VLINE_START_END__VLINE_START_MASK 0x3fff ++#define LB_VLINE_START_END__VLINE_START__SHIFT 0x0 ++#define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000 ++#define LB_VLINE_START_END__VLINE_END__SHIFT 0x10 ++#define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000 ++#define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f ++#define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff ++#define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0 ++#define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000 ++#define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10 ++#define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000 ++#define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f ++#define LB_V_COUNTER__V_COUNTER_MASK 0x7fff ++#define LB_V_COUNTER__V_COUNTER__SHIFT 0x0 ++#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff ++#define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0 ++#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1 ++#define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0 ++#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10 ++#define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4 ++#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100 ++#define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8 ++#define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1 ++#define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0 ++#define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10 ++#define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4 ++#define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000 ++#define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc ++#define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000 ++#define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10 ++#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000 ++#define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11 ++#define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1 ++#define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0 ++#define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10 ++#define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4 ++#define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000 ++#define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc ++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000 ++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10 ++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000 ++#define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11 ++#define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1 ++#define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0 ++#define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10 ++#define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4 ++#define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000 ++#define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc ++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000 ++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10 ++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000 ++#define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11 ++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3 ++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0 ++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10 ++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4 ++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00 ++#define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8 ++#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000 ++#define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16 ++#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0 ++#define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4 ++#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0 ++#define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4 ++#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0 ++#define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4 ++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1 ++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0 ++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100 ++#define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8 ++#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0 ++#define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4 ++#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0 ++#define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4 ++#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0 ++#define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4 ++#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0 ++#define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4 ++#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0 ++#define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4 ++#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0 ++#define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4 ++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f ++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0 ++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00 ++#define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa ++#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000 ++#define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10 ++#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000 ++#define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c ++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff ++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0 ++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000 ++#define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10 ++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff ++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0 ++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000 ++#define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10 ++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf ++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0 ++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10 ++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4 ++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100 ++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8 ++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000 ++#define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc ++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000 ++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10 ++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000 ++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14 ++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000 ++#define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18 ++#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1 ++#define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0 ++#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3 ++#define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0 ++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf ++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0 ++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10 ++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4 ++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100 ++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8 ++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000 ++#define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc ++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3 ++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0 ++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00 ++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8 ++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000 ++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18 ++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000 ++#define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e ++#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3 ++#define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0 ++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100 ++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8 ++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000 ++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc ++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000 ++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10 ++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000 ++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14 ++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000 ++#define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c ++#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000 ++#define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f ++#define LB_DEBUG__LB_DEBUG_MASK 0xffffffff ++#define LB_DEBUG__LB_DEBUG__SHIFT 0x0 ++#define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff ++#define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0 ++#define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff ++#define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0 ++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff ++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff ++#define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0 ++#define LBV_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3 ++#define LBV_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 ++#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4 ++#define LBV_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2 ++#define LBV_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8 ++#define LBV_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3 ++#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE_MASK 0x10 ++#define LBV_DATA_FORMAT__PIXEL_REDUCE_MODE__SHIFT 0x4 ++#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH_MASK 0x20 ++#define LBV_DATA_FORMAT__DYNAMIC_PIXEL_DEPTH__SHIFT 0x5 ++#define LBV_DATA_FORMAT__DITHER_EN_MASK 0x40 ++#define LBV_DATA_FORMAT__DITHER_EN__SHIFT 0x6 ++#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN_MASK 0x80 ++#define LBV_DATA_FORMAT__DOWNSCALE_PREFETCH_EN__SHIFT 0x7 ++#define LBV_DATA_FORMAT__PREFETCH_MASK 0x1000 ++#define LBV_DATA_FORMAT__PREFETCH__SHIFT 0xc ++#define LBV_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000 ++#define LBV_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18 ++#define LBV_DATA_FORMAT__ALPHA_EN_MASK 0x80000000 ++#define LBV_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f ++#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff ++#define LBV_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0 ++#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000 ++#define LBV_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 ++#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000 ++#define LBV_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14 ++#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff ++#define LBV_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0 ++#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff ++#define LBV_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0 ++#define LBV_VLINE_START_END__VLINE_START_MASK 0x3fff ++#define LBV_VLINE_START_END__VLINE_START__SHIFT 0x0 ++#define LBV_VLINE_START_END__VLINE_END_MASK 0x7fff0000 ++#define LBV_VLINE_START_END__VLINE_END__SHIFT 0x10 ++#define LBV_VLINE_START_END__VLINE_INV_MASK 0x80000000 ++#define LBV_VLINE_START_END__VLINE_INV__SHIFT 0x1f ++#define LBV_VLINE2_START_END__VLINE2_START_MASK 0x3fff ++#define LBV_VLINE2_START_END__VLINE2_START__SHIFT 0x0 ++#define LBV_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000 ++#define LBV_VLINE2_START_END__VLINE2_END__SHIFT 0x10 ++#define LBV_VLINE2_START_END__VLINE2_INV_MASK 0x80000000 ++#define LBV_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f ++#define LBV_V_COUNTER__V_COUNTER_MASK 0x7fff ++#define LBV_V_COUNTER__V_COUNTER__SHIFT 0x0 ++#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff ++#define LBV_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0 ++#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA_MASK 0x7fff ++#define LBV_V_COUNTER_CHROMA__V_COUNTER_CHROMA__SHIFT 0x0 ++#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA_MASK 0x7fff ++#define LBV_SNAPSHOT_V_COUNTER_CHROMA__SNAPSHOT_V_COUNTER_CHROMA__SHIFT 0x0 ++#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1 ++#define LBV_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0 ++#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10 ++#define LBV_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4 ++#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100 ++#define LBV_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8 ++#define LBV_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1 ++#define LBV_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0 ++#define LBV_VLINE_STATUS__VLINE_ACK_MASK 0x10 ++#define LBV_VLINE_STATUS__VLINE_ACK__SHIFT 0x4 ++#define LBV_VLINE_STATUS__VLINE_STAT_MASK 0x1000 ++#define LBV_VLINE_STATUS__VLINE_STAT__SHIFT 0xc ++#define LBV_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000 ++#define LBV_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10 ++#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000 ++#define LBV_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11 ++#define LBV_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1 ++#define LBV_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0 ++#define LBV_VLINE2_STATUS__VLINE2_ACK_MASK 0x10 ++#define LBV_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4 ++#define LBV_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000 ++#define LBV_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc ++#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000 ++#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10 ++#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000 ++#define LBV_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11 ++#define LBV_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1 ++#define LBV_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0 ++#define LBV_VBLANK_STATUS__VBLANK_ACK_MASK 0x10 ++#define LBV_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4 ++#define LBV_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000 ++#define LBV_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc ++#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000 ++#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10 ++#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000 ++#define LBV_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11 ++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3 ++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0 ++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10 ++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4 ++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00 ++#define LBV_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8 ++#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000 ++#define LBV_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16 ++#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0 ++#define LBV_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4 ++#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0 ++#define LBV_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4 ++#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0 ++#define LBV_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4 ++#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1 ++#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0 ++#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100 ++#define LBV_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8 ++#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0 ++#define LBV_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4 ++#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0 ++#define LBV_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4 ++#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0 ++#define LBV_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4 ++#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0 ++#define LBV_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4 ++#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0 ++#define LBV_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4 ++#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0 ++#define LBV_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4 ++#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f ++#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0 ++#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00 ++#define LBV_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa ++#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000 ++#define LBV_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10 ++#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000 ++#define LBV_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c ++#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff ++#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0 ++#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000 ++#define LBV_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10 ++#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff ++#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0 ++#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000 ++#define LBV_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10 ++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf ++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0 ++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10 ++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4 ++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100 ++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8 ++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000 ++#define LBV_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc ++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000 ++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10 ++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000 ++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14 ++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000 ++#define LBV_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18 ++#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1 ++#define LBV_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0 ++#define LBV_DEBUG__LB_DEBUG_MASK 0xffffffff ++#define LBV_DEBUG__LB_DEBUG__SHIFT 0x0 ++#define LBV_DEBUG2__LB_DEBUG2_MASK 0xffffffff ++#define LBV_DEBUG2__LB_DEBUG2__SHIFT 0x0 ++#define LBV_DEBUG3__LB_DEBUG3_MASK 0xffffffff ++#define LBV_DEBUG3__LB_DEBUG3__SHIFT 0x0 ++#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff ++#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define LBV_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff ++#define LBV_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0 ++#define MVP_CONTROL1__MVP_EN_MASK 0x1 ++#define MVP_CONTROL1__MVP_EN__SHIFT 0x0 ++#define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70 ++#define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4 ++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100 ++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8 ++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200 ++#define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9 ++#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400 ++#define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa ++#define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000 ++#define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc ++#define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000 ++#define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10 ++#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000 ++#define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14 ++#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000 ++#define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18 ++#define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000 ++#define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c ++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000 ++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e ++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000 ++#define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f ++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1 ++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0 ++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10 ++#define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4 ++#define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100 ++#define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8 ++#define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000 ++#define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc ++#define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000 ++#define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10 ++#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000 ++#define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14 ++#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000 ++#define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18 ++#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000 ++#define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c ++#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff ++#define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0 ++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00 ++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8 ++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000 ++#define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10 ++#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff ++#define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0 ++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100 ++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8 ++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000 ++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc ++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000 ++#define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10 ++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000 ++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14 ++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000 ++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18 ++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000 ++#define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c ++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000 ++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e ++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000 ++#define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f ++#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff ++#define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0 ++#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000 ++#define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10 ++#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1 ++#define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0 ++#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10 ++#define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4 ++#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00 ++#define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8 ++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff ++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0 ++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00 ++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa ++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000 ++#define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14 ++#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff ++#define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0 ++#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00 ++#define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8 ++#define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000 ++#define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10 ++#define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000 ++#define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c ++#define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000 ++#define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d ++#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000 ++#define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e ++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff ++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0 ++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000 ++#define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10 ++#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff ++#define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0 ++#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1 ++#define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0 ++#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10 ++#define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4 ++#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100 ++#define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8 ++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000 ++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc ++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000 ++#define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10 ++#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000 ++#define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14 ++#define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000 ++#define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18 ++#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000 ++#define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c ++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff ++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0 ++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000 ++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10 ++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000 ++#define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f ++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff ++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0 ++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000 ++#define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f ++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1 ++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0 ++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2 ++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1 ++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4 ++#define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2 ++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8 ++#define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3 ++#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10 ++#define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4 ++#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20 ++#define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5 ++#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40 ++#define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6 ++#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80 ++#define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7 ++#define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00 ++#define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8 ++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff ++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff ++#define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0 ++#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x6 ++#define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 ++#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x6 ++#define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 ++#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1 ++#define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0 ++#define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe ++#define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1 ++#define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1 ++#define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0 ++#define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe ++#define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1 ++#define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000 ++#define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19 ++#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000 ++#define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a ++#define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000 ++#define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b ++#define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7 ++#define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0 ++#define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38 ++#define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3 ++#define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0 ++#define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6 ++#define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200 ++#define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9 ++#define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400 ++#define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa ++#define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800 ++#define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb ++#define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000 ++#define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc ++#define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000 ++#define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd ++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000 ++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe ++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000 ++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf ++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000 ++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10 ++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000 ++#define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11 ++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000 ++#define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12 ++#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000 ++#define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13 ++#define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000 ++#define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14 ++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1 ++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0 ++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0 ++#define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2 ++#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8 ++#define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000 ++#define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18 ++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1 ++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0 ++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2 ++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1 ++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc ++#define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2 ++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf ++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0 ++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00 ++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8 ++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000 ++#define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10 ++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff ++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0 ++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 ++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf ++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000 ++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10 ++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 ++#define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f ++#define SCL_MODE__SCL_MODE_MASK 0x3 ++#define SCL_MODE__SCL_MODE__SHIFT 0x0 ++#define SCL_MODE__SCL_PSCL_EN_MASK 0x10 ++#define SCL_MODE__SCL_PSCL_EN__SHIFT 0x4 ++#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7 ++#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0 ++#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00 ++#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8 ++#define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1 ++#define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 ++#define SCL_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10 ++#define SCL_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4 ++#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3 ++#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0 ++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf ++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 ++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00 ++#define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 ++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1 ++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0 ++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000 ++#define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10 ++#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1 ++#define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0 ++#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100 ++#define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 ++#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff ++#define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 ++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff ++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 ++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000 ++#define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 ++#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1 ++#define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0 ++#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100 ++#define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 ++#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff ++#define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 ++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff ++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 ++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000 ++#define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 ++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff ++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 ++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000 ++#define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 ++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff ++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0 ++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 ++#define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10 ++#define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1 ++#define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 ++#define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100 ++#define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8 ++#define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000 ++#define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10 ++#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000 ++#define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18 ++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7 ++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0 ++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10 ++#define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4 ++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700 ++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8 ++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000 ++#define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc ++#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1 ++#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0 ++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1 ++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0 ++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100 ++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8 ++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000 ++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc ++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000 ++#define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 ++#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff ++#define VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0 ++#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000 ++#define VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10 ++#define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff ++#define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0 ++#define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000 ++#define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10 ++#define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff ++#define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0 ++#define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000 ++#define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10 ++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff ++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 ++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000 ++#define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 ++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff ++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 ++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000 ++#define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 ++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1 ++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0 ++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10 ++#define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4 ++#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80 ++#define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7 ++#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff ++#define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0 ++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff ++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0 ++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000 ++#define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10 ++#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1 ++#define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0 ++#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1 ++#define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0 ++#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6 ++#define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1 ++#define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8 ++#define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3 ++#define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff ++#define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0 ++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff ++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff ++#define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 ++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x3 ++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0 ++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x7f00 ++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8 ++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x30000 ++#define SCLV_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10 ++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff ++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0 ++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 ++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf ++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000 ++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10 ++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 ++#define SCLV_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f ++#define SCLV_MODE__SCL_MODE_MASK 0x1 ++#define SCLV_MODE__SCL_MODE__SHIFT 0x0 ++#define SCLV_MODE__SCL_MODE_C_MASK 0x2 ++#define SCLV_MODE__SCL_MODE_C__SHIFT 0x1 ++#define SCLV_MODE__SCL_PSCL_EN_MASK 0x10 ++#define SCLV_MODE__SCL_PSCL_EN__SHIFT 0x4 ++#define SCLV_MODE__SCL_PSCL_EN_C_MASK 0x20 ++#define SCLV_MODE__SCL_PSCL_EN_C__SHIFT 0x5 ++#define SCLV_MODE__SCL_INTERLACE_SOURCE_MASK 0x300 ++#define SCLV_MODE__SCL_INTERLACE_SOURCE__SHIFT 0x8 ++#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7 ++#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0 ++#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x70 ++#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x4 ++#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C_MASK 0x700 ++#define SCLV_TAP_CONTROL__SCL_V_NUM_OF_TAPS_C__SHIFT 0x8 ++#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C_MASK 0x7000 ++#define SCLV_TAP_CONTROL__SCL_H_NUM_OF_TAPS_C__SHIFT 0xc ++#define SCLV_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1 ++#define SCLV_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 ++#define SCLV_CONTROL__SCL_EARLY_EOL_MODE_MASK 0x10 ++#define SCLV_CONTROL__SCL_EARLY_EOL_MODE__SHIFT 0x4 ++#define SCLV_CONTROL__SCL_TOTAL_PHASE_MASK 0x100 ++#define SCLV_CONTROL__SCL_TOTAL_PHASE__SHIFT 0x8 ++#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf ++#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 ++#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00 ++#define SCLV_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 ++#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1 ++#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0 ++#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000 ++#define SCLV_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10 ++#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100 ++#define SCLV_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 ++#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff ++#define SCLV_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 ++#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff ++#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 ++#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000 ++#define SCLV_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 ++#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x3ffffff ++#define SCLV_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 ++#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0xffffff ++#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 ++#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0xf000000 ++#define SCLV_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 ++#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100 ++#define SCLV_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 ++#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff ++#define SCLV_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 ++#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff ++#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 ++#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000 ++#define SCLV_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 ++#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff ++#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 ++#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000 ++#define SCLV_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 ++#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x3ffffff ++#define SCLV_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 ++#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0xffffff ++#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 ++#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x7000000 ++#define SCLV_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 ++#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0xffffff ++#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 ++#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x7000000 ++#define SCLV_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 ++#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff ++#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0 ++#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 ++#define SCLV_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10 ++#define SCLV_UPDATE__SCL_UPDATE_PENDING_MASK 0x1 ++#define SCLV_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 ++#define SCLV_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100 ++#define SCLV_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8 ++#define SCLV_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000 ++#define SCLV_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10 ++#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000 ++#define SCLV_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18 ++#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1 ++#define SCLV_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0 ++#define SCLV_VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff ++#define SCLV_VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0 ++#define SCLV_VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000 ++#define SCLV_VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10 ++#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK 0x3fff ++#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT 0x0 ++#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK 0x3fff0000 ++#define SCLV_VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT 0x10 ++#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x1fff ++#define SCLV_VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0 ++#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x1fff0000 ++#define SCLV_VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10 ++#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C_MASK 0x3fff ++#define SCLV_VIEWPORT_START_C__VIEWPORT_Y_START_C__SHIFT 0x0 ++#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C_MASK 0x3fff0000 ++#define SCLV_VIEWPORT_START_C__VIEWPORT_X_START_C__SHIFT 0x10 ++#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C_MASK 0x3fff ++#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_Y_START_SECONDARY_C__SHIFT 0x0 ++#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C_MASK 0x3fff0000 ++#define SCLV_VIEWPORT_START_SECONDARY_C__VIEWPORT_X_START_SECONDARY_C__SHIFT 0x10 ++#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C_MASK 0x1fff ++#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_HEIGHT_C__SHIFT 0x0 ++#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C_MASK 0x1fff0000 ++#define SCLV_VIEWPORT_SIZE_C__VIEWPORT_WIDTH_C__SHIFT 0x10 ++#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff ++#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 ++#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000 ++#define SCLV_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 ++#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff ++#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 ++#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000 ++#define SCLV_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 ++#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1 ++#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0 ++#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10 ++#define SCLV_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4 ++#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80 ++#define SCLV_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7 ++#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff ++#define SCLV_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0 ++#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff ++#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0 ++#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000 ++#define SCLV_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10 ++#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1 ++#define SCLV_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0 ++#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT_MASK 0xffffff ++#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_FRAC_BOT__SHIFT 0x0 ++#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT_MASK 0xf000000 ++#define SCLV_HORZ_FILTER_INIT_BOT__SCL_H_INIT_INT_BOT__SHIFT 0x18 ++#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C_MASK 0xffffff ++#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_FRAC_BOT_C__SHIFT 0x0 ++#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C_MASK 0xf000000 ++#define SCLV_HORZ_FILTER_INIT_BOT_C__SCL_H_INIT_INT_BOT_C__SHIFT 0x18 ++#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1 ++#define SCLV_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0 ++#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6 ++#define SCLV_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1 ++#define SCLV_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8 ++#define SCLV_DEBUG2__SCL_DEBUG2__SHIFT 0x3 ++#define SCLV_DEBUG__SCL_DEBUG_MASK 0xffffffff ++#define SCLV_DEBUG__SCL_DEBUG__SHIFT 0x0 ++#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff ++#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define SCLV_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff ++#define SCLV_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 ++#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING_MASK 0x1 ++#define COL_MAN_UPDATE__COL_MAN_UPDATE_PENDING__SHIFT 0x0 ++#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN_MASK 0x2 ++#define COL_MAN_UPDATE__COL_MAN_UPDATE_TAKEN__SHIFT 0x1 ++#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK_MASK 0x10000 ++#define COL_MAN_UPDATE__COL_MAN_UPDATE_LOCK__SHIFT 0x10 ++#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 ++#define COL_MAN_UPDATE__COL_MAN_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 ++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE_MASK 0x3 ++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_MODE__SHIFT 0x0 ++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE_MASK 0x300 ++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_INPUT_TYPE__SHIFT 0x8 ++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE_MASK 0x10000 ++#define COL_MAN_INPUT_CSC_CONTROL__INPUT_CSC_CONVERSION_MODE__SHIFT 0x10 ++#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK 0xffff ++#define INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT 0x0 ++#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK 0xffff0000 ++#define INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT 0x10 ++#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK 0xffff ++#define INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT 0x0 ++#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK 0xffff0000 ++#define INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT 0x10 ++#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK 0xffff ++#define INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT 0x0 ++#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK 0xffff0000 ++#define INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT 0x10 ++#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK 0xffff ++#define INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT 0x0 ++#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK 0xffff0000 ++#define INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT 0x10 ++#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK 0xffff ++#define INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT 0x0 ++#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK 0xffff0000 ++#define INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT 0x10 ++#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK 0xffff ++#define INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT 0x0 ++#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK 0xffff0000 ++#define INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT 0x10 ++#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK 0xffff ++#define INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT 0x0 ++#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK 0xffff0000 ++#define INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT 0x10 ++#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK 0xffff ++#define INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT 0x0 ++#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK 0xffff0000 ++#define INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT 0x10 ++#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK 0xffff ++#define INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT 0x0 ++#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK 0xffff0000 ++#define INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT 0x10 ++#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK 0xffff ++#define INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT 0x0 ++#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK 0xffff0000 ++#define INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT 0x10 ++#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK 0xffff ++#define INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT 0x0 ++#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK 0xffff0000 ++#define INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT 0x10 ++#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK 0xffff ++#define INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT 0x0 ++#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK 0xffff0000 ++#define INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT 0x10 ++#define PRESCALE_CONTROL__PRESCALE_MODE_MASK 0x3 ++#define PRESCALE_CONTROL__PRESCALE_MODE__SHIFT 0x0 ++#define PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK 0xffff ++#define PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT 0x0 ++#define PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK 0xffff0000 ++#define PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT 0x10 ++#define PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK 0xffff ++#define PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT 0x0 ++#define PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK 0xffff0000 ++#define PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT 0x10 ++#define PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK 0xffff ++#define PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT 0x0 ++#define PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK 0xffff0000 ++#define PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT 0x10 ++#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE_MASK 0x7 ++#define COL_MAN_OUTPUT_CSC_CONTROL__OUTPUT_CSC_MODE__SHIFT 0x0 ++#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK 0xffff ++#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT 0x0 ++#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK 0xffff0000 ++#define OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT 0x10 ++#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK 0xffff ++#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT 0x0 ++#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK 0xffff0000 ++#define OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT 0x10 ++#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK 0xffff ++#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT 0x0 ++#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK 0xffff0000 ++#define OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT 0x10 ++#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK 0xffff ++#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT 0x0 ++#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK 0xffff0000 ++#define OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT 0x10 ++#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK 0xffff ++#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT 0x0 ++#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK 0xffff0000 ++#define OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT 0x10 ++#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK 0xffff ++#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT 0x0 ++#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK 0xffff0000 ++#define OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT 0x10 ++#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK 0xffff ++#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT 0x0 ++#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK 0xffff0000 ++#define OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT 0x10 ++#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK 0xffff ++#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT 0x0 ++#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK 0xffff0000 ++#define OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT 0x10 ++#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK 0xffff ++#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT 0x0 ++#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK 0xffff0000 ++#define OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT 0x10 ++#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK 0xffff ++#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT 0x0 ++#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK 0xffff0000 ++#define OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT 0x10 ++#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK 0xffff ++#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT 0x0 ++#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK 0xffff0000 ++#define OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT 0x10 ++#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK 0xffff ++#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT 0x0 ++#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK 0xffff0000 ++#define OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT 0x10 ++#define DENORM_CLAMP_CONTROL__DENORM_MODE_MASK 0x3 ++#define DENORM_CLAMP_CONTROL__DENORM_MODE__SHIFT 0x0 ++#define DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT_MASK 0x100 ++#define DENORM_CLAMP_CONTROL__DENORM_10BIT_OUT__SHIFT 0x8 ++#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR_MASK 0xfff ++#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MAX_R_CR__SHIFT 0x0 ++#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR_MASK 0xfff000 ++#define DENORM_CLAMP_RANGE_R_CR__RANGE_CLAMP_MIN_R_CR__SHIFT 0xc ++#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y_MASK 0xfff ++#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MAX_G_Y__SHIFT 0x0 ++#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y_MASK 0xfff000 ++#define DENORM_CLAMP_RANGE_G_Y__RANGE_CLAMP_MIN_G_Y__SHIFT 0xc ++#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB_MASK 0xfff ++#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MAX_B_CB__SHIFT 0x0 ++#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB_MASK 0xfff000 ++#define DENORM_CLAMP_RANGE_B_CB__RANGE_CLAMP_MIN_B_CB__SHIFT 0xc ++#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff ++#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_DATA__SHIFT 0x0 ++#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX_MASK 0x3f00000 ++#define COL_MAN_FP_CONVERTED_FIELD__COL_MAN_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14 ++#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE_MASK 0x3 ++#define GAMMA_CORR_CONTROL__GAMMA_CORR_MODE__SHIFT 0x0 ++#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX_MASK 0xff ++#define GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX__SHIFT 0x0 ++#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA_MASK 0x7ffff ++#define GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA__SHIFT 0x0 ++#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK_MASK 0x7 ++#define GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK__SHIFT 0x0 ++#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_MASK 0x3ffff ++#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START__SHIFT 0x0 ++#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000 ++#define GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14 ++#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff ++#define GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 ++#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END_MASK 0xffff ++#define GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END__SHIFT 0x0 ++#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff ++#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0 ++#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000 ++#define GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10 ++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_MASK 0x3ffff ++#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START__SHIFT 0x0 ++#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000 ++#define GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14 ++#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff ++#define GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 ++#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END_MASK 0xffff ++#define GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END__SHIFT 0x0 ++#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff ++#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0 ++#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000 ++#define GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10 ++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1b ++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0xff ++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 ++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x3800 ++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xb ++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x7f8000 ++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0xf ++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x38000000 ++#define GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1b ++#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED_MASK 0x1 ++#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED__SHIFT 0x0 ++#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK_MASK 0x2 ++#define PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK__SHIFT 0x1 ++#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED_MASK 0x100 ++#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED__SHIFT 0x8 ++#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK_MASK 0x200 ++#define PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK__SHIFT 0x9 ++#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED_MASK 0x10000 ++#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED__SHIFT 0x10 ++#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK_MASK 0x20000 ++#define PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK__SHIFT 0x11 ++#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED_MASK 0x1000000 ++#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED__SHIFT 0x18 ++#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK_MASK 0x2000000 ++#define PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK__SHIFT 0x19 ++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED_MASK 0x1 ++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED__SHIFT 0x0 ++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK_MASK 0x2 ++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK__SHIFT 0x1 ++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED_MASK 0x100 ++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED__SHIFT 0x8 ++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK_MASK 0x200 ++#define OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK__SHIFT 0x9 ++#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_MASK 0x1 ++#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL__SHIFT 0x0 ++#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE_MASK 0x2 ++#define INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE__SHIFT 0x1 ++#define INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX_MASK 0xff ++#define INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX__SHIFT 0x0 ++#define INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR_MASK 0xffff ++#define INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR__SHIFT 0x0 ++#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE_MASK 0xffff ++#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE__SHIFT 0x0 ++#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA_MASK 0xffff0000 ++#define INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA__SHIFT 0x10 ++#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE_MASK 0x3ff ++#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE__SHIFT 0x0 ++#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN_MASK 0xffc00 ++#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN__SHIFT 0xa ++#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED_MASK 0x3ff00000 ++#define INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED__SHIFT 0x14 ++#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE_MASK 0x3 ++#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_MODE__SHIFT 0x0 ++#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN_MASK 0x4000000 ++#define COL_MAN_INPUT_GAMMA_CONTROL1__INPUT_GAMMA_LUT_10BIT_BYPASS_EN__SHIFT 0x1a ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B_MASK 0x1e ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_B__SHIFT 0x1 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN_MASK 0x20 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_SIGNED_EN__SHIFT 0x5 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT_MASK 0xc0 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_B_FORMAT__SHIFT 0x6 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G_MASK 0xf00 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_G__SHIFT 0x8 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN_MASK 0x1000 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_SIGNED_EN__SHIFT 0xc ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT_MASK 0x6000 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_G_FORMAT__SHIFT 0xd ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R_MASK 0x78000 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_INC_R__SHIFT 0xf ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN_MASK 0x80000 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_SIGNED_EN__SHIFT 0x13 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT_MASK 0x300000 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_DATA_R_FORMAT__SHIFT 0x14 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE_MASK 0x400000 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_RW_MODE__SHIFT 0x16 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK_MASK 0x3800000 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_WRITE_EN_MASK__SHIFT 0x17 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE_MASK 0x4000000 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE__SHIFT 0x1a ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x8000000 ++#define COL_MAN_INPUT_GAMMA_CONTROL2__INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x1b ++#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B_MASK 0xffff ++#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B__SHIFT 0x0 ++#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B_MASK 0xffff0000 ++#define INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B__SHIFT 0x10 ++#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G_MASK 0xffff ++#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G__SHIFT 0x0 ++#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G_MASK 0xffff0000 ++#define INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G__SHIFT 0x10 ++#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R_MASK 0xffff ++#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R__SHIFT 0x0 ++#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R_MASK 0xffff0000 ++#define INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R__SHIFT 0x10 ++#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE_MASK 0x1 ++#define COL_MAN_DEBUG_CONTROL__COL_MAN_GLOBAL_PASSTHROUGH_ENABLE__SHIFT 0x0 ++#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX_MASK 0xff ++#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define COL_MAN_TEST_DEBUG_INDEX__COL_MAN_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA_MASK 0xffffffff ++#define COL_MAN_TEST_DEBUG_DATA__COL_MAN_TEST_DEBUG_DATA__SHIFT 0x0 ++#define UNP_GRPH_ENABLE__GRPH_ENABLE_MASK 0x1 ++#define UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0 ++#define UNP_GRPH_CONTROL__GRPH_DEPTH_MASK 0x3 ++#define UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0 ++#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc ++#define UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2 ++#define UNP_GRPH_CONTROL__GRPH_Z_MASK 0x30 ++#define UNP_GRPH_CONTROL__GRPH_Z__SHIFT 0x4 ++#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK 0xc0 ++#define UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT 0x6 ++#define UNP_GRPH_CONTROL__GRPH_FORMAT_MASK 0x700 ++#define UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8 ++#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK 0x1800 ++#define UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT 0xb ++#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK 0xe000 ++#define UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT 0xd ++#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 ++#define UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 ++#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 ++#define UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 ++#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK 0xc0000 ++#define UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT 0x12 ++#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000 ++#define UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14 ++#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000 ++#define UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18 ++#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK 0x60000000 ++#define UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT 0x1d ++#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000 ++#define UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f ++#define UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK 0xc0 ++#define UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT 0x6 ++#define UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK 0x1800 ++#define UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT 0xb ++#define UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK 0xe000 ++#define UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT 0xd ++#define UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK 0xc0000 ++#define UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT 0x12 ++#define UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK 0x60000000 ++#define UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT 0x1d ++#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK 0x7 ++#define UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT 0x0 ++#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3 ++#define UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0 ++#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30 ++#define UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4 ++#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0 ++#define UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6 ++#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300 ++#define UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8 ++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK 0xffffff00 ++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT 0x8 ++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK 0xffffff00 ++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x8 ++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff ++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 ++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff ++#define UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 ++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00 ++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8 ++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00 ++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8 ++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff ++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 ++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff ++#define UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 ++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK 0xffffff00 ++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT 0x8 ++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK 0xffffff00 ++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x8 ++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK 0xff ++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 ++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0xff ++#define UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 ++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK 0xffffff00 ++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT 0x8 ++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK 0xffffff00 ++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT 0x8 ++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK 0xff ++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT 0x0 ++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK 0xff ++#define UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 ++#define UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK 0x7fff ++#define UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT 0x0 ++#define UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK 0x7fff ++#define UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT 0x0 ++#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK 0x3fff ++#define UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT 0x0 ++#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK 0x3fff ++#define UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT 0x0 ++#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK 0x3fff ++#define UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT 0x0 ++#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK 0x3fff ++#define UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT 0x0 ++#define UNP_GRPH_X_START_L__GRPH_X_START_L_MASK 0x3fff ++#define UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT 0x0 ++#define UNP_GRPH_X_START_C__GRPH_X_START_C_MASK 0x3fff ++#define UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT 0x0 ++#define UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK 0x3fff ++#define UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT 0x0 ++#define UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK 0x3fff ++#define UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT 0x0 ++#define UNP_GRPH_X_END_L__GRPH_X_END_L_MASK 0x7fff ++#define UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT 0x0 ++#define UNP_GRPH_X_END_C__GRPH_X_END_C_MASK 0x7fff ++#define UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT 0x0 ++#define UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK 0x7fff ++#define UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT 0x0 ++#define UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK 0x7fff ++#define UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT 0x0 ++#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1 ++#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0 ++#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2 ++#define UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1 ++#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4 ++#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2 ++#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8 ++#define UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3 ++#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000 ++#define UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10 ++#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000 ++#define UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14 ++#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 ++#define UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 ++#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000 ++#define UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c ++#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK 0xff ++#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT 0x0 ++#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK 0xff00 ++#define UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT 0x8 ++#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK 0xffffff00 ++#define UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT 0x8 ++#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK 0xffffff00 ++#define UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT 0x8 ++#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK 0xff ++#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT 0x0 ++#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK 0xff ++#define UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT 0x0 ++#define UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK 0x1 ++#define UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT 0x0 ++#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK 0x1e ++#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT 0x1 ++#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK 0x1e0 ++#define UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT 0x5 ++#define UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK 0x7fe00 ++#define UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT 0x9 ++#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK 0x100000 ++#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT 0x14 ++#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK 0x200000 ++#define UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT 0x15 ++#define UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C_MASK 0x1 ++#define UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C__SHIFT 0x0 ++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C_MASK 0x1e ++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C__SHIFT 0x1 ++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C_MASK 0x1e0 ++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C__SHIFT 0x5 ++#define UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C_MASK 0x7fe00 ++#define UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C__SHIFT 0x9 ++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C_MASK 0x100000 ++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C__SHIFT 0x14 ++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C_MASK 0x200000 ++#define UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C__SHIFT 0x15 ++#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK 0x3f ++#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT 0x0 ++#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK 0xff00 ++#define UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT 0x8 ++#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C_MASK 0x3f ++#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C__SHIFT 0x0 ++#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C_MASK 0xff00 ++#define UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C__SHIFT 0x8 ++#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 ++#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0 ++#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 ++#define UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8 ++#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 ++#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0 ++#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100 ++#define UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x30 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x4 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK 0x100 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT 0x8 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK 0x3000 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT 0xc ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK 0x40000 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT 0x12 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK 0x80000 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT 0x13 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 ++#define UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c ++#define UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK 0x1 ++#define UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT 0x0 ++#define UNP_FLIP_CONTROL__UNP_DEBUG_SG_MASK 0xfffffffc ++#define UNP_FLIP_CONTROL__UNP_DEBUG_SG__SHIFT 0x2 ++#define UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK 0x1 ++#define UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT 0x0 ++#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK 0x1c ++#define UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT 0x2 ++#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK 0x300 ++#define UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT 0x8 ++#define UNP_CRC_MASK__UNP_CRC_MASK_MASK 0xffffffff ++#define UNP_CRC_MASK__UNP_CRC_MASK__SHIFT 0x0 ++#define UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK 0xffffffff ++#define UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT 0x0 ++#define UNP_CRC_LAST__UNP_CRC_LAST_MASK 0xffffffff ++#define UNP_CRC_LAST__UNP_CRC_LAST__SHIFT 0x0 ++#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK 0x1f0 ++#define UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT 0x4 ++#define UNP_HW_ROTATION__ROTATION_ANGLE_MASK 0x7 ++#define UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT 0x0 ++#define UNP_HW_ROTATION__PIXEL_DROP_MASK 0x10 ++#define UNP_HW_ROTATION__PIXEL_DROP__SHIFT 0x4 ++#define UNP_HW_ROTATION__BUFFER_MODE_MASK 0x100 ++#define UNP_HW_ROTATION__BUFFER_MODE__SHIFT 0x8 ++#define UNP_DEBUG__UNP_DEBUG_MASK 0xffffffff ++#define UNP_DEBUG__UNP_DEBUG__SHIFT 0x0 ++#define UNP_DEBUG2__UNP_DEBUG2_MASK 0xffffffff ++#define UNP_DEBUG2__UNP_DEBUG2__SHIFT 0x0 ++#define UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG_MASK 0xffff ++#define UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG__SHIFT 0x0 ++#define UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG_MASK 0xffff0000 ++#define UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG__SHIFT 0x10 ++#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX_MASK 0xff ++#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA_MASK 0xffffffff ++#define UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA__SHIFT 0x0 ++#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1 ++#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 ++#define GENMO_WT__VGA_RAM_EN_MASK 0x2 ++#define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 ++#define GENMO_WT__VGA_CKSEL_MASK 0xc ++#define GENMO_WT__VGA_CKSEL__SHIFT 0x2 ++#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20 ++#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 ++#define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 ++#define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 ++#define GENMO_WT__VGA_VSYNC_POL_MASK 0x80 ++#define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 ++#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1 ++#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 ++#define GENMO_RD__VGA_RAM_EN_MASK 0x2 ++#define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 ++#define GENMO_RD__VGA_CKSEL_MASK 0xc ++#define GENMO_RD__VGA_CKSEL__SHIFT 0x2 ++#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20 ++#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 ++#define GENMO_RD__VGA_HSYNC_POL_MASK 0x40 ++#define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 ++#define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 ++#define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 ++#define GENENB__BLK_IO_BASE_MASK 0xff ++#define GENENB__BLK_IO_BASE__SHIFT 0x0 ++#define GENFC_WT__VSYNC_SEL_W_MASK 0x8 ++#define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 ++#define GENFC_RD__VSYNC_SEL_R_MASK 0x8 ++#define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 ++#define GENS0__SENSE_SWITCH_MASK 0x10 ++#define GENS0__SENSE_SWITCH__SHIFT 0x4 ++#define GENS0__CRT_INTR_MASK 0x80 ++#define GENS0__CRT_INTR__SHIFT 0x7 ++#define GENS1__NO_DISPLAY_MASK 0x1 ++#define GENS1__NO_DISPLAY__SHIFT 0x0 ++#define GENS1__VGA_VSTATUS_MASK 0x8 ++#define GENS1__VGA_VSTATUS__SHIFT 0x3 ++#define GENS1__PIXEL_READ_BACK_MASK 0x30 ++#define GENS1__PIXEL_READ_BACK__SHIFT 0x4 ++#define DAC_DATA__DAC_DATA_MASK 0x3f ++#define DAC_DATA__DAC_DATA__SHIFT 0x0 ++#define DAC_MASK__DAC_MASK_MASK 0xff ++#define DAC_MASK__DAC_MASK__SHIFT 0x0 ++#define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff ++#define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 ++#define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff ++#define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 ++#define SEQ8_IDX__SEQ_IDX_MASK 0x7 ++#define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 ++#define SEQ8_DATA__SEQ_DATA_MASK 0xff ++#define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 ++#define SEQ00__SEQ_RST0B_MASK 0x1 ++#define SEQ00__SEQ_RST0B__SHIFT 0x0 ++#define SEQ00__SEQ_RST1B_MASK 0x2 ++#define SEQ00__SEQ_RST1B__SHIFT 0x1 ++#define SEQ01__SEQ_DOT8_MASK 0x1 ++#define SEQ01__SEQ_DOT8__SHIFT 0x0 ++#define SEQ01__SEQ_SHIFT2_MASK 0x4 ++#define SEQ01__SEQ_SHIFT2__SHIFT 0x2 ++#define SEQ01__SEQ_PCLKBY2_MASK 0x8 ++#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 ++#define SEQ01__SEQ_SHIFT4_MASK 0x10 ++#define SEQ01__SEQ_SHIFT4__SHIFT 0x4 ++#define SEQ01__SEQ_MAXBW_MASK 0x20 ++#define SEQ01__SEQ_MAXBW__SHIFT 0x5 ++#define SEQ02__SEQ_MAP0_EN_MASK 0x1 ++#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 ++#define SEQ02__SEQ_MAP1_EN_MASK 0x2 ++#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 ++#define SEQ02__SEQ_MAP2_EN_MASK 0x4 ++#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 ++#define SEQ02__SEQ_MAP3_EN_MASK 0x8 ++#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 ++#define SEQ03__SEQ_FONT_B1_MASK 0x1 ++#define SEQ03__SEQ_FONT_B1__SHIFT 0x0 ++#define SEQ03__SEQ_FONT_B2_MASK 0x2 ++#define SEQ03__SEQ_FONT_B2__SHIFT 0x1 ++#define SEQ03__SEQ_FONT_A1_MASK 0x4 ++#define SEQ03__SEQ_FONT_A1__SHIFT 0x2 ++#define SEQ03__SEQ_FONT_A2_MASK 0x8 ++#define SEQ03__SEQ_FONT_A2__SHIFT 0x3 ++#define SEQ03__SEQ_FONT_B0_MASK 0x10 ++#define SEQ03__SEQ_FONT_B0__SHIFT 0x4 ++#define SEQ03__SEQ_FONT_A0_MASK 0x20 ++#define SEQ03__SEQ_FONT_A0__SHIFT 0x5 ++#define SEQ04__SEQ_256K_MASK 0x2 ++#define SEQ04__SEQ_256K__SHIFT 0x1 ++#define SEQ04__SEQ_ODDEVEN_MASK 0x4 ++#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 ++#define SEQ04__SEQ_CHAIN_MASK 0x8 ++#define SEQ04__SEQ_CHAIN__SHIFT 0x3 ++#define CRTC8_IDX__VCRTC_IDX_MASK 0x3f ++#define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 ++#define CRTC8_DATA__VCRTC_DATA_MASK 0xff ++#define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 ++#define CRT00__H_TOTAL_MASK 0xff ++#define CRT00__H_TOTAL__SHIFT 0x0 ++#define CRT01__H_DISP_END_MASK 0xff ++#define CRT01__H_DISP_END__SHIFT 0x0 ++#define CRT02__H_BLANK_START_MASK 0xff ++#define CRT02__H_BLANK_START__SHIFT 0x0 ++#define CRT03__H_BLANK_END_MASK 0x1f ++#define CRT03__H_BLANK_END__SHIFT 0x0 ++#define CRT03__H_DE_SKEW_MASK 0x60 ++#define CRT03__H_DE_SKEW__SHIFT 0x5 ++#define CRT03__CR10CR11_R_DIS_B_MASK 0x80 ++#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 ++#define CRT04__H_SYNC_START_MASK 0xff ++#define CRT04__H_SYNC_START__SHIFT 0x0 ++#define CRT05__H_SYNC_END_MASK 0x1f ++#define CRT05__H_SYNC_END__SHIFT 0x0 ++#define CRT05__H_SYNC_SKEW_MASK 0x60 ++#define CRT05__H_SYNC_SKEW__SHIFT 0x5 ++#define CRT05__H_BLANK_END_B5_MASK 0x80 ++#define CRT05__H_BLANK_END_B5__SHIFT 0x7 ++#define CRT06__V_TOTAL_MASK 0xff ++#define CRT06__V_TOTAL__SHIFT 0x0 ++#define CRT07__V_TOTAL_B8_MASK 0x1 ++#define CRT07__V_TOTAL_B8__SHIFT 0x0 ++#define CRT07__V_DISP_END_B8_MASK 0x2 ++#define CRT07__V_DISP_END_B8__SHIFT 0x1 ++#define CRT07__V_SYNC_START_B8_MASK 0x4 ++#define CRT07__V_SYNC_START_B8__SHIFT 0x2 ++#define CRT07__V_BLANK_START_B8_MASK 0x8 ++#define CRT07__V_BLANK_START_B8__SHIFT 0x3 ++#define CRT07__LINE_CMP_B8_MASK 0x10 ++#define CRT07__LINE_CMP_B8__SHIFT 0x4 ++#define CRT07__V_TOTAL_B9_MASK 0x20 ++#define CRT07__V_TOTAL_B9__SHIFT 0x5 ++#define CRT07__V_DISP_END_B9_MASK 0x40 ++#define CRT07__V_DISP_END_B9__SHIFT 0x6 ++#define CRT07__V_SYNC_START_B9_MASK 0x80 ++#define CRT07__V_SYNC_START_B9__SHIFT 0x7 ++#define CRT08__ROW_SCAN_START_MASK 0x1f ++#define CRT08__ROW_SCAN_START__SHIFT 0x0 ++#define CRT08__BYTE_PAN_MASK 0x60 ++#define CRT08__BYTE_PAN__SHIFT 0x5 ++#define CRT09__MAX_ROW_SCAN_MASK 0x1f ++#define CRT09__MAX_ROW_SCAN__SHIFT 0x0 ++#define CRT09__V_BLANK_START_B9_MASK 0x20 ++#define CRT09__V_BLANK_START_B9__SHIFT 0x5 ++#define CRT09__LINE_CMP_B9_MASK 0x40 ++#define CRT09__LINE_CMP_B9__SHIFT 0x6 ++#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80 ++#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 ++#define CRT0A__CURSOR_START_MASK 0x1f ++#define CRT0A__CURSOR_START__SHIFT 0x0 ++#define CRT0A__CURSOR_DISABLE_MASK 0x20 ++#define CRT0A__CURSOR_DISABLE__SHIFT 0x5 ++#define CRT0B__CURSOR_END_MASK 0x1f ++#define CRT0B__CURSOR_END__SHIFT 0x0 ++#define CRT0B__CURSOR_SKEW_MASK 0x60 ++#define CRT0B__CURSOR_SKEW__SHIFT 0x5 ++#define CRT0C__DISP_START_MASK 0xff ++#define CRT0C__DISP_START__SHIFT 0x0 ++#define CRT0D__DISP_START_MASK 0xff ++#define CRT0D__DISP_START__SHIFT 0x0 ++#define CRT0E__CURSOR_LOC_HI_MASK 0xff ++#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 ++#define CRT0F__CURSOR_LOC_LO_MASK 0xff ++#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 ++#define CRT10__V_SYNC_START_MASK 0xff ++#define CRT10__V_SYNC_START__SHIFT 0x0 ++#define CRT11__V_SYNC_END_MASK 0xf ++#define CRT11__V_SYNC_END__SHIFT 0x0 ++#define CRT11__V_INTR_CLR_MASK 0x10 ++#define CRT11__V_INTR_CLR__SHIFT 0x4 ++#define CRT11__V_INTR_EN_MASK 0x20 ++#define CRT11__V_INTR_EN__SHIFT 0x5 ++#define CRT11__SEL5_REFRESH_CYC_MASK 0x40 ++#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 ++#define CRT11__C0T7_WR_ONLY_MASK 0x80 ++#define CRT11__C0T7_WR_ONLY__SHIFT 0x7 ++#define CRT12__V_DISP_END_MASK 0xff ++#define CRT12__V_DISP_END__SHIFT 0x0 ++#define CRT13__DISP_PITCH_MASK 0xff ++#define CRT13__DISP_PITCH__SHIFT 0x0 ++#define CRT14__UNDRLN_LOC_MASK 0x1f ++#define CRT14__UNDRLN_LOC__SHIFT 0x0 ++#define CRT14__ADDR_CNT_BY4_MASK 0x20 ++#define CRT14__ADDR_CNT_BY4__SHIFT 0x5 ++#define CRT14__DOUBLE_WORD_MASK 0x40 ++#define CRT14__DOUBLE_WORD__SHIFT 0x6 ++#define CRT15__V_BLANK_START_MASK 0xff ++#define CRT15__V_BLANK_START__SHIFT 0x0 ++#define CRT16__V_BLANK_END_MASK 0xff ++#define CRT16__V_BLANK_END__SHIFT 0x0 ++#define CRT17__RA0_AS_A13B_MASK 0x1 ++#define CRT17__RA0_AS_A13B__SHIFT 0x0 ++#define CRT17__RA1_AS_A14B_MASK 0x2 ++#define CRT17__RA1_AS_A14B__SHIFT 0x1 ++#define CRT17__VCOUNT_BY2_MASK 0x4 ++#define CRT17__VCOUNT_BY2__SHIFT 0x2 ++#define CRT17__ADDR_CNT_BY2_MASK 0x8 ++#define CRT17__ADDR_CNT_BY2__SHIFT 0x3 ++#define CRT17__WRAP_A15TOA0_MASK 0x20 ++#define CRT17__WRAP_A15TOA0__SHIFT 0x5 ++#define CRT17__BYTE_MODE_MASK 0x40 ++#define CRT17__BYTE_MODE__SHIFT 0x6 ++#define CRT17__CRTC_SYNC_EN_MASK 0x80 ++#define CRT17__CRTC_SYNC_EN__SHIFT 0x7 ++#define CRT18__LINE_CMP_MASK 0xff ++#define CRT18__LINE_CMP__SHIFT 0x0 ++#define CRT1E__GRPH_DEC_RD1_MASK 0x2 ++#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 ++#define CRT1F__GRPH_DEC_RD0_MASK 0xff ++#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 ++#define CRT22__GRPH_LATCH_DATA_MASK 0xff ++#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 ++#define GRPH8_IDX__GRPH_IDX_MASK 0xf ++#define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 ++#define GRPH8_DATA__GRPH_DATA_MASK 0xff ++#define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 ++#define GRA00__GRPH_SET_RESET0_MASK 0x1 ++#define GRA00__GRPH_SET_RESET0__SHIFT 0x0 ++#define GRA00__GRPH_SET_RESET1_MASK 0x2 ++#define GRA00__GRPH_SET_RESET1__SHIFT 0x1 ++#define GRA00__GRPH_SET_RESET2_MASK 0x4 ++#define GRA00__GRPH_SET_RESET2__SHIFT 0x2 ++#define GRA00__GRPH_SET_RESET3_MASK 0x8 ++#define GRA00__GRPH_SET_RESET3__SHIFT 0x3 ++#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1 ++#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 ++#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2 ++#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 ++#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4 ++#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 ++#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8 ++#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 ++#define GRA02__GRPH_CCOMP_MASK 0xf ++#define GRA02__GRPH_CCOMP__SHIFT 0x0 ++#define GRA03__GRPH_ROTATE_MASK 0x7 ++#define GRA03__GRPH_ROTATE__SHIFT 0x0 ++#define GRA03__GRPH_FN_SEL_MASK 0x18 ++#define GRA03__GRPH_FN_SEL__SHIFT 0x3 ++#define GRA04__GRPH_RMAP_MASK 0x3 ++#define GRA04__GRPH_RMAP__SHIFT 0x0 ++#define GRA05__GRPH_WRITE_MODE_MASK 0x3 ++#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 ++#define GRA05__GRPH_READ1_MASK 0x8 ++#define GRA05__GRPH_READ1__SHIFT 0x3 ++#define GRA05__CGA_ODDEVEN_MASK 0x10 ++#define GRA05__CGA_ODDEVEN__SHIFT 0x4 ++#define GRA05__GRPH_OES_MASK 0x20 ++#define GRA05__GRPH_OES__SHIFT 0x5 ++#define GRA05__GRPH_PACK_MASK 0x40 ++#define GRA05__GRPH_PACK__SHIFT 0x6 ++#define GRA06__GRPH_GRAPHICS_MASK 0x1 ++#define GRA06__GRPH_GRAPHICS__SHIFT 0x0 ++#define GRA06__GRPH_ODDEVEN_MASK 0x2 ++#define GRA06__GRPH_ODDEVEN__SHIFT 0x1 ++#define GRA06__GRPH_ADRSEL_MASK 0xc ++#define GRA06__GRPH_ADRSEL__SHIFT 0x2 ++#define GRA07__GRPH_XCARE0_MASK 0x1 ++#define GRA07__GRPH_XCARE0__SHIFT 0x0 ++#define GRA07__GRPH_XCARE1_MASK 0x2 ++#define GRA07__GRPH_XCARE1__SHIFT 0x1 ++#define GRA07__GRPH_XCARE2_MASK 0x4 ++#define GRA07__GRPH_XCARE2__SHIFT 0x2 ++#define GRA07__GRPH_XCARE3_MASK 0x8 ++#define GRA07__GRPH_XCARE3__SHIFT 0x3 ++#define GRA08__GRPH_BMSK_MASK 0xff ++#define GRA08__GRPH_BMSK__SHIFT 0x0 ++#define ATTRX__ATTR_IDX_MASK 0x1f ++#define ATTRX__ATTR_IDX__SHIFT 0x0 ++#define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20 ++#define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5 ++#define ATTRDW__ATTR_DATA_MASK 0xff ++#define ATTRDW__ATTR_DATA__SHIFT 0x0 ++#define ATTRDR__ATTR_DATA_MASK 0xff ++#define ATTRDR__ATTR_DATA__SHIFT 0x0 ++#define ATTR00__ATTR_PAL_MASK 0x3f ++#define ATTR00__ATTR_PAL__SHIFT 0x0 ++#define ATTR01__ATTR_PAL_MASK 0x3f ++#define ATTR01__ATTR_PAL__SHIFT 0x0 ++#define ATTR02__ATTR_PAL_MASK 0x3f ++#define ATTR02__ATTR_PAL__SHIFT 0x0 ++#define ATTR03__ATTR_PAL_MASK 0x3f ++#define ATTR03__ATTR_PAL__SHIFT 0x0 ++#define ATTR04__ATTR_PAL_MASK 0x3f ++#define ATTR04__ATTR_PAL__SHIFT 0x0 ++#define ATTR05__ATTR_PAL_MASK 0x3f ++#define ATTR05__ATTR_PAL__SHIFT 0x0 ++#define ATTR06__ATTR_PAL_MASK 0x3f ++#define ATTR06__ATTR_PAL__SHIFT 0x0 ++#define ATTR07__ATTR_PAL_MASK 0x3f ++#define ATTR07__ATTR_PAL__SHIFT 0x0 ++#define ATTR08__ATTR_PAL_MASK 0x3f ++#define ATTR08__ATTR_PAL__SHIFT 0x0 ++#define ATTR09__ATTR_PAL_MASK 0x3f ++#define ATTR09__ATTR_PAL__SHIFT 0x0 ++#define ATTR0A__ATTR_PAL_MASK 0x3f ++#define ATTR0A__ATTR_PAL__SHIFT 0x0 ++#define ATTR0B__ATTR_PAL_MASK 0x3f ++#define ATTR0B__ATTR_PAL__SHIFT 0x0 ++#define ATTR0C__ATTR_PAL_MASK 0x3f ++#define ATTR0C__ATTR_PAL__SHIFT 0x0 ++#define ATTR0D__ATTR_PAL_MASK 0x3f ++#define ATTR0D__ATTR_PAL__SHIFT 0x0 ++#define ATTR0E__ATTR_PAL_MASK 0x3f ++#define ATTR0E__ATTR_PAL__SHIFT 0x0 ++#define ATTR0F__ATTR_PAL_MASK 0x3f ++#define ATTR0F__ATTR_PAL__SHIFT 0x0 ++#define ATTR10__ATTR_GRPH_MODE_MASK 0x1 ++#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 ++#define ATTR10__ATTR_MONO_EN_MASK 0x2 ++#define ATTR10__ATTR_MONO_EN__SHIFT 0x1 ++#define ATTR10__ATTR_LGRPH_EN_MASK 0x4 ++#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 ++#define ATTR10__ATTR_BLINK_EN_MASK 0x8 ++#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 ++#define ATTR10__ATTR_PANTOPONLY_MASK 0x20 ++#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 ++#define ATTR10__ATTR_PCLKBY2_MASK 0x40 ++#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 ++#define ATTR10__ATTR_CSEL_EN_MASK 0x80 ++#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 ++#define ATTR11__ATTR_OVSC_MASK 0xff ++#define ATTR11__ATTR_OVSC__SHIFT 0x0 ++#define ATTR12__ATTR_MAP_EN_MASK 0xf ++#define ATTR12__ATTR_MAP_EN__SHIFT 0x0 ++#define ATTR12__ATTR_VSMUX_MASK 0x30 ++#define ATTR12__ATTR_VSMUX__SHIFT 0x4 ++#define ATTR13__ATTR_PPAN_MASK 0xf ++#define ATTR13__ATTR_PPAN__SHIFT 0x0 ++#define ATTR14__ATTR_CSEL1_MASK 0x3 ++#define ATTR14__ATTR_CSEL1__SHIFT 0x0 ++#define ATTR14__ATTR_CSEL2_MASK 0xc ++#define ATTR14__ATTR_CSEL2__SHIFT 0x2 ++#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f ++#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 ++#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60 ++#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 ++#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80 ++#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 ++#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100 ++#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 ++#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000 ++#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 ++#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000 ++#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 ++#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000 ++#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 ++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7 ++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 ++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700 ++#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 ++#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1 ++#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 ++#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2 ++#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 ++#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4 ++#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 ++#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8 ++#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 ++#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10 ++#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 ++#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20 ++#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 ++#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100 ++#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 ++#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200 ++#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 ++#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400 ++#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa ++#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800 ++#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb ++#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000 ++#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc ++#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000 ++#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd ++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000 ++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 ++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000 ++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 ++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000 ++#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 ++#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1 ++#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 ++#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30 ++#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 ++#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100 ++#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 ++#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000 ++#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 ++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3 ++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 ++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300 ++#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 ++#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff ++#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 ++#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff ++#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 ++#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff ++#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 ++#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff ++#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 ++#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1 ++#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 ++#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10 ++#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 ++#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100 ++#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 ++#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000 ++#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 ++#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000 ++#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 ++#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1 ++#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 ++#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100 ++#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 ++#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000 ++#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 ++#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000 ++#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 ++#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000 ++#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 ++#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1 ++#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 ++#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100 ++#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 ++#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200 ++#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 ++#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000 ++#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 ++#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000 ++#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 ++#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1 ++#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 ++#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100 ++#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 ++#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200 ++#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 ++#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000 ++#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 ++#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000 ++#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 ++#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1 ++#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 ++#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100 ++#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 ++#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200 ++#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 ++#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000 ++#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 ++#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000 ++#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 ++#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1 ++#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 ++#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100 ++#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 ++#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200 ++#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 ++#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000 ++#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 ++#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000 ++#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 ++#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1 ++#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 ++#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100 ++#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 ++#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200 ++#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 ++#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000 ++#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 ++#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000 ++#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 ++#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1 ++#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 ++#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100 ++#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 ++#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200 ++#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 ++#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000 ++#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 ++#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000 ++#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 ++#define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff ++#define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0 ++#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1 ++#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 ++#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2 ++#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 ++#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4 ++#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 ++#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8 ++#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 ++#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1 ++#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 ++#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100 ++#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 ++#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000 ++#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 ++#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000 ++#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 ++#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1 ++#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 ++#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100 ++#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 ++#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000 ++#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 ++#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000 ++#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 ++#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1 ++#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 ++#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2 ++#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 ++#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4 ++#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 ++#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8 ++#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 ++#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3 ++#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 ++#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18 ++#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 ++#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0 ++#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 ++#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300 ++#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 ++#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0xf000 ++#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc ++#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000 ++#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 ++#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000 ++#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 ++#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000 ++#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a ++#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000 ++#define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b ++#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000 ++#define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c ++#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000 ++#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d ++#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000 ++#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f ++#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1 ++#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 ++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100 ++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 ++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000 ++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 ++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000 ++#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 ++#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff ++#define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0 ++#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff ++#define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0 ++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff ++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 ++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000 ++#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 ++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff ++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 ++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000 ++#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 ++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff ++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff ++#define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0 ++#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff ++#define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 ++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3 ++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0 ++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00 ++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8 ++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000 ++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10 ++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000 ++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18 ++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000 ++#define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c ++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1 ++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0 ++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2 ++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1 ++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4 ++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2 ++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0 ++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4 ++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000 ++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14 ++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000 ++#define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c ++#define PLL_REF_DIV__PLL_REF_DIV_MASK 0x3ff ++#define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x0 ++#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0xf000 ++#define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0xc ++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0xf ++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x0 ++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x30 ++#define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 ++#define PLL_FB_DIV__PLL_FB_DIV_MASK 0xfff0000 ++#define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x10 ++#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x7f ++#define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x0 ++#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x80 ++#define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7 ++#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x7f00 ++#define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x8 ++#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x8000 ++#define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0xf ++#define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x7f0000 ++#define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x10 ++#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0xffff ++#define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x0 ++#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0xff ++#define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0 ++#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0xf00 ++#define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x8 ++#define PLL_SS_CNTL__PLL_SS_EN_MASK 0x1000 ++#define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0xc ++#define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x2000 ++#define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0xd ++#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000 ++#define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x10 ++#define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0xffff ++#define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x0 ++#define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x30000 ++#define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x10 ++#define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x40000 ++#define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x12 ++#define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x80000 ++#define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x13 ++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x1 ++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x0 ++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2 ++#define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x1 ++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x4 ++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2 ++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x8 ++#define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x3 ++#define PLL_IDCLK_CNTL__PLL_IDCLK_EN_MASK 0x10 ++#define PLL_IDCLK_CNTL__PLL_IDCLK_EN__SHIFT 0x4 ++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x100 ++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x8 ++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x1000 ++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0xc ++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0xf0000 ++#define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x10 ++#define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK 0x300000 ++#define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT 0x14 ++#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK 0xc00000 ++#define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT 0x16 ++#define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK 0x3000000 ++#define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT 0x18 ++#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR_MASK 0xc000000 ++#define PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR__SHIFT 0x1a ++#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR_MASK 0x30000000 ++#define PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR__SHIFT 0x1c ++#define PLL_CNTL__PLL_RESET_MASK 0x1 ++#define PLL_CNTL__PLL_RESET__SHIFT 0x0 ++#define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2 ++#define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x1 ++#define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x4 ++#define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2 ++#define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x8 ++#define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3 ++#define PLL_CNTL__PLL_VCOREF_MASK 0x30 ++#define PLL_CNTL__PLL_VCOREF__SHIFT 0x4 ++#define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x40 ++#define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x6 ++#define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x80 ++#define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x7 ++#define PLL_CNTL__PLL_CALREF_MASK 0x300 ++#define PLL_CNTL__PLL_CALREF__SHIFT 0x8 ++#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x400 ++#define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0xa ++#define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x1800 ++#define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0xb ++#define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x2000 ++#define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0xd ++#define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK 0x4000 ++#define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT 0xe ++#define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x70000 ++#define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x10 ++#define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x80000 ++#define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x13 ++#define PLL_CNTL__PLL_CALIB_DONE_MASK 0x100000 ++#define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x14 ++#define PLL_CNTL__PLL_LOCKED_MASK 0x200000 ++#define PLL_CNTL__PLL_LOCKED__SHIFT 0x15 ++#define PLL_CNTL__PLL_REFCLK_RECV_EN_MASK 0x400000 ++#define PLL_CNTL__PLL_REFCLK_RECV_EN__SHIFT 0x16 ++#define PLL_CNTL__PLL_REFCLK_RECV_SEL_MASK 0x800000 ++#define PLL_CNTL__PLL_REFCLK_RECV_SEL__SHIFT 0x17 ++#define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x3000000 ++#define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x18 ++#define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000 ++#define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x1a ++#define PLL_ANALOG__PLL_CAL_MODE_MASK 0x1f ++#define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x0 ++#define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x60 ++#define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x5 ++#define PLL_ANALOG__PLL_CP_MASK 0xf00 ++#define PLL_ANALOG__PLL_CP__SHIFT 0x8 ++#define PLL_ANALOG__PLL_LF_MODE_MASK 0x1ff000 ++#define PLL_ANALOG__PLL_LF_MODE__SHIFT 0xc ++#define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK 0xe00000 ++#define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT 0x15 ++#define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000 ++#define PLL_ANALOG__PLL_IBIAS__SHIFT 0x18 ++#define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0xfffff ++#define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x0 ++#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK 0x300000 ++#define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT 0x14 ++#define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x4000000 ++#define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x1a ++#define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000 ++#define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x1c ++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x1 ++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x0 ++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2 ++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x1 ++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x4 ++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2 ++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x70 ++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x4 ++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK 0x80 ++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT 0x7 ++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK 0x100 ++#define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT 0x8 ++#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x1 ++#define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x0 ++#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0xf0 ++#define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x4 ++#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x1f00 ++#define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x8 ++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK 0xff0000 ++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT 0x10 ++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK 0x7000000 ++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT 0x18 ++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK 0x8000000 ++#define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT 0x1b ++#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x1 ++#define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x0 ++#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x1 ++#define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x0 ++#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x100 ++#define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x8 ++#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x10000 ++#define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x10 ++#define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK 0x1 ++#define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT 0x0 ++#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2 ++#define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT 0x1 ++#define PLL_XOR_LOCK__PLL_SPARE_MASK 0x3f00 ++#define PLL_XOR_LOCK__PLL_SPARE__SHIFT 0x8 ++#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL_MASK 0xf0000 ++#define PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL__SHIFT 0x10 ++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF_MASK 0x700000 ++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF__SHIFT 0x14 ++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB_MASK 0x3800000 ++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB__SHIFT 0x17 ++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS_MASK 0xc000000 ++#define PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS__SHIFT 0x1a ++#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN_MASK 0x10000000 ++#define PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN__SHIFT 0x1c ++#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK 0x1 ++#define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT 0x0 ++#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK 0x1e ++#define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT 0x1 ++#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK 0x1e0 ++#define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT 0x5 ++#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM_MASK 0x3e00 ++#define PLL_ANALOG_CNTL__PLL_REGREF_TRIM__SHIFT 0x9 ++#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV_MASK 0x1c000 ++#define PLL_ANALOG_CNTL__PLL_CALIB_FBDIV__SHIFT 0xe ++#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL_MASK 0x20000 ++#define PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL__SHIFT 0x11 ++#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN_MASK 0x40000 ++#define PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN__SHIFT 0x12 ++#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x3ff ++#define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x0 ++#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x3ff ++#define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x0 ++#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x3ff ++#define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x0 ++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0xf ++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x0 ++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 ++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 ++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x7ff0000 ++#define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x10 ++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0xf ++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x0 ++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 ++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 ++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x7ff0000 ++#define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x10 ++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0xf ++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x0 ++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 ++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 ++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x7ff0000 ++#define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x10 ++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f ++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 ++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 ++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 ++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 ++#define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x10 ++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x7f ++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 ++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 ++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 ++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 ++#define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x10 ++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x7f ++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 ++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 ++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 ++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 ++#define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x10 ++#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x1f ++#define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x0 ++#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x60 ++#define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x5 ++#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0xf00 ++#define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x8 ++#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x1ff000 ++#define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0xc ++#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000 ++#define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x18 ++#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x1f ++#define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x0 ++#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x60 ++#define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x5 ++#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0xf00 ++#define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x8 ++#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x1ff000 ++#define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0xc ++#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000 ++#define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x18 ++#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x1f ++#define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x0 ++#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x60 ++#define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x5 ++#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0xf00 ++#define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x8 ++#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x1ff000 ++#define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0xc ++#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000 ++#define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x18 ++#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x1 ++#define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x0 ++#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0xf0 ++#define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x4 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED_MASK 0x1 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED__SHIFT 0x0 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED_MASK 0x2 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED__SHIFT 0x1 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING_MASK 0x4 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING__SHIFT 0x2 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE_MASK 0x18 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE__SHIFT 0x3 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE_MASK 0x20 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE__SHIFT 0x5 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ_MASK 0x40 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ__SHIFT 0x6 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK_MASK 0x80 ++#define PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK__SHIFT 0x7 ++#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS_MASK 0xffff ++#define PPLL_STATUS_DEBUG__PLL_DEBUG_BUS__SHIFT 0x0 ++#define PPLL_STATUS_DEBUG__PLL_UNLOCK_MASK 0x10000 ++#define PPLL_STATUS_DEBUG__PLL_UNLOCK__SHIFT 0x10 ++#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT_MASK 0x1e0000 ++#define PPLL_STATUS_DEBUG__PLL_CAL_RESULT__SHIFT 0x11 ++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB_MASK 0x1000000 ++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB__SHIFT 0x18 ++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S_MASK 0x2000000 ++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_S__SHIFT 0x19 ++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V_MASK 0x4000000 ++#define PPLL_STATUS_DEBUG__PLL_POWERGOOD_V__SHIFT 0x1a ++#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL_MASK 0x1f ++#define PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL__SHIFT 0x0 ++#define PPLL_SPARE0__PLL_SPARE0_MASK 0xffffffff ++#define PPLL_SPARE0__PLL_SPARE0__SHIFT 0x0 ++#define PPLL_SPARE1__PLL_SPARE1_MASK 0xffffffff ++#define PPLL_SPARE1__PLL_SPARE1__SHIFT 0x0 ++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x7 ++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x0 ++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x70 ++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x4 ++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x700 ++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x8 ++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x7000 ++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0xc ++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x70000 ++#define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x10 ++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x300000 ++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x14 ++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0xc00000 ++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x16 ++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x3000000 ++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x18 ++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0xc000000 ++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x1a ++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000 ++#define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x1c ++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x3 ++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x0 ++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x30 ++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x4 ++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x300 ++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x8 ++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x3000 ++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0xc ++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x30000 ++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x10 ++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x100000 ++#define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x14 ++#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x600000 ++#define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x15 ++#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x1800000 ++#define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x17 ++#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x6000000 ++#define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x19 ++#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000 ++#define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x1b ++#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000 ++#define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x1d ++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x3 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x0 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0xc ++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0xf0 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x4 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0xf00 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x8 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0xf000 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0xc ++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0xf0000 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x10 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x100000 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x14 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x200000 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x15 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x400000 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x16 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x800000 ++#define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x17 ++#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000 ++#define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x18 ++#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000 ++#define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x1f ++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x1f ++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x0 ++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x3e0 ++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x5 ++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x1f000 ++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0xc ++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x3e0000 ++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x11 ++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x7000000 ++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x18 ++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000 ++#define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x1c ++#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x1 ++#define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x0 ++#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2 ++#define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x1 ++#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0xc ++#define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2 ++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0xf00 ++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x8 ++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0xf000 ++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0xc ++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0xf0000 ++#define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x10 ++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0xfffc ++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2 ++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0xfff0000 ++#define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x10 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x1 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x0 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x1 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x4 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x8 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x3 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0xf0 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x4 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x7f00 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x8 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0xff0000 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x10 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x1000000 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x18 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x2000000 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x19 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x4000000 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x1a ++#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000 ++#define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x1c ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x3 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x0 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0xc ++#define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x10 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x4 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x20 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x5 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x6 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x700 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x8 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x800 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0xb ++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x1000 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0xc ++#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x2000 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0xd ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x10000 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x10 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x80000 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x13 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x100000 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x14 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x18 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000 ++#define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x1d ++#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x3ffffff ++#define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x0 ++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0xfff ++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x0 ++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x1000 ++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0xc ++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x2000 ++#define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0xd ++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x1 ++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x0 ++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x30 ++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x4 ++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x40 ++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x6 ++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x100 ++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x8 ++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x10000 ++#define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x10 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x1f ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK 0x1e0 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT 0x5 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK 0x200 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT 0x9 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK 0x400 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT 0xa ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x8000 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0xf ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x10000 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x10 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x20000 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x11 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x1f00000 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x14 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0xe000000 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x19 ++#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW_MASK 0x10000000 ++#define UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW__SHIFT 0x1c ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x1d ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK 0x40000000 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT 0x1e ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK 0x80000000 ++#define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT 0x1f ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x1 ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x0 ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2 ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x1 ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0xf00 ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x8 ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x1f0000 ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x10 ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x1000000 ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x18 ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK 0x2000000 ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT 0x19 ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK 0x4000000 ++#define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT 0x1a ++#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK 0xffff ++#define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT 0x0 ++#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN_MASK 0x1 ++#define UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN__SHIFT 0x0 ++#define UNIPHY_TMDP_REG0__ICALRA_MODE_MASK 0x2 ++#define UNIPHY_TMDP_REG0__ICALRA_MODE__SHIFT 0x1 ++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG_MASK 0x7fc ++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG__SHIFT 0x2 ++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG_MASK 0xff800 ++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG__SHIFT 0xb ++#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL_MASK 0x100000 ++#define UNIPHY_TMDP_REG0__ITXA_TPC_SEL__SHIFT 0x14 ++#define UNIPHY_TMDP_REG0__ITXA_PCALEN_MASK 0x200000 ++#define UNIPHY_TMDP_REG0__ITXA_PCALEN__SHIFT 0x15 ++#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN_MASK 0x400000 ++#define UNIPHY_TMDP_REG0__ITXA_DPPC_PWN__SHIFT 0x16 ++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN_MASK 0x800000 ++#define UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN__SHIFT 0x17 ++#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL_MASK 0x3000000 ++#define UNIPHY_TMDP_REG0__ITXA_TPC_CNTL__SHIFT 0x18 ++#define UNIPHY_TMDP_REG0__ITXA_VSCALEN_MASK 0x4000000 ++#define UNIPHY_TMDP_REG0__ITXA_VSCALEN__SHIFT 0x1a ++#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL_MASK 0x78000000 ++#define UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL__SHIFT 0x1b ++#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN_MASK 0x80000000 ++#define UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN__SHIFT 0x1f ++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST_MASK 0x1f ++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST__SHIFT 0x0 ++#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ_MASK 0x1e0 ++#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ__SHIFT 0x5 ++#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ_MASK 0x1e00 ++#define UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ__SHIFT 0x9 ++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ_MASK 0x1e000 ++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ__SHIFT 0xd ++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN_MASK 0x20000 ++#define UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN__SHIFT 0x11 ++#define UNIPHY_TMDP_REG1__ITXA_IOCNTL_MASK 0xffc0000 ++#define UNIPHY_TMDP_REG1__ITXA_IOCNTL__SHIFT 0x12 ++#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL_MASK 0x10000000 ++#define UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL__SHIFT 0x1c ++#define UNIPHY_TMDP_REG1__ITX_EDPSEL_MASK 0xe0000000 ++#define UNIPHY_TMDP_REG1__ITX_EDPSEL__SHIFT 0x1d ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN_MASK 0x1 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN__SHIFT 0x0 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN_MASK 0x2 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN__SHIFT 0x1 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_MASK 0x3c ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET__SHIFT 0x2 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN_MASK 0x40 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN__SHIFT 0x6 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_MASK 0x3f80 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE__SHIFT 0x7 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET_MASK 0x4000 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET__SHIFT 0xe ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN_MASK 0x10000 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN__SHIFT 0x10 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN_MASK 0x20000 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN__SHIFT 0x11 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_MASK 0x3c0000 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET__SHIFT 0x12 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN_MASK 0x400000 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN__SHIFT 0x16 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_MASK 0x3f800000 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE__SHIFT 0x17 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET_MASK 0x40000000 ++#define UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET__SHIFT 0x1e ++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN_MASK 0x1 ++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN__SHIFT 0x0 ++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN_MASK 0x2 ++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN__SHIFT 0x1 ++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_MASK 0x3c ++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET__SHIFT 0x2 ++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN_MASK 0x40 ++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN__SHIFT 0x6 ++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_MASK 0x3f80 ++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE__SHIFT 0x7 ++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET_MASK 0x4000 ++#define UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET__SHIFT 0xe ++#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ_MASK 0xf8000 ++#define UNIPHY_TMDP_REG3__ITXA_PREM_ADJ__SHIFT 0xf ++#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL_MASK 0x1f00000 ++#define UNIPHY_TMDP_REG3__OTXA_RES_NCAL__SHIFT 0x14 ++#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL_MASK 0x3e000000 ++#define UNIPHY_TMDP_REG3__OTXA_RES_PCAL__SHIFT 0x19 ++#define UNIPHY_TMDP_REG4__RESERVED_MASK 0x3fffff ++#define UNIPHY_TMDP_REG4__RESERVED__SHIFT 0x0 ++#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF_MASK 0x7fc00000 ++#define UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF__SHIFT 0x16 ++#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT_MASK 0x1 ++#define UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT__SHIFT 0x0 ++#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE_MASK 0x2 ++#define UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE__SHIFT 0x1 ++#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT_MASK 0x4 ++#define UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT__SHIFT 0x2 ++#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE_MASK 0x8 ++#define UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE__SHIFT 0x3 ++#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT_MASK 0x10 ++#define UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT__SHIFT 0x4 ++#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE_MASK 0x20 ++#define UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE__SHIFT 0x5 ++#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT_MASK 0x40 ++#define UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT__SHIFT 0x6 ++#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE_MASK 0x80 ++#define UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE__SHIFT 0x7 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_MASK 0x1ff00 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN__SHIFT 0x8 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE_MASK 0x20000 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE__SHIFT 0x11 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR_MASK 0x40000 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR__SHIFT 0x12 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_MASK 0x780000 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP__SHIFT 0x13 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE_MASK 0x800000 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE__SHIFT 0x17 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR_MASK 0x1000000 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR__SHIFT 0x18 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_MASK 0x3e000000 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS__SHIFT 0x19 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE_MASK 0x40000000 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE__SHIFT 0x1e ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR_MASK 0x80000000 ++#define UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR__SHIFT 0x1f ++#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ_MASK 0x1 ++#define UNIPHY_TMDP_REG6__IRXA_OS_ADJ__SHIFT 0x0 ++#define UNIPHY_TMDP_REG6__IRXA_OS_POLB_MASK 0x2 ++#define UNIPHY_TMDP_REG6__IRXA_OS_POLB__SHIFT 0x1 ++#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL_MASK 0x4 ++#define UNIPHY_TMDP_REG6__IRXA_BIST_SEL__SHIFT 0x2 ++#define UNIPHY_TMDP_REG6__IRXA_SENADJ_MASK 0x78 ++#define UNIPHY_TMDP_REG6__IRXA_SENADJ__SHIFT 0x3 ++#define UNIPHY_TMDP_REG6__IRXA_CPSEL_MASK 0x780 ++#define UNIPHY_TMDP_REG6__IRXA_CPSEL__SHIFT 0x7 ++#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x800 ++#define UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0xb ++#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN_MASK 0x3ff ++#define UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN__SHIFT 0x0 ++#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN_MASK 0x10000 ++#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN__SHIFT 0x10 ++#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL_MASK 0xe0000 ++#define UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL__SHIFT 0x11 ++#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED_MASK 0x7fffff ++#define UNIPHY_TPG_SEED__UNIPHY_TPG_SEED__SHIFT 0x0 ++#define UNIPHY_DEBUG__DEBUG0_MASK 0x3ff000 ++#define UNIPHY_DEBUG__DEBUG0__SHIFT 0xc ++#define UNIPHY_DEBUG__DEBUG1_MASK 0x1c00000 ++#define UNIPHY_DEBUG__DEBUG1__SHIFT 0x16 ++#define UNIPHY_DEBUG__DBG_SEL_MASK 0x6000000 ++#define UNIPHY_DEBUG__DBG_SEL__SHIFT 0x19 ++#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff ++#define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 ++#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 ++#define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 ++#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff ++#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 ++#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 ++#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 ++#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3 ++#define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 ++#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300 ++#define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 ++#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000 ++#define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 ++#define DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000 ++#define DPG_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18 ++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff ++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 ++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 ++#define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 ++#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 ++#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 ++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 ++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 ++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 ++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 ++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 ++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc ++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 ++#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 ++#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 ++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 ++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 ++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 ++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 ++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 ++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 ++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 ++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 ++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 ++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa ++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000 ++#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 ++#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb ++#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 ++#define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 ++#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 ++#define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 ++#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff ++#define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 ++#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff ++#define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 ++#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1 ++#define DPG_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0 ++#define DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1 ++#define DPG_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0 ++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff ++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0 ++#define DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff ++#define DPGV0_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 ++#define DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 ++#define DPGV0_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 ++#define DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff ++#define DPGV1_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 ++#define DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 ++#define DPGV1_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 ++#define DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff ++#define DPGV0_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 ++#define DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 ++#define DPGV0_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 ++#define DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff ++#define DPGV1_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 ++#define DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 ++#define DPGV1_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 ++#define DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3 ++#define DPGV0_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 ++#define DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300 ++#define DPGV0_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 ++#define DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000 ++#define DPGV0_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 ++#define DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000 ++#define DPGV0_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18 ++#define DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3 ++#define DPGV1_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 ++#define DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300 ++#define DPGV1_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 ++#define DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000 ++#define DPGV1_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 ++#define DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT_MASK 0x1000000 ++#define DPGV1_WATERMARK_MASK_CONTROL__DISABLE_FLIP_URGENT__SHIFT 0x18 ++#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff ++#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 ++#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 ++#define DPGV0_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 ++#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff ++#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 ++#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 ++#define DPGV1_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 ++#define DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 ++#define DPGV0_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 ++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 ++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 ++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 ++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 ++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 ++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc ++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 ++#define DPGV0_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 ++#define DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 ++#define DPGV1_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 ++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 ++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 ++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 ++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 ++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 ++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc ++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 ++#define DPGV1_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 ++#define DPGV0_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 ++#define DPGV1_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 ++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 ++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 ++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 ++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 ++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 ++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 ++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 ++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 ++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 ++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa ++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000 ++#define DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10 ++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 ++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 ++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 ++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 ++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 ++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 ++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 ++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 ++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 ++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa ++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000 ++#define DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 ++#define DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 ++#define DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb ++#define DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 ++#define DPGV0_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 ++#define DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 ++#define DPGV0_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 ++#define DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 ++#define DPGV1_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 ++#define DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 ++#define DPGV1_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 ++#define DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff ++#define DPGV0_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 ++#define DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff ++#define DPGV1_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 ++#define DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff ++#define DPGV0_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 ++#define DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff ++#define DPGV1_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 ++#define DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1 ++#define DPGV0_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0 ++#define DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11_MASK 0x1 ++#define DPGV1_HW_DEBUG_11__DPG_HW_DEBUG_11__SHIFT 0x0 ++#define DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1 ++#define DPGV0_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0 ++#define DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK_MASK 0x1 ++#define DPGV1_CHK_PRE_PROC_CNTL__DPG_DISABLE_DMIF_BUF_CHK__SHIFT 0x0 ++#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff ++#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DPGV_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DPGV_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0 ++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff ++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 ++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff ++#define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff ++#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 ++#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff ++#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 ++#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff ++#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 ++#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f ++#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 ++#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff ++#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 ++#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff ++#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7 ++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70 ++#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 ++#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f ++#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 ++#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f ++#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 ++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7 ++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 ++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10 ++#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 ++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x7 ++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 ++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10 ++#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 ++#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON_MASK 0x3f ++#define AZALIA_F0_CODEC_DEBUG__DISABLE_FORMAT_COMPARISON__SHIFT 0x0 ++#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffc0 ++#define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x6 ++#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff ++#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 ++#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff ++#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 ++#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff ++#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 ++#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff ++#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 ++#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff ++#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 ++#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff ++#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 ++#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff ++#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 ++#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1 ++#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0 ++#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 ++#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 ++#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8 ++#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3 ++#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00 ++#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8 ++#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000 ++#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc ++#define MINOR_VERSION__MINOR_VERSION_MASK 0xff ++#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0 ++#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff ++#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0 ++#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff ++#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 ++#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff ++#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 ++#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1 ++#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0 ++#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2 ++#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1 ++#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100 ++#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8 ++#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1 ++#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0 ++#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1 ++#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0 ++#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2 ++#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1 ++#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff ++#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0 ++#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff ++#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0 ++#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x1 ++#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0 ++#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x2 ++#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1 ++#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x4 ++#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2 ++#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x8 ++#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3 ++#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x10 ++#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4 ++#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x20 ++#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5 ++#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x40 ++#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6 ++#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x80 ++#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7 ++#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x100 ++#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8 ++#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x200 ++#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9 ++#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x400 ++#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa ++#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x800 ++#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb ++#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x1000 ++#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc ++#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x2000 ++#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd ++#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x4000 ++#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe ++#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x8000 ++#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf ++#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000 ++#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e ++#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000 ++#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f ++#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x1 ++#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0 ++#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x2 ++#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1 ++#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x4 ++#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2 ++#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x8 ++#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3 ++#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x10 ++#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4 ++#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x20 ++#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5 ++#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x40 ++#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6 ++#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x80 ++#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7 ++#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x100 ++#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8 ++#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x200 ++#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9 ++#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x400 ++#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa ++#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x800 ++#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb ++#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x1000 ++#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc ++#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x2000 ++#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd ++#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x4000 ++#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe ++#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x8000 ++#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf ++#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000 ++#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e ++#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000 ++#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f ++#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff ++#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0 ++#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1 ++#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0 ++#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2 ++#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1 ++#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4 ++#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2 ++#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8 ++#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3 ++#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10 ++#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4 ++#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20 ++#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5 ++#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x40 ++#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6 ++#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x80 ++#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7 ++#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x100 ++#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8 ++#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x200 ++#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9 ++#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x400 ++#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa ++#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x800 ++#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb ++#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x1000 ++#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc ++#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x2000 ++#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd ++#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x4000 ++#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe ++#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x8000 ++#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf ++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f ++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 ++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80 ++#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7 ++#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff ++#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0 ++#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff ++#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 ++#define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff ++#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 ++#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000 ++#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf ++#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1 ++#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 ++#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2 ++#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 ++#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1 ++#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 ++#define CORB_SIZE__CORB_SIZE_MASK 0x3 ++#define CORB_SIZE__CORB_SIZE__SHIFT 0x0 ++#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0 ++#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 ++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f ++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 ++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80 ++#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 ++#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff ++#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 ++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff ++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 ++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000 ++#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf ++#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff ++#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 ++#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 ++#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 ++#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2 ++#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 ++#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4 ++#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 ++#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1 ++#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 ++#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4 ++#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 ++#define RIRB_SIZE__RIRB_SIZE_MASK 0x3 ++#define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 ++#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0 ++#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 ++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff ++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 ++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000 ++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c ++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff ++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 ++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff ++#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 ++#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff ++#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 ++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1 ++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 ++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2 ++#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 ++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1 ++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 ++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e ++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 ++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80 ++#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 ++#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff ++#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 ++#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff ++#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000 ++#define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d ++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff ++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 ++#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff ++#define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 ++#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff ++#define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 ++#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff ++#define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 ++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf ++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 ++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70 ++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 ++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 ++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 ++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 ++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb ++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 ++#define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe ++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f ++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 ++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80 ++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 ++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff ++#define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 ++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff ++#define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 ++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff ++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 ++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff ++#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff ++#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 ++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 ++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 ++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 ++#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 ++#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff ++#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 ++#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 ++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f ++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 ++#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0xfc00 ++#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa ++#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff ++#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x3 ++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78 ++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 ++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80 ++#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78 ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 ++#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 ++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff ++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 ++#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 ++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10 ++#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff ++#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff ++#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff ++#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff ++#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff ++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff ++#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 ++#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 ++#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff ++#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 ++#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 ++#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff ++#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 ++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 ++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff ++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff ++#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff ++#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2 ++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00 ++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 ++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000 ++#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 ++#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3 ++#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10 ++#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 ++#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1 ++#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 ++#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10 ++#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 ++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff ++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 ++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000 ++#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 ++#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300 ++#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 ++#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30 ++#define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4 ++#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff ++#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 ++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3 ++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 ++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0xc ++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 ++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30 ++#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 ++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0xc0 ++#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 ++#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000 ++#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 ++#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000 ++#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 ++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3 ++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 ++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0xc ++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 ++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30 ++#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 ++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0xc0 ++#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 ++#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1 ++#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 ++#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10 ++#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 ++#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x1e0 ++#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 ++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1 ++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 ++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10 ++#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 ++#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff ++#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 ++#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1 ++#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 ++#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 ++#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 ++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff ++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 ++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000 ++#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 ++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff ++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 ++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100 ++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 ++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0xff0000 ++#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 ++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff ++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 ++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xffff0000 ++#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 ++#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff ++#define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0 ++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x3 ++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 ++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x4 ++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x18 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x20 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0xc0 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x100 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x600 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x800 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x3000 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x4000 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x18000 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x20000 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0xc0000 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x100000 ++#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 ++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000 ++#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c ++#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x3 ++#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 ++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0xc ++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 ++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x30 ++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 ++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0xc0 ++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 ++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x300 ++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 ++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0xc00 ++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa ++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x3000 ++#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc ++#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN_MASK 0x1 ++#define DCI_PG_DEBUG_CONFIG__DCI_PG_DBG_EN__SHIFT 0x0 ++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x1 ++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 ++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10 ++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 ++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700 ++#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 ++#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff ++#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 ++#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff ++#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 ++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1 ++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 ++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 ++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 ++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700 ++#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 ++#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff ++#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 ++#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff ++#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 ++#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff ++#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 ++#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff ++#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 ++#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff ++#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 ++#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff ++#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 ++#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff ++#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 ++#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff ++#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 ++#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff ++#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 ++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x1 ++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 ++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x10 ++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 ++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x700 ++#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 ++#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xffffffff ++#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 ++#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0xffff ++#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 ++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x1 ++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 ++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 ++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 ++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x700 ++#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 ++#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xffffffff ++#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 ++#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xffffffff ++#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 ++#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xffffffff ++#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 ++#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xffffffff ++#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 ++#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xffffffff ++#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 ++#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xffffffff ++#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 ++#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xffffffff ++#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 ++#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xffffffff ++#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 ++#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xffffffff ++#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 ++#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1 ++#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 ++#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 ++#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 ++#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 ++#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 ++#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 ++#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc ++#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff ++#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 ++#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff ++#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 ++#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1 ++#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 ++#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 ++#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 ++#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 ++#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 ++#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff ++#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 ++#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff ++#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 ++#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff ++#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 ++#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff ++#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 ++#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff ++#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 ++#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff ++#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 ++#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff ++#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 ++#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff ++#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 ++#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff ++#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 ++#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1 ++#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 ++#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 ++#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 ++#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 ++#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 ++#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 ++#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc ++#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff ++#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 ++#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff ++#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 ++#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1 ++#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 ++#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 ++#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 ++#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 ++#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 ++#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff ++#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 ++#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff ++#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 ++#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff ++#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 ++#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff ++#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 ++#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff ++#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 ++#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff ++#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 ++#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff ++#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 ++#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff ++#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 ++#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff ++#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 ++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff ++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff ++#define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0 ++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff ++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 ++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100 ++#define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 ++#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff ++#define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 ++#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f ++#define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 ++#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00 ++#define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 ++#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000 ++#define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 ++#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1 ++#define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 ++#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff ++#define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 ++#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff ++#define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 ++#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff ++#define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 ++#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff ++#define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 ++#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff ++#define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 ++#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff ++#define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 ++#define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 ++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 ++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 ++#define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff ++#define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff ++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff ++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 ++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff ++#define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 ++#define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 ++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f ++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 ++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 ++#define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0xfc0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x3000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 ++#define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1 ++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 ++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f ++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff ++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 ++#define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 ++#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff ++#define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 ++#define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 ++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff ++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff ++#define AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0xff ++#define AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x1 ++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x2 ++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 ++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0xff00 ++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 ++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0xff0000 ++#define AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x3 ++#define AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x1 ++#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x10 ++#define AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 ++#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x1 ++#define AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 ++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x1 ++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 ++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x10 ++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 ++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x100 ++#define AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 ++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x1 ++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 ++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x10 ++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 ++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x100 ++#define AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 ++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x1 ++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 ++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x10 ++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 ++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x100 ++#define AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 ++#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x3fff ++#define AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xffffffff ++#define AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xffffffff ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 ++#define AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 ++#define AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x100 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x200 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x10000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x20000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf00000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1000000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2000000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0000000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x1 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x2 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x100 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x200 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x10000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x20000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0xf00000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff ++#define AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 ++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x1ffff ++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 ++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff ++#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 ++#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 ++#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x20 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x6 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x10 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x20 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x7 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0xff00 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0xff0000 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xffffffff ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xffffffff ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x1 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0xff00 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xffffffff ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xffffffff ++#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 ++#define BLND_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff ++#define BLND_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0 ++#define BLND_CONTROL__BLND_MODE_MASK 0x300 ++#define BLND_CONTROL__BLND_MODE__SHIFT 0x8 ++#define BLND_CONTROL__BLND_STEREO_TYPE_MASK 0xc00 ++#define BLND_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa ++#define BLND_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000 ++#define BLND_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc ++#define BLND_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000 ++#define BLND_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd ++#define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000 ++#define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10 ++#define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000 ++#define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14 ++#define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000 ++#define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18 ++#define BLND_SM_CONTROL2__SM_MODE_MASK 0x7 ++#define BLND_SM_CONTROL2__SM_MODE__SHIFT 0x0 ++#define BLND_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10 ++#define BLND_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4 ++#define BLND_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20 ++#define BLND_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5 ++#define BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300 ++#define BLND_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 ++#define BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000 ++#define BLND_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 ++#define BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000 ++#define BLND_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18 ++#define BLND_CONTROL2__PTI_ENABLE_MASK 0x1 ++#define BLND_CONTROL2__PTI_ENABLE__SHIFT 0x0 ++#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30 ++#define BLND_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4 ++#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40 ++#define BLND_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6 ++#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80 ++#define BLND_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7 ++#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100 ++#define BLND_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8 ++#define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1 ++#define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0 ++#define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100 ++#define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8 ++#define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000 ++#define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10 ++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1 ++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0 ++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100 ++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8 ++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000 ++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc ++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000 ++#define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10 ++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1 ++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0 ++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2 ++#define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1 ++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000 ++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10 ++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000 ++#define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18 ++#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000 ++#define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c ++#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000 ++#define BLND_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d ++#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000 ++#define BLND_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f ++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1 ++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0 ++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2 ++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1 ++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4 ++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2 ++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8 ++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3 ++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40 ++#define BLND_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6 ++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80 ++#define BLND_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7 ++#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100 ++#define BLND_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8 ++#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200 ++#define BLND_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9 ++#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400 ++#define BLND_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa ++#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800 ++#define BLND_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb ++#define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1 ++#define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0 ++#define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe ++#define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1 ++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff ++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff ++#define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0 ++#define WB_ENABLE__WB_ENABLE_MASK 0x1 ++#define WB_ENABLE__WB_ENABLE__SHIFT 0x0 ++#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x1 ++#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0 ++#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x2 ++#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1 ++#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x4 ++#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2 ++#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x40 ++#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x6 ++#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x80 ++#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x7 ++#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x100 ++#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x8 ++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x600 ++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0x9 ++#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0xf000 ++#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0xc ++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x10000 ++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0x10 ++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x60000 ++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0x11 ++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x180000 ++#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x13 ++#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x800000 ++#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17 ++#define WB_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000 ++#define WB_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c ++#define WB_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000 ++#define WB_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e ++#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x300 ++#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8 ++#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x1000 ++#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc ++#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x6000 ++#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd ++#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x8000 ++#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf ++#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000 ++#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 ++#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x40000 ++#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12 ++#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x80000 ++#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13 ++#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x100000 ++#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14 ++#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000 ++#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 ++#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000 ++#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f ++#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff ++#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 ++#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000 ++#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 ++#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff ++#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 ++#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000 ++#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 ++#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1 ++#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 ++#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100 ++#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 ++#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000 ++#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 ++#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff ++#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 ++#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000 ++#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 ++#define CNV_CSC_CONTROL__CNV_CSC_BYPASS_MASK 0x1 ++#define CNV_CSC_CONTROL__CNV_CSC_BYPASS__SHIFT 0x0 ++#define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff ++#define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0 ++#define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000 ++#define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10 ++#define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff ++#define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0 ++#define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000 ++#define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10 ++#define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff ++#define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0 ++#define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000 ++#define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10 ++#define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff ++#define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0 ++#define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000 ++#define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10 ++#define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff ++#define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0 ++#define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000 ++#define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10 ++#define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff ++#define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0 ++#define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000 ++#define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10 ++#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff ++#define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0 ++#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff ++#define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0 ++#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff ++#define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0 ++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff ++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0 ++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000 ++#define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10 ++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff ++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0 ++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000 ++#define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10 ++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff ++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0 ++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000 ++#define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10 ++#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10 ++#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 ++#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100 ++#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 ++#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000 ++#define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10 ++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xfff0 ++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4 ++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000 ++#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 ++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xfff0 ++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4 ++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000 ++#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 ++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xfff0 ++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4 ++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000 ++#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 ++#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x1 ++#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT 0x0 ++#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0xc0 ++#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6 ++#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x1 ++#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0 ++#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x2 ++#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1 ++#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x4 ++#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2 ++#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x8 ++#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3 ++#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x100 ++#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8 ++#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7fff0000 ++#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10 ++#define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xffffffff ++#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0 ++#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT_MASK 0x3 ++#define CNV_INPUT_SELECT__CNV_INPUT_SRC_SELECT__SHIFT 0x0 ++#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT_MASK 0x1c ++#define CNV_INPUT_SELECT__CNV_INPUT_PIPE_SELECT__SHIFT 0x2 ++#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x1 ++#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0 ++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff ++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff ++#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0 ++#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10 ++#define DCFE_CLOCK_CONTROL__DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4 ++#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100 ++#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8 ++#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000 ++#define DCFE_CLOCK_CONTROL__DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc ++#define DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE_MASK 0x8000 ++#define DCFE_CLOCK_CONTROL__DISPCLK_G_PSCL_GATE_DISABLE__SHIFT 0xf ++#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_LOW_POWER_GATE_DISABLE_MASK 0x20000 ++#define DCFE_CLOCK_CONTROL__DISPCLK_G_DCP_LOW_POWER_GATE_DISABLE__SHIFT 0x11 ++#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL_MASK 0x1f000000 ++#define DCFE_CLOCK_CONTROL__DCFE_TEST_CLK_SEL__SHIFT 0x18 ++#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE_MASK 0x80000000 ++#define DCFE_CLOCK_CONTROL__DCFE_CLOCK_ENABLE__SHIFT 0x1f ++#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET_MASK 0x1 ++#define DCFE_SOFT_RESET__DCP_PIXPIPE_SOFT_RESET__SHIFT 0x0 ++#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET_MASK 0x2 ++#define DCFE_SOFT_RESET__DCP_REQ_SOFT_RESET__SHIFT 0x1 ++#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET_MASK 0x4 ++#define DCFE_SOFT_RESET__SCL_ALU_SOFT_RESET__SHIFT 0x2 ++#define DCFE_SOFT_RESET__SCL_SOFT_RESET_MASK 0x8 ++#define DCFE_SOFT_RESET__SCL_SOFT_RESET__SHIFT 0x3 ++#define DCFE_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10 ++#define DCFE_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4 ++#define DCFE_SOFT_RESET__PSCL_SOFT_RESET_MASK 0x20 ++#define DCFE_SOFT_RESET__PSCL_SOFT_RESET__SHIFT 0x5 ++#define DCFE_SOFT_RESET__DCP_LOW_POWER_SOFT_RESET_MASK 0x40 ++#define DCFE_SOFT_RESET__DCP_LOW_POWER_SOFT_RESET__SHIFT 0x6 ++#define DCFE_DBG_CONFIG__DCFE_DBG_EN_MASK 0x1 ++#define DCFE_DBG_CONFIG__DCFE_DBG_EN__SHIFT 0x0 ++#define DCFE_DBG_CONFIG__DCFE_DBG_SEL_MASK 0xf0 ++#define DCFE_DBG_CONFIG__DCFE_DBG_SEL__SHIFT 0x4 ++#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE_MASK 0x3 ++#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_FORCE__SHIFT 0x0 ++#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS_MASK 0x4 ++#define DCFE_MEM_PWR_CTRL__DCP_LUT_MEM_PWR_DIS__SHIFT 0x2 ++#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE_MASK 0x18 ++#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_FORCE__SHIFT 0x3 ++#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS_MASK 0x20 ++#define DCFE_MEM_PWR_CTRL__DCP_REGAMMA_MEM_PWR_DIS__SHIFT 0x5 ++#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE_MASK 0xc0 ++#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_FORCE__SHIFT 0x6 ++#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS_MASK 0x100 ++#define DCFE_MEM_PWR_CTRL__SCL_COEFF_MEM_PWR_DIS__SHIFT 0x8 ++#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE_MASK 0x600 ++#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_FORCE__SHIFT 0x9 ++#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x800 ++#define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS__SHIFT 0xb ++#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE_MASK 0x3000 ++#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_FORCE__SHIFT 0xc ++#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS_MASK 0x4000 ++#define DCFE_MEM_PWR_CTRL__LB0_ALPHA_MEM_PWR_DIS__SHIFT 0xe ++#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE_MASK 0x18000 ++#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_FORCE__SHIFT 0xf ++#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS_MASK 0x20000 ++#define DCFE_MEM_PWR_CTRL__LB1_ALPHA_MEM_PWR_DIS__SHIFT 0x11 ++#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE_MASK 0xc0000 ++#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_FORCE__SHIFT 0x12 ++#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS_MASK 0x100000 ++#define DCFE_MEM_PWR_CTRL__LB2_ALPHA_MEM_PWR_DIS__SHIFT 0x14 ++#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE_MASK 0x600000 ++#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_FORCE__SHIFT 0x15 ++#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS_MASK 0x800000 ++#define DCFE_MEM_PWR_CTRL__LB0_MEM_PWR_DIS__SHIFT 0x17 ++#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE_MASK 0x3000000 ++#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_FORCE__SHIFT 0x18 ++#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS_MASK 0x4000000 ++#define DCFE_MEM_PWR_CTRL__LB1_MEM_PWR_DIS__SHIFT 0x1a ++#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE_MASK 0x18000000 ++#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_FORCE__SHIFT 0x1b ++#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS_MASK 0x20000000 ++#define DCFE_MEM_PWR_CTRL__LB2_MEM_PWR_DIS__SHIFT 0x1d ++#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL_MASK 0x3 ++#define DCFE_MEM_PWR_CTRL2__DCP_LUT_MEM_PWR_MODE_SEL__SHIFT 0x0 ++#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL_MASK 0xc ++#define DCFE_MEM_PWR_CTRL2__DCP_REGAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2 ++#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL_MASK 0x30 ++#define DCFE_MEM_PWR_CTRL2__SCL_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4 ++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL_MASK 0xc0 ++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR_MEM_PWR_MODE_SEL__SHIFT 0x6 ++#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL_MASK 0x300 ++#define DCFE_MEM_PWR_CTRL2__LB_ALPHA_MEM_PWR_MODE_SEL__SHIFT 0x8 ++#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL_MASK 0xc00 ++#define DCFE_MEM_PWR_CTRL2__LB_MEM_PWR_MODE_SEL__SHIFT 0xa ++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL_MASK 0x3000 ++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_MODE_SEL__SHIFT 0xc ++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL_MASK 0xc000 ++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_MODE_SEL__SHIFT 0xe ++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE_MASK 0x30000 ++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_FORCE__SHIFT 0x10 ++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS_MASK 0x40000 ++#define DCFE_MEM_PWR_CTRL2__BLND_MEM_PWR_DIS__SHIFT 0x12 ++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE_MASK 0x600000 ++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_FORCE__SHIFT 0x15 ++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS_MASK 0x800000 ++#define DCFE_MEM_PWR_CTRL2__DCP_CURSOR2_MEM_PWR_DIS__SHIFT 0x17 ++#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE_MASK 0x3 ++#define DCFE_MEM_PWR_STATUS__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0 ++#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE_MASK 0xc ++#define DCFE_MEM_PWR_STATUS__DCP_REGAMMA_MEM_PWR_STATE__SHIFT 0x2 ++#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE_MASK 0x30 ++#define DCFE_MEM_PWR_STATUS__SCL_COEFF_MEM_PWR_STATE__SHIFT 0x4 ++#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE_MASK 0xc0 ++#define DCFE_MEM_PWR_STATUS__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x6 ++#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE_MASK 0x300 ++#define DCFE_MEM_PWR_STATUS__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0x8 ++#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE_MASK 0xc00 ++#define DCFE_MEM_PWR_STATUS__LB0_ALPHA_MEM_PWR_STATE__SHIFT 0xa ++#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE_MASK 0x3000 ++#define DCFE_MEM_PWR_STATUS__LB1_ALPHA_MEM_PWR_STATE__SHIFT 0xc ++#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE_MASK 0xc000 ++#define DCFE_MEM_PWR_STATUS__LB2_ALPHA_MEM_PWR_STATE__SHIFT 0xe ++#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE_MASK 0x30000 ++#define DCFE_MEM_PWR_STATUS__LB0_MEM_PWR_STATE__SHIFT 0x10 ++#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE_MASK 0xc0000 ++#define DCFE_MEM_PWR_STATUS__LB1_MEM_PWR_STATE__SHIFT 0x12 ++#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE_MASK 0x300000 ++#define DCFE_MEM_PWR_STATUS__LB2_MEM_PWR_STATE__SHIFT 0x14 ++#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE_MASK 0xc00000 ++#define DCFE_MEM_PWR_STATUS__BLND_MEM_PWR_STATE__SHIFT 0x16 ++#define DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN_MASK 0x1 ++#define DCFE_MISC__DCFE_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0 ++#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE_MASK 0x8 ++#define DCFEV_CLOCK_CONTROL__DISPCLK_R_DCFEV_GATE_DISABLE__SHIFT 0x3 ++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE_MASK 0x80 ++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_UNP_GATE_DISABLE__SHIFT 0x7 ++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE_MASK 0x200 ++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_SCLV_GATE_DISABLE__SHIFT 0x9 ++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE_MASK 0x800 ++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_COL_MAN_GATE_DISABLE__SHIFT 0xb ++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE_MASK 0x2000 ++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_PSCLV_GATE_DISABLE__SHIFT 0xd ++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE_MASK 0x8000 ++#define DCFEV_CLOCK_CONTROL__DISPCLK_G_CRTC_GATE_DISABLE__SHIFT 0xf ++#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL_MASK 0x1f000000 ++#define DCFEV_CLOCK_CONTROL__DCFEV_TEST_CLK_SEL__SHIFT 0x18 ++#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE_MASK 0x80000000 ++#define DCFEV_CLOCK_CONTROL__DCFEV_CLOCK_ENABLE__SHIFT 0x1f ++#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET_MASK 0x1 ++#define DCFEV_SOFT_RESET__UNP_PIXPIPE_SOFT_RESET__SHIFT 0x0 ++#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET_MASK 0x2 ++#define DCFEV_SOFT_RESET__UNP_REQ_SOFT_RESET__SHIFT 0x1 ++#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET_MASK 0x4 ++#define DCFEV_SOFT_RESET__SCLV_ALU_SOFT_RESET__SHIFT 0x2 ++#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET_MASK 0x8 ++#define DCFEV_SOFT_RESET__SCLV_SOFT_RESET__SHIFT 0x3 ++#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET_MASK 0x10 ++#define DCFEV_SOFT_RESET__CRTC_SOFT_RESET__SHIFT 0x4 ++#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET_MASK 0x20 ++#define DCFEV_SOFT_RESET__PSCLV_SOFT_RESET__SHIFT 0x5 ++#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET_MASK 0x40 ++#define DCFEV_SOFT_RESET__COL_MAN_SOFT_RESET__SHIFT 0x6 ++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS_MASK 0x8 ++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x3 ++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS_MASK 0x10 ++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVL_GATE_DIS__SHIFT 0x4 ++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS_MASK 0x20 ++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_DISPCLK_G_DMIFVC_GATE_DIS__SHIFT 0x5 ++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET_MASK 0x40 ++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_SOFT_RESET__SHIFT 0x6 ++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL_MASK 0x1f000000 ++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_TEST_CLK_SEL__SHIFT 0x18 ++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE_MASK 0x80000000 ++#define DCFEV_DMIFV_CLOCK_CONTROL__DMIFV_BUFFER_MODE__SHIFT 0x1f ++#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN_MASK 0x1 ++#define DCFEV_DBG_CONFIG__DCFEV_DBG_EN__SHIFT 0x0 ++#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL_MASK 0xf0 ++#define DCFEV_DBG_CONFIG__DCFEV_DBG_SEL__SHIFT 0x4 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL_MASK 0x3 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_SEL__SHIFT 0x0 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE_MASK 0x4 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_0_FORCE__SHIFT 0x2 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE_MASK 0x8 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_1_FORCE__SHIFT 0x3 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE_MASK 0x10 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_2_FORCE__SHIFT 0x4 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE_MASK 0x20 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_3_FORCE__SHIFT 0x5 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE_MASK 0x40 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_LUMA_4_FORCE__SHIFT 0x6 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE_MASK 0x80 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_0_FORCE__SHIFT 0x7 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE_MASK 0x100 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_1_FORCE__SHIFT 0x8 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE_MASK 0x200 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_2_FORCE__SHIFT 0x9 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE_MASK 0x400 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_3_FORCE__SHIFT 0xa ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE_MASK 0x800 ++#define DCFEV_DMIFV_MEM_PWR_CTRL__DMIFV_MEM_PWR_CHROMA_4_FORCE__SHIFT 0xb ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE_MASK 0x3 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_0_STATE__SHIFT 0x0 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE_MASK 0xc ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_1_STATE__SHIFT 0x2 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE_MASK 0x30 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_2_STATE__SHIFT 0x4 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE_MASK 0xc0 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_3_STATE__SHIFT 0x6 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE_MASK 0x300 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_LUMA_4_STATE__SHIFT 0x8 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE_MASK 0xc00 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_0_STATE__SHIFT 0xa ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE_MASK 0x3000 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_1_STATE__SHIFT 0xc ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE_MASK 0xc000 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_2_STATE__SHIFT 0xe ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE_MASK 0x30000 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_3_STATE__SHIFT 0x10 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE_MASK 0xc0000 ++#define DCFEV_DMIFV_MEM_PWR_STATUS__DMIFV_MEM_PWR_CHROMA_4_STATE__SHIFT 0x12 ++#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE_MASK 0x3 ++#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_FORCE__SHIFT 0x0 ++#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS_MASK 0x4 ++#define DCFEV_MEM_PWR_CTRL__COL_MAN_GAMMA_CORR_MEM_PWR_DIS__SHIFT 0x2 ++#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE_MASK 0x18 ++#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE__SHIFT 0x3 ++#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS_MASK 0x20 ++#define DCFEV_MEM_PWR_CTRL__COL_MAN_INPUT_GAMMA_MEM_PWR_DIS__SHIFT 0x5 ++#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE_MASK 0xc0 ++#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_FORCE__SHIFT 0x6 ++#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS_MASK 0x100 ++#define DCFEV_MEM_PWR_CTRL__SCLV_COEFF_MEM_PWR_DIS__SHIFT 0x8 ++#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE_MASK 0x600 ++#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_FORCE__SHIFT 0x9 ++#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS_MASK 0x800 ++#define DCFEV_MEM_PWR_CTRL__LBV0_MEM_PWR_DIS__SHIFT 0xb ++#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE_MASK 0x3000 ++#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_FORCE__SHIFT 0xc ++#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS_MASK 0x4000 ++#define DCFEV_MEM_PWR_CTRL__LBV1_MEM_PWR_DIS__SHIFT 0xe ++#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE_MASK 0x18000 ++#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_FORCE__SHIFT 0xf ++#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS_MASK 0x20000 ++#define DCFEV_MEM_PWR_CTRL__LBV2_MEM_PWR_DIS__SHIFT 0x11 ++#define DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL_MASK 0x3 ++#define DCFEV_MEM_PWR_CTRL2__COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL__SHIFT 0x0 ++#define DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL_MASK 0xc ++#define DCFEV_MEM_PWR_CTRL2__COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL__SHIFT 0x2 ++#define DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL_MASK 0x30 ++#define DCFEV_MEM_PWR_CTRL2__SCLV_COEFF_MEM_PWR_MODE_SEL__SHIFT 0x4 ++#define DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL_MASK 0xc0 ++#define DCFEV_MEM_PWR_CTRL2__LBV_MEM_PWR_MODE_SEL__SHIFT 0x6 ++#define DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE_MASK 0x3 ++#define DCFEV_MEM_PWR_STATUS__COL_MAN_GAMMA_CORR_MEM_PWR_STATE__SHIFT 0x0 ++#define DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE_MASK 0xc ++#define DCFEV_MEM_PWR_STATUS__COL_MAN_INPUT_GAMMA_MEM_PWR_STATE__SHIFT 0x2 ++#define DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE_MASK 0x30 ++#define DCFEV_MEM_PWR_STATUS__SCLV_COEFF_MEM_PWR_STATE__SHIFT 0x4 ++#define DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE_MASK 0xc0 ++#define DCFEV_MEM_PWR_STATUS__LBV0_MEM_PWR_STATE__SHIFT 0x6 ++#define DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE_MASK 0x300 ++#define DCFEV_MEM_PWR_STATUS__LBV1_MEM_PWR_STATE__SHIFT 0x8 ++#define DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE_MASK 0xc00 ++#define DCFEV_MEM_PWR_STATUS__LBV2_MEM_PWR_STATE__SHIFT 0xa ++#define DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE_MASK 0x3000 ++#define DCFEV_MEM_PWR_STATUS__LBV3_MEM_PWR_STATE__SHIFT 0xc ++#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL_MASK 0xf ++#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_BUS_SEL__SHIFT 0x0 ++#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA_MASK 0x10 ++#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LUMA_VS_CHROMA__SHIFT 0x4 ++#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER_MASK 0x20 ++#define DCFEV_DMIFV_DEBUG__DMIFV_DEBUG_LOWER_UPPER__SHIFT 0x5 ++#define DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN_MASK 0x1 ++#define DCFEV_MISC__DCFEV_DPG_ALLOW_SR_ECO_EN__SHIFT 0x0 ++#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x1 ++#define DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 ++#define DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x2 ++#define DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 ++#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x10 ++#define DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 ++#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x100 ++#define DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 ++#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 ++#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc ++#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 ++#define DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 ++#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x1 ++#define DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 ++#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x100 ++#define DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 ++#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x10000 ++#define DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 ++#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x100000 ++#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 ++#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x1000000 ++#define DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 ++#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x1fff ++#define DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 ++#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x3ff0000 ++#define DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 ++#define DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000 ++#define DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c ++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0xff ++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 ++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 ++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc ++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x1000000 ++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 ++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 ++#define DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c ++#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0xff ++#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 ++#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0xff00000 ++#define DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 ++#define DCO_SCRATCH0__DCO_SCRATCH0_MASK 0xffffffff ++#define DCO_SCRATCH0__DCO_SCRATCH0__SHIFT 0x0 ++#define DCO_SCRATCH1__DCO_SCRATCH1_MASK 0xffffffff ++#define DCO_SCRATCH1__DCO_SCRATCH1__SHIFT 0x0 ++#define DCO_SCRATCH2__DCO_SCRATCH2_MASK 0xffffffff ++#define DCO_SCRATCH2__DCO_SCRATCH2__SHIFT 0x0 ++#define DCO_SCRATCH3__DCO_SCRATCH3_MASK 0xffffffff ++#define DCO_SCRATCH3__DCO_SCRATCH3__SHIFT 0x0 ++#define DCO_SCRATCH4__DCO_SCRATCH4_MASK 0xffffffff ++#define DCO_SCRATCH4__DCO_SCRATCH4__SHIFT 0x0 ++#define DCO_SCRATCH5__DCO_SCRATCH5_MASK 0xffffffff ++#define DCO_SCRATCH5__DCO_SCRATCH5__SHIFT 0x0 ++#define DCO_SCRATCH6__DCO_SCRATCH6_MASK 0xffffffff ++#define DCO_SCRATCH6__DCO_SCRATCH6__SHIFT 0x0 ++#define DCO_SCRATCH7__DCO_SCRATCH7_MASK 0xffffffff ++#define DCO_SCRATCH7__DCO_SCRATCH7__SHIFT 0x0 ++#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7 ++#define DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0 ++#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70 ++#define DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4 ++#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1 ++#define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0 ++#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 ++#define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 ++#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4 ++#define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2 ++#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8 ++#define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3 ++#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10 ++#define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4 ++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 ++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 ++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 ++#define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 ++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80 ++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7 ++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100 ++#define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8 ++#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200 ++#define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9 ++#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 ++#define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa ++#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 ++#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf ++#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 ++#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 ++#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 ++#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 ++#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000 ++#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 ++#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000 ++#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 ++#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000 ++#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 ++#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000 ++#define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15 ++#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000 ++#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16 ++#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000 ++#define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17 ++#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000 ++#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 ++#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000 ++#define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19 ++#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000 ++#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a ++#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000 ++#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b ++#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000 ++#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c ++#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000 ++#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d ++#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000 ++#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e ++#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000 ++#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f ++#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0 ++#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa ++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf ++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 ++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 ++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 ++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 ++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15 ++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16 ++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e ++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f ++#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa ++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf ++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e ++#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f ++#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa ++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf ++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e ++#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f ++#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa ++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf ++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e ++#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f ++#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa ++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf ++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e ++#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DCRX_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT_MASK 0x200 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB0_IHIF_INTERRUPT__SHIFT 0x9 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT_MASK 0x400 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__BUFMGR_CWB1_IHIF_INTERRUPT__SHIFT 0xa ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a ++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b ++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c ++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d ++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__WB_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a ++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b ++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c ++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d ++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__WB_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a ++#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__WB_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000 ++#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f ++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10 ++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x4 ++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20 ++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x5 ++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x400 ++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xa ++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x800 ++#define DISP_INTERRUPT_STATUS_CONTINUE10__DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0xb ++#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x1 ++#define DCO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0 ++#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE_MASK 0x4 ++#define DCO_MEM_PWR_STATUS__MVP_MEM_PWR_STATE__SHIFT 0x2 ++#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x8 ++#define DCO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3 ++#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x10 ++#define DCO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4 ++#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x20 ++#define DCO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5 ++#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x40 ++#define DCO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6 ++#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x80 ++#define DCO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7 ++#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x100 ++#define DCO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8 ++#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x200 ++#define DCO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9 ++#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE_MASK 0xc00 ++#define DCO_MEM_PWR_STATUS__HDMI0_MEM_PWR_STATE__SHIFT 0xa ++#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE_MASK 0x3000 ++#define DCO_MEM_PWR_STATUS__HDMI1_MEM_PWR_STATE__SHIFT 0xc ++#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE_MASK 0xc000 ++#define DCO_MEM_PWR_STATUS__HDMI2_MEM_PWR_STATE__SHIFT 0xe ++#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE_MASK 0x30000 ++#define DCO_MEM_PWR_STATUS__HDMI3_MEM_PWR_STATE__SHIFT 0x10 ++#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE_MASK 0xc0000 ++#define DCO_MEM_PWR_STATUS__HDMI4_MEM_PWR_STATE__SHIFT 0x12 ++#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE_MASK 0x300000 ++#define DCO_MEM_PWR_STATUS__HDMI5_MEM_PWR_STATE__SHIFT 0x14 ++#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE_MASK 0xc00000 ++#define DCO_MEM_PWR_STATUS__HDMI6_MEM_PWR_STATE__SHIFT 0x16 ++#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE_MASK 0x1 ++#define DCO_MEM_PWR_STATUS1__DPLPA_MEM_PWR_STATE__SHIFT 0x0 ++#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE_MASK 0x2 ++#define DCO_MEM_PWR_STATUS1__DPLPB_MEM_PWR_STATE__SHIFT 0x1 ++#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE_MASK 0xc00 ++#define DCO_MEM_PWR_STATUS1__HDMILP0_MEM_PWR_STATE__SHIFT 0xa ++#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE_MASK 0x3000 ++#define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 0xc ++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x1 ++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0 ++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x2 ++#define DCO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1 ++#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS_MASK 0x8 ++#define DCO_MEM_PWR_CTRL__MVP_LIGHT_SLEEP_DIS__SHIFT 0x3 ++#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x10 ++#define DCO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4 ++#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x20 ++#define DCO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5 ++#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x40 ++#define DCO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6 ++#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x80 ++#define DCO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7 ++#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x100 ++#define DCO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8 ++#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x200 ++#define DCO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9 ++#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x400 ++#define DCO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa ++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE_MASK 0x1800 ++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_FORCE__SHIFT 0xb ++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS_MASK 0x2000 ++#define DCO_MEM_PWR_CTRL__HDMI0_MEM_PWR_DIS__SHIFT 0xd ++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE_MASK 0xc000 ++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_FORCE__SHIFT 0xe ++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS_MASK 0x10000 ++#define DCO_MEM_PWR_CTRL__HDMI1_MEM_PWR_DIS__SHIFT 0x10 ++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE_MASK 0x60000 ++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_FORCE__SHIFT 0x11 ++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS_MASK 0x80000 ++#define DCO_MEM_PWR_CTRL__HDMI2_MEM_PWR_DIS__SHIFT 0x13 ++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE_MASK 0x300000 ++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_FORCE__SHIFT 0x14 ++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS_MASK 0x400000 ++#define DCO_MEM_PWR_CTRL__HDMI3_MEM_PWR_DIS__SHIFT 0x16 ++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE_MASK 0x1800000 ++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_FORCE__SHIFT 0x17 ++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS_MASK 0x2000000 ++#define DCO_MEM_PWR_CTRL__HDMI4_MEM_PWR_DIS__SHIFT 0x19 ++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE_MASK 0xc000000 ++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_FORCE__SHIFT 0x1a ++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS_MASK 0x10000000 ++#define DCO_MEM_PWR_CTRL__HDMI5_MEM_PWR_DIS__SHIFT 0x1c ++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE_MASK 0x60000000 ++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_FORCE__SHIFT 0x1d ++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS_MASK 0x80000000 ++#define DCO_MEM_PWR_CTRL__HDMI6_MEM_PWR_DIS__SHIFT 0x1f ++#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL_MASK 0x3 ++#define DCO_MEM_PWR_CTRL2__HDMI_MEM_PWR_MODE_SEL__SHIFT 0x0 ++#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS_MASK 0x4 ++#define DCO_MEM_PWR_CTRL2__DPLPA_LIGHT_SLEEP_DIS__SHIFT 0x2 ++#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS_MASK 0x8 ++#define DCO_MEM_PWR_CTRL2__DPLPB_LIGHT_SLEEP_DIS__SHIFT 0x3 ++#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE_MASK 0x30000 ++#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_FORCE__SHIFT 0x10 ++#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS_MASK 0x40000 ++#define DCO_MEM_PWR_CTRL2__HDMILP0_MEM_PWR_DIS__SHIFT 0x12 ++#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE_MASK 0x180000 ++#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_FORCE__SHIFT 0x13 ++#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS_MASK 0x200000 ++#define DCO_MEM_PWR_CTRL2__HDMILP1_MEM_PWR_DIS__SHIFT 0x15 ++#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20 ++#define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5 ++#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40 ++#define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6 ++#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80 ++#define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7 ++#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100 ++#define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8 ++#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200 ++#define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9 ++#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS_MASK 0x400 ++#define DCO_CLK_CNTL__REFCLK_R_DCO_GATE_DIS__SHIFT 0xa ++#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000 ++#define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10 ++#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000 ++#define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11 ++#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000 ++#define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12 ++#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000 ++#define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13 ++#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000 ++#define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14 ++#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000 ++#define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS_MASK 0x400000 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGLPA_GATE_DIS__SHIFT 0x16 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS_MASK 0x800000 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGLPB_GATE_DIS__SHIFT 0x17 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a ++#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b ++#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c ++#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d ++#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000 ++#define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e ++#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL_MASK 0x7f ++#define DCO_CLK_CNTL2__DCO_TEST_CLK_SEL__SHIFT 0x0 ++#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS_MASK 0x80 ++#define DCO_CLK_CNTL2__SCLK_G_AFMTA_GATE_DIS__SHIFT 0x7 ++#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS_MASK 0x100 ++#define DCO_CLK_CNTL2__SCLK_G_AFMTB_GATE_DIS__SHIFT 0x8 ++#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS_MASK 0x200 ++#define DCO_CLK_CNTL2__SCLK_G_AFMTC_GATE_DIS__SHIFT 0x9 ++#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS_MASK 0x400 ++#define DCO_CLK_CNTL2__SCLK_G_AFMTD_GATE_DIS__SHIFT 0xa ++#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS_MASK 0x800 ++#define DCO_CLK_CNTL2__SCLK_G_AFMTE_GATE_DIS__SHIFT 0xb ++#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS_MASK 0x1000 ++#define DCO_CLK_CNTL2__SCLK_G_AFMTF_GATE_DIS__SHIFT 0xc ++#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS_MASK 0x2000 ++#define DCO_CLK_CNTL2__SCLK_G_AFMTG_GATE_DIS__SHIFT 0xd ++#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS_MASK 0x8000 ++#define DCO_CLK_CNTL2__SCLK_G_AFMTLPA_GATE_DIS__SHIFT 0xf ++#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS_MASK 0x10000 ++#define DCO_CLK_CNTL2__SCLK_G_AFMTLPB_GATE_DIS__SHIFT 0x10 ++#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x20000 ++#define DCO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11 ++#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x40000 ++#define DCO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12 ++#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x80000 ++#define DCO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13 ++#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x100000 ++#define DCO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14 ++#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x200000 ++#define DCO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15 ++#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x400000 ++#define DCO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16 ++#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x800000 ++#define DCO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17 ++#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS_MASK 0x2000000 ++#define DCO_CLK_CNTL2__SYMCLKLPA_FE_G_AFMT_GATE_DIS__SHIFT 0x19 ++#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS_MASK 0x4000000 ++#define DCO_CLK_CNTL2__SYMCLKLPB_FE_G_AFMT_GATE_DIS__SHIFT 0x1a ++#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x1 ++#define DCO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0 ++#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x2 ++#define DCO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1 ++#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x4 ++#define DCO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2 ++#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x8 ++#define DCO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3 ++#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x10 ++#define DCO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4 ++#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x20 ++#define DCO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5 ++#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x40 ++#define DCO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6 ++#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS_MASK 0x100 ++#define DCO_CLK_CNTL3__SYMCLKLPA_FE_G_TMDS_GATE_DIS__SHIFT 0x8 ++#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS_MASK 0x200 ++#define DCO_CLK_CNTL3__SYMCLKLPB_FE_G_TMDS_GATE_DIS__SHIFT 0x9 ++#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x400 ++#define DCO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa ++#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x800 ++#define DCO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb ++#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x1000 ++#define DCO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc ++#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x2000 ++#define DCO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd ++#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x4000 ++#define DCO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe ++#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x8000 ++#define DCO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf ++#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x10000 ++#define DCO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10 ++#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS_MASK 0x40000 ++#define DCO_CLK_CNTL3__SYMCLKLPA_G_TMDS_GATE_DIS__SHIFT 0x12 ++#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS_MASK 0x80000 ++#define DCO_CLK_CNTL3__SYMCLKLPB_G_TMDS_GATE_DIS__SHIFT 0x13 ++#define DPDBG_CNTL__DPDBG_ENABLE_MASK 0x1 ++#define DPDBG_CNTL__DPDBG_ENABLE__SHIFT 0x0 ++#define DPDBG_CNTL__DPDBG_INPUT_ENABLE_MASK 0x2 ++#define DPDBG_CNTL__DPDBG_INPUT_ENABLE__SHIFT 0x1 ++#define DPDBG_CNTL__DPDBG_SYMCLK_ON_MASK 0x10 ++#define DPDBG_CNTL__DPDBG_SYMCLK_ON__SHIFT 0x4 ++#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE_MASK 0x100 ++#define DPDBG_CNTL__DPDBG_ERROR_DETECTION_MODE__SHIFT 0x8 ++#define DPDBG_CNTL__DPDBG_LINE_LENGTH_MASK 0xffff0000 ++#define DPDBG_CNTL__DPDBG_LINE_LENGTH__SHIFT 0x10 ++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK_MASK 0x1 ++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_MASK__SHIFT 0x0 ++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE_MASK 0x2 ++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_TYPE__SHIFT 0x1 ++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK_MASK 0x100 ++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_ACK__SHIFT 0x8 ++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED_MASK 0x10000 ++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_OCCURRED__SHIFT 0x10 ++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS_MASK 0x1000000 ++#define DPDBG_INTERRUPT__DPDBG_FIFO_OVERFLOW_INT_STATUS__SHIFT 0x18 ++#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1 ++#define DCO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 ++#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100 ++#define DCO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 ++#define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1 ++#define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0 ++#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10 ++#define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4 ++#define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20 ++#define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5 ++#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40 ++#define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6 ++#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET_MASK 0x1000 ++#define DCO_SOFT_RESET__DB_CLK_SOFT_RESET__SHIFT 0xc ++#define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000 ++#define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10 ++#define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000 ++#define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11 ++#define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000 ++#define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12 ++#define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000 ++#define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13 ++#define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000 ++#define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14 ++#define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000 ++#define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15 ++#define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000 ++#define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18 ++#define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000 ++#define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19 ++#define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000 ++#define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b ++#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1 ++#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 ++#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2 ++#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 ++#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10 ++#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 ++#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20 ++#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 ++#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100 ++#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 ++#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200 ++#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 ++#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000 ++#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc ++#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000 ++#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd ++#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000 ++#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 ++#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000 ++#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 ++#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000 ++#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 ++#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000 ++#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 ++#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000 ++#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 ++#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000 ++#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 ++#define DIG_SOFT_RESET__DPDBG_SOFT_RESET_MASK 0x80000000 ++#define DIG_SOFT_RESET__DPDBG_SOFT_RESET__SHIFT 0x1f ++#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET_MASK 0x1 ++#define DIG_SOFT_RESET_2__DIGLPA_FE_SOFT_RESET__SHIFT 0x0 ++#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET_MASK 0x2 ++#define DIG_SOFT_RESET_2__DIGLPA_BE_SOFT_RESET__SHIFT 0x1 ++#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET_MASK 0x10 ++#define DIG_SOFT_RESET_2__DIGLPB_FE_SOFT_RESET__SHIFT 0x4 ++#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET_MASK 0x20 ++#define DIG_SOFT_RESET_2__DIGLPB_BE_SOFT_RESET__SHIFT 0x5 ++#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7 ++#define DCO_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0 ++#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000 ++#define DCO_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10 ++#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX_MASK 0xff ++#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define DCO_TEST_DEBUG_INDEX__DCO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA_MASK 0xffffffff ++#define DCO_TEST_DEBUG_DATA__DCO_TEST_DEBUG_DATA__SHIFT 0x0 ++#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1 ++#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 ++#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2 ++#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 ++#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4 ++#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 ++#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8 ++#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 ++#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700 ++#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 ++#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000 ++#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 ++#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000 ++#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f ++#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3 ++#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 ++#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc ++#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 ++#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10 ++#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 ++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100 ++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 ++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000 ++#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc ++#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000 ++#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 ++#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000 ++#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 ++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000 ++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 ++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000 ++#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000 ++#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d ++#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc ++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd ++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe ++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf ++#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000 ++#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000 ++#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3 ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8 ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000 ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000 ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000 ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000 ++#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3 ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8 ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000 ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000 ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000 ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000 ++#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3 ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8 ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000 ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000 ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000 ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000 ++#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3 ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8 ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000 ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000 ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000 ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000 ++#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3 ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0 ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8 ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3 ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000 ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10 ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000 ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11 ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000 ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14 ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000 ++#define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c ++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3 ++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 ++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10 ++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 ++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x300 ++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 ++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000 ++#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000 ++#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 ++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3 ++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 ++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10 ++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 ++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x300 ++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 ++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000 ++#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000 ++#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 ++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3 ++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 ++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10 ++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 ++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x300 ++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 ++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000 ++#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000 ++#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 ++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3 ++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 ++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10 ++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 ++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x300 ++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 ++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000 ++#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000 ++#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 ++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3 ++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 ++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10 ++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 ++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x300 ++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 ++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000 ++#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000 ++#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 ++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3 ++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0 ++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10 ++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 ++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL_MASK 0x300 ++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_START_STOP_TIMING_CNTL__SHIFT 0x8 ++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000 ++#define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000 ++#define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18 ++#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1 ++#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 ++#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100 ++#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 ++#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000 ++#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc ++#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000 ++#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd ++#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0xff0000 ++#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 ++#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1 ++#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 ++#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100 ++#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 ++#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000 ++#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc ++#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000 ++#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd ++#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0xff0000 ++#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 ++#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1 ++#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 ++#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100 ++#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 ++#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000 ++#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc ++#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000 ++#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd ++#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0xff0000 ++#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 ++#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1 ++#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 ++#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100 ++#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 ++#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000 ++#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc ++#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000 ++#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd ++#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0xff0000 ++#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 ++#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1 ++#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 ++#define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00 ++#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 ++#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0xff0000 ++#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 ++#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000 ++#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3 ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0 ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8 ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3 ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000 ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10 ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000 ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11 ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000 ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14 ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000 ++#define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c ++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3 ++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0 ++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10 ++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 ++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL_MASK 0x300 ++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_START_STOP_TIMING_CNTL__SHIFT 0x8 ++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000 ++#define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000 ++#define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18 ++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff ++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 ++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000 ++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 ++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000 ++#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x1 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x2 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x4 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x8 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x10 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x20 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x40 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x80 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x100 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x200 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x400 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x800 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x1000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x2000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x4000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x8000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x10000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x20000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x40000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x80000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x100000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x200000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x400000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x800000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x1000000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x2000000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x4000000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x8000000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000 ++#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f ++#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1 ++#define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0 ++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2 ++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1 ++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4 ++#define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2 ++#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8 ++#define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3 ++#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000 ++#define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1 ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0 ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2 ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1 ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4 ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2 ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED_MASK 0x100 ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED__SHIFT 0x8 ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_MASK 0x200 ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT__SHIFT 0x9 ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK_MASK 0x400 ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK__SHIFT 0xa ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK_MASK 0x800 ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK__SHIFT 0xb ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x1000 ++#define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0xc ++#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf ++#define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0 ++#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10 ++#define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4 ++#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20 ++#define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5 ++#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40 ++#define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6 ++#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200 ++#define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9 ++#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400 ++#define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa ++#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3 ++#define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0 ++#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10 ++#define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 ++#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK 0x300 ++#define GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT 0x8 ++#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000 ++#define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10 ++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1 ++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0 ++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2 ++#define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1 ++#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80 ++#define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7 ++#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00 ++#define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8 ++#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000 ++#define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18 ++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1 ++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0 ++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100 ++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8 ++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200 ++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9 ++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000 ++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc ++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000 ++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd ++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000 ++#define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10 ++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1 ++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0 ++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00 ++#define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8 ++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000 ++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10 ++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000 ++#define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f ++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f ++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0 ++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00 ++#define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8 ++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1 ++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0 ++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2 ++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1 ++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4 ++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2 ++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10 ++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4 ++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20 ++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5 ++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40 ++#define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6 ++#define BLNDV_CONTROL__BLND_GLOBAL_GAIN_MASK 0xff ++#define BLNDV_CONTROL__BLND_GLOBAL_GAIN__SHIFT 0x0 ++#define BLNDV_CONTROL__BLND_MODE_MASK 0x300 ++#define BLNDV_CONTROL__BLND_MODE__SHIFT 0x8 ++#define BLNDV_CONTROL__BLND_STEREO_TYPE_MASK 0xc00 ++#define BLNDV_CONTROL__BLND_STEREO_TYPE__SHIFT 0xa ++#define BLNDV_CONTROL__BLND_STEREO_POLARITY_MASK 0x1000 ++#define BLNDV_CONTROL__BLND_STEREO_POLARITY__SHIFT 0xc ++#define BLNDV_CONTROL__BLND_FEEDTHROUGH_EN_MASK 0x2000 ++#define BLNDV_CONTROL__BLND_FEEDTHROUGH_EN__SHIFT 0xd ++#define BLNDV_CONTROL__BLND_ALPHA_MODE_MASK 0x30000 ++#define BLNDV_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10 ++#define BLNDV_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000 ++#define BLNDV_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14 ++#define BLNDV_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000 ++#define BLNDV_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18 ++#define BLNDV_SM_CONTROL2__SM_MODE_MASK 0x7 ++#define BLNDV_SM_CONTROL2__SM_MODE__SHIFT 0x0 ++#define BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10 ++#define BLNDV_SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4 ++#define BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20 ++#define BLNDV_SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5 ++#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300 ++#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 ++#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000 ++#define BLNDV_SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 ++#define BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000 ++#define BLNDV_SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18 ++#define BLNDV_CONTROL2__PTI_ENABLE_MASK 0x1 ++#define BLNDV_CONTROL2__PTI_ENABLE__SHIFT 0x0 ++#define BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP_MASK 0x30 ++#define BLNDV_CONTROL2__PTI_NEW_PIXEL_GAP__SHIFT 0x4 ++#define BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE_MASK 0x40 ++#define BLNDV_CONTROL2__BLND_NEW_PIXEL_MODE__SHIFT 0x6 ++#define BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN_MASK 0x80 ++#define BLNDV_CONTROL2__BLND_SUPERAA_DEGAMMA_EN__SHIFT 0x7 ++#define BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN_MASK 0x100 ++#define BLNDV_CONTROL2__BLND_SUPERAA_REGAMMA_EN__SHIFT 0x8 ++#define BLNDV_UPDATE__BLND_UPDATE_PENDING_MASK 0x1 ++#define BLNDV_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0 ++#define BLNDV_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100 ++#define BLNDV_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8 ++#define BLNDV_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000 ++#define BLNDV_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10 ++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1 ++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0 ++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100 ++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8 ++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000 ++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc ++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000 ++#define BLNDV_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10 ++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1 ++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0 ++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2 ++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1 ++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000 ++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10 ++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000 ++#define BLNDV_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18 ++#define BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000 ++#define BLNDV_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c ++#define BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK_MASK 0x20000000 ++#define BLNDV_V_UPDATE_LOCK__BLND_BLND_V_UPDATE_LOCK__SHIFT 0x1d ++#define BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE_MASK 0x80000000 ++#define BLNDV_V_UPDATE_LOCK__BLND_V_UPDATE_LOCK_MODE__SHIFT 0x1f ++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING_MASK 0x1 ++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_UPDATE_PENDING__SHIFT 0x0 ++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING_MASK 0x2 ++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_UPDATE_PENDING__SHIFT 0x1 ++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING_MASK 0x4 ++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2 ++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING_MASK 0x8 ++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3 ++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING_MASK 0x40 ++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDC_CUR_UPDATE_PENDING__SHIFT 0x6 ++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING_MASK 0x80 ++#define BLNDV_REG_UPDATE_STATUS__DCP_BLNDO_CUR_UPDATE_PENDING__SHIFT 0x7 ++#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING_MASK 0x100 ++#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDC_UPDATE_PENDING__SHIFT 0x8 ++#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING_MASK 0x200 ++#define BLNDV_REG_UPDATE_STATUS__SCL_BLNDO_UPDATE_PENDING__SHIFT 0x9 ++#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING_MASK 0x400 ++#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDC_UPDATE_PENDING__SHIFT 0xa ++#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING_MASK 0x800 ++#define BLNDV_REG_UPDATE_STATUS__BLND_BLNDO_UPDATE_PENDING__SHIFT 0xb ++#define BLNDV_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1 ++#define BLNDV_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0 ++#define BLNDV_DEBUG__BLND_DEBUG_MASK 0xfffffffe ++#define BLNDV_DEBUG__BLND_DEBUG__SHIFT 0x1 ++#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff ++#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define BLNDV_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff ++#define BLNDV_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0 ++#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff ++#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0 ++#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000 ++#define CRTCV_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10 ++#define CRTCV_H_TOTAL__CRTC_H_TOTAL_MASK 0x3fff ++#define CRTCV_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0 ++#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x3fff ++#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0 ++#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x3fff0000 ++#define CRTCV_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10 ++#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x3fff ++#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0 ++#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x3fff0000 ++#define CRTCV_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10 ++#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1 ++#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0 ++#define CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000 ++#define CRTCV_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10 ++#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000 ++#define CRTCV_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11 ++#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x3fff ++#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0 ++#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x3fff0000 ++#define CRTCV_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10 ++#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1 ++#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0 ++#define CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000 ++#define CRTCV_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10 ++#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000 ++#define CRTCV_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11 ++#define CRTCV_VBI_END__CRTC_VBI_V_END_MASK 0x3fff ++#define CRTCV_VBI_END__CRTC_VBI_V_END__SHIFT 0x0 ++#define CRTCV_VBI_END__CRTC_VBI_H_END_MASK 0x3fff0000 ++#define CRTCV_VBI_END__CRTC_VBI_H_END__SHIFT 0x10 ++#define CRTCV_V_TOTAL__CRTC_V_TOTAL_MASK 0x3fff ++#define CRTCV_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0 ++#define CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x3fff ++#define CRTCV_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0 ++#define CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x3fff ++#define CRTCV_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0 ++#define CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000 ++#define CRTCV_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10 ++#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1 ++#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0 ++#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10 ++#define CRTCV_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4 ++#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100 ++#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8 ++#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000 ++#define CRTCV_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc ++#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000 ++#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf ++#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000 ++#define CRTCV_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 ++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1 ++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 ++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10 ++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 ++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100 ++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 ++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000 ++#define CRTCV_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc ++#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1 ++#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0 ++#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10 ++#define CRTCV_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 ++#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x3fff ++#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0 ++#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x3fff0000 ++#define CRTCV_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10 ++#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x3fff ++#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0 ++#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x3fff0000 ++#define CRTCV_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10 ++#define CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1 ++#define CRTCV_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0 ++#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x3fff ++#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0 ++#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x3fff0000 ++#define CRTCV_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10 ++#define CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1 ++#define CRTCV_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0 ++#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1 ++#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0 ++#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e ++#define CRTCV_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1 ++#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x3fff ++#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0 ++#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x3fff0000 ++#define CRTCV_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000 ++#define CRTCV_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f ++#define CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1 ++#define CRTCV_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000 ++#define CRTCV_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f ++#define CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1 ++#define CRTCV_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0 ++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3 ++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0 ++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10 ++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 ++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100 ++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 ++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000 ++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 ++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000 ++#define CRTCV_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 ++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f ++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 ++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100 ++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8 ++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000 ++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 ++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000 ++#define CRTCV_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 ++#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3 ++#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 ++#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER_MASK 0xff00 ++#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_FRAME_COUNTER__SHIFT 0x8 ++#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER_MASK 0x1fff0000 ++#define CRTCV_STEREO_FORCE_NEXT_EYE__CRTC_AVSYNC_LINE_COUNTER__SHIFT 0x10 ++#define CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER_MASK 0xffffffff ++#define CRTCV_AVSYNC_COUNTER__CRTC_AVSYNC_COUNTER__SHIFT 0x0 ++#define CRTCV_CONTROL__CRTC_MASTER_EN_MASK 0x1 ++#define CRTCV_CONTROL__CRTC_MASTER_EN__SHIFT 0x0 ++#define CRTCV_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10 ++#define CRTCV_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4 ++#define CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300 ++#define CRTCV_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8 ++#define CRTCV_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000 ++#define CRTCV_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc ++#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000 ++#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd ++#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000 ++#define CRTCV_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe ++#define CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000 ++#define CRTCV_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10 ++#define CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000 ++#define CRTCV_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14 ++#define CRTCV_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000 ++#define CRTCV_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 ++#define CRTCV_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000 ++#define CRTCV_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d ++#define CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000 ++#define CRTCV_CONTROL__CRTC_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e ++#define CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000 ++#define CRTCV_CONTROL__CRTC_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f ++#define CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1 ++#define CRTCV_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0 ++#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100 ++#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8 ++#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000 ++#define CRTCV_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10 ++#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1 ++#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0 ++#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000 ++#define CRTCV_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 ++#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1 ++#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0 ++#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2 ++#define CRTCV_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1 ++#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1 ++#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 ++#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2 ++#define CRTCV_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1 ++#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff ++#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0 ++#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000 ++#define CRTCV_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10 ++#define CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff ++#define CRTCV_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0 ++#define CRTCV_STATUS__CRTC_V_BLANK_MASK 0x1 ++#define CRTCV_STATUS__CRTC_V_BLANK__SHIFT 0x0 ++#define CRTCV_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2 ++#define CRTCV_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1 ++#define CRTCV_STATUS__CRTC_V_SYNC_A_MASK 0x4 ++#define CRTCV_STATUS__CRTC_V_SYNC_A__SHIFT 0x2 ++#define CRTCV_STATUS__CRTC_V_UPDATE_MASK 0x8 ++#define CRTCV_STATUS__CRTC_V_UPDATE__SHIFT 0x3 ++#define CRTCV_STATUS__CRTC_V_START_LINE_MASK 0x10 ++#define CRTCV_STATUS__CRTC_V_START_LINE__SHIFT 0x4 ++#define CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20 ++#define CRTCV_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5 ++#define CRTCV_STATUS__CRTC_H_BLANK_MASK 0x10000 ++#define CRTCV_STATUS__CRTC_H_BLANK__SHIFT 0x10 ++#define CRTCV_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000 ++#define CRTCV_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11 ++#define CRTCV_STATUS__CRTC_H_SYNC_A_MASK 0x40000 ++#define CRTCV_STATUS__CRTC_H_SYNC_A__SHIFT 0x12 ++#define CRTCV_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x3fff ++#define CRTCV_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0 ++#define CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x3fff0000 ++#define CRTCV_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10 ++#define CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x3fff ++#define CRTCV_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0 ++#define CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff ++#define CRTCV_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0 ++#define CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x3fffffff ++#define CRTCV_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0 ++#define CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x3fffffff ++#define CRTCV_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0 ++#define CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1 ++#define CRTCV_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0 ++#define CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e ++#define CRTCV_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1 ++#define CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1 ++#define CRTCV_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0 ++#define CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1 ++#define CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 ++#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1 ++#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 ++#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100 ++#define CRTCV_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 ++#define CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000 ++#define CRTCV_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 ++#define CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1 ++#define CRTCV_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0 ++#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100 ++#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8 ++#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000 ++#define CRTCV_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10 ++#define CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG_MASK 0x100000 ++#define CRTCV_STEREO_STATUS__CRTC_STEREO_EYE_FLAG__SHIFT 0x14 ++#define CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000 ++#define CRTCV_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 ++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x3fff ++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 ++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000 ++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf ++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000 ++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10 ++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY_MASK 0x20000 ++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 ++#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x40000 ++#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 ++#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM_MASK 0x80000 ++#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_FIELD_NUM__SHIFT 0x13 ++#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x100000 ++#define CRTCV_STEREO_CONTROL__CRTC_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 ++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000 ++#define CRTCV_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18 ++#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1 ++#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0 ++#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2 ++#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1 ++#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4 ++#define CRTCV_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 ++#define CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3 ++#define CRTCV_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 ++#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x3fff ++#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0 ++#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x3fff0000 ++#define CRTCV_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 ++#define CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff ++#define CRTCV_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 ++#define CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1 ++#define CRTCV_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0 ++#define CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x2 ++#define CRTCV_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x1 ++#define CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x4 ++#define CRTCV_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x2 ++#define CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100 ++#define CRTCV_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x8 ++#define CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xff000 ++#define CRTCV_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0xc ++#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a ++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b ++#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c ++#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d ++#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e ++#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000 ++#define CRTCV_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f ++#define CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1 ++#define CRTCV_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0 ++#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1 ++#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0 ++#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100 ++#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8 ++#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000 ++#define CRTCV_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 ++#define CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1 ++#define CRTCV_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0 ++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1 ++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0 ++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700 ++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8 ++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000 ++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 ++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000 ++#define CRTCV_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 ++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf ++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0 ++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0 ++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4 ++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00 ++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8 ++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000 ++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc ++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000 ++#define CRTCV_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 ++#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff ++#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0 ++#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000 ++#define CRTCV_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10 ++#define CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1 ++#define CRTCV_MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0 ++#define CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100 ++#define CRTCV_MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8 ++#define CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK_MASK 0x10000 ++#define CRTCV_MASTER_UPDATE_LOCK__UNDERFLOW_UPDATE_LOCK__SHIFT 0x10 ++#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7 ++#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0 ++#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000 ++#define CRTCV_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10 ++#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3 ++#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0 ++#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00 ++#define CRTCV_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8 ++#define CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff ++#define CRTCV_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0 ++#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1 ++#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0 ++#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10 ++#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4 ++#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000 ++#define CRTCV_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10 ++#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000 ++#define CRTCV_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14 ++#define CRTCV_MASTER_EN__CRTC_MASTER_EN_MASK 0x1 ++#define CRTCV_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0 ++#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff ++#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0 ++#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000 ++#define CRTCV_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10 ++#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1 ++#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0 ++#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100 ++#define CRTCV_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8 ++#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff ++#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0 ++#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00 ++#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa ++#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000 ++#define CRTCV_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14 ++#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3 ++#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0 ++#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300 ++#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8 ++#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000 ++#define CRTCV_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10 ++#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff ++#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 ++#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00 ++#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa ++#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000 ++#define CRTCV_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 ++#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3 ++#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 ++#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300 ++#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 ++#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000 ++#define CRTCV_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 ++#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff ++#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0 ++#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00 ++#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa ++#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000 ++#define CRTCV_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14 ++#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3 ++#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 ++#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300 ++#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 ++#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000 ++#define CRTCV_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 ++#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x3fff ++#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 ++#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x3fff0000 ++#define CRTCV_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 ++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10 ++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 ++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100 ++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 ++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000 ++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc ++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000 ++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 ++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000 ++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 ++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000 ++#define CRTCV_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 ++#define CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x3fff ++#define CRTCV_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 ++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100 ++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 ++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000 ++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc ++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000 ++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 ++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000 ++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 ++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000 ++#define CRTCV_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 ++#define CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x3fff ++#define CRTCV_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 ++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100 ++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 ++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000 ++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc ++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000 ++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 ++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000 ++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 ++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000 ++#define CRTCV_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 ++#define CRTCV_CRC_CNTL__CRTC_CRC_EN_MASK 0x1 ++#define CRTCV_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0 ++#define CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10 ++#define CRTCV_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4 ++#define CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300 ++#define CRTCV_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8 ++#define CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000 ++#define CRTCV_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc ++#define CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 ++#define CRTCV_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 ++#define CRTCV_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000 ++#define CRTCV_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14 ++#define CRTCV_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000 ++#define CRTCV_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18 ++#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x3fff ++#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0 ++#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x3fff0000 ++#define CRTCV_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10 ++#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x3fff ++#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0 ++#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x3fff0000 ++#define CRTCV_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10 ++#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x3fff ++#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0 ++#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x3fff0000 ++#define CRTCV_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10 ++#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x3fff ++#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0 ++#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x3fff0000 ++#define CRTCV_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10 ++#define CRTCV_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff ++#define CRTCV_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 ++#define CRTCV_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000 ++#define CRTCV_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 ++#define CRTCV_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff ++#define CRTCV_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 ++#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x3fff ++#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0 ++#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x3fff0000 ++#define CRTCV_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10 ++#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x3fff ++#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0 ++#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x3fff0000 ++#define CRTCV_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10 ++#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x3fff ++#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0 ++#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x3fff0000 ++#define CRTCV_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10 ++#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x3fff ++#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0 ++#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x3fff0000 ++#define CRTCV_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10 ++#define CRTCV_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff ++#define CRTCV_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 ++#define CRTCV_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000 ++#define CRTCV_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 ++#define CRTCV_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff ++#define CRTCV_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000 ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000 ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18 ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000 ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19 ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000 ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000 ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000 ++#define CRTCV_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1 ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0 ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10 ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4 ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300 ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000 ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000 ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000 ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000 ++#define CRTCV_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000 ++#define CRTCV_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18 ++#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x3fff ++#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0 ++#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x3fff0000 ++#define CRTCV_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10 ++#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x3fff ++#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0 ++#define CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000 ++#define CRTCV_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10 ++#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000 ++#define CRTCV_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c ++#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff ++#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define CRTCV_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define CRTCV_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff ++#define CRTCV_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0 ++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300 ++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8 ++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000 ++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc ++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000 ++#define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10 ++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf ++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0 ++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70 ++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4 ++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300 ++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8 ++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00 ++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa ++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000 ++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc ++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000 ++#define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14 ++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7 ++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0 ++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000 ++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14 ++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000 ++#define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b ++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100 ++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8 ++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200 ++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9 ++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400 ++#define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa ++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000 ++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10 ++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000 ++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11 ++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000 ++#define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12 ++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000 ++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14 ++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000 ++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15 ++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000 ++#define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000 ++#define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE_MASK 0x3 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_CORE_IDLE_STATE__SHIFT 0x0 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE_MASK 0xc ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_IDLE_STATE__SHIFT 0x2 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE_MASK 0x180000 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_STATE__SHIFT 0x13 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS_MASK 0x200000 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_PCIE_TRANS__SHIFT 0x15 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE_MASK 0xc00000 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_STATE__SHIFT 0x16 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS_MASK 0x2000000 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_RD_TRANS__SHIFT 0x19 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE_MASK 0xc000000 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_STATE__SHIFT 0x1a ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS_MASK 0x10000000 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_WR_TRANS__SHIFT 0x1c ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE_MASK 0x60000000 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_STATE__SHIFT 0x1d ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS_MASK 0x80000000 ++#define XDMA_MEM_POWER_CNTL__XDMA_MEM_IF_BIF_TRANS__SHIFT 0x1f ++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf ++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0 ++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100 ++#define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8 ++#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff ++#define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0 ++#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1 ++#define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0 ++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff ++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff ++#define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0 ++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7 ++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0 ++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8 ++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3 ++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000 ++#define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf ++#define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff ++#define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0 ++#define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff ++#define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0 ++#define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff ++#define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0 ++#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000 ++#define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18 ++#define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000 ++#define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19 ++#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000 ++#define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a ++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff ++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0 ++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100 ++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 ++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200 ++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9 ++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN_MASK 0x400 ++#define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_OUT_EN__SHIFT 0xa ++#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff ++#define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0 ++#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000 ++#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc ++#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000 ++#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe ++#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000 ++#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10 ++#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000 ++#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12 ++#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000 ++#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14 ++#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000 ++#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15 ++#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff ++#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0 ++#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000 ++#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10 ++#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000 ++#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c ++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300 ++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8 ++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000 ++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc ++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000 ++#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10 ++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff ++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0 ++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff ++#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0 ++#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff ++#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0 ++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1 ++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0 ++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00 ++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8 ++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000 ++#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc ++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1 ++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0 ++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0 ++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4 ++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00 ++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8 ++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000 ++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc ++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000 ++#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10 ++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff ++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0 ++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000 ++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc ++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000 ++#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10 ++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff ++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0 ++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000 ++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc ++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000 ++#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10 ++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7 ++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0 ++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00 ++#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE_MASK 0x10000000 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_SUPERAA_ENABLE__SHIFT 0x1c ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP_MASK 0x60000000 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_HSYNC_GSL_GROUP__SHIFT 0x1d ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER_MASK 0x80000000 ++#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_GSL_GROUP_MASTER__SHIFT 0x1f ++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff ++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0 ++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000 ++#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10 ++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff ++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0 ++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000 ++#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10 ++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff ++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0 ++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000 ++#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10 ++#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff ++#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0 ++#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff ++#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0 ++#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff ++#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0 ++#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff ++#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0 ++#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff ++#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0 ++#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff ++#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0 ++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff ++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0 ++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE_MASK 0x60000000 ++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_STATE__SHIFT 0x1d ++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS_MASK 0x80000000 ++#define XDMA_MSTR_CACHE__XDMA_MSTR_CACHE_TLB_PG_TRANS__SHIFT 0x1f ++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff ++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0 ++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000 ++#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10 ++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff ++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0 ++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000 ++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18 ++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000 ++#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e ++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff ++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0 ++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000 ++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc ++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000 ++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11 ++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000 ++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13 ++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000 ++#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f ++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1 ++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0 ++#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200 ++#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9 ++#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400 ++#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa ++#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000 ++#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc ++#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000 ++#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10 ++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000 ++#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13 ++#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000 ++#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14 ++#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000 ++#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18 ++#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET_MASK 0x2000000 ++#define XDMA_SLV_CNTL__XDMA_SLV_WB_BURST_RESET__SHIFT 0x19 ++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300 ++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8 ++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000 ++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc ++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000 ++#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10 ++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff ++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0 ++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000 ++#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10 ++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1 ++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0 ++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0 ++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4 ++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00 ++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8 ++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000 ++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc ++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000 ++#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10 ++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1 ++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0 ++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00 ++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8 ++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000 ++#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc ++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff ++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0 ++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000 ++#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10 ++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff ++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0 ++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000 ++#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10 ++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff ++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0 ++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000 ++#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14 ++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff ++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0 ++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000 ++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc ++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000 ++#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10 ++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff ++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0 ++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000 ++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10 ++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000 ++#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f ++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff ++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0 ++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000 ++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc ++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE_MASK 0xc00000 ++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_STATE__SHIFT 0x16 ++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS_MASK 0x1000000 ++#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_PG_TRANS__SHIFT 0x18 ++#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff ++#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0 ++#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1 ++#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0 ++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff ++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0 ++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000 ++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10 ++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000 ++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11 ++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000 ++#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18 ++#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff ++#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0 ++#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff ++#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0 ++ ++#endif /* DCE_11_0_SH_MASK_H */ +-- +cgit v0.10.2 + |