diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-drm-amdgpu-Add-initial-VI-support.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-drm-amdgpu-Add-initial-VI-support.patch | 37757 |
1 files changed, 37757 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-drm-amdgpu-Add-initial-VI-support.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-drm-amdgpu-Add-initial-VI-support.patch new file mode 100644 index 00000000..e066809d --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-drm-amdgpu-Add-initial-VI-support.patch @@ -0,0 +1,37757 @@ +From 00f68a4d67bf0cb36586416022e251f300d6938e Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 16 Apr 2015 15:16:08 -0400 +Subject: drm/amdgpu: add BIF 5.1 register headers + +These are register headers for the BIF (Bus InterFace) block on +the GPU. + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Sanjay R Mehta <Sanju.Mehta@amd.com> + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h +new file mode 100644 +index 0000000..b52c9aa +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_d.h +@@ -0,0 +1,3577 @@ ++/* ++ * BIF_5_1 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef BIF_5_1_D_H ++#define BIF_5_1_D_H ++ ++#define mmMM_INDEX 0x0 ++#define mmMM_INDEX_HI 0x6 ++#define mmMM_DATA 0x1 ++#define mmBIF_MM_INDACCESS_CNTL 0x1500 ++#define mmBUS_CNTL 0x1508 ++#define mmCONFIG_CNTL 0x1509 ++#define mmCONFIG_MEMSIZE 0x150a ++#define mmCONFIG_F0_BASE 0x150b ++#define mmCONFIG_APER_SIZE 0x150c ++#define mmCONFIG_REG_APER_SIZE 0x150d ++#define mmBIF_SCRATCH0 0x150e ++#define mmBIF_SCRATCH1 0x150f ++#define mmBX_RESET_EN 0x1514 ++#define mmMM_CFGREGS_CNTL 0x1513 ++#define mmHW_DEBUG 0x1515 ++#define mmMASTER_CREDIT_CNTL 0x1516 ++#define mmSLAVE_REQ_CREDIT_CNTL 0x1517 ++#define mmBX_RESET_CNTL 0x1518 ++#define mmINTERRUPT_CNTL 0x151a ++#define mmINTERRUPT_CNTL2 0x151b ++#define mmBIF_DEBUG_CNTL 0x151c ++#define mmBIF_DEBUG_MUX 0x151d ++#define mmBIF_DEBUG_OUT 0x151e ++#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 ++#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 ++#define mmCLKREQB_PAD_CNTL 0x1521 ++#define mmSMBDAT_PAD_CNTL 0x1522 ++#define mmSMBCLK_PAD_CNTL 0x1523 ++#define mmBIF_XDMA_LO 0x14c0 ++#define mmBIF_XDMA_HI 0x14c1 ++#define mmBIF_FEATURES_CONTROL_MISC 0x14c2 ++#define mmBIF_DOORBELL_CNTL 0x14c3 ++#define mmBIF_SLVARB_MODE 0x14c4 ++#define mmBIF_FB_EN 0x1524 ++#define mmBIF_BUSNUM_CNTL1 0x1525 ++#define mmBIF_BUSNUM_LIST0 0x1526 ++#define mmBIF_BUSNUM_LIST1 0x1527 ++#define mmBIF_BUSNUM_CNTL2 0x152b ++#define mmBIF_BUSY_DELAY_CNTR 0x1529 ++#define mmBIF_PERFMON_CNTL 0x152c ++#define mmBIF_PERFCOUNTER0_RESULT 0x152d ++#define mmBIF_PERFCOUNTER1_RESULT 0x152e ++#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 ++#define mmGPU_HDP_FLUSH_REQ 0x1537 ++#define mmGPU_HDP_FLUSH_DONE 0x1538 ++#define mmSLAVE_HANG_ERROR 0x153b ++#define mmCAPTURE_HOST_BUSNUM 0x153c ++#define mmHOST_BUSNUM 0x153d ++#define mmPEER_REG_RANGE0 0x153e ++#define mmPEER_REG_RANGE1 0x153f ++#define mmPEER0_FB_OFFSET_HI 0x14f3 ++#define mmPEER0_FB_OFFSET_LO 0x14f2 ++#define mmPEER1_FB_OFFSET_HI 0x14f1 ++#define mmPEER1_FB_OFFSET_LO 0x14f0 ++#define mmPEER2_FB_OFFSET_HI 0x14ef ++#define mmPEER2_FB_OFFSET_LO 0x14ee ++#define mmPEER3_FB_OFFSET_HI 0x14ed ++#define mmPEER3_FB_OFFSET_LO 0x14ec ++#define mmDBG_BYPASS_SRBM_ACCESS 0x14eb ++#define mmSMBUS_BACO_DUMMY 0x14c6 ++#define mmBIF_DEVFUNCNUM_LIST0 0x14e8 ++#define mmBIF_DEVFUNCNUM_LIST1 0x14e7 ++#define mmBACO_CNTL 0x14e5 ++#define mmBF_ANA_ISO_CNTL 0x14c7 ++#define mmMEM_TYPE_CNTL 0x14e4 ++#define mmBIF_BACO_DEBUG 0x14df ++#define mmBIF_BACO_DEBUG_LATCH 0x14dc ++#define mmBACO_CNTL_MISC 0x14db ++#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8 ++#define mmBIF_VDDGFX_GFX0_LOWER 0x1428 ++#define mmBIF_VDDGFX_GFX0_UPPER 0x1429 ++#define mmBIF_VDDGFX_GFX1_LOWER 0x142a ++#define mmBIF_VDDGFX_GFX1_UPPER 0x142b ++#define mmBIF_VDDGFX_GFX2_LOWER 0x142c ++#define mmBIF_VDDGFX_GFX2_UPPER 0x142d ++#define mmBIF_VDDGFX_GFX3_LOWER 0x142e ++#define mmBIF_VDDGFX_GFX3_UPPER 0x142f ++#define mmBIF_VDDGFX_GFX4_LOWER 0x1430 ++#define mmBIF_VDDGFX_GFX4_UPPER 0x1431 ++#define mmBIF_VDDGFX_GFX5_LOWER 0x1432 ++#define mmBIF_VDDGFX_GFX5_UPPER 0x1433 ++#define mmBIF_VDDGFX_RSV1_LOWER 0x1434 ++#define mmBIF_VDDGFX_RSV1_UPPER 0x1435 ++#define mmBIF_VDDGFX_RSV2_LOWER 0x1436 ++#define mmBIF_VDDGFX_RSV2_UPPER 0x1437 ++#define mmBIF_VDDGFX_RSV3_LOWER 0x1438 ++#define mmBIF_VDDGFX_RSV3_UPPER 0x1439 ++#define mmBIF_VDDGFX_RSV4_LOWER 0x143a ++#define mmBIF_VDDGFX_RSV4_UPPER 0x143b ++#define mmBIF_VDDGFX_FB_CMP 0x143c ++#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x14fc ++#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x14fd ++#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x14fe ++#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x14ff ++#define mmBIF_SMU_INDEX 0x143d ++#define mmBIF_SMU_DATA 0x143e ++#define mmIMPCTL_RESET 0x14f5 ++#define mmGARLIC_FLUSH_CNTL 0x1401 ++#define mmGARLIC_FLUSH_ADDR_START_0 0x1402 ++#define mmGARLIC_FLUSH_ADDR_START_1 0x1404 ++#define mmGARLIC_FLUSH_ADDR_START_2 0x1406 ++#define mmGARLIC_FLUSH_ADDR_START_3 0x1408 ++#define mmGARLIC_FLUSH_ADDR_START_4 0x140a ++#define mmGARLIC_FLUSH_ADDR_START_5 0x140c ++#define mmGARLIC_FLUSH_ADDR_START_6 0x140e ++#define mmGARLIC_FLUSH_ADDR_START_7 0x1410 ++#define mmGARLIC_FLUSH_ADDR_END_0 0x1403 ++#define mmGARLIC_FLUSH_ADDR_END_1 0x1405 ++#define mmGARLIC_FLUSH_ADDR_END_2 0x1407 ++#define mmGARLIC_FLUSH_ADDR_END_3 0x1409 ++#define mmGARLIC_FLUSH_ADDR_END_4 0x140b ++#define mmGARLIC_FLUSH_ADDR_END_5 0x140d ++#define mmGARLIC_FLUSH_ADDR_END_6 0x140f ++#define mmGARLIC_FLUSH_ADDR_END_7 0x1411 ++#define mmGARLIC_FLUSH_REQ 0x1412 ++#define mmGPU_GARLIC_FLUSH_REQ 0x1413 ++#define mmGPU_GARLIC_FLUSH_DONE 0x1414 ++#define mmGARLIC_COHE_CP_RB0_WPTR 0x1415 ++#define mmGARLIC_COHE_CP_RB1_WPTR 0x1416 ++#define mmGARLIC_COHE_CP_RB2_WPTR 0x1417 ++#define mmGARLIC_COHE_UVD_RBC_RB_WPTR 0x1418 ++#define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR 0x1419 ++#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR 0x141a ++#define mmGARLIC_COHE_CP_DMA_ME_COMMAND 0x141b ++#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND 0x141c ++#define mmGARLIC_COHE_SAM_SAB_RBI_WPTR 0x141d ++#define mmGARLIC_COHE_SAM_SAB_RBO_WPTR 0x141e ++#define mmGARLIC_COHE_VCE_OUT_RB_WPTR 0x141f ++#define mmGARLIC_COHE_VCE_RB_WPTR2 0x1420 ++#define mmGARLIC_COHE_VCE_RB_WPTR 0x1421 ++#define mmGARLIC_COHE_SDMA2_GFX_RB_WPTR 0x1422 ++#define mmGARLIC_COHE_SDMA3_GFX_RB_WPTR 0x1423 ++#define mmGARLIC_COHE_CP_DMA_PIO_COMMAND 0x1424 ++#define mmGARLIC_COHE_GARLIC_FLUSH_REQ 0x1425 ++#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x1426 ++#define mmREMAP_HDP_REG_FLUSH_CNTL 0x1427 ++#define mmBIOS_SCRATCH_0 0x5c9 ++#define mmBIOS_SCRATCH_1 0x5ca ++#define mmBIOS_SCRATCH_2 0x5cb ++#define mmBIOS_SCRATCH_3 0x5cc ++#define mmBIOS_SCRATCH_4 0x5cd ++#define mmBIOS_SCRATCH_5 0x5ce ++#define mmBIOS_SCRATCH_6 0x5cf ++#define mmBIOS_SCRATCH_7 0x5d0 ++#define mmBIOS_SCRATCH_8 0x5d1 ++#define mmBIOS_SCRATCH_9 0x5d2 ++#define mmBIOS_SCRATCH_10 0x5d3 ++#define mmBIOS_SCRATCH_11 0x5d4 ++#define mmBIOS_SCRATCH_12 0x5d5 ++#define mmBIOS_SCRATCH_13 0x5d6 ++#define mmBIOS_SCRATCH_14 0x5d7 ++#define mmBIOS_SCRATCH_15 0x5d8 ++#define mmBIF_RB_CNTL 0x1530 ++#define mmBIF_RB_BASE 0x1531 ++#define mmBIF_RB_RPTR 0x1532 ++#define mmBIF_RB_WPTR 0x1533 ++#define mmBIF_RB_WPTR_ADDR_HI 0x1534 ++#define mmBIF_RB_WPTR_ADDR_LO 0x1535 ++#define mmVENDOR_ID 0x0 ++#define mmDEVICE_ID 0x0 ++#define mmCOMMAND 0x1 ++#define mmSTATUS 0x1 ++#define mmREVISION_ID 0x2 ++#define mmPROG_INTERFACE 0x2 ++#define mmSUB_CLASS 0x2 ++#define mmBASE_CLASS 0x2 ++#define mmCACHE_LINE 0x3 ++#define mmLATENCY 0x3 ++#define mmHEADER 0x3 ++#define mmBIST 0x3 ++#define mmBASE_ADDR_1 0x4 ++#define mmBASE_ADDR_2 0x5 ++#define mmBASE_ADDR_3 0x6 ++#define mmBASE_ADDR_4 0x7 ++#define mmBASE_ADDR_5 0x8 ++#define mmBASE_ADDR_6 0x9 ++#define mmROM_BASE_ADDR 0xc ++#define mmCAP_PTR 0xd ++#define mmINTERRUPT_LINE 0xf ++#define mmINTERRUPT_PIN 0xf ++#define mmADAPTER_ID 0xb ++#define mmMIN_GRANT 0xf ++#define mmMAX_LATENCY 0xf ++#define mmVENDOR_CAP_LIST 0x12 ++#define mmADAPTER_ID_W 0x13 ++#define mmPMI_CAP_LIST 0x14 ++#define mmPMI_CAP 0x14 ++#define mmPMI_STATUS_CNTL 0x15 ++#define mmPCIE_CAP_LIST 0x16 ++#define mmPCIE_CAP 0x16 ++#define mmDEVICE_CAP 0x17 ++#define mmDEVICE_CNTL 0x18 ++#define mmDEVICE_STATUS 0x18 ++#define mmLINK_CAP 0x19 ++#define mmLINK_CNTL 0x1a ++#define mmLINK_STATUS 0x1a ++#define mmDEVICE_CAP2 0x1f ++#define mmDEVICE_CNTL2 0x20 ++#define mmDEVICE_STATUS2 0x20 ++#define mmLINK_CAP2 0x21 ++#define mmLINK_CNTL2 0x22 ++#define mmLINK_STATUS2 0x22 ++#define mmMSI_CAP_LIST 0x28 ++#define mmMSI_MSG_CNTL 0x28 ++#define mmMSI_MSG_ADDR_LO 0x29 ++#define mmMSI_MSG_ADDR_HI 0x2a ++#define mmMSI_MSG_DATA_64 0x2b ++#define mmMSI_MSG_DATA 0x2a ++#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40 ++#define mmPCIE_VENDOR_SPECIFIC_HDR 0x41 ++#define mmPCIE_VENDOR_SPECIFIC1 0x42 ++#define mmPCIE_VENDOR_SPECIFIC2 0x43 ++#define mmPCIE_VC_ENH_CAP_LIST 0x44 ++#define mmPCIE_PORT_VC_CAP_REG1 0x45 ++#define mmPCIE_PORT_VC_CAP_REG2 0x46 ++#define mmPCIE_PORT_VC_CNTL 0x47 ++#define mmPCIE_PORT_VC_STATUS 0x47 ++#define mmPCIE_VC0_RESOURCE_CAP 0x48 ++#define mmPCIE_VC0_RESOURCE_CNTL 0x49 ++#define mmPCIE_VC0_RESOURCE_STATUS 0x4a ++#define mmPCIE_VC1_RESOURCE_CAP 0x4b ++#define mmPCIE_VC1_RESOURCE_CNTL 0x4c ++#define mmPCIE_VC1_RESOURCE_STATUS 0x4d ++#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50 ++#define mmPCIE_DEV_SERIAL_NUM_DW1 0x51 ++#define mmPCIE_DEV_SERIAL_NUM_DW2 0x52 ++#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54 ++#define mmPCIE_UNCORR_ERR_STATUS 0x55 ++#define mmPCIE_UNCORR_ERR_MASK 0x56 ++#define mmPCIE_UNCORR_ERR_SEVERITY 0x57 ++#define mmPCIE_CORR_ERR_STATUS 0x58 ++#define mmPCIE_CORR_ERR_MASK 0x59 ++#define mmPCIE_ADV_ERR_CAP_CNTL 0x5a ++#define mmPCIE_HDR_LOG0 0x5b ++#define mmPCIE_HDR_LOG1 0x5c ++#define mmPCIE_HDR_LOG2 0x5d ++#define mmPCIE_HDR_LOG3 0x5e ++#define mmPCIE_TLP_PREFIX_LOG0 0x62 ++#define mmPCIE_TLP_PREFIX_LOG1 0x63 ++#define mmPCIE_TLP_PREFIX_LOG2 0x64 ++#define mmPCIE_TLP_PREFIX_LOG3 0x65 ++#define mmPCIE_BAR_ENH_CAP_LIST 0x80 ++#define mmPCIE_BAR1_CAP 0x81 ++#define mmPCIE_BAR1_CNTL 0x82 ++#define mmPCIE_BAR2_CAP 0x83 ++#define mmPCIE_BAR2_CNTL 0x84 ++#define mmPCIE_BAR3_CAP 0x85 ++#define mmPCIE_BAR3_CNTL 0x86 ++#define mmPCIE_BAR4_CAP 0x87 ++#define mmPCIE_BAR4_CNTL 0x88 ++#define mmPCIE_BAR5_CAP 0x89 ++#define mmPCIE_BAR5_CNTL 0x8a ++#define mmPCIE_BAR6_CAP 0x8b ++#define mmPCIE_BAR6_CNTL 0x8c ++#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90 ++#define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91 ++#define mmPCIE_PWR_BUDGET_DATA 0x92 ++#define mmPCIE_PWR_BUDGET_CAP 0x93 ++#define mmPCIE_DPA_ENH_CAP_LIST 0x94 ++#define mmPCIE_DPA_CAP 0x95 ++#define mmPCIE_DPA_LATENCY_INDICATOR 0x96 ++#define mmPCIE_DPA_STATUS 0x97 ++#define mmPCIE_DPA_CNTL 0x97 ++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98 ++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98 ++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98 ++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98 ++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99 ++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99 ++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99 ++#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99 ++#define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c ++#define mmPCIE_LINK_CNTL3 0x9d ++#define mmPCIE_LANE_ERROR_STATUS 0x9e ++#define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f ++#define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f ++#define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0 ++#define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0 ++#define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1 ++#define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1 ++#define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2 ++#define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2 ++#define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3 ++#define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3 ++#define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4 ++#define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4 ++#define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5 ++#define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5 ++#define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6 ++#define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6 ++#define mmPCIE_ACS_ENH_CAP_LIST 0xa8 ++#define mmPCIE_ACS_CAP 0xa9 ++#define mmPCIE_ACS_CNTL 0xa9 ++#define mmPCIE_ATS_ENH_CAP_LIST 0xac ++#define mmPCIE_ATS_CAP 0xad ++#define mmPCIE_ATS_CNTL 0xad ++#define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0 ++#define mmPCIE_PAGE_REQ_CNTL 0xb1 ++#define mmPCIE_PAGE_REQ_STATUS 0xb1 ++#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2 ++#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3 ++#define mmPCIE_PASID_ENH_CAP_LIST 0xb4 ++#define mmPCIE_PASID_CAP 0xb5 ++#define mmPCIE_PASID_CNTL 0xb5 ++#define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8 ++#define mmPCIE_TPH_REQR_CAP 0xb9 ++#define mmPCIE_TPH_REQR_CNTL 0xba ++#define mmPCIE_MC_ENH_CAP_LIST 0xbc ++#define mmPCIE_MC_CAP 0xbd ++#define mmPCIE_MC_CNTL 0xbd ++#define mmPCIE_MC_ADDR0 0xbe ++#define mmPCIE_MC_ADDR1 0xbf ++#define mmPCIE_MC_RCV0 0xc0 ++#define mmPCIE_MC_RCV1 0xc1 ++#define mmPCIE_MC_BLOCK_ALL0 0xc2 ++#define mmPCIE_MC_BLOCK_ALL1 0xc3 ++#define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4 ++#define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5 ++#define mmPCIE_LTR_ENH_CAP_LIST 0xc8 ++#define mmPCIE_LTR_CAP 0xc9 ++#define ixMM_INDEX_IND 0x1090000 ++#define ixMM_INDEX_HI_IND 0x1090006 ++#define ixMM_DATA_IND 0x1090001 ++#define ixBIF_MM_INDACCESS_CNTL_IND 0x1091500 ++#define ixBUS_CNTL_IND 0x1091508 ++#define ixCONFIG_CNTL_IND 0x1091509 ++#define ixCONFIG_MEMSIZE_IND 0x109150a ++#define ixCONFIG_F0_BASE_IND 0x109150b ++#define ixCONFIG_APER_SIZE_IND 0x109150c ++#define ixCONFIG_REG_APER_SIZE_IND 0x109150d ++#define ixBIF_SCRATCH0_IND 0x109150e ++#define ixBIF_SCRATCH1_IND 0x109150f ++#define ixBX_RESET_EN_IND 0x1091514 ++#define ixMM_CFGREGS_CNTL_IND 0x1091513 ++#define ixHW_DEBUG_IND 0x1091515 ++#define ixMASTER_CREDIT_CNTL_IND 0x1091516 ++#define ixSLAVE_REQ_CREDIT_CNTL_IND 0x1091517 ++#define ixBX_RESET_CNTL_IND 0x1091518 ++#define ixINTERRUPT_CNTL_IND 0x109151a ++#define ixINTERRUPT_CNTL2_IND 0x109151b ++#define ixBIF_DEBUG_CNTL_IND 0x109151c ++#define ixBIF_DEBUG_MUX_IND 0x109151d ++#define ixBIF_DEBUG_OUT_IND 0x109151e ++#define ixHDP_REG_COHERENCY_FLUSH_CNTL_IND 0x1091528 ++#define ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND 0x1091520 ++#define ixCLKREQB_PAD_CNTL_IND 0x1091521 ++#define ixSMBDAT_PAD_CNTL_IND 0x1091522 ++#define ixSMBCLK_PAD_CNTL_IND 0x1091523 ++#define ixBIF_XDMA_LO_IND 0x10914c0 ++#define ixBIF_XDMA_HI_IND 0x10914c1 ++#define ixBIF_FEATURES_CONTROL_MISC_IND 0x10914c2 ++#define ixBIF_DOORBELL_CNTL_IND 0x10914c3 ++#define ixBIF_SLVARB_MODE_IND 0x10914c4 ++#define ixBIF_FB_EN_IND 0x1091524 ++#define ixBIF_BUSNUM_CNTL1_IND 0x1091525 ++#define ixBIF_BUSNUM_LIST0_IND 0x1091526 ++#define ixBIF_BUSNUM_LIST1_IND 0x1091527 ++#define ixBIF_BUSNUM_CNTL2_IND 0x109152b ++#define ixBIF_BUSY_DELAY_CNTR_IND 0x1091529 ++#define ixBIF_PERFMON_CNTL_IND 0x109152c ++#define ixBIF_PERFCOUNTER0_RESULT_IND 0x109152d ++#define ixBIF_PERFCOUNTER1_RESULT_IND 0x109152e ++#define ixSLAVE_HANG_PROTECTION_CNTL_IND 0x1091536 ++#define ixGPU_HDP_FLUSH_REQ_IND 0x1091537 ++#define ixGPU_HDP_FLUSH_DONE_IND 0x1091538 ++#define ixSLAVE_HANG_ERROR_IND 0x109153b ++#define ixCAPTURE_HOST_BUSNUM_IND 0x109153c ++#define ixHOST_BUSNUM_IND 0x109153d ++#define ixPEER_REG_RANGE0_IND 0x109153e ++#define ixPEER_REG_RANGE1_IND 0x109153f ++#define ixPEER0_FB_OFFSET_HI_IND 0x10914f3 ++#define ixPEER0_FB_OFFSET_LO_IND 0x10914f2 ++#define ixPEER1_FB_OFFSET_HI_IND 0x10914f1 ++#define ixPEER1_FB_OFFSET_LO_IND 0x10914f0 ++#define ixPEER2_FB_OFFSET_HI_IND 0x10914ef ++#define ixPEER2_FB_OFFSET_LO_IND 0x10914ee ++#define ixPEER3_FB_OFFSET_HI_IND 0x10914ed ++#define ixPEER3_FB_OFFSET_LO_IND 0x10914ec ++#define ixDBG_BYPASS_SRBM_ACCESS_IND 0x10914eb ++#define ixSMBUS_BACO_DUMMY_IND 0x10914c6 ++#define ixBIF_DEVFUNCNUM_LIST0_IND 0x10914e8 ++#define ixBIF_DEVFUNCNUM_LIST1_IND 0x10914e7 ++#define ixBACO_CNTL_IND 0x10914e5 ++#define ixBF_ANA_ISO_CNTL_IND 0x10914c7 ++#define ixMEM_TYPE_CNTL_IND 0x10914e4 ++#define ixBIF_BACO_DEBUG_IND 0x10914df ++#define ixBIF_BACO_DEBUG_LATCH_IND 0x10914dc ++#define ixBACO_CNTL_MISC_IND 0x10914db ++#define ixSMU_BIF_VDDGFX_PWR_STATUS_IND 0x10914f8 ++#define ixBIF_VDDGFX_GFX0_LOWER_IND 0x1091428 ++#define ixBIF_VDDGFX_GFX0_UPPER_IND 0x1091429 ++#define ixBIF_VDDGFX_GFX1_LOWER_IND 0x109142a ++#define ixBIF_VDDGFX_GFX1_UPPER_IND 0x109142b ++#define ixBIF_VDDGFX_GFX2_LOWER_IND 0x109142c ++#define ixBIF_VDDGFX_GFX2_UPPER_IND 0x109142d ++#define ixBIF_VDDGFX_GFX3_LOWER_IND 0x109142e ++#define ixBIF_VDDGFX_GFX3_UPPER_IND 0x109142f ++#define ixBIF_VDDGFX_GFX4_LOWER_IND 0x1091430 ++#define ixBIF_VDDGFX_GFX4_UPPER_IND 0x1091431 ++#define ixBIF_VDDGFX_GFX5_LOWER_IND 0x1091432 ++#define ixBIF_VDDGFX_GFX5_UPPER_IND 0x1091433 ++#define ixBIF_VDDGFX_RSV1_LOWER_IND 0x1091434 ++#define ixBIF_VDDGFX_RSV1_UPPER_IND 0x1091435 ++#define ixBIF_VDDGFX_RSV2_LOWER_IND 0x1091436 ++#define ixBIF_VDDGFX_RSV2_UPPER_IND 0x1091437 ++#define ixBIF_VDDGFX_RSV3_LOWER_IND 0x1091438 ++#define ixBIF_VDDGFX_RSV3_UPPER_IND 0x1091439 ++#define ixBIF_VDDGFX_RSV4_LOWER_IND 0x109143a ++#define ixBIF_VDDGFX_RSV4_UPPER_IND 0x109143b ++#define ixBIF_VDDGFX_FB_CMP_IND 0x109143c ++#define ixBIF_DOORBELL_GBLAPER1_LOWER_IND 0x10914fc ++#define ixBIF_DOORBELL_GBLAPER1_UPPER_IND 0x10914fd ++#define ixBIF_DOORBELL_GBLAPER2_LOWER_IND 0x10914fe ++#define ixBIF_DOORBELL_GBLAPER2_UPPER_IND 0x10914ff ++#define ixBIF_SMU_INDEX_IND 0x109143d ++#define ixBIF_SMU_DATA_IND 0x109143e ++#define ixIMPCTL_RESET_IND 0x10914f5 ++#define ixGARLIC_FLUSH_CNTL_IND 0x1091401 ++#define ixGARLIC_FLUSH_REQ_IND 0x1091412 ++#define ixGPU_GARLIC_FLUSH_REQ_IND 0x1091413 ++#define ixGPU_GARLIC_FLUSH_DONE_IND 0x1091414 ++#define ixGARLIC_COHE_CP_RB0_WPTR_IND 0x1091415 ++#define ixGARLIC_COHE_CP_RB1_WPTR_IND 0x1091416 ++#define ixGARLIC_COHE_CP_RB2_WPTR_IND 0x1091417 ++#define ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND 0x1091418 ++#define ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND 0x1091419 ++#define ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND 0x109141a ++#define ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND 0x109141b ++#define ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND 0x109141c ++#define ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND 0x109141d ++#define ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND 0x109141e ++#define ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND 0x109141f ++#define ixGARLIC_COHE_VCE_RB_WPTR2_IND 0x1091420 ++#define ixGARLIC_COHE_VCE_RB_WPTR_IND 0x1091421 ++#define ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND 0x1091422 ++#define ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND 0x1091423 ++#define ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND 0x1091424 ++#define ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND 0x1091425 ++#define ixREMAP_HDP_MEM_FLUSH_CNTL_IND 0x1091426 ++#define ixREMAP_HDP_REG_FLUSH_CNTL_IND 0x1091427 ++#define ixBIOS_SCRATCH_0_IND 0x10905c9 ++#define ixBIOS_SCRATCH_1_IND 0x10905ca ++#define ixBIOS_SCRATCH_2_IND 0x10905cb ++#define ixBIOS_SCRATCH_3_IND 0x10905cc ++#define ixBIOS_SCRATCH_4_IND 0x10905cd ++#define ixBIOS_SCRATCH_5_IND 0x10905ce ++#define ixBIOS_SCRATCH_6_IND 0x10905cf ++#define ixBIOS_SCRATCH_7_IND 0x10905d0 ++#define ixBIOS_SCRATCH_8_IND 0x10905d1 ++#define ixBIOS_SCRATCH_9_IND 0x10905d2 ++#define ixBIOS_SCRATCH_10_IND 0x10905d3 ++#define ixBIOS_SCRATCH_11_IND 0x10905d4 ++#define ixBIOS_SCRATCH_12_IND 0x10905d5 ++#define ixBIOS_SCRATCH_13_IND 0x10905d6 ++#define ixBIOS_SCRATCH_14_IND 0x10905d7 ++#define ixBIOS_SCRATCH_15_IND 0x10905d8 ++#define ixBIF_RB_CNTL_IND 0x1091530 ++#define ixBIF_RB_BASE_IND 0x1091531 ++#define ixBIF_RB_RPTR_IND 0x1091532 ++#define ixBIF_RB_WPTR_IND 0x1091533 ++#define ixBIF_RB_WPTR_ADDR_HI_IND 0x1091534 ++#define ixBIF_RB_WPTR_ADDR_LO_IND 0x1091535 ++#define mmNB_GBIF_INDEX 0x34 ++#define mmNB_GBIF_DATA 0x35 ++#define mmPCIE_INDEX 0xe ++#define mmPCIE_DATA 0xf ++#define mmPCIE_INDEX_2 0xc ++#define mmPCIE_DATA_2 0xd ++#define ixPCIE_RESERVED 0x1400000 ++#define ixPCIE_SCRATCH 0x1400001 ++#define ixPCIE_HW_DEBUG 0x1400002 ++#define ixPCIE_RX_NUM_NAK 0x140000e ++#define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f ++#define ixPCIE_CNTL 0x1400010 ++#define ixPCIE_CONFIG_CNTL 0x1400011 ++#define ixPCIE_DEBUG_CNTL 0x1400012 ++#define ixPCIE_INT_CNTL 0x140001a ++#define ixPCIE_INT_STATUS 0x140001b ++#define ixPCIE_CNTL2 0x140001c ++#define ixPCIE_RX_CNTL2 0x140001d ++#define ixPCIE_TX_F0_ATTR_CNTL 0x140001e ++#define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f ++#define ixPCIE_CI_CNTL 0x1400020 ++#define ixPCIE_BUS_CNTL 0x1400021 ++#define ixPCIE_LC_STATE6 0x1400022 ++#define ixPCIE_LC_STATE7 0x1400023 ++#define ixPCIE_LC_STATE8 0x1400024 ++#define ixPCIE_LC_STATE9 0x1400025 ++#define ixPCIE_LC_STATE10 0x1400026 ++#define ixPCIE_LC_STATE11 0x1400027 ++#define ixPCIE_LC_STATUS1 0x1400028 ++#define ixPCIE_LC_STATUS2 0x1400029 ++#define ixPCIE_WPR_CNTL 0x1400030 ++#define ixPCIE_RX_LAST_TLP0 0x1400031 ++#define ixPCIE_RX_LAST_TLP1 0x1400032 ++#define ixPCIE_RX_LAST_TLP2 0x1400033 ++#define ixPCIE_RX_LAST_TLP3 0x1400034 ++#define ixPCIE_TX_LAST_TLP0 0x1400035 ++#define ixPCIE_TX_LAST_TLP1 0x1400036 ++#define ixPCIE_TX_LAST_TLP2 0x1400037 ++#define ixPCIE_TX_LAST_TLP3 0x1400038 ++#define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a ++#define ixPCIE_I2C_REG_DATA 0x140003b ++#define ixPCIE_CFG_CNTL 0x140003c ++#define ixPCIE_P_CNTL 0x1400040 ++#define ixPCIE_P_BUF_STATUS 0x1400041 ++#define ixPCIE_P_DECODER_STATUS 0x1400042 ++#define ixPCIE_P_MISC_STATUS 0x1400043 ++#define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050 ++#define ixPCIE_OBFF_CNTL 0x1400061 ++#define ixPCIE_TX_LTR_CNTL 0x1400060 ++#define ixPCIE_PERF_COUNT_CNTL 0x1400080 ++#define ixPCIE_PERF_CNTL_TXCLK 0x1400081 ++#define ixPCIE_PERF_COUNT0_TXCLK 0x1400082 ++#define ixPCIE_PERF_COUNT1_TXCLK 0x1400083 ++#define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084 ++#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085 ++#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086 ++#define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087 ++#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088 ++#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089 ++#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a ++#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b ++#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c ++#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d ++#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e ++#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f ++#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 ++#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 ++#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 ++#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 ++#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 ++#define ixPCIE_PERF_CNTL_TXCLK2 0x1400095 ++#define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096 ++#define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097 ++#define ixPCIE_STRAP_F0 0x14000b0 ++#define ixPCIE_STRAP_F1 0x14000b1 ++#define ixPCIE_STRAP_F2 0x14000b2 ++#define ixPCIE_STRAP_F3 0x14000b3 ++#define ixPCIE_STRAP_F4 0x14000b4 ++#define ixPCIE_STRAP_F5 0x14000b5 ++#define ixPCIE_STRAP_F6 0x14000b6 ++#define ixPCIE_STRAP_F7 0x14000b7 ++#define ixPCIE_STRAP_MISC 0x14000c0 ++#define ixPCIE_STRAP_MISC2 0x14000c1 ++#define ixPCIE_STRAP_PI 0x14000c2 ++#define ixPCIE_STRAP_I2C_BD 0x14000c4 ++#define ixPCIE_PRBS_CLR 0x14000c8 ++#define ixPCIE_PRBS_STATUS1 0x14000c9 ++#define ixPCIE_PRBS_STATUS2 0x14000ca ++#define ixPCIE_PRBS_FREERUN 0x14000cb ++#define ixPCIE_PRBS_MISC 0x14000cc ++#define ixPCIE_PRBS_USER_PATTERN 0x14000cd ++#define ixPCIE_PRBS_LO_BITCNT 0x14000ce ++#define ixPCIE_PRBS_HI_BITCNT 0x14000cf ++#define ixPCIE_PRBS_ERRCNT_0 0x14000d0 ++#define ixPCIE_PRBS_ERRCNT_1 0x14000d1 ++#define ixPCIE_PRBS_ERRCNT_2 0x14000d2 ++#define ixPCIE_PRBS_ERRCNT_3 0x14000d3 ++#define ixPCIE_PRBS_ERRCNT_4 0x14000d4 ++#define ixPCIE_PRBS_ERRCNT_5 0x14000d5 ++#define ixPCIE_PRBS_ERRCNT_6 0x14000d6 ++#define ixPCIE_PRBS_ERRCNT_7 0x14000d7 ++#define ixPCIE_PRBS_ERRCNT_8 0x14000d8 ++#define ixPCIE_PRBS_ERRCNT_9 0x14000d9 ++#define ixPCIE_PRBS_ERRCNT_10 0x14000da ++#define ixPCIE_PRBS_ERRCNT_11 0x14000db ++#define ixPCIE_PRBS_ERRCNT_12 0x14000dc ++#define ixPCIE_PRBS_ERRCNT_13 0x14000dd ++#define ixPCIE_PRBS_ERRCNT_14 0x14000de ++#define ixPCIE_PRBS_ERRCNT_15 0x14000df ++#define ixPCIE_F0_DPA_CAP 0x14000e0 ++#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4 ++#define ixPCIE_F0_DPA_CNTL 0x14000e5 ++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7 ++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8 ++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9 ++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea ++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb ++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec ++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed ++#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee ++#define ixPCIEP_RESERVED 0x10010000 ++#define ixPCIEP_SCRATCH 0x10010001 ++#define ixPCIEP_HW_DEBUG 0x10010002 ++#define ixPCIEP_PORT_CNTL 0x10010010 ++#define ixPCIE_TX_CNTL 0x10010020 ++#define ixPCIE_TX_REQUESTER_ID 0x10010021 ++#define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022 ++#define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023 ++#define ixPCIE_TX_SEQ 0x10010024 ++#define ixPCIE_TX_REPLAY 0x10010025 ++#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026 ++#define ixPCIE_TX_CREDITS_ADVT_P 0x10010030 ++#define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031 ++#define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032 ++#define ixPCIE_TX_CREDITS_INIT_P 0x10010033 ++#define ixPCIE_TX_CREDITS_INIT_NP 0x10010034 ++#define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035 ++#define ixPCIE_TX_CREDITS_STATUS 0x10010036 ++#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037 ++#define ixPCIE_P_PORT_LANE_STATUS 0x10010050 ++#define ixPCIE_FC_P 0x10010060 ++#define ixPCIE_FC_NP 0x10010061 ++#define ixPCIE_FC_CPL 0x10010062 ++#define ixPCIE_ERR_CNTL 0x1001006a ++#define ixPCIE_RX_CNTL 0x10010070 ++#define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071 ++#define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072 ++#define ixPCIE_RX_CNTL3 0x10010074 ++#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080 ++#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081 ++#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082 ++#define ixPCIE_LC_CNTL 0x100100a0 ++#define ixPCIE_LC_CNTL2 0x100100b1 ++#define ixPCIE_LC_CNTL3 0x100100b5 ++#define ixPCIE_LC_CNTL4 0x100100b6 ++#define ixPCIE_LC_CNTL5 0x100100b7 ++#define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2 ++#define ixPCIE_LC_TRAINING_CNTL 0x100100a1 ++#define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2 ++#define ixPCIE_LC_N_FTS_CNTL 0x100100a3 ++#define ixPCIE_LC_SPEED_CNTL 0x100100a4 ++#define ixPCIE_LC_CDR_CNTL 0x100100b3 ++#define ixPCIE_LC_LANE_CNTL 0x100100b4 ++#define ixPCIE_LC_FORCE_COEFF 0x100100b8 ++#define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9 ++#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba ++#define ixPCIE_LC_STATE0 0x100100a5 ++#define ixPCIE_LC_STATE1 0x100100a6 ++#define ixPCIE_LC_STATE2 0x100100a7 ++#define ixPCIE_LC_STATE3 0x100100a8 ++#define ixPCIE_LC_STATE4 0x100100a9 ++#define ixPCIE_LC_STATE5 0x100100aa ++#define ixPCIEP_STRAP_LC 0x100100c0 ++#define ixPCIEP_STRAP_MISC 0x100100c1 ++#define ixPCIEP_BCH_ECC_CNTL 0x100100d0 ++#define mmBIF_RFE_SNOOP_REG 0x27 ++#define mmBIF_RFE_WARMRST_CNTL 0x1459 ++#define mmBIF_RFE_SOFTRST_CNTL 0x1441 ++#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442 ++#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443 ++#define mmBIF_PWDN_COMMAND 0x1444 ++#define mmBIF_PWDN_STATUS 0x1445 ++#define mmBIF_RFE_MST_FBU_CMDSTATUS 0x1446 ++#define mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS 0x1447 ++#define mmBIF_RFE_MST_BX_CMDSTATUS 0x1448 ++#define mmBIF_RFE_MST_TMOUT_STATUS 0x144b ++#define mmBIF_RFE_MMCFG_CNTL 0x144c ++#define ixBIF_CLOCKS_BITS_IND 0x1301489 ++#define ixBIF_LNCNT_RESET_IND 0x1301488 ++#define ixLNCNT_CONTROL_IND 0x1301487 ++#define ixNEW_REFCLKB_TIMER_IND 0x1301485 ++#define ixNEW_REFCLKB_TIMER_1_IND 0x1301484 ++#define ixBIF_CLK_PDWN_DELAY_TIMER_IND 0x1301483 ++#define ixBIF_RESET_EN_IND 0x1301482 ++#define ixBIF_PIF_TXCLK_SWITCH_TIMER_IND 0x1301481 ++#define ixBIF_BACO_MSIC_IND 0x1301480 ++#define ixBIF_RESET_CNTL_IND 0x1301486 ++#define ixBIF_RFE_CNTL_MISC_IND 0x130148c ++#define ixBIF_MEM_PG_CNTL_IND 0x130148a ++#define mmNB_GBIF_INDEX 0x34 ++#define mmNB_GBIF_DATA 0x35 ++#define mmBIF_CLOCKS_BITS 0x1489 ++#define mmBIF_LNCNT_RESET 0x1488 ++#define mmLNCNT_CONTROL 0x1487 ++#define mmNEW_REFCLKB_TIMER 0x1485 ++#define mmNEW_REFCLKB_TIMER_1 0x1484 ++#define mmBIF_CLK_PDWN_DELAY_TIMER 0x1483 ++#define mmBIF_RESET_EN 0x1482 ++#define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x1481 ++#define mmBIF_BACO_MSIC 0x1480 ++#define mmBIF_RESET_CNTL 0x1486 ++#define mmBIF_RFE_CNTL_MISC 0x148c ++#define mmBIF_MEM_PG_CNTL 0x148a ++#define mmC_PCIE_P_INDEX 0x38 ++#define mmC_PCIE_P_DATA 0x39 ++#define ixD2F1_PCIE_PORT_INDEX 0x2000038 ++#define ixD2F1_PCIE_PORT_DATA 0x2000039 ++#define ixD2F1_PCIEP_RESERVED 0x0 ++#define ixD2F1_PCIEP_SCRATCH 0x1 ++#define ixD2F1_PCIEP_HW_DEBUG 0x2 ++#define ixD2F1_PCIEP_PORT_CNTL 0x10 ++#define ixD2F1_PCIE_TX_CNTL 0x20 ++#define ixD2F1_PCIE_TX_REQUESTER_ID 0x21 ++#define ixD2F1_PCIE_TX_VENDOR_SPECIFIC 0x22 ++#define ixD2F1_PCIE_TX_REQUEST_NUM_CNTL 0x23 ++#define ixD2F1_PCIE_TX_SEQ 0x24 ++#define ixD2F1_PCIE_TX_REPLAY 0x25 ++#define ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT 0x26 ++#define ixD2F1_PCIE_TX_CREDITS_ADVT_P 0x30 ++#define ixD2F1_PCIE_TX_CREDITS_ADVT_NP 0x31 ++#define ixD2F1_PCIE_TX_CREDITS_ADVT_CPL 0x32 ++#define ixD2F1_PCIE_TX_CREDITS_INIT_P 0x33 ++#define ixD2F1_PCIE_TX_CREDITS_INIT_NP 0x34 ++#define ixD2F1_PCIE_TX_CREDITS_INIT_CPL 0x35 ++#define ixD2F1_PCIE_TX_CREDITS_STATUS 0x36 ++#define ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 ++#define ixD2F1_PCIE_P_PORT_LANE_STATUS 0x50 ++#define ixD2F1_PCIE_FC_P 0x60 ++#define ixD2F1_PCIE_FC_NP 0x61 ++#define ixD2F1_PCIE_FC_CPL 0x62 ++#define ixD2F1_PCIE_ERR_CNTL 0x6a ++#define ixD2F1_PCIE_RX_CNTL 0x70 ++#define ixD2F1_PCIE_RX_EXPECTED_SEQNUM 0x71 ++#define ixD2F1_PCIE_RX_VENDOR_SPECIFIC 0x72 ++#define ixD2F1_PCIE_RX_CNTL3 0x74 ++#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P 0x80 ++#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 ++#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 ++#define ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL 0x83 ++#define ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION 0x84 ++#define ixD2F1_PCIE_LC_CNTL 0xa0 ++#define ixD2F1_PCIE_LC_CNTL2 0xb1 ++#define ixD2F1_PCIE_LC_CNTL3 0xb5 ++#define ixD2F1_PCIE_LC_CNTL4 0xb6 ++#define ixD2F1_PCIE_LC_CNTL5 0xb7 ++#define ixD2F1_PCIE_LC_CNTL6 0xbb ++#define ixD2F1_PCIE_LC_BW_CHANGE_CNTL 0xb2 ++#define ixD2F1_PCIE_LC_TRAINING_CNTL 0xa1 ++#define ixD2F1_PCIE_LC_LINK_WIDTH_CNTL 0xa2 ++#define ixD2F1_PCIE_LC_N_FTS_CNTL 0xa3 ++#define ixD2F1_PCIE_LC_SPEED_CNTL 0xa4 ++#define ixD2F1_PCIE_LC_CDR_CNTL 0xb3 ++#define ixD2F1_PCIE_LC_LANE_CNTL 0xb4 ++#define ixD2F1_PCIE_LC_FORCE_COEFF 0xb8 ++#define ixD2F1_PCIE_LC_BEST_EQ_SETTINGS 0xb9 ++#define ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba ++#define ixD2F1_PCIE_LC_STATE0 0xa5 ++#define ixD2F1_PCIE_LC_STATE1 0xa6 ++#define ixD2F1_PCIE_LC_STATE2 0xa7 ++#define ixD2F1_PCIE_LC_STATE3 0xa8 ++#define ixD2F1_PCIE_LC_STATE4 0xa9 ++#define ixD2F1_PCIE_LC_STATE5 0xaa ++#define ixD2F1_PCIEP_STRAP_LC 0xc0 ++#define ixD2F1_PCIEP_STRAP_MISC 0xc1 ++#define ixD2F1_PCIEP_BCH_ECC_CNTL 0xd0 ++#define ixD2F1_PCIEP_HPGI_PRIVATE 0xd2 ++#define ixD2F1_PCIEP_HPGI 0xda ++#define ixD2F1_VENDOR_ID 0x2000000 ++#define ixD2F1_DEVICE_ID 0x2000000 ++#define ixD2F1_COMMAND 0x2000001 ++#define ixD2F1_STATUS 0x2000001 ++#define ixD2F1_REVISION_ID 0x2000002 ++#define ixD2F1_PROG_INTERFACE 0x2000002 ++#define ixD2F1_SUB_CLASS 0x2000002 ++#define ixD2F1_BASE_CLASS 0x2000002 ++#define ixD2F1_CACHE_LINE 0x2000003 ++#define ixD2F1_LATENCY 0x2000003 ++#define ixD2F1_HEADER 0x2000003 ++#define ixD2F1_BIST 0x2000003 ++#define ixD2F1_SUB_BUS_NUMBER_LATENCY 0x2000006 ++#define ixD2F1_IO_BASE_LIMIT 0x2000007 ++#define ixD2F1_SECONDARY_STATUS 0x2000007 ++#define ixD2F1_MEM_BASE_LIMIT 0x2000008 ++#define ixD2F1_PREF_BASE_LIMIT 0x2000009 ++#define ixD2F1_PREF_BASE_UPPER 0x200000a ++#define ixD2F1_PREF_LIMIT_UPPER 0x200000b ++#define ixD2F1_IO_BASE_LIMIT_HI 0x200000c ++#define ixD2F1_IRQ_BRIDGE_CNTL 0x200000f ++#define ixD2F1_CAP_PTR 0x200000d ++#define ixD2F1_INTERRUPT_LINE 0x200000f ++#define ixD2F1_INTERRUPT_PIN 0x200000f ++#define ixD2F1_EXT_BRIDGE_CNTL 0x2000010 ++#define ixD2F1_PMI_CAP_LIST 0x2000014 ++#define ixD2F1_PMI_CAP 0x2000014 ++#define ixD2F1_PMI_STATUS_CNTL 0x2000015 ++#define ixD2F1_PCIE_CAP_LIST 0x2000016 ++#define ixD2F1_PCIE_CAP 0x2000016 ++#define ixD2F1_DEVICE_CAP 0x2000017 ++#define ixD2F1_DEVICE_CNTL 0x2000018 ++#define ixD2F1_DEVICE_STATUS 0x2000018 ++#define ixD2F1_LINK_CAP 0x2000019 ++#define ixD2F1_LINK_CNTL 0x200001a ++#define ixD2F1_LINK_STATUS 0x200001a ++#define ixD2F1_SLOT_CAP 0x200001b ++#define ixD2F1_SLOT_CNTL 0x200001c ++#define ixD2F1_SLOT_STATUS 0x200001c ++#define ixD2F1_ROOT_CNTL 0x200001d ++#define ixD2F1_ROOT_CAP 0x200001d ++#define ixD2F1_ROOT_STATUS 0x200001e ++#define ixD2F1_DEVICE_CAP2 0x200001f ++#define ixD2F1_DEVICE_CNTL2 0x2000020 ++#define ixD2F1_DEVICE_STATUS2 0x2000020 ++#define ixD2F1_LINK_CAP2 0x2000021 ++#define ixD2F1_LINK_CNTL2 0x2000022 ++#define ixD2F1_LINK_STATUS2 0x2000022 ++#define ixD2F1_SLOT_CAP2 0x2000023 ++#define ixD2F1_SLOT_CNTL2 0x2000024 ++#define ixD2F1_SLOT_STATUS2 0x2000024 ++#define ixD2F1_MSI_CAP_LIST 0x2000028 ++#define ixD2F1_MSI_MSG_CNTL 0x2000028 ++#define ixD2F1_MSI_MSG_ADDR_LO 0x2000029 ++#define ixD2F1_MSI_MSG_ADDR_HI 0x200002a ++#define ixD2F1_MSI_MSG_DATA_64 0x200002b ++#define ixD2F1_MSI_MSG_DATA 0x200002a ++#define ixD2F1_SSID_CAP_LIST 0x2000030 ++#define ixD2F1_SSID_CAP 0x2000031 ++#define ixD2F1_MSI_MAP_CAP_LIST 0x2000032 ++#define ixD2F1_MSI_MAP_CAP 0x2000032 ++#define ixD2F1_MSI_MAP_ADDR_LO 0x2000033 ++#define ixD2F1_MSI_MAP_ADDR_HI 0x2000034 ++#define ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x2000040 ++#define ixD2F1_PCIE_VENDOR_SPECIFIC_HDR 0x2000041 ++#define ixD2F1_PCIE_VENDOR_SPECIFIC1 0x2000042 ++#define ixD2F1_PCIE_VENDOR_SPECIFIC2 0x2000043 ++#define ixD2F1_PCIE_VC_ENH_CAP_LIST 0x2000044 ++#define ixD2F1_PCIE_PORT_VC_CAP_REG1 0x2000045 ++#define ixD2F1_PCIE_PORT_VC_CAP_REG2 0x2000046 ++#define ixD2F1_PCIE_PORT_VC_CNTL 0x2000047 ++#define ixD2F1_PCIE_PORT_VC_STATUS 0x2000047 ++#define ixD2F1_PCIE_VC0_RESOURCE_CAP 0x2000048 ++#define ixD2F1_PCIE_VC0_RESOURCE_CNTL 0x2000049 ++#define ixD2F1_PCIE_VC0_RESOURCE_STATUS 0x200004a ++#define ixD2F1_PCIE_VC1_RESOURCE_CAP 0x200004b ++#define ixD2F1_PCIE_VC1_RESOURCE_CNTL 0x200004c ++#define ixD2F1_PCIE_VC1_RESOURCE_STATUS 0x200004d ++#define ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x2000050 ++#define ixD2F1_PCIE_DEV_SERIAL_NUM_DW1 0x2000051 ++#define ixD2F1_PCIE_DEV_SERIAL_NUM_DW2 0x2000052 ++#define ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x2000054 ++#define ixD2F1_PCIE_UNCORR_ERR_STATUS 0x2000055 ++#define ixD2F1_PCIE_UNCORR_ERR_MASK 0x2000056 ++#define ixD2F1_PCIE_UNCORR_ERR_SEVERITY 0x2000057 ++#define ixD2F1_PCIE_CORR_ERR_STATUS 0x2000058 ++#define ixD2F1_PCIE_CORR_ERR_MASK 0x2000059 ++#define ixD2F1_PCIE_ADV_ERR_CAP_CNTL 0x200005a ++#define ixD2F1_PCIE_HDR_LOG0 0x200005b ++#define ixD2F1_PCIE_HDR_LOG1 0x200005c ++#define ixD2F1_PCIE_HDR_LOG2 0x200005d ++#define ixD2F1_PCIE_HDR_LOG3 0x200005e ++#define ixD2F1_PCIE_ROOT_ERR_CMD 0x200005f ++#define ixD2F1_PCIE_ROOT_ERR_STATUS 0x2000060 ++#define ixD2F1_PCIE_ERR_SRC_ID 0x2000061 ++#define ixD2F1_PCIE_TLP_PREFIX_LOG0 0x2000062 ++#define ixD2F1_PCIE_TLP_PREFIX_LOG1 0x2000063 ++#define ixD2F1_PCIE_TLP_PREFIX_LOG2 0x2000064 ++#define ixD2F1_PCIE_TLP_PREFIX_LOG3 0x2000065 ++#define ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST 0x200009c ++#define ixD2F1_PCIE_LINK_CNTL3 0x200009d ++#define ixD2F1_PCIE_LANE_ERROR_STATUS 0x200009e ++#define ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL 0x200009f ++#define ixD2F1_PCIE_LANE_1_EQUALIZATION_CNTL 0x200009f ++#define ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL 0x20000a0 ++#define ixD2F1_PCIE_LANE_3_EQUALIZATION_CNTL 0x20000a0 ++#define ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL 0x20000a1 ++#define ixD2F1_PCIE_LANE_5_EQUALIZATION_CNTL 0x20000a1 ++#define ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL 0x20000a2 ++#define ixD2F1_PCIE_LANE_7_EQUALIZATION_CNTL 0x20000a2 ++#define ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL 0x20000a3 ++#define ixD2F1_PCIE_LANE_9_EQUALIZATION_CNTL 0x20000a3 ++#define ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL 0x20000a4 ++#define ixD2F1_PCIE_LANE_11_EQUALIZATION_CNTL 0x20000a4 ++#define ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL 0x20000a5 ++#define ixD2F1_PCIE_LANE_13_EQUALIZATION_CNTL 0x20000a5 ++#define ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL 0x20000a6 ++#define ixD2F1_PCIE_LANE_15_EQUALIZATION_CNTL 0x20000a6 ++#define ixD2F1_PCIE_ACS_ENH_CAP_LIST 0x20000a8 ++#define ixD2F1_PCIE_ACS_CAP 0x20000a9 ++#define ixD2F1_PCIE_ACS_CNTL 0x20000a9 ++#define ixD2F1_PCIE_MC_ENH_CAP_LIST 0x20000bc ++#define ixD2F1_PCIE_MC_CAP 0x20000bd ++#define ixD2F1_PCIE_MC_CNTL 0x20000bd ++#define ixD2F1_PCIE_MC_ADDR0 0x20000be ++#define ixD2F1_PCIE_MC_ADDR1 0x20000bf ++#define ixD2F1_PCIE_MC_RCV0 0x20000c0 ++#define ixD2F1_PCIE_MC_RCV1 0x20000c1 ++#define ixD2F1_PCIE_MC_BLOCK_ALL0 0x20000c2 ++#define ixD2F1_PCIE_MC_BLOCK_ALL1 0x20000c3 ++#define ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x20000c4 ++#define ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x20000c5 ++#define ixD2F1_PCIE_MC_OVERLAY_BAR0 0x20000c6 ++#define ixD2F1_PCIE_MC_OVERLAY_BAR1 0x20000c7 ++#define ixD2F2_PCIE_PORT_INDEX 0x3000038 ++#define ixD2F2_PCIE_PORT_DATA 0x3000039 ++#define ixD2F2_PCIEP_RESERVED 0x0 ++#define ixD2F2_PCIEP_SCRATCH 0x1 ++#define ixD2F2_PCIEP_HW_DEBUG 0x2 ++#define ixD2F2_PCIEP_PORT_CNTL 0x10 ++#define ixD2F2_PCIE_TX_CNTL 0x20 ++#define ixD2F2_PCIE_TX_REQUESTER_ID 0x21 ++#define ixD2F2_PCIE_TX_VENDOR_SPECIFIC 0x22 ++#define ixD2F2_PCIE_TX_REQUEST_NUM_CNTL 0x23 ++#define ixD2F2_PCIE_TX_SEQ 0x24 ++#define ixD2F2_PCIE_TX_REPLAY 0x25 ++#define ixD2F2_PCIE_TX_ACK_LATENCY_LIMIT 0x26 ++#define ixD2F2_PCIE_TX_CREDITS_ADVT_P 0x30 ++#define ixD2F2_PCIE_TX_CREDITS_ADVT_NP 0x31 ++#define ixD2F2_PCIE_TX_CREDITS_ADVT_CPL 0x32 ++#define ixD2F2_PCIE_TX_CREDITS_INIT_P 0x33 ++#define ixD2F2_PCIE_TX_CREDITS_INIT_NP 0x34 ++#define ixD2F2_PCIE_TX_CREDITS_INIT_CPL 0x35 ++#define ixD2F2_PCIE_TX_CREDITS_STATUS 0x36 ++#define ixD2F2_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 ++#define ixD2F2_PCIE_P_PORT_LANE_STATUS 0x50 ++#define ixD2F2_PCIE_FC_P 0x60 ++#define ixD2F2_PCIE_FC_NP 0x61 ++#define ixD2F2_PCIE_FC_CPL 0x62 ++#define ixD2F2_PCIE_ERR_CNTL 0x6a ++#define ixD2F2_PCIE_RX_CNTL 0x70 ++#define ixD2F2_PCIE_RX_EXPECTED_SEQNUM 0x71 ++#define ixD2F2_PCIE_RX_VENDOR_SPECIFIC 0x72 ++#define ixD2F2_PCIE_RX_CNTL3 0x74 ++#define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_P 0x80 ++#define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 ++#define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 ++#define ixD2F2_PCIEP_ERROR_INJECT_PHYSICAL 0x83 ++#define ixD2F2_PCIEP_ERROR_INJECT_TRANSACTION 0x84 ++#define ixD2F2_PCIE_LC_CNTL 0xa0 ++#define ixD2F2_PCIE_LC_CNTL2 0xb1 ++#define ixD2F2_PCIE_LC_CNTL3 0xb5 ++#define ixD2F2_PCIE_LC_CNTL4 0xb6 ++#define ixD2F2_PCIE_LC_CNTL5 0xb7 ++#define ixD2F2_PCIE_LC_CNTL6 0xbb ++#define ixD2F2_PCIE_LC_BW_CHANGE_CNTL 0xb2 ++#define ixD2F2_PCIE_LC_TRAINING_CNTL 0xa1 ++#define ixD2F2_PCIE_LC_LINK_WIDTH_CNTL 0xa2 ++#define ixD2F2_PCIE_LC_N_FTS_CNTL 0xa3 ++#define ixD2F2_PCIE_LC_SPEED_CNTL 0xa4 ++#define ixD2F2_PCIE_LC_CDR_CNTL 0xb3 ++#define ixD2F2_PCIE_LC_LANE_CNTL 0xb4 ++#define ixD2F2_PCIE_LC_FORCE_COEFF 0xb8 ++#define ixD2F2_PCIE_LC_BEST_EQ_SETTINGS 0xb9 ++#define ixD2F2_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba ++#define ixD2F2_PCIE_LC_STATE0 0xa5 ++#define ixD2F2_PCIE_LC_STATE1 0xa6 ++#define ixD2F2_PCIE_LC_STATE2 0xa7 ++#define ixD2F2_PCIE_LC_STATE3 0xa8 ++#define ixD2F2_PCIE_LC_STATE4 0xa9 ++#define ixD2F2_PCIE_LC_STATE5 0xaa ++#define ixD2F2_PCIEP_STRAP_LC 0xc0 ++#define ixD2F2_PCIEP_STRAP_MISC 0xc1 ++#define ixD2F2_PCIEP_BCH_ECC_CNTL 0xd0 ++#define ixD2F2_PCIEP_HPGI_PRIVATE 0xd2 ++#define ixD2F2_PCIEP_HPGI 0xda ++#define ixD2F2_VENDOR_ID 0x3000000 ++#define ixD2F2_DEVICE_ID 0x3000000 ++#define ixD2F2_COMMAND 0x3000001 ++#define ixD2F2_STATUS 0x3000001 ++#define ixD2F2_REVISION_ID 0x3000002 ++#define ixD2F2_PROG_INTERFACE 0x3000002 ++#define ixD2F2_SUB_CLASS 0x3000002 ++#define ixD2F2_BASE_CLASS 0x3000002 ++#define ixD2F2_CACHE_LINE 0x3000003 ++#define ixD2F2_LATENCY 0x3000003 ++#define ixD2F2_HEADER 0x3000003 ++#define ixD2F2_BIST 0x3000003 ++#define ixD2F2_SUB_BUS_NUMBER_LATENCY 0x3000006 ++#define ixD2F2_IO_BASE_LIMIT 0x3000007 ++#define ixD2F2_SECONDARY_STATUS 0x3000007 ++#define ixD2F2_MEM_BASE_LIMIT 0x3000008 ++#define ixD2F2_PREF_BASE_LIMIT 0x3000009 ++#define ixD2F2_PREF_BASE_UPPER 0x300000a ++#define ixD2F2_PREF_LIMIT_UPPER 0x300000b ++#define ixD2F2_IO_BASE_LIMIT_HI 0x300000c ++#define ixD2F2_IRQ_BRIDGE_CNTL 0x300000f ++#define ixD2F2_CAP_PTR 0x300000d ++#define ixD2F2_INTERRUPT_LINE 0x300000f ++#define ixD2F2_INTERRUPT_PIN 0x300000f ++#define ixD2F2_EXT_BRIDGE_CNTL 0x3000010 ++#define ixD2F2_PMI_CAP_LIST 0x3000014 ++#define ixD2F2_PMI_CAP 0x3000014 ++#define ixD2F2_PMI_STATUS_CNTL 0x3000015 ++#define ixD2F2_PCIE_CAP_LIST 0x3000016 ++#define ixD2F2_PCIE_CAP 0x3000016 ++#define ixD2F2_DEVICE_CAP 0x3000017 ++#define ixD2F2_DEVICE_CNTL 0x3000018 ++#define ixD2F2_DEVICE_STATUS 0x3000018 ++#define ixD2F2_LINK_CAP 0x3000019 ++#define ixD2F2_LINK_CNTL 0x300001a ++#define ixD2F2_LINK_STATUS 0x300001a ++#define ixD2F2_SLOT_CAP 0x300001b ++#define ixD2F2_SLOT_CNTL 0x300001c ++#define ixD2F2_SLOT_STATUS 0x300001c ++#define ixD2F2_ROOT_CNTL 0x300001d ++#define ixD2F2_ROOT_CAP 0x300001d ++#define ixD2F2_ROOT_STATUS 0x300001e ++#define ixD2F2_DEVICE_CAP2 0x300001f ++#define ixD2F2_DEVICE_CNTL2 0x3000020 ++#define ixD2F2_DEVICE_STATUS2 0x3000020 ++#define ixD2F2_LINK_CAP2 0x3000021 ++#define ixD2F2_LINK_CNTL2 0x3000022 ++#define ixD2F2_LINK_STATUS2 0x3000022 ++#define ixD2F2_SLOT_CAP2 0x3000023 ++#define ixD2F2_SLOT_CNTL2 0x3000024 ++#define ixD2F2_SLOT_STATUS2 0x3000024 ++#define ixD2F2_MSI_CAP_LIST 0x3000028 ++#define ixD2F2_MSI_MSG_CNTL 0x3000028 ++#define ixD2F2_MSI_MSG_ADDR_LO 0x3000029 ++#define ixD2F2_MSI_MSG_ADDR_HI 0x300002a ++#define ixD2F2_MSI_MSG_DATA_64 0x300002b ++#define ixD2F2_MSI_MSG_DATA 0x300002a ++#define ixD2F2_SSID_CAP_LIST 0x3000030 ++#define ixD2F2_SSID_CAP 0x3000031 ++#define ixD2F2_MSI_MAP_CAP_LIST 0x3000032 ++#define ixD2F2_MSI_MAP_CAP 0x3000032 ++#define ixD2F2_MSI_MAP_ADDR_LO 0x3000033 ++#define ixD2F2_MSI_MAP_ADDR_HI 0x3000034 ++#define ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3000040 ++#define ixD2F2_PCIE_VENDOR_SPECIFIC_HDR 0x3000041 ++#define ixD2F2_PCIE_VENDOR_SPECIFIC1 0x3000042 ++#define ixD2F2_PCIE_VENDOR_SPECIFIC2 0x3000043 ++#define ixD2F2_PCIE_VC_ENH_CAP_LIST 0x3000044 ++#define ixD2F2_PCIE_PORT_VC_CAP_REG1 0x3000045 ++#define ixD2F2_PCIE_PORT_VC_CAP_REG2 0x3000046 ++#define ixD2F2_PCIE_PORT_VC_CNTL 0x3000047 ++#define ixD2F2_PCIE_PORT_VC_STATUS 0x3000047 ++#define ixD2F2_PCIE_VC0_RESOURCE_CAP 0x3000048 ++#define ixD2F2_PCIE_VC0_RESOURCE_CNTL 0x3000049 ++#define ixD2F2_PCIE_VC0_RESOURCE_STATUS 0x300004a ++#define ixD2F2_PCIE_VC1_RESOURCE_CAP 0x300004b ++#define ixD2F2_PCIE_VC1_RESOURCE_CNTL 0x300004c ++#define ixD2F2_PCIE_VC1_RESOURCE_STATUS 0x300004d ++#define ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3000050 ++#define ixD2F2_PCIE_DEV_SERIAL_NUM_DW1 0x3000051 ++#define ixD2F2_PCIE_DEV_SERIAL_NUM_DW2 0x3000052 ++#define ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3000054 ++#define ixD2F2_PCIE_UNCORR_ERR_STATUS 0x3000055 ++#define ixD2F2_PCIE_UNCORR_ERR_MASK 0x3000056 ++#define ixD2F2_PCIE_UNCORR_ERR_SEVERITY 0x3000057 ++#define ixD2F2_PCIE_CORR_ERR_STATUS 0x3000058 ++#define ixD2F2_PCIE_CORR_ERR_MASK 0x3000059 ++#define ixD2F2_PCIE_ADV_ERR_CAP_CNTL 0x300005a ++#define ixD2F2_PCIE_HDR_LOG0 0x300005b ++#define ixD2F2_PCIE_HDR_LOG1 0x300005c ++#define ixD2F2_PCIE_HDR_LOG2 0x300005d ++#define ixD2F2_PCIE_HDR_LOG3 0x300005e ++#define ixD2F2_PCIE_ROOT_ERR_CMD 0x300005f ++#define ixD2F2_PCIE_ROOT_ERR_STATUS 0x3000060 ++#define ixD2F2_PCIE_ERR_SRC_ID 0x3000061 ++#define ixD2F2_PCIE_TLP_PREFIX_LOG0 0x3000062 ++#define ixD2F2_PCIE_TLP_PREFIX_LOG1 0x3000063 ++#define ixD2F2_PCIE_TLP_PREFIX_LOG2 0x3000064 ++#define ixD2F2_PCIE_TLP_PREFIX_LOG3 0x3000065 ++#define ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST 0x300009c ++#define ixD2F2_PCIE_LINK_CNTL3 0x300009d ++#define ixD2F2_PCIE_LANE_ERROR_STATUS 0x300009e ++#define ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL 0x300009f ++#define ixD2F2_PCIE_LANE_1_EQUALIZATION_CNTL 0x300009f ++#define ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL 0x30000a0 ++#define ixD2F2_PCIE_LANE_3_EQUALIZATION_CNTL 0x30000a0 ++#define ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL 0x30000a1 ++#define ixD2F2_PCIE_LANE_5_EQUALIZATION_CNTL 0x30000a1 ++#define ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL 0x30000a2 ++#define ixD2F2_PCIE_LANE_7_EQUALIZATION_CNTL 0x30000a2 ++#define ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL 0x30000a3 ++#define ixD2F2_PCIE_LANE_9_EQUALIZATION_CNTL 0x30000a3 ++#define ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL 0x30000a4 ++#define ixD2F2_PCIE_LANE_11_EQUALIZATION_CNTL 0x30000a4 ++#define ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL 0x30000a5 ++#define ixD2F2_PCIE_LANE_13_EQUALIZATION_CNTL 0x30000a5 ++#define ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL 0x30000a6 ++#define ixD2F2_PCIE_LANE_15_EQUALIZATION_CNTL 0x30000a6 ++#define ixD2F2_PCIE_ACS_ENH_CAP_LIST 0x30000a8 ++#define ixD2F2_PCIE_ACS_CAP 0x30000a9 ++#define ixD2F2_PCIE_ACS_CNTL 0x30000a9 ++#define ixD2F2_PCIE_MC_ENH_CAP_LIST 0x30000bc ++#define ixD2F2_PCIE_MC_CAP 0x30000bd ++#define ixD2F2_PCIE_MC_CNTL 0x30000bd ++#define ixD2F2_PCIE_MC_ADDR0 0x30000be ++#define ixD2F2_PCIE_MC_ADDR1 0x30000bf ++#define ixD2F2_PCIE_MC_RCV0 0x30000c0 ++#define ixD2F2_PCIE_MC_RCV1 0x30000c1 ++#define ixD2F2_PCIE_MC_BLOCK_ALL0 0x30000c2 ++#define ixD2F2_PCIE_MC_BLOCK_ALL1 0x30000c3 ++#define ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x30000c4 ++#define ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x30000c5 ++#define ixD2F2_PCIE_MC_OVERLAY_BAR0 0x30000c6 ++#define ixD2F2_PCIE_MC_OVERLAY_BAR1 0x30000c7 ++#define ixD2F3_PCIE_PORT_INDEX 0x4000038 ++#define ixD2F3_PCIE_PORT_DATA 0x4000039 ++#define ixD2F3_PCIEP_RESERVED 0x0 ++#define ixD2F3_PCIEP_SCRATCH 0x1 ++#define ixD2F3_PCIEP_HW_DEBUG 0x2 ++#define ixD2F3_PCIEP_PORT_CNTL 0x10 ++#define ixD2F3_PCIE_TX_CNTL 0x20 ++#define ixD2F3_PCIE_TX_REQUESTER_ID 0x21 ++#define ixD2F3_PCIE_TX_VENDOR_SPECIFIC 0x22 ++#define ixD2F3_PCIE_TX_REQUEST_NUM_CNTL 0x23 ++#define ixD2F3_PCIE_TX_SEQ 0x24 ++#define ixD2F3_PCIE_TX_REPLAY 0x25 ++#define ixD2F3_PCIE_TX_ACK_LATENCY_LIMIT 0x26 ++#define ixD2F3_PCIE_TX_CREDITS_ADVT_P 0x30 ++#define ixD2F3_PCIE_TX_CREDITS_ADVT_NP 0x31 ++#define ixD2F3_PCIE_TX_CREDITS_ADVT_CPL 0x32 ++#define ixD2F3_PCIE_TX_CREDITS_INIT_P 0x33 ++#define ixD2F3_PCIE_TX_CREDITS_INIT_NP 0x34 ++#define ixD2F3_PCIE_TX_CREDITS_INIT_CPL 0x35 ++#define ixD2F3_PCIE_TX_CREDITS_STATUS 0x36 ++#define ixD2F3_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 ++#define ixD2F3_PCIE_P_PORT_LANE_STATUS 0x50 ++#define ixD2F3_PCIE_FC_P 0x60 ++#define ixD2F3_PCIE_FC_NP 0x61 ++#define ixD2F3_PCIE_FC_CPL 0x62 ++#define ixD2F3_PCIE_ERR_CNTL 0x6a ++#define ixD2F3_PCIE_RX_CNTL 0x70 ++#define ixD2F3_PCIE_RX_EXPECTED_SEQNUM 0x71 ++#define ixD2F3_PCIE_RX_VENDOR_SPECIFIC 0x72 ++#define ixD2F3_PCIE_RX_CNTL3 0x74 ++#define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_P 0x80 ++#define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 ++#define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 ++#define ixD2F3_PCIEP_ERROR_INJECT_PHYSICAL 0x83 ++#define ixD2F3_PCIEP_ERROR_INJECT_TRANSACTION 0x84 ++#define ixD2F3_PCIE_LC_CNTL 0xa0 ++#define ixD2F3_PCIE_LC_CNTL2 0xb1 ++#define ixD2F3_PCIE_LC_CNTL3 0xb5 ++#define ixD2F3_PCIE_LC_CNTL4 0xb6 ++#define ixD2F3_PCIE_LC_CNTL5 0xb7 ++#define ixD2F3_PCIE_LC_CNTL6 0xbb ++#define ixD2F3_PCIE_LC_BW_CHANGE_CNTL 0xb2 ++#define ixD2F3_PCIE_LC_TRAINING_CNTL 0xa1 ++#define ixD2F3_PCIE_LC_LINK_WIDTH_CNTL 0xa2 ++#define ixD2F3_PCIE_LC_N_FTS_CNTL 0xa3 ++#define ixD2F3_PCIE_LC_SPEED_CNTL 0xa4 ++#define ixD2F3_PCIE_LC_CDR_CNTL 0xb3 ++#define ixD2F3_PCIE_LC_LANE_CNTL 0xb4 ++#define ixD2F3_PCIE_LC_FORCE_COEFF 0xb8 ++#define ixD2F3_PCIE_LC_BEST_EQ_SETTINGS 0xb9 ++#define ixD2F3_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba ++#define ixD2F3_PCIE_LC_STATE0 0xa5 ++#define ixD2F3_PCIE_LC_STATE1 0xa6 ++#define ixD2F3_PCIE_LC_STATE2 0xa7 ++#define ixD2F3_PCIE_LC_STATE3 0xa8 ++#define ixD2F3_PCIE_LC_STATE4 0xa9 ++#define ixD2F3_PCIE_LC_STATE5 0xaa ++#define ixD2F3_PCIEP_STRAP_LC 0xc0 ++#define ixD2F3_PCIEP_STRAP_MISC 0xc1 ++#define ixD2F3_PCIEP_BCH_ECC_CNTL 0xd0 ++#define ixD2F3_PCIEP_HPGI_PRIVATE 0xd2 ++#define ixD2F3_PCIEP_HPGI 0xda ++#define ixD2F3_VENDOR_ID 0x4000000 ++#define ixD2F3_DEVICE_ID 0x4000000 ++#define ixD2F3_COMMAND 0x4000001 ++#define ixD2F3_STATUS 0x4000001 ++#define ixD2F3_REVISION_ID 0x4000002 ++#define ixD2F3_PROG_INTERFACE 0x4000002 ++#define ixD2F3_SUB_CLASS 0x4000002 ++#define ixD2F3_BASE_CLASS 0x4000002 ++#define ixD2F3_CACHE_LINE 0x4000003 ++#define ixD2F3_LATENCY 0x4000003 ++#define ixD2F3_HEADER 0x4000003 ++#define ixD2F3_BIST 0x4000003 ++#define ixD2F3_SUB_BUS_NUMBER_LATENCY 0x4000006 ++#define ixD2F3_IO_BASE_LIMIT 0x4000007 ++#define ixD2F3_SECONDARY_STATUS 0x4000007 ++#define ixD2F3_MEM_BASE_LIMIT 0x4000008 ++#define ixD2F3_PREF_BASE_LIMIT 0x4000009 ++#define ixD2F3_PREF_BASE_UPPER 0x400000a ++#define ixD2F3_PREF_LIMIT_UPPER 0x400000b ++#define ixD2F3_IO_BASE_LIMIT_HI 0x400000c ++#define ixD2F3_IRQ_BRIDGE_CNTL 0x400000f ++#define ixD2F3_CAP_PTR 0x400000d ++#define ixD2F3_INTERRUPT_LINE 0x400000f ++#define ixD2F3_INTERRUPT_PIN 0x400000f ++#define ixD2F3_EXT_BRIDGE_CNTL 0x4000010 ++#define ixD2F3_PMI_CAP_LIST 0x4000014 ++#define ixD2F3_PMI_CAP 0x4000014 ++#define ixD2F3_PMI_STATUS_CNTL 0x4000015 ++#define ixD2F3_PCIE_CAP_LIST 0x4000016 ++#define ixD2F3_PCIE_CAP 0x4000016 ++#define ixD2F3_DEVICE_CAP 0x4000017 ++#define ixD2F3_DEVICE_CNTL 0x4000018 ++#define ixD2F3_DEVICE_STATUS 0x4000018 ++#define ixD2F3_LINK_CAP 0x4000019 ++#define ixD2F3_LINK_CNTL 0x400001a ++#define ixD2F3_LINK_STATUS 0x400001a ++#define ixD2F3_SLOT_CAP 0x400001b ++#define ixD2F3_SLOT_CNTL 0x400001c ++#define ixD2F3_SLOT_STATUS 0x400001c ++#define ixD2F3_ROOT_CNTL 0x400001d ++#define ixD2F3_ROOT_CAP 0x400001d ++#define ixD2F3_ROOT_STATUS 0x400001e ++#define ixD2F3_DEVICE_CAP2 0x400001f ++#define ixD2F3_DEVICE_CNTL2 0x4000020 ++#define ixD2F3_DEVICE_STATUS2 0x4000020 ++#define ixD2F3_LINK_CAP2 0x4000021 ++#define ixD2F3_LINK_CNTL2 0x4000022 ++#define ixD2F3_LINK_STATUS2 0x4000022 ++#define ixD2F3_SLOT_CAP2 0x4000023 ++#define ixD2F3_SLOT_CNTL2 0x4000024 ++#define ixD2F3_SLOT_STATUS2 0x4000024 ++#define ixD2F3_MSI_CAP_LIST 0x4000028 ++#define ixD2F3_MSI_MSG_CNTL 0x4000028 ++#define ixD2F3_MSI_MSG_ADDR_LO 0x4000029 ++#define ixD2F3_MSI_MSG_ADDR_HI 0x400002a ++#define ixD2F3_MSI_MSG_DATA_64 0x400002b ++#define ixD2F3_MSI_MSG_DATA 0x400002a ++#define ixD2F3_SSID_CAP_LIST 0x4000030 ++#define ixD2F3_SSID_CAP 0x4000031 ++#define ixD2F3_MSI_MAP_CAP_LIST 0x4000032 ++#define ixD2F3_MSI_MAP_CAP 0x4000032 ++#define ixD2F3_MSI_MAP_ADDR_LO 0x4000033 ++#define ixD2F3_MSI_MAP_ADDR_HI 0x4000034 ++#define ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x4000040 ++#define ixD2F3_PCIE_VENDOR_SPECIFIC_HDR 0x4000041 ++#define ixD2F3_PCIE_VENDOR_SPECIFIC1 0x4000042 ++#define ixD2F3_PCIE_VENDOR_SPECIFIC2 0x4000043 ++#define ixD2F3_PCIE_VC_ENH_CAP_LIST 0x4000044 ++#define ixD2F3_PCIE_PORT_VC_CAP_REG1 0x4000045 ++#define ixD2F3_PCIE_PORT_VC_CAP_REG2 0x4000046 ++#define ixD2F3_PCIE_PORT_VC_CNTL 0x4000047 ++#define ixD2F3_PCIE_PORT_VC_STATUS 0x4000047 ++#define ixD2F3_PCIE_VC0_RESOURCE_CAP 0x4000048 ++#define ixD2F3_PCIE_VC0_RESOURCE_CNTL 0x4000049 ++#define ixD2F3_PCIE_VC0_RESOURCE_STATUS 0x400004a ++#define ixD2F3_PCIE_VC1_RESOURCE_CAP 0x400004b ++#define ixD2F3_PCIE_VC1_RESOURCE_CNTL 0x400004c ++#define ixD2F3_PCIE_VC1_RESOURCE_STATUS 0x400004d ++#define ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x4000050 ++#define ixD2F3_PCIE_DEV_SERIAL_NUM_DW1 0x4000051 ++#define ixD2F3_PCIE_DEV_SERIAL_NUM_DW2 0x4000052 ++#define ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x4000054 ++#define ixD2F3_PCIE_UNCORR_ERR_STATUS 0x4000055 ++#define ixD2F3_PCIE_UNCORR_ERR_MASK 0x4000056 ++#define ixD2F3_PCIE_UNCORR_ERR_SEVERITY 0x4000057 ++#define ixD2F3_PCIE_CORR_ERR_STATUS 0x4000058 ++#define ixD2F3_PCIE_CORR_ERR_MASK 0x4000059 ++#define ixD2F3_PCIE_ADV_ERR_CAP_CNTL 0x400005a ++#define ixD2F3_PCIE_HDR_LOG0 0x400005b ++#define ixD2F3_PCIE_HDR_LOG1 0x400005c ++#define ixD2F3_PCIE_HDR_LOG2 0x400005d ++#define ixD2F3_PCIE_HDR_LOG3 0x400005e ++#define ixD2F3_PCIE_ROOT_ERR_CMD 0x400005f ++#define ixD2F3_PCIE_ROOT_ERR_STATUS 0x4000060 ++#define ixD2F3_PCIE_ERR_SRC_ID 0x4000061 ++#define ixD2F3_PCIE_TLP_PREFIX_LOG0 0x4000062 ++#define ixD2F3_PCIE_TLP_PREFIX_LOG1 0x4000063 ++#define ixD2F3_PCIE_TLP_PREFIX_LOG2 0x4000064 ++#define ixD2F3_PCIE_TLP_PREFIX_LOG3 0x4000065 ++#define ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST 0x400009c ++#define ixD2F3_PCIE_LINK_CNTL3 0x400009d ++#define ixD2F3_PCIE_LANE_ERROR_STATUS 0x400009e ++#define ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL 0x400009f ++#define ixD2F3_PCIE_LANE_1_EQUALIZATION_CNTL 0x400009f ++#define ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL 0x40000a0 ++#define ixD2F3_PCIE_LANE_3_EQUALIZATION_CNTL 0x40000a0 ++#define ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL 0x40000a1 ++#define ixD2F3_PCIE_LANE_5_EQUALIZATION_CNTL 0x40000a1 ++#define ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL 0x40000a2 ++#define ixD2F3_PCIE_LANE_7_EQUALIZATION_CNTL 0x40000a2 ++#define ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL 0x40000a3 ++#define ixD2F3_PCIE_LANE_9_EQUALIZATION_CNTL 0x40000a3 ++#define ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL 0x40000a4 ++#define ixD2F3_PCIE_LANE_11_EQUALIZATION_CNTL 0x40000a4 ++#define ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL 0x40000a5 ++#define ixD2F3_PCIE_LANE_13_EQUALIZATION_CNTL 0x40000a5 ++#define ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL 0x40000a6 ++#define ixD2F3_PCIE_LANE_15_EQUALIZATION_CNTL 0x40000a6 ++#define ixD2F3_PCIE_ACS_ENH_CAP_LIST 0x40000a8 ++#define ixD2F3_PCIE_ACS_CAP 0x40000a9 ++#define ixD2F3_PCIE_ACS_CNTL 0x40000a9 ++#define ixD2F3_PCIE_MC_ENH_CAP_LIST 0x40000bc ++#define ixD2F3_PCIE_MC_CAP 0x40000bd ++#define ixD2F3_PCIE_MC_CNTL 0x40000bd ++#define ixD2F3_PCIE_MC_ADDR0 0x40000be ++#define ixD2F3_PCIE_MC_ADDR1 0x40000bf ++#define ixD2F3_PCIE_MC_RCV0 0x40000c0 ++#define ixD2F3_PCIE_MC_RCV1 0x40000c1 ++#define ixD2F3_PCIE_MC_BLOCK_ALL0 0x40000c2 ++#define ixD2F3_PCIE_MC_BLOCK_ALL1 0x40000c3 ++#define ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0 0x40000c4 ++#define ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1 0x40000c5 ++#define ixD2F3_PCIE_MC_OVERLAY_BAR0 0x40000c6 ++#define ixD2F3_PCIE_MC_OVERLAY_BAR1 0x40000c7 ++#define ixD2F4_PCIE_PORT_INDEX 0x5000038 ++#define ixD2F4_PCIE_PORT_DATA 0x5000039 ++#define ixD2F4_PCIEP_RESERVED 0x0 ++#define ixD2F4_PCIEP_SCRATCH 0x1 ++#define ixD2F4_PCIEP_HW_DEBUG 0x2 ++#define ixD2F4_PCIEP_PORT_CNTL 0x10 ++#define ixD2F4_PCIE_TX_CNTL 0x20 ++#define ixD2F4_PCIE_TX_REQUESTER_ID 0x21 ++#define ixD2F4_PCIE_TX_VENDOR_SPECIFIC 0x22 ++#define ixD2F4_PCIE_TX_REQUEST_NUM_CNTL 0x23 ++#define ixD2F4_PCIE_TX_SEQ 0x24 ++#define ixD2F4_PCIE_TX_REPLAY 0x25 ++#define ixD2F4_PCIE_TX_ACK_LATENCY_LIMIT 0x26 ++#define ixD2F4_PCIE_TX_CREDITS_ADVT_P 0x30 ++#define ixD2F4_PCIE_TX_CREDITS_ADVT_NP 0x31 ++#define ixD2F4_PCIE_TX_CREDITS_ADVT_CPL 0x32 ++#define ixD2F4_PCIE_TX_CREDITS_INIT_P 0x33 ++#define ixD2F4_PCIE_TX_CREDITS_INIT_NP 0x34 ++#define ixD2F4_PCIE_TX_CREDITS_INIT_CPL 0x35 ++#define ixD2F4_PCIE_TX_CREDITS_STATUS 0x36 ++#define ixD2F4_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 ++#define ixD2F4_PCIE_P_PORT_LANE_STATUS 0x50 ++#define ixD2F4_PCIE_FC_P 0x60 ++#define ixD2F4_PCIE_FC_NP 0x61 ++#define ixD2F4_PCIE_FC_CPL 0x62 ++#define ixD2F4_PCIE_ERR_CNTL 0x6a ++#define ixD2F4_PCIE_RX_CNTL 0x70 ++#define ixD2F4_PCIE_RX_EXPECTED_SEQNUM 0x71 ++#define ixD2F4_PCIE_RX_VENDOR_SPECIFIC 0x72 ++#define ixD2F4_PCIE_RX_CNTL3 0x74 ++#define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_P 0x80 ++#define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 ++#define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 ++#define ixD2F4_PCIEP_ERROR_INJECT_PHYSICAL 0x83 ++#define ixD2F4_PCIEP_ERROR_INJECT_TRANSACTION 0x84 ++#define ixD2F4_PCIE_LC_CNTL 0xa0 ++#define ixD2F4_PCIE_LC_CNTL2 0xb1 ++#define ixD2F4_PCIE_LC_CNTL3 0xb5 ++#define ixD2F4_PCIE_LC_CNTL4 0xb6 ++#define ixD2F4_PCIE_LC_CNTL5 0xb7 ++#define ixD2F4_PCIE_LC_CNTL6 0xbb ++#define ixD2F4_PCIE_LC_BW_CHANGE_CNTL 0xb2 ++#define ixD2F4_PCIE_LC_TRAINING_CNTL 0xa1 ++#define ixD2F4_PCIE_LC_LINK_WIDTH_CNTL 0xa2 ++#define ixD2F4_PCIE_LC_N_FTS_CNTL 0xa3 ++#define ixD2F4_PCIE_LC_SPEED_CNTL 0xa4 ++#define ixD2F4_PCIE_LC_CDR_CNTL 0xb3 ++#define ixD2F4_PCIE_LC_LANE_CNTL 0xb4 ++#define ixD2F4_PCIE_LC_FORCE_COEFF 0xb8 ++#define ixD2F4_PCIE_LC_BEST_EQ_SETTINGS 0xb9 ++#define ixD2F4_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba ++#define ixD2F4_PCIE_LC_STATE0 0xa5 ++#define ixD2F4_PCIE_LC_STATE1 0xa6 ++#define ixD2F4_PCIE_LC_STATE2 0xa7 ++#define ixD2F4_PCIE_LC_STATE3 0xa8 ++#define ixD2F4_PCIE_LC_STATE4 0xa9 ++#define ixD2F4_PCIE_LC_STATE5 0xaa ++#define ixD2F4_PCIEP_STRAP_LC 0xc0 ++#define ixD2F4_PCIEP_STRAP_MISC 0xc1 ++#define ixD2F4_PCIEP_BCH_ECC_CNTL 0xd0 ++#define ixD2F4_PCIEP_HPGI_PRIVATE 0xd2 ++#define ixD2F4_PCIEP_HPGI 0xda ++#define ixD2F4_VENDOR_ID 0x5000000 ++#define ixD2F4_DEVICE_ID 0x5000000 ++#define ixD2F4_COMMAND 0x5000001 ++#define ixD2F4_STATUS 0x5000001 ++#define ixD2F4_REVISION_ID 0x5000002 ++#define ixD2F4_PROG_INTERFACE 0x5000002 ++#define ixD2F4_SUB_CLASS 0x5000002 ++#define ixD2F4_BASE_CLASS 0x5000002 ++#define ixD2F4_CACHE_LINE 0x5000003 ++#define ixD2F4_LATENCY 0x5000003 ++#define ixD2F4_HEADER 0x5000003 ++#define ixD2F4_BIST 0x5000003 ++#define ixD2F4_SUB_BUS_NUMBER_LATENCY 0x5000006 ++#define ixD2F4_IO_BASE_LIMIT 0x5000007 ++#define ixD2F4_SECONDARY_STATUS 0x5000007 ++#define ixD2F4_MEM_BASE_LIMIT 0x5000008 ++#define ixD2F4_PREF_BASE_LIMIT 0x5000009 ++#define ixD2F4_PREF_BASE_UPPER 0x500000a ++#define ixD2F4_PREF_LIMIT_UPPER 0x500000b ++#define ixD2F4_IO_BASE_LIMIT_HI 0x500000c ++#define ixD2F4_IRQ_BRIDGE_CNTL 0x500000f ++#define ixD2F4_CAP_PTR 0x500000d ++#define ixD2F4_INTERRUPT_LINE 0x500000f ++#define ixD2F4_INTERRUPT_PIN 0x500000f ++#define ixD2F4_EXT_BRIDGE_CNTL 0x5000010 ++#define ixD2F4_PMI_CAP_LIST 0x5000014 ++#define ixD2F4_PMI_CAP 0x5000014 ++#define ixD2F4_PMI_STATUS_CNTL 0x5000015 ++#define ixD2F4_PCIE_CAP_LIST 0x5000016 ++#define ixD2F4_PCIE_CAP 0x5000016 ++#define ixD2F4_DEVICE_CAP 0x5000017 ++#define ixD2F4_DEVICE_CNTL 0x5000018 ++#define ixD2F4_DEVICE_STATUS 0x5000018 ++#define ixD2F4_LINK_CAP 0x5000019 ++#define ixD2F4_LINK_CNTL 0x500001a ++#define ixD2F4_LINK_STATUS 0x500001a ++#define ixD2F4_SLOT_CAP 0x500001b ++#define ixD2F4_SLOT_CNTL 0x500001c ++#define ixD2F4_SLOT_STATUS 0x500001c ++#define ixD2F4_ROOT_CNTL 0x500001d ++#define ixD2F4_ROOT_CAP 0x500001d ++#define ixD2F4_ROOT_STATUS 0x500001e ++#define ixD2F4_DEVICE_CAP2 0x500001f ++#define ixD2F4_DEVICE_CNTL2 0x5000020 ++#define ixD2F4_DEVICE_STATUS2 0x5000020 ++#define ixD2F4_LINK_CAP2 0x5000021 ++#define ixD2F4_LINK_CNTL2 0x5000022 ++#define ixD2F4_LINK_STATUS2 0x5000022 ++#define ixD2F4_SLOT_CAP2 0x5000023 ++#define ixD2F4_SLOT_CNTL2 0x5000024 ++#define ixD2F4_SLOT_STATUS2 0x5000024 ++#define ixD2F4_MSI_CAP_LIST 0x5000028 ++#define ixD2F4_MSI_MSG_CNTL 0x5000028 ++#define ixD2F4_MSI_MSG_ADDR_LO 0x5000029 ++#define ixD2F4_MSI_MSG_ADDR_HI 0x500002a ++#define ixD2F4_MSI_MSG_DATA_64 0x500002b ++#define ixD2F4_MSI_MSG_DATA 0x500002a ++#define ixD2F4_SSID_CAP_LIST 0x5000030 ++#define ixD2F4_SSID_CAP 0x5000031 ++#define ixD2F4_MSI_MAP_CAP_LIST 0x5000032 ++#define ixD2F4_MSI_MAP_CAP 0x5000032 ++#define ixD2F4_MSI_MAP_ADDR_LO 0x5000033 ++#define ixD2F4_MSI_MAP_ADDR_HI 0x5000034 ++#define ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x5000040 ++#define ixD2F4_PCIE_VENDOR_SPECIFIC_HDR 0x5000041 ++#define ixD2F4_PCIE_VENDOR_SPECIFIC1 0x5000042 ++#define ixD2F4_PCIE_VENDOR_SPECIFIC2 0x5000043 ++#define ixD2F4_PCIE_VC_ENH_CAP_LIST 0x5000044 ++#define ixD2F4_PCIE_PORT_VC_CAP_REG1 0x5000045 ++#define ixD2F4_PCIE_PORT_VC_CAP_REG2 0x5000046 ++#define ixD2F4_PCIE_PORT_VC_CNTL 0x5000047 ++#define ixD2F4_PCIE_PORT_VC_STATUS 0x5000047 ++#define ixD2F4_PCIE_VC0_RESOURCE_CAP 0x5000048 ++#define ixD2F4_PCIE_VC0_RESOURCE_CNTL 0x5000049 ++#define ixD2F4_PCIE_VC0_RESOURCE_STATUS 0x500004a ++#define ixD2F4_PCIE_VC1_RESOURCE_CAP 0x500004b ++#define ixD2F4_PCIE_VC1_RESOURCE_CNTL 0x500004c ++#define ixD2F4_PCIE_VC1_RESOURCE_STATUS 0x500004d ++#define ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x5000050 ++#define ixD2F4_PCIE_DEV_SERIAL_NUM_DW1 0x5000051 ++#define ixD2F4_PCIE_DEV_SERIAL_NUM_DW2 0x5000052 ++#define ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x5000054 ++#define ixD2F4_PCIE_UNCORR_ERR_STATUS 0x5000055 ++#define ixD2F4_PCIE_UNCORR_ERR_MASK 0x5000056 ++#define ixD2F4_PCIE_UNCORR_ERR_SEVERITY 0x5000057 ++#define ixD2F4_PCIE_CORR_ERR_STATUS 0x5000058 ++#define ixD2F4_PCIE_CORR_ERR_MASK 0x5000059 ++#define ixD2F4_PCIE_ADV_ERR_CAP_CNTL 0x500005a ++#define ixD2F4_PCIE_HDR_LOG0 0x500005b ++#define ixD2F4_PCIE_HDR_LOG1 0x500005c ++#define ixD2F4_PCIE_HDR_LOG2 0x500005d ++#define ixD2F4_PCIE_HDR_LOG3 0x500005e ++#define ixD2F4_PCIE_ROOT_ERR_CMD 0x500005f ++#define ixD2F4_PCIE_ROOT_ERR_STATUS 0x5000060 ++#define ixD2F4_PCIE_ERR_SRC_ID 0x5000061 ++#define ixD2F4_PCIE_TLP_PREFIX_LOG0 0x5000062 ++#define ixD2F4_PCIE_TLP_PREFIX_LOG1 0x5000063 ++#define ixD2F4_PCIE_TLP_PREFIX_LOG2 0x5000064 ++#define ixD2F4_PCIE_TLP_PREFIX_LOG3 0x5000065 ++#define ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST 0x500009c ++#define ixD2F4_PCIE_LINK_CNTL3 0x500009d ++#define ixD2F4_PCIE_LANE_ERROR_STATUS 0x500009e ++#define ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL 0x500009f ++#define ixD2F4_PCIE_LANE_1_EQUALIZATION_CNTL 0x500009f ++#define ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL 0x50000a0 ++#define ixD2F4_PCIE_LANE_3_EQUALIZATION_CNTL 0x50000a0 ++#define ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL 0x50000a1 ++#define ixD2F4_PCIE_LANE_5_EQUALIZATION_CNTL 0x50000a1 ++#define ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL 0x50000a2 ++#define ixD2F4_PCIE_LANE_7_EQUALIZATION_CNTL 0x50000a2 ++#define ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL 0x50000a3 ++#define ixD2F4_PCIE_LANE_9_EQUALIZATION_CNTL 0x50000a3 ++#define ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL 0x50000a4 ++#define ixD2F4_PCIE_LANE_11_EQUALIZATION_CNTL 0x50000a4 ++#define ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL 0x50000a5 ++#define ixD2F4_PCIE_LANE_13_EQUALIZATION_CNTL 0x50000a5 ++#define ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL 0x50000a6 ++#define ixD2F4_PCIE_LANE_15_EQUALIZATION_CNTL 0x50000a6 ++#define ixD2F4_PCIE_ACS_ENH_CAP_LIST 0x50000a8 ++#define ixD2F4_PCIE_ACS_CAP 0x50000a9 ++#define ixD2F4_PCIE_ACS_CNTL 0x50000a9 ++#define ixD2F4_PCIE_MC_ENH_CAP_LIST 0x50000bc ++#define ixD2F4_PCIE_MC_CAP 0x50000bd ++#define ixD2F4_PCIE_MC_CNTL 0x50000bd ++#define ixD2F4_PCIE_MC_ADDR0 0x50000be ++#define ixD2F4_PCIE_MC_ADDR1 0x50000bf ++#define ixD2F4_PCIE_MC_RCV0 0x50000c0 ++#define ixD2F4_PCIE_MC_RCV1 0x50000c1 ++#define ixD2F4_PCIE_MC_BLOCK_ALL0 0x50000c2 ++#define ixD2F4_PCIE_MC_BLOCK_ALL1 0x50000c3 ++#define ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0 0x50000c4 ++#define ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1 0x50000c5 ++#define ixD2F4_PCIE_MC_OVERLAY_BAR0 0x50000c6 ++#define ixD2F4_PCIE_MC_OVERLAY_BAR1 0x50000c7 ++#define ixD2F5_PCIE_PORT_INDEX 0x6000038 ++#define ixD2F5_PCIE_PORT_DATA 0x6000039 ++#define ixD2F5_PCIEP_RESERVED 0x0 ++#define ixD2F5_PCIEP_SCRATCH 0x1 ++#define ixD2F5_PCIEP_HW_DEBUG 0x2 ++#define ixD2F5_PCIEP_PORT_CNTL 0x10 ++#define ixD2F5_PCIE_TX_CNTL 0x20 ++#define ixD2F5_PCIE_TX_REQUESTER_ID 0x21 ++#define ixD2F5_PCIE_TX_VENDOR_SPECIFIC 0x22 ++#define ixD2F5_PCIE_TX_REQUEST_NUM_CNTL 0x23 ++#define ixD2F5_PCIE_TX_SEQ 0x24 ++#define ixD2F5_PCIE_TX_REPLAY 0x25 ++#define ixD2F5_PCIE_TX_ACK_LATENCY_LIMIT 0x26 ++#define ixD2F5_PCIE_TX_CREDITS_ADVT_P 0x30 ++#define ixD2F5_PCIE_TX_CREDITS_ADVT_NP 0x31 ++#define ixD2F5_PCIE_TX_CREDITS_ADVT_CPL 0x32 ++#define ixD2F5_PCIE_TX_CREDITS_INIT_P 0x33 ++#define ixD2F5_PCIE_TX_CREDITS_INIT_NP 0x34 ++#define ixD2F5_PCIE_TX_CREDITS_INIT_CPL 0x35 ++#define ixD2F5_PCIE_TX_CREDITS_STATUS 0x36 ++#define ixD2F5_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 ++#define ixD2F5_PCIE_P_PORT_LANE_STATUS 0x50 ++#define ixD2F5_PCIE_FC_P 0x60 ++#define ixD2F5_PCIE_FC_NP 0x61 ++#define ixD2F5_PCIE_FC_CPL 0x62 ++#define ixD2F5_PCIE_ERR_CNTL 0x6a ++#define ixD2F5_PCIE_RX_CNTL 0x70 ++#define ixD2F5_PCIE_RX_EXPECTED_SEQNUM 0x71 ++#define ixD2F5_PCIE_RX_VENDOR_SPECIFIC 0x72 ++#define ixD2F5_PCIE_RX_CNTL3 0x74 ++#define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_P 0x80 ++#define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 ++#define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 ++#define ixD2F5_PCIEP_ERROR_INJECT_PHYSICAL 0x83 ++#define ixD2F5_PCIEP_ERROR_INJECT_TRANSACTION 0x84 ++#define ixD2F5_PCIE_LC_CNTL 0xa0 ++#define ixD2F5_PCIE_LC_CNTL2 0xb1 ++#define ixD2F5_PCIE_LC_CNTL3 0xb5 ++#define ixD2F5_PCIE_LC_CNTL4 0xb6 ++#define ixD2F5_PCIE_LC_CNTL5 0xb7 ++#define ixD2F5_PCIE_LC_CNTL6 0xbb ++#define ixD2F5_PCIE_LC_BW_CHANGE_CNTL 0xb2 ++#define ixD2F5_PCIE_LC_TRAINING_CNTL 0xa1 ++#define ixD2F5_PCIE_LC_LINK_WIDTH_CNTL 0xa2 ++#define ixD2F5_PCIE_LC_N_FTS_CNTL 0xa3 ++#define ixD2F5_PCIE_LC_SPEED_CNTL 0xa4 ++#define ixD2F5_PCIE_LC_CDR_CNTL 0xb3 ++#define ixD2F5_PCIE_LC_LANE_CNTL 0xb4 ++#define ixD2F5_PCIE_LC_FORCE_COEFF 0xb8 ++#define ixD2F5_PCIE_LC_BEST_EQ_SETTINGS 0xb9 ++#define ixD2F5_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba ++#define ixD2F5_PCIE_LC_STATE0 0xa5 ++#define ixD2F5_PCIE_LC_STATE1 0xa6 ++#define ixD2F5_PCIE_LC_STATE2 0xa7 ++#define ixD2F5_PCIE_LC_STATE3 0xa8 ++#define ixD2F5_PCIE_LC_STATE4 0xa9 ++#define ixD2F5_PCIE_LC_STATE5 0xaa ++#define ixD2F5_PCIEP_STRAP_LC 0xc0 ++#define ixD2F5_PCIEP_STRAP_MISC 0xc1 ++#define ixD2F5_PCIEP_BCH_ECC_CNTL 0xd0 ++#define ixD2F5_PCIEP_HPGI_PRIVATE 0xd2 ++#define ixD2F5_PCIEP_HPGI 0xda ++#define ixD2F5_VENDOR_ID 0x6000000 ++#define ixD2F5_DEVICE_ID 0x6000000 ++#define ixD2F5_COMMAND 0x6000001 ++#define ixD2F5_STATUS 0x6000001 ++#define ixD2F5_REVISION_ID 0x6000002 ++#define ixD2F5_PROG_INTERFACE 0x6000002 ++#define ixD2F5_SUB_CLASS 0x6000002 ++#define ixD2F5_BASE_CLASS 0x6000002 ++#define ixD2F5_CACHE_LINE 0x6000003 ++#define ixD2F5_LATENCY 0x6000003 ++#define ixD2F5_HEADER 0x6000003 ++#define ixD2F5_BIST 0x6000003 ++#define ixD2F5_SUB_BUS_NUMBER_LATENCY 0x6000006 ++#define ixD2F5_IO_BASE_LIMIT 0x6000007 ++#define ixD2F5_SECONDARY_STATUS 0x6000007 ++#define ixD2F5_MEM_BASE_LIMIT 0x6000008 ++#define ixD2F5_PREF_BASE_LIMIT 0x6000009 ++#define ixD2F5_PREF_BASE_UPPER 0x600000a ++#define ixD2F5_PREF_LIMIT_UPPER 0x600000b ++#define ixD2F5_IO_BASE_LIMIT_HI 0x600000c ++#define ixD2F5_IRQ_BRIDGE_CNTL 0x600000f ++#define ixD2F5_CAP_PTR 0x600000d ++#define ixD2F5_INTERRUPT_LINE 0x600000f ++#define ixD2F5_INTERRUPT_PIN 0x600000f ++#define ixD2F5_EXT_BRIDGE_CNTL 0x6000010 ++#define ixD2F5_PMI_CAP_LIST 0x6000014 ++#define ixD2F5_PMI_CAP 0x6000014 ++#define ixD2F5_PMI_STATUS_CNTL 0x6000015 ++#define ixD2F5_PCIE_CAP_LIST 0x6000016 ++#define ixD2F5_PCIE_CAP 0x6000016 ++#define ixD2F5_DEVICE_CAP 0x6000017 ++#define ixD2F5_DEVICE_CNTL 0x6000018 ++#define ixD2F5_DEVICE_STATUS 0x6000018 ++#define ixD2F5_LINK_CAP 0x6000019 ++#define ixD2F5_LINK_CNTL 0x600001a ++#define ixD2F5_LINK_STATUS 0x600001a ++#define ixD2F5_SLOT_CAP 0x600001b ++#define ixD2F5_SLOT_CNTL 0x600001c ++#define ixD2F5_SLOT_STATUS 0x600001c ++#define ixD2F5_ROOT_CNTL 0x600001d ++#define ixD2F5_ROOT_CAP 0x600001d ++#define ixD2F5_ROOT_STATUS 0x600001e ++#define ixD2F5_DEVICE_CAP2 0x600001f ++#define ixD2F5_DEVICE_CNTL2 0x6000020 ++#define ixD2F5_DEVICE_STATUS2 0x6000020 ++#define ixD2F5_LINK_CAP2 0x6000021 ++#define ixD2F5_LINK_CNTL2 0x6000022 ++#define ixD2F5_LINK_STATUS2 0x6000022 ++#define ixD2F5_SLOT_CAP2 0x6000023 ++#define ixD2F5_SLOT_CNTL2 0x6000024 ++#define ixD2F5_SLOT_STATUS2 0x6000024 ++#define ixD2F5_MSI_CAP_LIST 0x6000028 ++#define ixD2F5_MSI_MSG_CNTL 0x6000028 ++#define ixD2F5_MSI_MSG_ADDR_LO 0x6000029 ++#define ixD2F5_MSI_MSG_ADDR_HI 0x600002a ++#define ixD2F5_MSI_MSG_DATA_64 0x600002b ++#define ixD2F5_MSI_MSG_DATA 0x600002a ++#define ixD2F5_SSID_CAP_LIST 0x6000030 ++#define ixD2F5_SSID_CAP 0x6000031 ++#define ixD2F5_MSI_MAP_CAP_LIST 0x6000032 ++#define ixD2F5_MSI_MAP_CAP 0x6000032 ++#define ixD2F5_MSI_MAP_ADDR_LO 0x6000033 ++#define ixD2F5_MSI_MAP_ADDR_HI 0x6000034 ++#define ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x6000040 ++#define ixD2F5_PCIE_VENDOR_SPECIFIC_HDR 0x6000041 ++#define ixD2F5_PCIE_VENDOR_SPECIFIC1 0x6000042 ++#define ixD2F5_PCIE_VENDOR_SPECIFIC2 0x6000043 ++#define ixD2F5_PCIE_VC_ENH_CAP_LIST 0x6000044 ++#define ixD2F5_PCIE_PORT_VC_CAP_REG1 0x6000045 ++#define ixD2F5_PCIE_PORT_VC_CAP_REG2 0x6000046 ++#define ixD2F5_PCIE_PORT_VC_CNTL 0x6000047 ++#define ixD2F5_PCIE_PORT_VC_STATUS 0x6000047 ++#define ixD2F5_PCIE_VC0_RESOURCE_CAP 0x6000048 ++#define ixD2F5_PCIE_VC0_RESOURCE_CNTL 0x6000049 ++#define ixD2F5_PCIE_VC0_RESOURCE_STATUS 0x600004a ++#define ixD2F5_PCIE_VC1_RESOURCE_CAP 0x600004b ++#define ixD2F5_PCIE_VC1_RESOURCE_CNTL 0x600004c ++#define ixD2F5_PCIE_VC1_RESOURCE_STATUS 0x600004d ++#define ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x6000050 ++#define ixD2F5_PCIE_DEV_SERIAL_NUM_DW1 0x6000051 ++#define ixD2F5_PCIE_DEV_SERIAL_NUM_DW2 0x6000052 ++#define ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x6000054 ++#define ixD2F5_PCIE_UNCORR_ERR_STATUS 0x6000055 ++#define ixD2F5_PCIE_UNCORR_ERR_MASK 0x6000056 ++#define ixD2F5_PCIE_UNCORR_ERR_SEVERITY 0x6000057 ++#define ixD2F5_PCIE_CORR_ERR_STATUS 0x6000058 ++#define ixD2F5_PCIE_CORR_ERR_MASK 0x6000059 ++#define ixD2F5_PCIE_ADV_ERR_CAP_CNTL 0x600005a ++#define ixD2F5_PCIE_HDR_LOG0 0x600005b ++#define ixD2F5_PCIE_HDR_LOG1 0x600005c ++#define ixD2F5_PCIE_HDR_LOG2 0x600005d ++#define ixD2F5_PCIE_HDR_LOG3 0x600005e ++#define ixD2F5_PCIE_ROOT_ERR_CMD 0x600005f ++#define ixD2F5_PCIE_ROOT_ERR_STATUS 0x6000060 ++#define ixD2F5_PCIE_ERR_SRC_ID 0x6000061 ++#define ixD2F5_PCIE_TLP_PREFIX_LOG0 0x6000062 ++#define ixD2F5_PCIE_TLP_PREFIX_LOG1 0x6000063 ++#define ixD2F5_PCIE_TLP_PREFIX_LOG2 0x6000064 ++#define ixD2F5_PCIE_TLP_PREFIX_LOG3 0x6000065 ++#define ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST 0x600009c ++#define ixD2F5_PCIE_LINK_CNTL3 0x600009d ++#define ixD2F5_PCIE_LANE_ERROR_STATUS 0x600009e ++#define ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL 0x600009f ++#define ixD2F5_PCIE_LANE_1_EQUALIZATION_CNTL 0x600009f ++#define ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL 0x60000a0 ++#define ixD2F5_PCIE_LANE_3_EQUALIZATION_CNTL 0x60000a0 ++#define ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL 0x60000a1 ++#define ixD2F5_PCIE_LANE_5_EQUALIZATION_CNTL 0x60000a1 ++#define ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL 0x60000a2 ++#define ixD2F5_PCIE_LANE_7_EQUALIZATION_CNTL 0x60000a2 ++#define ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL 0x60000a3 ++#define ixD2F5_PCIE_LANE_9_EQUALIZATION_CNTL 0x60000a3 ++#define ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL 0x60000a4 ++#define ixD2F5_PCIE_LANE_11_EQUALIZATION_CNTL 0x60000a4 ++#define ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL 0x60000a5 ++#define ixD2F5_PCIE_LANE_13_EQUALIZATION_CNTL 0x60000a5 ++#define ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL 0x60000a6 ++#define ixD2F5_PCIE_LANE_15_EQUALIZATION_CNTL 0x60000a6 ++#define ixD2F5_PCIE_ACS_ENH_CAP_LIST 0x60000a8 ++#define ixD2F5_PCIE_ACS_CAP 0x60000a9 ++#define ixD2F5_PCIE_ACS_CNTL 0x60000a9 ++#define ixD2F5_PCIE_MC_ENH_CAP_LIST 0x60000bc ++#define ixD2F5_PCIE_MC_CAP 0x60000bd ++#define ixD2F5_PCIE_MC_CNTL 0x60000bd ++#define ixD2F5_PCIE_MC_ADDR0 0x60000be ++#define ixD2F5_PCIE_MC_ADDR1 0x60000bf ++#define ixD2F5_PCIE_MC_RCV0 0x60000c0 ++#define ixD2F5_PCIE_MC_RCV1 0x60000c1 ++#define ixD2F5_PCIE_MC_BLOCK_ALL0 0x60000c2 ++#define ixD2F5_PCIE_MC_BLOCK_ALL1 0x60000c3 ++#define ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0 0x60000c4 ++#define ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1 0x60000c5 ++#define ixD2F5_PCIE_MC_OVERLAY_BAR0 0x60000c6 ++#define ixD2F5_PCIE_MC_OVERLAY_BAR1 0x60000c7 ++#define ixD3F1_PCIE_PORT_INDEX 0x7000038 ++#define ixD3F1_PCIE_PORT_DATA 0x7000039 ++#define ixD3F1_PCIEP_RESERVED 0x0 ++#define ixD3F1_PCIEP_SCRATCH 0x1 ++#define ixD3F1_PCIEP_HW_DEBUG 0x2 ++#define ixD3F1_PCIEP_PORT_CNTL 0x10 ++#define ixD3F1_PCIE_TX_CNTL 0x20 ++#define ixD3F1_PCIE_TX_REQUESTER_ID 0x21 ++#define ixD3F1_PCIE_TX_VENDOR_SPECIFIC 0x22 ++#define ixD3F1_PCIE_TX_REQUEST_NUM_CNTL 0x23 ++#define ixD3F1_PCIE_TX_SEQ 0x24 ++#define ixD3F1_PCIE_TX_REPLAY 0x25 ++#define ixD3F1_PCIE_TX_ACK_LATENCY_LIMIT 0x26 ++#define ixD3F1_PCIE_TX_CREDITS_ADVT_P 0x30 ++#define ixD3F1_PCIE_TX_CREDITS_ADVT_NP 0x31 ++#define ixD3F1_PCIE_TX_CREDITS_ADVT_CPL 0x32 ++#define ixD3F1_PCIE_TX_CREDITS_INIT_P 0x33 ++#define ixD3F1_PCIE_TX_CREDITS_INIT_NP 0x34 ++#define ixD3F1_PCIE_TX_CREDITS_INIT_CPL 0x35 ++#define ixD3F1_PCIE_TX_CREDITS_STATUS 0x36 ++#define ixD3F1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 ++#define ixD3F1_PCIE_P_PORT_LANE_STATUS 0x50 ++#define ixD3F1_PCIE_FC_P 0x60 ++#define ixD3F1_PCIE_FC_NP 0x61 ++#define ixD3F1_PCIE_FC_CPL 0x62 ++#define ixD3F1_PCIE_ERR_CNTL 0x6a ++#define ixD3F1_PCIE_RX_CNTL 0x70 ++#define ixD3F1_PCIE_RX_EXPECTED_SEQNUM 0x71 ++#define ixD3F1_PCIE_RX_VENDOR_SPECIFIC 0x72 ++#define ixD3F1_PCIE_RX_CNTL3 0x74 ++#define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_P 0x80 ++#define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 ++#define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 ++#define ixD3F1_PCIEP_ERROR_INJECT_PHYSICAL 0x83 ++#define ixD3F1_PCIEP_ERROR_INJECT_TRANSACTION 0x84 ++#define ixD3F1_PCIE_LC_CNTL 0xa0 ++#define ixD3F1_PCIE_LC_CNTL2 0xb1 ++#define ixD3F1_PCIE_LC_CNTL3 0xb5 ++#define ixD3F1_PCIE_LC_CNTL4 0xb6 ++#define ixD3F1_PCIE_LC_CNTL5 0xb7 ++#define ixD3F1_PCIE_LC_CNTL6 0xbb ++#define ixD3F1_PCIE_LC_BW_CHANGE_CNTL 0xb2 ++#define ixD3F1_PCIE_LC_TRAINING_CNTL 0xa1 ++#define ixD3F1_PCIE_LC_LINK_WIDTH_CNTL 0xa2 ++#define ixD3F1_PCIE_LC_N_FTS_CNTL 0xa3 ++#define ixD3F1_PCIE_LC_SPEED_CNTL 0xa4 ++#define ixD3F1_PCIE_LC_CDR_CNTL 0xb3 ++#define ixD3F1_PCIE_LC_LANE_CNTL 0xb4 ++#define ixD3F1_PCIE_LC_FORCE_COEFF 0xb8 ++#define ixD3F1_PCIE_LC_BEST_EQ_SETTINGS 0xb9 ++#define ixD3F1_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba ++#define ixD3F1_PCIE_LC_STATE0 0xa5 ++#define ixD3F1_PCIE_LC_STATE1 0xa6 ++#define ixD3F1_PCIE_LC_STATE2 0xa7 ++#define ixD3F1_PCIE_LC_STATE3 0xa8 ++#define ixD3F1_PCIE_LC_STATE4 0xa9 ++#define ixD3F1_PCIE_LC_STATE5 0xaa ++#define ixD3F1_PCIEP_STRAP_LC 0xc0 ++#define ixD3F1_PCIEP_STRAP_MISC 0xc1 ++#define ixD3F1_PCIEP_BCH_ECC_CNTL 0xd0 ++#define ixD3F1_PCIEP_HPGI_PRIVATE 0xd2 ++#define ixD3F1_PCIEP_HPGI 0xda ++#define ixD3F1_VENDOR_ID 0x7000000 ++#define ixD3F1_DEVICE_ID 0x7000000 ++#define ixD3F1_COMMAND 0x7000001 ++#define ixD3F1_STATUS 0x7000001 ++#define ixD3F1_REVISION_ID 0x7000002 ++#define ixD3F1_PROG_INTERFACE 0x7000002 ++#define ixD3F1_SUB_CLASS 0x7000002 ++#define ixD3F1_BASE_CLASS 0x7000002 ++#define ixD3F1_CACHE_LINE 0x7000003 ++#define ixD3F1_LATENCY 0x7000003 ++#define ixD3F1_HEADER 0x7000003 ++#define ixD3F1_BIST 0x7000003 ++#define ixD3F1_SUB_BUS_NUMBER_LATENCY 0x7000006 ++#define ixD3F1_IO_BASE_LIMIT 0x7000007 ++#define ixD3F1_SECONDARY_STATUS 0x7000007 ++#define ixD3F1_MEM_BASE_LIMIT 0x7000008 ++#define ixD3F1_PREF_BASE_LIMIT 0x7000009 ++#define ixD3F1_PREF_BASE_UPPER 0x700000a ++#define ixD3F1_PREF_LIMIT_UPPER 0x700000b ++#define ixD3F1_IO_BASE_LIMIT_HI 0x700000c ++#define ixD3F1_IRQ_BRIDGE_CNTL 0x700000f ++#define ixD3F1_CAP_PTR 0x700000d ++#define ixD3F1_INTERRUPT_LINE 0x700000f ++#define ixD3F1_INTERRUPT_PIN 0x700000f ++#define ixD3F1_EXT_BRIDGE_CNTL 0x7000010 ++#define ixD3F1_PMI_CAP_LIST 0x7000014 ++#define ixD3F1_PMI_CAP 0x7000014 ++#define ixD3F1_PMI_STATUS_CNTL 0x7000015 ++#define ixD3F1_PCIE_CAP_LIST 0x7000016 ++#define ixD3F1_PCIE_CAP 0x7000016 ++#define ixD3F1_DEVICE_CAP 0x7000017 ++#define ixD3F1_DEVICE_CNTL 0x7000018 ++#define ixD3F1_DEVICE_STATUS 0x7000018 ++#define ixD3F1_LINK_CAP 0x7000019 ++#define ixD3F1_LINK_CNTL 0x700001a ++#define ixD3F1_LINK_STATUS 0x700001a ++#define ixD3F1_SLOT_CAP 0x700001b ++#define ixD3F1_SLOT_CNTL 0x700001c ++#define ixD3F1_SLOT_STATUS 0x700001c ++#define ixD3F1_ROOT_CNTL 0x700001d ++#define ixD3F1_ROOT_CAP 0x700001d ++#define ixD3F1_ROOT_STATUS 0x700001e ++#define ixD3F1_DEVICE_CAP2 0x700001f ++#define ixD3F1_DEVICE_CNTL2 0x7000020 ++#define ixD3F1_DEVICE_STATUS2 0x7000020 ++#define ixD3F1_LINK_CAP2 0x7000021 ++#define ixD3F1_LINK_CNTL2 0x7000022 ++#define ixD3F1_LINK_STATUS2 0x7000022 ++#define ixD3F1_SLOT_CAP2 0x7000023 ++#define ixD3F1_SLOT_CNTL2 0x7000024 ++#define ixD3F1_SLOT_STATUS2 0x7000024 ++#define ixD3F1_MSI_CAP_LIST 0x7000028 ++#define ixD3F1_MSI_MSG_CNTL 0x7000028 ++#define ixD3F1_MSI_MSG_ADDR_LO 0x7000029 ++#define ixD3F1_MSI_MSG_ADDR_HI 0x700002a ++#define ixD3F1_MSI_MSG_DATA_64 0x700002b ++#define ixD3F1_MSI_MSG_DATA 0x700002a ++#define ixD3F1_SSID_CAP_LIST 0x7000030 ++#define ixD3F1_SSID_CAP 0x7000031 ++#define ixD3F1_MSI_MAP_CAP_LIST 0x7000032 ++#define ixD3F1_MSI_MAP_CAP 0x7000032 ++#define ixD3F1_MSI_MAP_ADDR_LO 0x7000033 ++#define ixD3F1_MSI_MAP_ADDR_HI 0x7000034 ++#define ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x7000040 ++#define ixD3F1_PCIE_VENDOR_SPECIFIC_HDR 0x7000041 ++#define ixD3F1_PCIE_VENDOR_SPECIFIC1 0x7000042 ++#define ixD3F1_PCIE_VENDOR_SPECIFIC2 0x7000043 ++#define ixD3F1_PCIE_VC_ENH_CAP_LIST 0x7000044 ++#define ixD3F1_PCIE_PORT_VC_CAP_REG1 0x7000045 ++#define ixD3F1_PCIE_PORT_VC_CAP_REG2 0x7000046 ++#define ixD3F1_PCIE_PORT_VC_CNTL 0x7000047 ++#define ixD3F1_PCIE_PORT_VC_STATUS 0x7000047 ++#define ixD3F1_PCIE_VC0_RESOURCE_CAP 0x7000048 ++#define ixD3F1_PCIE_VC0_RESOURCE_CNTL 0x7000049 ++#define ixD3F1_PCIE_VC0_RESOURCE_STATUS 0x700004a ++#define ixD3F1_PCIE_VC1_RESOURCE_CAP 0x700004b ++#define ixD3F1_PCIE_VC1_RESOURCE_CNTL 0x700004c ++#define ixD3F1_PCIE_VC1_RESOURCE_STATUS 0x700004d ++#define ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x7000050 ++#define ixD3F1_PCIE_DEV_SERIAL_NUM_DW1 0x7000051 ++#define ixD3F1_PCIE_DEV_SERIAL_NUM_DW2 0x7000052 ++#define ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x7000054 ++#define ixD3F1_PCIE_UNCORR_ERR_STATUS 0x7000055 ++#define ixD3F1_PCIE_UNCORR_ERR_MASK 0x7000056 ++#define ixD3F1_PCIE_UNCORR_ERR_SEVERITY 0x7000057 ++#define ixD3F1_PCIE_CORR_ERR_STATUS 0x7000058 ++#define ixD3F1_PCIE_CORR_ERR_MASK 0x7000059 ++#define ixD3F1_PCIE_ADV_ERR_CAP_CNTL 0x700005a ++#define ixD3F1_PCIE_HDR_LOG0 0x700005b ++#define ixD3F1_PCIE_HDR_LOG1 0x700005c ++#define ixD3F1_PCIE_HDR_LOG2 0x700005d ++#define ixD3F1_PCIE_HDR_LOG3 0x700005e ++#define ixD3F1_PCIE_ROOT_ERR_CMD 0x700005f ++#define ixD3F1_PCIE_ROOT_ERR_STATUS 0x7000060 ++#define ixD3F1_PCIE_ERR_SRC_ID 0x7000061 ++#define ixD3F1_PCIE_TLP_PREFIX_LOG0 0x7000062 ++#define ixD3F1_PCIE_TLP_PREFIX_LOG1 0x7000063 ++#define ixD3F1_PCIE_TLP_PREFIX_LOG2 0x7000064 ++#define ixD3F1_PCIE_TLP_PREFIX_LOG3 0x7000065 ++#define ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST 0x700009c ++#define ixD3F1_PCIE_LINK_CNTL3 0x700009d ++#define ixD3F1_PCIE_LANE_ERROR_STATUS 0x700009e ++#define ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL 0x700009f ++#define ixD3F1_PCIE_LANE_1_EQUALIZATION_CNTL 0x700009f ++#define ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL 0x70000a0 ++#define ixD3F1_PCIE_LANE_3_EQUALIZATION_CNTL 0x70000a0 ++#define ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL 0x70000a1 ++#define ixD3F1_PCIE_LANE_5_EQUALIZATION_CNTL 0x70000a1 ++#define ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL 0x70000a2 ++#define ixD3F1_PCIE_LANE_7_EQUALIZATION_CNTL 0x70000a2 ++#define ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL 0x70000a3 ++#define ixD3F1_PCIE_LANE_9_EQUALIZATION_CNTL 0x70000a3 ++#define ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL 0x70000a4 ++#define ixD3F1_PCIE_LANE_11_EQUALIZATION_CNTL 0x70000a4 ++#define ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL 0x70000a5 ++#define ixD3F1_PCIE_LANE_13_EQUALIZATION_CNTL 0x70000a5 ++#define ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL 0x70000a6 ++#define ixD3F1_PCIE_LANE_15_EQUALIZATION_CNTL 0x70000a6 ++#define ixD3F1_PCIE_ACS_ENH_CAP_LIST 0x70000a8 ++#define ixD3F1_PCIE_ACS_CAP 0x70000a9 ++#define ixD3F1_PCIE_ACS_CNTL 0x70000a9 ++#define ixD3F1_PCIE_MC_ENH_CAP_LIST 0x70000bc ++#define ixD3F1_PCIE_MC_CAP 0x70000bd ++#define ixD3F1_PCIE_MC_CNTL 0x70000bd ++#define ixD3F1_PCIE_MC_ADDR0 0x70000be ++#define ixD3F1_PCIE_MC_ADDR1 0x70000bf ++#define ixD3F1_PCIE_MC_RCV0 0x70000c0 ++#define ixD3F1_PCIE_MC_RCV1 0x70000c1 ++#define ixD3F1_PCIE_MC_BLOCK_ALL0 0x70000c2 ++#define ixD3F1_PCIE_MC_BLOCK_ALL1 0x70000c3 ++#define ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x70000c4 ++#define ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x70000c5 ++#define ixD3F1_PCIE_MC_OVERLAY_BAR0 0x70000c6 ++#define ixD3F1_PCIE_MC_OVERLAY_BAR1 0x70000c7 ++#define ixD3F2_PCIE_PORT_INDEX 0x8000038 ++#define ixD3F2_PCIE_PORT_DATA 0x8000039 ++#define ixD3F2_PCIEP_RESERVED 0x0 ++#define ixD3F2_PCIEP_SCRATCH 0x1 ++#define ixD3F2_PCIEP_HW_DEBUG 0x2 ++#define ixD3F2_PCIEP_PORT_CNTL 0x10 ++#define ixD3F2_PCIE_TX_CNTL 0x20 ++#define ixD3F2_PCIE_TX_REQUESTER_ID 0x21 ++#define ixD3F2_PCIE_TX_VENDOR_SPECIFIC 0x22 ++#define ixD3F2_PCIE_TX_REQUEST_NUM_CNTL 0x23 ++#define ixD3F2_PCIE_TX_SEQ 0x24 ++#define ixD3F2_PCIE_TX_REPLAY 0x25 ++#define ixD3F2_PCIE_TX_ACK_LATENCY_LIMIT 0x26 ++#define ixD3F2_PCIE_TX_CREDITS_ADVT_P 0x30 ++#define ixD3F2_PCIE_TX_CREDITS_ADVT_NP 0x31 ++#define ixD3F2_PCIE_TX_CREDITS_ADVT_CPL 0x32 ++#define ixD3F2_PCIE_TX_CREDITS_INIT_P 0x33 ++#define ixD3F2_PCIE_TX_CREDITS_INIT_NP 0x34 ++#define ixD3F2_PCIE_TX_CREDITS_INIT_CPL 0x35 ++#define ixD3F2_PCIE_TX_CREDITS_STATUS 0x36 ++#define ixD3F2_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 ++#define ixD3F2_PCIE_P_PORT_LANE_STATUS 0x50 ++#define ixD3F2_PCIE_FC_P 0x60 ++#define ixD3F2_PCIE_FC_NP 0x61 ++#define ixD3F2_PCIE_FC_CPL 0x62 ++#define ixD3F2_PCIE_ERR_CNTL 0x6a ++#define ixD3F2_PCIE_RX_CNTL 0x70 ++#define ixD3F2_PCIE_RX_EXPECTED_SEQNUM 0x71 ++#define ixD3F2_PCIE_RX_VENDOR_SPECIFIC 0x72 ++#define ixD3F2_PCIE_RX_CNTL3 0x74 ++#define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_P 0x80 ++#define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 ++#define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 ++#define ixD3F2_PCIEP_ERROR_INJECT_PHYSICAL 0x83 ++#define ixD3F2_PCIEP_ERROR_INJECT_TRANSACTION 0x84 ++#define ixD3F2_PCIE_LC_CNTL 0xa0 ++#define ixD3F2_PCIE_LC_CNTL2 0xb1 ++#define ixD3F2_PCIE_LC_CNTL3 0xb5 ++#define ixD3F2_PCIE_LC_CNTL4 0xb6 ++#define ixD3F2_PCIE_LC_CNTL5 0xb7 ++#define ixD3F2_PCIE_LC_CNTL6 0xbb ++#define ixD3F2_PCIE_LC_BW_CHANGE_CNTL 0xb2 ++#define ixD3F2_PCIE_LC_TRAINING_CNTL 0xa1 ++#define ixD3F2_PCIE_LC_LINK_WIDTH_CNTL 0xa2 ++#define ixD3F2_PCIE_LC_N_FTS_CNTL 0xa3 ++#define ixD3F2_PCIE_LC_SPEED_CNTL 0xa4 ++#define ixD3F2_PCIE_LC_CDR_CNTL 0xb3 ++#define ixD3F2_PCIE_LC_LANE_CNTL 0xb4 ++#define ixD3F2_PCIE_LC_FORCE_COEFF 0xb8 ++#define ixD3F2_PCIE_LC_BEST_EQ_SETTINGS 0xb9 ++#define ixD3F2_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba ++#define ixD3F2_PCIE_LC_STATE0 0xa5 ++#define ixD3F2_PCIE_LC_STATE1 0xa6 ++#define ixD3F2_PCIE_LC_STATE2 0xa7 ++#define ixD3F2_PCIE_LC_STATE3 0xa8 ++#define ixD3F2_PCIE_LC_STATE4 0xa9 ++#define ixD3F2_PCIE_LC_STATE5 0xaa ++#define ixD3F2_PCIEP_STRAP_LC 0xc0 ++#define ixD3F2_PCIEP_STRAP_MISC 0xc1 ++#define ixD3F2_PCIEP_BCH_ECC_CNTL 0xd0 ++#define ixD3F2_PCIEP_HPGI_PRIVATE 0xd2 ++#define ixD3F2_PCIEP_HPGI 0xda ++#define ixD3F2_VENDOR_ID 0x8000000 ++#define ixD3F2_DEVICE_ID 0x8000000 ++#define ixD3F2_COMMAND 0x8000001 ++#define ixD3F2_STATUS 0x8000001 ++#define ixD3F2_REVISION_ID 0x8000002 ++#define ixD3F2_PROG_INTERFACE 0x8000002 ++#define ixD3F2_SUB_CLASS 0x8000002 ++#define ixD3F2_BASE_CLASS 0x8000002 ++#define ixD3F2_CACHE_LINE 0x8000003 ++#define ixD3F2_LATENCY 0x8000003 ++#define ixD3F2_HEADER 0x8000003 ++#define ixD3F2_BIST 0x8000003 ++#define ixD3F2_SUB_BUS_NUMBER_LATENCY 0x8000006 ++#define ixD3F2_IO_BASE_LIMIT 0x8000007 ++#define ixD3F2_SECONDARY_STATUS 0x8000007 ++#define ixD3F2_MEM_BASE_LIMIT 0x8000008 ++#define ixD3F2_PREF_BASE_LIMIT 0x8000009 ++#define ixD3F2_PREF_BASE_UPPER 0x800000a ++#define ixD3F2_PREF_LIMIT_UPPER 0x800000b ++#define ixD3F2_IO_BASE_LIMIT_HI 0x800000c ++#define ixD3F2_IRQ_BRIDGE_CNTL 0x800000f ++#define ixD3F2_CAP_PTR 0x800000d ++#define ixD3F2_INTERRUPT_LINE 0x800000f ++#define ixD3F2_INTERRUPT_PIN 0x800000f ++#define ixD3F2_EXT_BRIDGE_CNTL 0x8000010 ++#define ixD3F2_PMI_CAP_LIST 0x8000014 ++#define ixD3F2_PMI_CAP 0x8000014 ++#define ixD3F2_PMI_STATUS_CNTL 0x8000015 ++#define ixD3F2_PCIE_CAP_LIST 0x8000016 ++#define ixD3F2_PCIE_CAP 0x8000016 ++#define ixD3F2_DEVICE_CAP 0x8000017 ++#define ixD3F2_DEVICE_CNTL 0x8000018 ++#define ixD3F2_DEVICE_STATUS 0x8000018 ++#define ixD3F2_LINK_CAP 0x8000019 ++#define ixD3F2_LINK_CNTL 0x800001a ++#define ixD3F2_LINK_STATUS 0x800001a ++#define ixD3F2_SLOT_CAP 0x800001b ++#define ixD3F2_SLOT_CNTL 0x800001c ++#define ixD3F2_SLOT_STATUS 0x800001c ++#define ixD3F2_ROOT_CNTL 0x800001d ++#define ixD3F2_ROOT_CAP 0x800001d ++#define ixD3F2_ROOT_STATUS 0x800001e ++#define ixD3F2_DEVICE_CAP2 0x800001f ++#define ixD3F2_DEVICE_CNTL2 0x8000020 ++#define ixD3F2_DEVICE_STATUS2 0x8000020 ++#define ixD3F2_LINK_CAP2 0x8000021 ++#define ixD3F2_LINK_CNTL2 0x8000022 ++#define ixD3F2_LINK_STATUS2 0x8000022 ++#define ixD3F2_SLOT_CAP2 0x8000023 ++#define ixD3F2_SLOT_CNTL2 0x8000024 ++#define ixD3F2_SLOT_STATUS2 0x8000024 ++#define ixD3F2_MSI_CAP_LIST 0x8000028 ++#define ixD3F2_MSI_MSG_CNTL 0x8000028 ++#define ixD3F2_MSI_MSG_ADDR_LO 0x8000029 ++#define ixD3F2_MSI_MSG_ADDR_HI 0x800002a ++#define ixD3F2_MSI_MSG_DATA_64 0x800002b ++#define ixD3F2_MSI_MSG_DATA 0x800002a ++#define ixD3F2_SSID_CAP_LIST 0x8000030 ++#define ixD3F2_SSID_CAP 0x8000031 ++#define ixD3F2_MSI_MAP_CAP_LIST 0x8000032 ++#define ixD3F2_MSI_MAP_CAP 0x8000032 ++#define ixD3F2_MSI_MAP_ADDR_LO 0x8000033 ++#define ixD3F2_MSI_MAP_ADDR_HI 0x8000034 ++#define ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x8000040 ++#define ixD3F2_PCIE_VENDOR_SPECIFIC_HDR 0x8000041 ++#define ixD3F2_PCIE_VENDOR_SPECIFIC1 0x8000042 ++#define ixD3F2_PCIE_VENDOR_SPECIFIC2 0x8000043 ++#define ixD3F2_PCIE_VC_ENH_CAP_LIST 0x8000044 ++#define ixD3F2_PCIE_PORT_VC_CAP_REG1 0x8000045 ++#define ixD3F2_PCIE_PORT_VC_CAP_REG2 0x8000046 ++#define ixD3F2_PCIE_PORT_VC_CNTL 0x8000047 ++#define ixD3F2_PCIE_PORT_VC_STATUS 0x8000047 ++#define ixD3F2_PCIE_VC0_RESOURCE_CAP 0x8000048 ++#define ixD3F2_PCIE_VC0_RESOURCE_CNTL 0x8000049 ++#define ixD3F2_PCIE_VC0_RESOURCE_STATUS 0x800004a ++#define ixD3F2_PCIE_VC1_RESOURCE_CAP 0x800004b ++#define ixD3F2_PCIE_VC1_RESOURCE_CNTL 0x800004c ++#define ixD3F2_PCIE_VC1_RESOURCE_STATUS 0x800004d ++#define ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x8000050 ++#define ixD3F2_PCIE_DEV_SERIAL_NUM_DW1 0x8000051 ++#define ixD3F2_PCIE_DEV_SERIAL_NUM_DW2 0x8000052 ++#define ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x8000054 ++#define ixD3F2_PCIE_UNCORR_ERR_STATUS 0x8000055 ++#define ixD3F2_PCIE_UNCORR_ERR_MASK 0x8000056 ++#define ixD3F2_PCIE_UNCORR_ERR_SEVERITY 0x8000057 ++#define ixD3F2_PCIE_CORR_ERR_STATUS 0x8000058 ++#define ixD3F2_PCIE_CORR_ERR_MASK 0x8000059 ++#define ixD3F2_PCIE_ADV_ERR_CAP_CNTL 0x800005a ++#define ixD3F2_PCIE_HDR_LOG0 0x800005b ++#define ixD3F2_PCIE_HDR_LOG1 0x800005c ++#define ixD3F2_PCIE_HDR_LOG2 0x800005d ++#define ixD3F2_PCIE_HDR_LOG3 0x800005e ++#define ixD3F2_PCIE_ROOT_ERR_CMD 0x800005f ++#define ixD3F2_PCIE_ROOT_ERR_STATUS 0x8000060 ++#define ixD3F2_PCIE_ERR_SRC_ID 0x8000061 ++#define ixD3F2_PCIE_TLP_PREFIX_LOG0 0x8000062 ++#define ixD3F2_PCIE_TLP_PREFIX_LOG1 0x8000063 ++#define ixD3F2_PCIE_TLP_PREFIX_LOG2 0x8000064 ++#define ixD3F2_PCIE_TLP_PREFIX_LOG3 0x8000065 ++#define ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST 0x800009c ++#define ixD3F2_PCIE_LINK_CNTL3 0x800009d ++#define ixD3F2_PCIE_LANE_ERROR_STATUS 0x800009e ++#define ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL 0x800009f ++#define ixD3F2_PCIE_LANE_1_EQUALIZATION_CNTL 0x800009f ++#define ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL 0x80000a0 ++#define ixD3F2_PCIE_LANE_3_EQUALIZATION_CNTL 0x80000a0 ++#define ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL 0x80000a1 ++#define ixD3F2_PCIE_LANE_5_EQUALIZATION_CNTL 0x80000a1 ++#define ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL 0x80000a2 ++#define ixD3F2_PCIE_LANE_7_EQUALIZATION_CNTL 0x80000a2 ++#define ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL 0x80000a3 ++#define ixD3F2_PCIE_LANE_9_EQUALIZATION_CNTL 0x80000a3 ++#define ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL 0x80000a4 ++#define ixD3F2_PCIE_LANE_11_EQUALIZATION_CNTL 0x80000a4 ++#define ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL 0x80000a5 ++#define ixD3F2_PCIE_LANE_13_EQUALIZATION_CNTL 0x80000a5 ++#define ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL 0x80000a6 ++#define ixD3F2_PCIE_LANE_15_EQUALIZATION_CNTL 0x80000a6 ++#define ixD3F2_PCIE_ACS_ENH_CAP_LIST 0x80000a8 ++#define ixD3F2_PCIE_ACS_CAP 0x80000a9 ++#define ixD3F2_PCIE_ACS_CNTL 0x80000a9 ++#define ixD3F2_PCIE_MC_ENH_CAP_LIST 0x80000bc ++#define ixD3F2_PCIE_MC_CAP 0x80000bd ++#define ixD3F2_PCIE_MC_CNTL 0x80000bd ++#define ixD3F2_PCIE_MC_ADDR0 0x80000be ++#define ixD3F2_PCIE_MC_ADDR1 0x80000bf ++#define ixD3F2_PCIE_MC_RCV0 0x80000c0 ++#define ixD3F2_PCIE_MC_RCV1 0x80000c1 ++#define ixD3F2_PCIE_MC_BLOCK_ALL0 0x80000c2 ++#define ixD3F2_PCIE_MC_BLOCK_ALL1 0x80000c3 ++#define ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x80000c4 ++#define ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x80000c5 ++#define ixD3F2_PCIE_MC_OVERLAY_BAR0 0x80000c6 ++#define ixD3F2_PCIE_MC_OVERLAY_BAR1 0x80000c7 ++#define ixD3F3_PCIE_PORT_INDEX 0x9000038 ++#define ixD3F3_PCIE_PORT_DATA 0x9000039 ++#define ixD3F3_PCIEP_RESERVED 0x0 ++#define ixD3F3_PCIEP_SCRATCH 0x1 ++#define ixD3F3_PCIEP_HW_DEBUG 0x2 ++#define ixD3F3_PCIEP_PORT_CNTL 0x10 ++#define ixD3F3_PCIE_TX_CNTL 0x20 ++#define ixD3F3_PCIE_TX_REQUESTER_ID 0x21 ++#define ixD3F3_PCIE_TX_VENDOR_SPECIFIC 0x22 ++#define ixD3F3_PCIE_TX_REQUEST_NUM_CNTL 0x23 ++#define ixD3F3_PCIE_TX_SEQ 0x24 ++#define ixD3F3_PCIE_TX_REPLAY 0x25 ++#define ixD3F3_PCIE_TX_ACK_LATENCY_LIMIT 0x26 ++#define ixD3F3_PCIE_TX_CREDITS_ADVT_P 0x30 ++#define ixD3F3_PCIE_TX_CREDITS_ADVT_NP 0x31 ++#define ixD3F3_PCIE_TX_CREDITS_ADVT_CPL 0x32 ++#define ixD3F3_PCIE_TX_CREDITS_INIT_P 0x33 ++#define ixD3F3_PCIE_TX_CREDITS_INIT_NP 0x34 ++#define ixD3F3_PCIE_TX_CREDITS_INIT_CPL 0x35 ++#define ixD3F3_PCIE_TX_CREDITS_STATUS 0x36 ++#define ixD3F3_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 ++#define ixD3F3_PCIE_P_PORT_LANE_STATUS 0x50 ++#define ixD3F3_PCIE_FC_P 0x60 ++#define ixD3F3_PCIE_FC_NP 0x61 ++#define ixD3F3_PCIE_FC_CPL 0x62 ++#define ixD3F3_PCIE_ERR_CNTL 0x6a ++#define ixD3F3_PCIE_RX_CNTL 0x70 ++#define ixD3F3_PCIE_RX_EXPECTED_SEQNUM 0x71 ++#define ixD3F3_PCIE_RX_VENDOR_SPECIFIC 0x72 ++#define ixD3F3_PCIE_RX_CNTL3 0x74 ++#define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_P 0x80 ++#define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 ++#define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 ++#define ixD3F3_PCIEP_ERROR_INJECT_PHYSICAL 0x83 ++#define ixD3F3_PCIEP_ERROR_INJECT_TRANSACTION 0x84 ++#define ixD3F3_PCIE_LC_CNTL 0xa0 ++#define ixD3F3_PCIE_LC_CNTL2 0xb1 ++#define ixD3F3_PCIE_LC_CNTL3 0xb5 ++#define ixD3F3_PCIE_LC_CNTL4 0xb6 ++#define ixD3F3_PCIE_LC_CNTL5 0xb7 ++#define ixD3F3_PCIE_LC_CNTL6 0xbb ++#define ixD3F3_PCIE_LC_BW_CHANGE_CNTL 0xb2 ++#define ixD3F3_PCIE_LC_TRAINING_CNTL 0xa1 ++#define ixD3F3_PCIE_LC_LINK_WIDTH_CNTL 0xa2 ++#define ixD3F3_PCIE_LC_N_FTS_CNTL 0xa3 ++#define ixD3F3_PCIE_LC_SPEED_CNTL 0xa4 ++#define ixD3F3_PCIE_LC_CDR_CNTL 0xb3 ++#define ixD3F3_PCIE_LC_LANE_CNTL 0xb4 ++#define ixD3F3_PCIE_LC_FORCE_COEFF 0xb8 ++#define ixD3F3_PCIE_LC_BEST_EQ_SETTINGS 0xb9 ++#define ixD3F3_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba ++#define ixD3F3_PCIE_LC_STATE0 0xa5 ++#define ixD3F3_PCIE_LC_STATE1 0xa6 ++#define ixD3F3_PCIE_LC_STATE2 0xa7 ++#define ixD3F3_PCIE_LC_STATE3 0xa8 ++#define ixD3F3_PCIE_LC_STATE4 0xa9 ++#define ixD3F3_PCIE_LC_STATE5 0xaa ++#define ixD3F3_PCIEP_STRAP_LC 0xc0 ++#define ixD3F3_PCIEP_STRAP_MISC 0xc1 ++#define ixD3F3_PCIEP_BCH_ECC_CNTL 0xd0 ++#define ixD3F3_PCIEP_HPGI_PRIVATE 0xd2 ++#define ixD3F3_PCIEP_HPGI 0xda ++#define ixD3F3_VENDOR_ID 0x9000000 ++#define ixD3F3_DEVICE_ID 0x9000000 ++#define ixD3F3_COMMAND 0x9000001 ++#define ixD3F3_STATUS 0x9000001 ++#define ixD3F3_REVISION_ID 0x9000002 ++#define ixD3F3_PROG_INTERFACE 0x9000002 ++#define ixD3F3_SUB_CLASS 0x9000002 ++#define ixD3F3_BASE_CLASS 0x9000002 ++#define ixD3F3_CACHE_LINE 0x9000003 ++#define ixD3F3_LATENCY 0x9000003 ++#define ixD3F3_HEADER 0x9000003 ++#define ixD3F3_BIST 0x9000003 ++#define ixD3F3_SUB_BUS_NUMBER_LATENCY 0x9000006 ++#define ixD3F3_IO_BASE_LIMIT 0x9000007 ++#define ixD3F3_SECONDARY_STATUS 0x9000007 ++#define ixD3F3_MEM_BASE_LIMIT 0x9000008 ++#define ixD3F3_PREF_BASE_LIMIT 0x9000009 ++#define ixD3F3_PREF_BASE_UPPER 0x900000a ++#define ixD3F3_PREF_LIMIT_UPPER 0x900000b ++#define ixD3F3_IO_BASE_LIMIT_HI 0x900000c ++#define ixD3F3_IRQ_BRIDGE_CNTL 0x900000f ++#define ixD3F3_CAP_PTR 0x900000d ++#define ixD3F3_INTERRUPT_LINE 0x900000f ++#define ixD3F3_INTERRUPT_PIN 0x900000f ++#define ixD3F3_EXT_BRIDGE_CNTL 0x9000010 ++#define ixD3F3_PMI_CAP_LIST 0x9000014 ++#define ixD3F3_PMI_CAP 0x9000014 ++#define ixD3F3_PMI_STATUS_CNTL 0x9000015 ++#define ixD3F3_PCIE_CAP_LIST 0x9000016 ++#define ixD3F3_PCIE_CAP 0x9000016 ++#define ixD3F3_DEVICE_CAP 0x9000017 ++#define ixD3F3_DEVICE_CNTL 0x9000018 ++#define ixD3F3_DEVICE_STATUS 0x9000018 ++#define ixD3F3_LINK_CAP 0x9000019 ++#define ixD3F3_LINK_CNTL 0x900001a ++#define ixD3F3_LINK_STATUS 0x900001a ++#define ixD3F3_SLOT_CAP 0x900001b ++#define ixD3F3_SLOT_CNTL 0x900001c ++#define ixD3F3_SLOT_STATUS 0x900001c ++#define ixD3F3_ROOT_CNTL 0x900001d ++#define ixD3F3_ROOT_CAP 0x900001d ++#define ixD3F3_ROOT_STATUS 0x900001e ++#define ixD3F3_DEVICE_CAP2 0x900001f ++#define ixD3F3_DEVICE_CNTL2 0x9000020 ++#define ixD3F3_DEVICE_STATUS2 0x9000020 ++#define ixD3F3_LINK_CAP2 0x9000021 ++#define ixD3F3_LINK_CNTL2 0x9000022 ++#define ixD3F3_LINK_STATUS2 0x9000022 ++#define ixD3F3_SLOT_CAP2 0x9000023 ++#define ixD3F3_SLOT_CNTL2 0x9000024 ++#define ixD3F3_SLOT_STATUS2 0x9000024 ++#define ixD3F3_MSI_CAP_LIST 0x9000028 ++#define ixD3F3_MSI_MSG_CNTL 0x9000028 ++#define ixD3F3_MSI_MSG_ADDR_LO 0x9000029 ++#define ixD3F3_MSI_MSG_ADDR_HI 0x900002a ++#define ixD3F3_MSI_MSG_DATA_64 0x900002b ++#define ixD3F3_MSI_MSG_DATA 0x900002a ++#define ixD3F3_SSID_CAP_LIST 0x9000030 ++#define ixD3F3_SSID_CAP 0x9000031 ++#define ixD3F3_MSI_MAP_CAP_LIST 0x9000032 ++#define ixD3F3_MSI_MAP_CAP 0x9000032 ++#define ixD3F3_MSI_MAP_ADDR_LO 0x9000033 ++#define ixD3F3_MSI_MAP_ADDR_HI 0x9000034 ++#define ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x9000040 ++#define ixD3F3_PCIE_VENDOR_SPECIFIC_HDR 0x9000041 ++#define ixD3F3_PCIE_VENDOR_SPECIFIC1 0x9000042 ++#define ixD3F3_PCIE_VENDOR_SPECIFIC2 0x9000043 ++#define ixD3F3_PCIE_VC_ENH_CAP_LIST 0x9000044 ++#define ixD3F3_PCIE_PORT_VC_CAP_REG1 0x9000045 ++#define ixD3F3_PCIE_PORT_VC_CAP_REG2 0x9000046 ++#define ixD3F3_PCIE_PORT_VC_CNTL 0x9000047 ++#define ixD3F3_PCIE_PORT_VC_STATUS 0x9000047 ++#define ixD3F3_PCIE_VC0_RESOURCE_CAP 0x9000048 ++#define ixD3F3_PCIE_VC0_RESOURCE_CNTL 0x9000049 ++#define ixD3F3_PCIE_VC0_RESOURCE_STATUS 0x900004a ++#define ixD3F3_PCIE_VC1_RESOURCE_CAP 0x900004b ++#define ixD3F3_PCIE_VC1_RESOURCE_CNTL 0x900004c ++#define ixD3F3_PCIE_VC1_RESOURCE_STATUS 0x900004d ++#define ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x9000050 ++#define ixD3F3_PCIE_DEV_SERIAL_NUM_DW1 0x9000051 ++#define ixD3F3_PCIE_DEV_SERIAL_NUM_DW2 0x9000052 ++#define ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x9000054 ++#define ixD3F3_PCIE_UNCORR_ERR_STATUS 0x9000055 ++#define ixD3F3_PCIE_UNCORR_ERR_MASK 0x9000056 ++#define ixD3F3_PCIE_UNCORR_ERR_SEVERITY 0x9000057 ++#define ixD3F3_PCIE_CORR_ERR_STATUS 0x9000058 ++#define ixD3F3_PCIE_CORR_ERR_MASK 0x9000059 ++#define ixD3F3_PCIE_ADV_ERR_CAP_CNTL 0x900005a ++#define ixD3F3_PCIE_HDR_LOG0 0x900005b ++#define ixD3F3_PCIE_HDR_LOG1 0x900005c ++#define ixD3F3_PCIE_HDR_LOG2 0x900005d ++#define ixD3F3_PCIE_HDR_LOG3 0x900005e ++#define ixD3F3_PCIE_ROOT_ERR_CMD 0x900005f ++#define ixD3F3_PCIE_ROOT_ERR_STATUS 0x9000060 ++#define ixD3F3_PCIE_ERR_SRC_ID 0x9000061 ++#define ixD3F3_PCIE_TLP_PREFIX_LOG0 0x9000062 ++#define ixD3F3_PCIE_TLP_PREFIX_LOG1 0x9000063 ++#define ixD3F3_PCIE_TLP_PREFIX_LOG2 0x9000064 ++#define ixD3F3_PCIE_TLP_PREFIX_LOG3 0x9000065 ++#define ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST 0x900009c ++#define ixD3F3_PCIE_LINK_CNTL3 0x900009d ++#define ixD3F3_PCIE_LANE_ERROR_STATUS 0x900009e ++#define ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL 0x900009f ++#define ixD3F3_PCIE_LANE_1_EQUALIZATION_CNTL 0x900009f ++#define ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL 0x90000a0 ++#define ixD3F3_PCIE_LANE_3_EQUALIZATION_CNTL 0x90000a0 ++#define ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL 0x90000a1 ++#define ixD3F3_PCIE_LANE_5_EQUALIZATION_CNTL 0x90000a1 ++#define ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL 0x90000a2 ++#define ixD3F3_PCIE_LANE_7_EQUALIZATION_CNTL 0x90000a2 ++#define ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL 0x90000a3 ++#define ixD3F3_PCIE_LANE_9_EQUALIZATION_CNTL 0x90000a3 ++#define ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL 0x90000a4 ++#define ixD3F3_PCIE_LANE_11_EQUALIZATION_CNTL 0x90000a4 ++#define ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL 0x90000a5 ++#define ixD3F3_PCIE_LANE_13_EQUALIZATION_CNTL 0x90000a5 ++#define ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL 0x90000a6 ++#define ixD3F3_PCIE_LANE_15_EQUALIZATION_CNTL 0x90000a6 ++#define ixD3F3_PCIE_ACS_ENH_CAP_LIST 0x90000a8 ++#define ixD3F3_PCIE_ACS_CAP 0x90000a9 ++#define ixD3F3_PCIE_ACS_CNTL 0x90000a9 ++#define ixD3F3_PCIE_MC_ENH_CAP_LIST 0x90000bc ++#define ixD3F3_PCIE_MC_CAP 0x90000bd ++#define ixD3F3_PCIE_MC_CNTL 0x90000bd ++#define ixD3F3_PCIE_MC_ADDR0 0x90000be ++#define ixD3F3_PCIE_MC_ADDR1 0x90000bf ++#define ixD3F3_PCIE_MC_RCV0 0x90000c0 ++#define ixD3F3_PCIE_MC_RCV1 0x90000c1 ++#define ixD3F3_PCIE_MC_BLOCK_ALL0 0x90000c2 ++#define ixD3F3_PCIE_MC_BLOCK_ALL1 0x90000c3 ++#define ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0 0x90000c4 ++#define ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1 0x90000c5 ++#define ixD3F3_PCIE_MC_OVERLAY_BAR0 0x90000c6 ++#define ixD3F3_PCIE_MC_OVERLAY_BAR1 0x90000c7 ++#define ixD3F4_PCIE_PORT_INDEX 0xa000038 ++#define ixD3F4_PCIE_PORT_DATA 0xa000039 ++#define ixD3F4_PCIEP_RESERVED 0x0 ++#define ixD3F4_PCIEP_SCRATCH 0x1 ++#define ixD3F4_PCIEP_HW_DEBUG 0x2 ++#define ixD3F4_PCIEP_PORT_CNTL 0x10 ++#define ixD3F4_PCIE_TX_CNTL 0x20 ++#define ixD3F4_PCIE_TX_REQUESTER_ID 0x21 ++#define ixD3F4_PCIE_TX_VENDOR_SPECIFIC 0x22 ++#define ixD3F4_PCIE_TX_REQUEST_NUM_CNTL 0x23 ++#define ixD3F4_PCIE_TX_SEQ 0x24 ++#define ixD3F4_PCIE_TX_REPLAY 0x25 ++#define ixD3F4_PCIE_TX_ACK_LATENCY_LIMIT 0x26 ++#define ixD3F4_PCIE_TX_CREDITS_ADVT_P 0x30 ++#define ixD3F4_PCIE_TX_CREDITS_ADVT_NP 0x31 ++#define ixD3F4_PCIE_TX_CREDITS_ADVT_CPL 0x32 ++#define ixD3F4_PCIE_TX_CREDITS_INIT_P 0x33 ++#define ixD3F4_PCIE_TX_CREDITS_INIT_NP 0x34 ++#define ixD3F4_PCIE_TX_CREDITS_INIT_CPL 0x35 ++#define ixD3F4_PCIE_TX_CREDITS_STATUS 0x36 ++#define ixD3F4_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 ++#define ixD3F4_PCIE_P_PORT_LANE_STATUS 0x50 ++#define ixD3F4_PCIE_FC_P 0x60 ++#define ixD3F4_PCIE_FC_NP 0x61 ++#define ixD3F4_PCIE_FC_CPL 0x62 ++#define ixD3F4_PCIE_ERR_CNTL 0x6a ++#define ixD3F4_PCIE_RX_CNTL 0x70 ++#define ixD3F4_PCIE_RX_EXPECTED_SEQNUM 0x71 ++#define ixD3F4_PCIE_RX_VENDOR_SPECIFIC 0x72 ++#define ixD3F4_PCIE_RX_CNTL3 0x74 ++#define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_P 0x80 ++#define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 ++#define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 ++#define ixD3F4_PCIEP_ERROR_INJECT_PHYSICAL 0x83 ++#define ixD3F4_PCIEP_ERROR_INJECT_TRANSACTION 0x84 ++#define ixD3F4_PCIE_LC_CNTL 0xa0 ++#define ixD3F4_PCIE_LC_CNTL2 0xb1 ++#define ixD3F4_PCIE_LC_CNTL3 0xb5 ++#define ixD3F4_PCIE_LC_CNTL4 0xb6 ++#define ixD3F4_PCIE_LC_CNTL5 0xb7 ++#define ixD3F4_PCIE_LC_CNTL6 0xbb ++#define ixD3F4_PCIE_LC_BW_CHANGE_CNTL 0xb2 ++#define ixD3F4_PCIE_LC_TRAINING_CNTL 0xa1 ++#define ixD3F4_PCIE_LC_LINK_WIDTH_CNTL 0xa2 ++#define ixD3F4_PCIE_LC_N_FTS_CNTL 0xa3 ++#define ixD3F4_PCIE_LC_SPEED_CNTL 0xa4 ++#define ixD3F4_PCIE_LC_CDR_CNTL 0xb3 ++#define ixD3F4_PCIE_LC_LANE_CNTL 0xb4 ++#define ixD3F4_PCIE_LC_FORCE_COEFF 0xb8 ++#define ixD3F4_PCIE_LC_BEST_EQ_SETTINGS 0xb9 ++#define ixD3F4_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba ++#define ixD3F4_PCIE_LC_STATE0 0xa5 ++#define ixD3F4_PCIE_LC_STATE1 0xa6 ++#define ixD3F4_PCIE_LC_STATE2 0xa7 ++#define ixD3F4_PCIE_LC_STATE3 0xa8 ++#define ixD3F4_PCIE_LC_STATE4 0xa9 ++#define ixD3F4_PCIE_LC_STATE5 0xaa ++#define ixD3F4_PCIEP_STRAP_LC 0xc0 ++#define ixD3F4_PCIEP_STRAP_MISC 0xc1 ++#define ixD3F4_PCIEP_BCH_ECC_CNTL 0xd0 ++#define ixD3F4_PCIEP_HPGI_PRIVATE 0xd2 ++#define ixD3F4_PCIEP_HPGI 0xda ++#define ixD3F4_VENDOR_ID 0xa000000 ++#define ixD3F4_DEVICE_ID 0xa000000 ++#define ixD3F4_COMMAND 0xa000001 ++#define ixD3F4_STATUS 0xa000001 ++#define ixD3F4_REVISION_ID 0xa000002 ++#define ixD3F4_PROG_INTERFACE 0xa000002 ++#define ixD3F4_SUB_CLASS 0xa000002 ++#define ixD3F4_BASE_CLASS 0xa000002 ++#define ixD3F4_CACHE_LINE 0xa000003 ++#define ixD3F4_LATENCY 0xa000003 ++#define ixD3F4_HEADER 0xa000003 ++#define ixD3F4_BIST 0xa000003 ++#define ixD3F4_SUB_BUS_NUMBER_LATENCY 0xa000006 ++#define ixD3F4_IO_BASE_LIMIT 0xa000007 ++#define ixD3F4_SECONDARY_STATUS 0xa000007 ++#define ixD3F4_MEM_BASE_LIMIT 0xa000008 ++#define ixD3F4_PREF_BASE_LIMIT 0xa000009 ++#define ixD3F4_PREF_BASE_UPPER 0xa00000a ++#define ixD3F4_PREF_LIMIT_UPPER 0xa00000b ++#define ixD3F4_IO_BASE_LIMIT_HI 0xa00000c ++#define ixD3F4_IRQ_BRIDGE_CNTL 0xa00000f ++#define ixD3F4_CAP_PTR 0xa00000d ++#define ixD3F4_INTERRUPT_LINE 0xa00000f ++#define ixD3F4_INTERRUPT_PIN 0xa00000f ++#define ixD3F4_EXT_BRIDGE_CNTL 0xa000010 ++#define ixD3F4_PMI_CAP_LIST 0xa000014 ++#define ixD3F4_PMI_CAP 0xa000014 ++#define ixD3F4_PMI_STATUS_CNTL 0xa000015 ++#define ixD3F4_PCIE_CAP_LIST 0xa000016 ++#define ixD3F4_PCIE_CAP 0xa000016 ++#define ixD3F4_DEVICE_CAP 0xa000017 ++#define ixD3F4_DEVICE_CNTL 0xa000018 ++#define ixD3F4_DEVICE_STATUS 0xa000018 ++#define ixD3F4_LINK_CAP 0xa000019 ++#define ixD3F4_LINK_CNTL 0xa00001a ++#define ixD3F4_LINK_STATUS 0xa00001a ++#define ixD3F4_SLOT_CAP 0xa00001b ++#define ixD3F4_SLOT_CNTL 0xa00001c ++#define ixD3F4_SLOT_STATUS 0xa00001c ++#define ixD3F4_ROOT_CNTL 0xa00001d ++#define ixD3F4_ROOT_CAP 0xa00001d ++#define ixD3F4_ROOT_STATUS 0xa00001e ++#define ixD3F4_DEVICE_CAP2 0xa00001f ++#define ixD3F4_DEVICE_CNTL2 0xa000020 ++#define ixD3F4_DEVICE_STATUS2 0xa000020 ++#define ixD3F4_LINK_CAP2 0xa000021 ++#define ixD3F4_LINK_CNTL2 0xa000022 ++#define ixD3F4_LINK_STATUS2 0xa000022 ++#define ixD3F4_SLOT_CAP2 0xa000023 ++#define ixD3F4_SLOT_CNTL2 0xa000024 ++#define ixD3F4_SLOT_STATUS2 0xa000024 ++#define ixD3F4_MSI_CAP_LIST 0xa000028 ++#define ixD3F4_MSI_MSG_CNTL 0xa000028 ++#define ixD3F4_MSI_MSG_ADDR_LO 0xa000029 ++#define ixD3F4_MSI_MSG_ADDR_HI 0xa00002a ++#define ixD3F4_MSI_MSG_DATA_64 0xa00002b ++#define ixD3F4_MSI_MSG_DATA 0xa00002a ++#define ixD3F4_SSID_CAP_LIST 0xa000030 ++#define ixD3F4_SSID_CAP 0xa000031 ++#define ixD3F4_MSI_MAP_CAP_LIST 0xa000032 ++#define ixD3F4_MSI_MAP_CAP 0xa000032 ++#define ixD3F4_MSI_MAP_ADDR_LO 0xa000033 ++#define ixD3F4_MSI_MAP_ADDR_HI 0xa000034 ++#define ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xa000040 ++#define ixD3F4_PCIE_VENDOR_SPECIFIC_HDR 0xa000041 ++#define ixD3F4_PCIE_VENDOR_SPECIFIC1 0xa000042 ++#define ixD3F4_PCIE_VENDOR_SPECIFIC2 0xa000043 ++#define ixD3F4_PCIE_VC_ENH_CAP_LIST 0xa000044 ++#define ixD3F4_PCIE_PORT_VC_CAP_REG1 0xa000045 ++#define ixD3F4_PCIE_PORT_VC_CAP_REG2 0xa000046 ++#define ixD3F4_PCIE_PORT_VC_CNTL 0xa000047 ++#define ixD3F4_PCIE_PORT_VC_STATUS 0xa000047 ++#define ixD3F4_PCIE_VC0_RESOURCE_CAP 0xa000048 ++#define ixD3F4_PCIE_VC0_RESOURCE_CNTL 0xa000049 ++#define ixD3F4_PCIE_VC0_RESOURCE_STATUS 0xa00004a ++#define ixD3F4_PCIE_VC1_RESOURCE_CAP 0xa00004b ++#define ixD3F4_PCIE_VC1_RESOURCE_CNTL 0xa00004c ++#define ixD3F4_PCIE_VC1_RESOURCE_STATUS 0xa00004d ++#define ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xa000050 ++#define ixD3F4_PCIE_DEV_SERIAL_NUM_DW1 0xa000051 ++#define ixD3F4_PCIE_DEV_SERIAL_NUM_DW2 0xa000052 ++#define ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xa000054 ++#define ixD3F4_PCIE_UNCORR_ERR_STATUS 0xa000055 ++#define ixD3F4_PCIE_UNCORR_ERR_MASK 0xa000056 ++#define ixD3F4_PCIE_UNCORR_ERR_SEVERITY 0xa000057 ++#define ixD3F4_PCIE_CORR_ERR_STATUS 0xa000058 ++#define ixD3F4_PCIE_CORR_ERR_MASK 0xa000059 ++#define ixD3F4_PCIE_ADV_ERR_CAP_CNTL 0xa00005a ++#define ixD3F4_PCIE_HDR_LOG0 0xa00005b ++#define ixD3F4_PCIE_HDR_LOG1 0xa00005c ++#define ixD3F4_PCIE_HDR_LOG2 0xa00005d ++#define ixD3F4_PCIE_HDR_LOG3 0xa00005e ++#define ixD3F4_PCIE_ROOT_ERR_CMD 0xa00005f ++#define ixD3F4_PCIE_ROOT_ERR_STATUS 0xa000060 ++#define ixD3F4_PCIE_ERR_SRC_ID 0xa000061 ++#define ixD3F4_PCIE_TLP_PREFIX_LOG0 0xa000062 ++#define ixD3F4_PCIE_TLP_PREFIX_LOG1 0xa000063 ++#define ixD3F4_PCIE_TLP_PREFIX_LOG2 0xa000064 ++#define ixD3F4_PCIE_TLP_PREFIX_LOG3 0xa000065 ++#define ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST 0xa00009c ++#define ixD3F4_PCIE_LINK_CNTL3 0xa00009d ++#define ixD3F4_PCIE_LANE_ERROR_STATUS 0xa00009e ++#define ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL 0xa00009f ++#define ixD3F4_PCIE_LANE_1_EQUALIZATION_CNTL 0xa00009f ++#define ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL 0xa0000a0 ++#define ixD3F4_PCIE_LANE_3_EQUALIZATION_CNTL 0xa0000a0 ++#define ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL 0xa0000a1 ++#define ixD3F4_PCIE_LANE_5_EQUALIZATION_CNTL 0xa0000a1 ++#define ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL 0xa0000a2 ++#define ixD3F4_PCIE_LANE_7_EQUALIZATION_CNTL 0xa0000a2 ++#define ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL 0xa0000a3 ++#define ixD3F4_PCIE_LANE_9_EQUALIZATION_CNTL 0xa0000a3 ++#define ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL 0xa0000a4 ++#define ixD3F4_PCIE_LANE_11_EQUALIZATION_CNTL 0xa0000a4 ++#define ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL 0xa0000a5 ++#define ixD3F4_PCIE_LANE_13_EQUALIZATION_CNTL 0xa0000a5 ++#define ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL 0xa0000a6 ++#define ixD3F4_PCIE_LANE_15_EQUALIZATION_CNTL 0xa0000a6 ++#define ixD3F4_PCIE_ACS_ENH_CAP_LIST 0xa0000a8 ++#define ixD3F4_PCIE_ACS_CAP 0xa0000a9 ++#define ixD3F4_PCIE_ACS_CNTL 0xa0000a9 ++#define ixD3F4_PCIE_MC_ENH_CAP_LIST 0xa0000bc ++#define ixD3F4_PCIE_MC_CAP 0xa0000bd ++#define ixD3F4_PCIE_MC_CNTL 0xa0000bd ++#define ixD3F4_PCIE_MC_ADDR0 0xa0000be ++#define ixD3F4_PCIE_MC_ADDR1 0xa0000bf ++#define ixD3F4_PCIE_MC_RCV0 0xa0000c0 ++#define ixD3F4_PCIE_MC_RCV1 0xa0000c1 ++#define ixD3F4_PCIE_MC_BLOCK_ALL0 0xa0000c2 ++#define ixD3F4_PCIE_MC_BLOCK_ALL1 0xa0000c3 ++#define ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0 0xa0000c4 ++#define ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1 0xa0000c5 ++#define ixD3F4_PCIE_MC_OVERLAY_BAR0 0xa0000c6 ++#define ixD3F4_PCIE_MC_OVERLAY_BAR1 0xa0000c7 ++#define ixD3F5_PCIE_PORT_INDEX 0xb000038 ++#define ixD3F5_PCIE_PORT_DATA 0xb000039 ++#define ixD3F5_PCIEP_RESERVED 0x0 ++#define ixD3F5_PCIEP_SCRATCH 0x1 ++#define ixD3F5_PCIEP_HW_DEBUG 0x2 ++#define ixD3F5_PCIEP_PORT_CNTL 0x10 ++#define ixD3F5_PCIE_TX_CNTL 0x20 ++#define ixD3F5_PCIE_TX_REQUESTER_ID 0x21 ++#define ixD3F5_PCIE_TX_VENDOR_SPECIFIC 0x22 ++#define ixD3F5_PCIE_TX_REQUEST_NUM_CNTL 0x23 ++#define ixD3F5_PCIE_TX_SEQ 0x24 ++#define ixD3F5_PCIE_TX_REPLAY 0x25 ++#define ixD3F5_PCIE_TX_ACK_LATENCY_LIMIT 0x26 ++#define ixD3F5_PCIE_TX_CREDITS_ADVT_P 0x30 ++#define ixD3F5_PCIE_TX_CREDITS_ADVT_NP 0x31 ++#define ixD3F5_PCIE_TX_CREDITS_ADVT_CPL 0x32 ++#define ixD3F5_PCIE_TX_CREDITS_INIT_P 0x33 ++#define ixD3F5_PCIE_TX_CREDITS_INIT_NP 0x34 ++#define ixD3F5_PCIE_TX_CREDITS_INIT_CPL 0x35 ++#define ixD3F5_PCIE_TX_CREDITS_STATUS 0x36 ++#define ixD3F5_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 ++#define ixD3F5_PCIE_P_PORT_LANE_STATUS 0x50 ++#define ixD3F5_PCIE_FC_P 0x60 ++#define ixD3F5_PCIE_FC_NP 0x61 ++#define ixD3F5_PCIE_FC_CPL 0x62 ++#define ixD3F5_PCIE_ERR_CNTL 0x6a ++#define ixD3F5_PCIE_RX_CNTL 0x70 ++#define ixD3F5_PCIE_RX_EXPECTED_SEQNUM 0x71 ++#define ixD3F5_PCIE_RX_VENDOR_SPECIFIC 0x72 ++#define ixD3F5_PCIE_RX_CNTL3 0x74 ++#define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_P 0x80 ++#define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 ++#define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 ++#define ixD3F5_PCIEP_ERROR_INJECT_PHYSICAL 0x83 ++#define ixD3F5_PCIEP_ERROR_INJECT_TRANSACTION 0x84 ++#define ixD3F5_PCIE_LC_CNTL 0xa0 ++#define ixD3F5_PCIE_LC_CNTL2 0xb1 ++#define ixD3F5_PCIE_LC_CNTL3 0xb5 ++#define ixD3F5_PCIE_LC_CNTL4 0xb6 ++#define ixD3F5_PCIE_LC_CNTL5 0xb7 ++#define ixD3F5_PCIE_LC_CNTL6 0xbb ++#define ixD3F5_PCIE_LC_BW_CHANGE_CNTL 0xb2 ++#define ixD3F5_PCIE_LC_TRAINING_CNTL 0xa1 ++#define ixD3F5_PCIE_LC_LINK_WIDTH_CNTL 0xa2 ++#define ixD3F5_PCIE_LC_N_FTS_CNTL 0xa3 ++#define ixD3F5_PCIE_LC_SPEED_CNTL 0xa4 ++#define ixD3F5_PCIE_LC_CDR_CNTL 0xb3 ++#define ixD3F5_PCIE_LC_LANE_CNTL 0xb4 ++#define ixD3F5_PCIE_LC_FORCE_COEFF 0xb8 ++#define ixD3F5_PCIE_LC_BEST_EQ_SETTINGS 0xb9 ++#define ixD3F5_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba ++#define ixD3F5_PCIE_LC_STATE0 0xa5 ++#define ixD3F5_PCIE_LC_STATE1 0xa6 ++#define ixD3F5_PCIE_LC_STATE2 0xa7 ++#define ixD3F5_PCIE_LC_STATE3 0xa8 ++#define ixD3F5_PCIE_LC_STATE4 0xa9 ++#define ixD3F5_PCIE_LC_STATE5 0xaa ++#define ixD3F5_PCIEP_STRAP_LC 0xc0 ++#define ixD3F5_PCIEP_STRAP_MISC 0xc1 ++#define ixD3F5_PCIEP_BCH_ECC_CNTL 0xd0 ++#define ixD3F5_PCIEP_HPGI_PRIVATE 0xd2 ++#define ixD3F5_PCIEP_HPGI 0xda ++#define ixD3F5_VENDOR_ID 0xb000000 ++#define ixD3F5_DEVICE_ID 0xb000000 ++#define ixD3F5_COMMAND 0xb000001 ++#define ixD3F5_STATUS 0xb000001 ++#define ixD3F5_REVISION_ID 0xb000002 ++#define ixD3F5_PROG_INTERFACE 0xb000002 ++#define ixD3F5_SUB_CLASS 0xb000002 ++#define ixD3F5_BASE_CLASS 0xb000002 ++#define ixD3F5_CACHE_LINE 0xb000003 ++#define ixD3F5_LATENCY 0xb000003 ++#define ixD3F5_HEADER 0xb000003 ++#define ixD3F5_BIST 0xb000003 ++#define ixD3F5_SUB_BUS_NUMBER_LATENCY 0xb000006 ++#define ixD3F5_IO_BASE_LIMIT 0xb000007 ++#define ixD3F5_SECONDARY_STATUS 0xb000007 ++#define ixD3F5_MEM_BASE_LIMIT 0xb000008 ++#define ixD3F5_PREF_BASE_LIMIT 0xb000009 ++#define ixD3F5_PREF_BASE_UPPER 0xb00000a ++#define ixD3F5_PREF_LIMIT_UPPER 0xb00000b ++#define ixD3F5_IO_BASE_LIMIT_HI 0xb00000c ++#define ixD3F5_IRQ_BRIDGE_CNTL 0xb00000f ++#define ixD3F5_CAP_PTR 0xb00000d ++#define ixD3F5_INTERRUPT_LINE 0xb00000f ++#define ixD3F5_INTERRUPT_PIN 0xb00000f ++#define ixD3F5_EXT_BRIDGE_CNTL 0xb000010 ++#define ixD3F5_PMI_CAP_LIST 0xb000014 ++#define ixD3F5_PMI_CAP 0xb000014 ++#define ixD3F5_PMI_STATUS_CNTL 0xb000015 ++#define ixD3F5_PCIE_CAP_LIST 0xb000016 ++#define ixD3F5_PCIE_CAP 0xb000016 ++#define ixD3F5_DEVICE_CAP 0xb000017 ++#define ixD3F5_DEVICE_CNTL 0xb000018 ++#define ixD3F5_DEVICE_STATUS 0xb000018 ++#define ixD3F5_LINK_CAP 0xb000019 ++#define ixD3F5_LINK_CNTL 0xb00001a ++#define ixD3F5_LINK_STATUS 0xb00001a ++#define ixD3F5_SLOT_CAP 0xb00001b ++#define ixD3F5_SLOT_CNTL 0xb00001c ++#define ixD3F5_SLOT_STATUS 0xb00001c ++#define ixD3F5_ROOT_CNTL 0xb00001d ++#define ixD3F5_ROOT_CAP 0xb00001d ++#define ixD3F5_ROOT_STATUS 0xb00001e ++#define ixD3F5_DEVICE_CAP2 0xb00001f ++#define ixD3F5_DEVICE_CNTL2 0xb000020 ++#define ixD3F5_DEVICE_STATUS2 0xb000020 ++#define ixD3F5_LINK_CAP2 0xb000021 ++#define ixD3F5_LINK_CNTL2 0xb000022 ++#define ixD3F5_LINK_STATUS2 0xb000022 ++#define ixD3F5_SLOT_CAP2 0xb000023 ++#define ixD3F5_SLOT_CNTL2 0xb000024 ++#define ixD3F5_SLOT_STATUS2 0xb000024 ++#define ixD3F5_MSI_CAP_LIST 0xb000028 ++#define ixD3F5_MSI_MSG_CNTL 0xb000028 ++#define ixD3F5_MSI_MSG_ADDR_LO 0xb000029 ++#define ixD3F5_MSI_MSG_ADDR_HI 0xb00002a ++#define ixD3F5_MSI_MSG_DATA_64 0xb00002b ++#define ixD3F5_MSI_MSG_DATA 0xb00002a ++#define ixD3F5_SSID_CAP_LIST 0xb000030 ++#define ixD3F5_SSID_CAP 0xb000031 ++#define ixD3F5_MSI_MAP_CAP_LIST 0xb000032 ++#define ixD3F5_MSI_MAP_CAP 0xb000032 ++#define ixD3F5_MSI_MAP_ADDR_LO 0xb000033 ++#define ixD3F5_MSI_MAP_ADDR_HI 0xb000034 ++#define ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xb000040 ++#define ixD3F5_PCIE_VENDOR_SPECIFIC_HDR 0xb000041 ++#define ixD3F5_PCIE_VENDOR_SPECIFIC1 0xb000042 ++#define ixD3F5_PCIE_VENDOR_SPECIFIC2 0xb000043 ++#define ixD3F5_PCIE_VC_ENH_CAP_LIST 0xb000044 ++#define ixD3F5_PCIE_PORT_VC_CAP_REG1 0xb000045 ++#define ixD3F5_PCIE_PORT_VC_CAP_REG2 0xb000046 ++#define ixD3F5_PCIE_PORT_VC_CNTL 0xb000047 ++#define ixD3F5_PCIE_PORT_VC_STATUS 0xb000047 ++#define ixD3F5_PCIE_VC0_RESOURCE_CAP 0xb000048 ++#define ixD3F5_PCIE_VC0_RESOURCE_CNTL 0xb000049 ++#define ixD3F5_PCIE_VC0_RESOURCE_STATUS 0xb00004a ++#define ixD3F5_PCIE_VC1_RESOURCE_CAP 0xb00004b ++#define ixD3F5_PCIE_VC1_RESOURCE_CNTL 0xb00004c ++#define ixD3F5_PCIE_VC1_RESOURCE_STATUS 0xb00004d ++#define ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xb000050 ++#define ixD3F5_PCIE_DEV_SERIAL_NUM_DW1 0xb000051 ++#define ixD3F5_PCIE_DEV_SERIAL_NUM_DW2 0xb000052 ++#define ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xb000054 ++#define ixD3F5_PCIE_UNCORR_ERR_STATUS 0xb000055 ++#define ixD3F5_PCIE_UNCORR_ERR_MASK 0xb000056 ++#define ixD3F5_PCIE_UNCORR_ERR_SEVERITY 0xb000057 ++#define ixD3F5_PCIE_CORR_ERR_STATUS 0xb000058 ++#define ixD3F5_PCIE_CORR_ERR_MASK 0xb000059 ++#define ixD3F5_PCIE_ADV_ERR_CAP_CNTL 0xb00005a ++#define ixD3F5_PCIE_HDR_LOG0 0xb00005b ++#define ixD3F5_PCIE_HDR_LOG1 0xb00005c ++#define ixD3F5_PCIE_HDR_LOG2 0xb00005d ++#define ixD3F5_PCIE_HDR_LOG3 0xb00005e ++#define ixD3F5_PCIE_ROOT_ERR_CMD 0xb00005f ++#define ixD3F5_PCIE_ROOT_ERR_STATUS 0xb000060 ++#define ixD3F5_PCIE_ERR_SRC_ID 0xb000061 ++#define ixD3F5_PCIE_TLP_PREFIX_LOG0 0xb000062 ++#define ixD3F5_PCIE_TLP_PREFIX_LOG1 0xb000063 ++#define ixD3F5_PCIE_TLP_PREFIX_LOG2 0xb000064 ++#define ixD3F5_PCIE_TLP_PREFIX_LOG3 0xb000065 ++#define ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST 0xb00009c ++#define ixD3F5_PCIE_LINK_CNTL3 0xb00009d ++#define ixD3F5_PCIE_LANE_ERROR_STATUS 0xb00009e ++#define ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL 0xb00009f ++#define ixD3F5_PCIE_LANE_1_EQUALIZATION_CNTL 0xb00009f ++#define ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL 0xb0000a0 ++#define ixD3F5_PCIE_LANE_3_EQUALIZATION_CNTL 0xb0000a0 ++#define ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL 0xb0000a1 ++#define ixD3F5_PCIE_LANE_5_EQUALIZATION_CNTL 0xb0000a1 ++#define ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL 0xb0000a2 ++#define ixD3F5_PCIE_LANE_7_EQUALIZATION_CNTL 0xb0000a2 ++#define ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL 0xb0000a3 ++#define ixD3F5_PCIE_LANE_9_EQUALIZATION_CNTL 0xb0000a3 ++#define ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL 0xb0000a4 ++#define ixD3F5_PCIE_LANE_11_EQUALIZATION_CNTL 0xb0000a4 ++#define ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL 0xb0000a5 ++#define ixD3F5_PCIE_LANE_13_EQUALIZATION_CNTL 0xb0000a5 ++#define ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL 0xb0000a6 ++#define ixD3F5_PCIE_LANE_15_EQUALIZATION_CNTL 0xb0000a6 ++#define ixD3F5_PCIE_ACS_ENH_CAP_LIST 0xb0000a8 ++#define ixD3F5_PCIE_ACS_CAP 0xb0000a9 ++#define ixD3F5_PCIE_ACS_CNTL 0xb0000a9 ++#define ixD3F5_PCIE_MC_ENH_CAP_LIST 0xb0000bc ++#define ixD3F5_PCIE_MC_CAP 0xb0000bd ++#define ixD3F5_PCIE_MC_CNTL 0xb0000bd ++#define ixD3F5_PCIE_MC_ADDR0 0xb0000be ++#define ixD3F5_PCIE_MC_ADDR1 0xb0000bf ++#define ixD3F5_PCIE_MC_RCV0 0xb0000c0 ++#define ixD3F5_PCIE_MC_RCV1 0xb0000c1 ++#define ixD3F5_PCIE_MC_BLOCK_ALL0 0xb0000c2 ++#define ixD3F5_PCIE_MC_BLOCK_ALL1 0xb0000c3 ++#define ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0 0xb0000c4 ++#define ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1 0xb0000c5 ++#define ixD3F5_PCIE_MC_OVERLAY_BAR0 0xb0000c6 ++#define ixD3F5_PCIE_MC_OVERLAY_BAR1 0xb0000c7 ++#define mmC_PCIE_INDEX 0x28 ++#define mmPCIE_WRAPPER0_C_PCIE_INDEX 0x28 ++#define mmPCIE_WRAPPER1_C_PCIE_INDEX 0x38 ++#define mmC_PCIE_DATA 0x29 ++#define mmPCIE_WRAPPER0_C_PCIE_DATA 0x29 ++#define mmPCIE_WRAPPER1_C_PCIE_DATA 0x39 ++#define mmRFE_SNOOP_RST 0x3c ++#define ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1 0x1500000 ++#define ixPSX80_WRP_BIF_STRAP_PI_CNTL 0x1500001 ++#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE 0x1500002 ++#define ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE 0x1500003 ++#define ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE 0x1500004 ++#define ixPSX80_WRP_BIF_STRAP_TEST_DFT 0x1500005 ++#define ixPSX80_WRP_BIF_STRAP_ID 0x1500006 ++#define ixPSX80_WRP_BIF_STRAP_REV_ID 0x1500007 ++#define ixPSX80_WRP_BIF_STRAP_I2C_CNTL 0x1500008 ++#define ixPSX80_WRP_BIF_INT_CNTL 0x1500009 ++#define ixPSX80_WRP_BIF_STRAP_ACS 0x150000a ++#define ixPSX80_WRP_BIF_STRAP_PM 0x150000b ++#define ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2 0x150000c ++#define ixPSX80_WRP_BIF_SERIAL_NUM 0x1500045 ++#define ixPSX80_WRP_BIF_SSID 0x1500046 ++#define ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL 0x1500050 ++#define ixPSX80_WRP_PCIE_LINK_CONFIG 0x1500080 ++#define ixPSX80_WRP_PCIE_HOLD_TRAINING_A 0x1500800 ++#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A 0x1500801 ++#define ixPSX80_WRP_BIF_STRAP_ASPM_A 0x1500802 ++#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A 0x1500803 ++#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_A 0x1500804 ++#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A 0x1500805 ++#define ixPSX80_WRP_PCIE_PORT_IS_SB_A 0x1500813 ++#define ixPSX80_WRP_PCIE_HOLD_TRAINING_B 0x1500900 ++#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B 0x1500901 ++#define ixPSX80_WRP_BIF_STRAP_ASPM_B 0x1500902 ++#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B 0x1500903 ++#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_B 0x1500904 ++#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B 0x1500905 ++#define ixPSX80_WRP_PCIE_PORT_IS_SB_B 0x1500913 ++#define ixPSX80_WRP_PCIE_HOLD_TRAINING_C 0x1500a00 ++#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C 0x1500a01 ++#define ixPSX80_WRP_BIF_STRAP_ASPM_C 0x1500a02 ++#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C 0x1500a03 ++#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_C 0x1500a04 ++#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C 0x1500a05 ++#define ixPSX80_WRP_PCIE_PORT_IS_SB_C 0x1500a13 ++#define ixPSX80_WRP_PCIE_HOLD_TRAINING_D 0x1500b00 ++#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D 0x1500b01 ++#define ixPSX80_WRP_BIF_STRAP_ASPM_D 0x1500b02 ++#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D 0x1500b03 ++#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_D 0x1500b04 ++#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D 0x1500b05 ++#define ixPSX80_WRP_PCIE_PORT_IS_SB_D 0x1500b13 ++#define ixPSX80_WRP_PCIE_HOLD_TRAINING_E 0x1500c00 ++#define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E 0x1500c01 ++#define ixPSX80_WRP_BIF_STRAP_ASPM_E 0x1500c02 ++#define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E 0x1500c03 ++#define ixPSX80_WRP_BIF_STRAP_MISC_PORT_E 0x1500c04 ++#define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E 0x1500c05 ++#define ixPSX80_WRP_PCIE_PORT_IS_SB_E 0x1500c13 ++#define ixPSX80_WRP_LNCNT_CONTROL 0x1508030 ++#define ixPSX80_WRP_CFG_LNC_WINDOW 0x1508031 ++#define ixPSX80_WRP_LNCNT_QUAN_THRD 0x1508032 ++#define ixPSX80_WRP_LNCNT_WEIGHT 0x1508033 ++#define ixPSX80_WRP_LNC_TOTAL_WACC 0x1508034 ++#define ixPSX80_WRP_LNC_BW_WACC 0x1508035 ++#define ixPSX80_WRP_LNC_CMN_WACC 0x1508036 ++#define ixPSX80_WRP_PCIE_EFUSE 0x150fff0 ++#define ixPSX80_WRP_PCIE_EFUSE2 0x150fff1 ++#define ixPSX80_WRP_PCIE_EFUSE3 0x150fff2 ++#define ixPSX80_WRP_PCIE_EFUSE4 0x150fff3 ++#define ixPSX80_WRP_PCIE_EFUSE5 0x150fff4 ++#define ixPSX80_WRP_PCIE_EFUSE6 0x150fff5 ++#define ixPSX80_WRP_PCIE_EFUSE7 0x150fff6 ++#define ixPSX80_WRP_PCIE_WRAP_SCRATCH1 0x1308001 ++#define ixPSX80_WRP_PCIE_WRAP_SCRATCH2 0x1308002 ++#define ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC 0x1308005 ++#define ixPSX80_WRP_PCIE_WRAP_DTM_MISC 0x1308006 ++#define ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1308007 ++#define ixPSX80_WRP_PCIE_WRAP_MISC 0x1308008 ++#define ixPSX80_WRP_PCIE_WRAP_PIF_MISC 0x1308009 ++#define ixPSX80_WRP_PCIE_RXDET_OVERRIDE 0x130800a ++#define ixPSX80_WRP_IMPCTL_CNTL_PIF0 0x1308070 ++#define ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL 0x1308090 ++#define ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL 0x1308096 ++#define ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL 0x1308097 ++#define ixPSX80_WRP_REG_ADAPT_pif0_CONTROL 0x1308098 ++#define ixPSX80_WRP_BIOSTIMER_CMD 0x13080f0 ++#define ixPSX80_WRP_BIOSTIMER_CNTL 0x13080f1 ++#define ixPSX80_WRP_BIOSTIMER_DEBUG 0x13080f2 ++#define ixPSX80_WRP_DTM_RX_BP_CNTL 0x130ffe0 ++#define ixPSX80_WRP_DTM_CNTL 0x130ffe1 ++#define ixPSX80_WRP_DTM_CNTL_LEGACY 0x130ffe2 ++#define ixPSX80_WRP_DTM_STI_LCLK_CTRL 0x130ffe3 ++#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x 0x130ffe4 ++#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt 0x130ffe5 ++#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x 0x130ffe6 ++#define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt 0x130ffe7 ++#define ixPSX80_WRP_DELAYLINE_COMMAND 0x130ffd0 ++#define ixPSX80_WRP_DELAYLINE_STATUS 0x130ffd1 ++#define ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1 0x1510000 ++#define ixPSX81_WRP_BIF_STRAP_PI_CNTL 0x1510001 ++#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE 0x1510002 ++#define ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE 0x1510003 ++#define ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE 0x1510004 ++#define ixPSX81_WRP_BIF_STRAP_TEST_DFT 0x1510005 ++#define ixPSX81_WRP_BIF_STRAP_ID 0x1510006 ++#define ixPSX81_WRP_BIF_STRAP_REV_ID 0x1510007 ++#define ixPSX81_WRP_BIF_STRAP_I2C_CNTL 0x1510008 ++#define ixPSX81_WRP_BIF_INT_CNTL 0x1510009 ++#define ixPSX81_WRP_BIF_STRAP_ACS 0x151000a ++#define ixPSX81_WRP_BIF_STRAP_PM 0x151000b ++#define ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2 0x151000c ++#define ixPSX81_WRP_BIF_SERIAL_NUM 0x1510045 ++#define ixPSX81_WRP_BIF_SSID 0x1510046 ++#define ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL 0x1510050 ++#define ixPSX81_WRP_PCIE_LINK_CONFIG 0x1510080 ++#define ixPSX81_WRP_PCIE_HOLD_TRAINING_A 0x1510800 ++#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A 0x1510801 ++#define ixPSX81_WRP_BIF_STRAP_ASPM_A 0x1510802 ++#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A 0x1510803 ++#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_A 0x1510804 ++#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A 0x1510805 ++#define ixPSX81_WRP_PCIE_PORT_IS_SB_A 0x1510813 ++#define ixPSX81_WRP_PCIE_HOLD_TRAINING_B 0x1510900 ++#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B 0x1510901 ++#define ixPSX81_WRP_BIF_STRAP_ASPM_B 0x1510902 ++#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B 0x1510903 ++#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_B 0x1510904 ++#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B 0x1510905 ++#define ixPSX81_WRP_PCIE_PORT_IS_SB_B 0x1510913 ++#define ixPSX81_WRP_PCIE_HOLD_TRAINING_C 0x1510a00 ++#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C 0x1510a01 ++#define ixPSX81_WRP_BIF_STRAP_ASPM_C 0x1510a02 ++#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C 0x1510a03 ++#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_C 0x1510a04 ++#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C 0x1510a05 ++#define ixPSX81_WRP_PCIE_PORT_IS_SB_C 0x1510a13 ++#define ixPSX81_WRP_PCIE_HOLD_TRAINING_D 0x1510b00 ++#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D 0x1510b01 ++#define ixPSX81_WRP_BIF_STRAP_ASPM_D 0x1510b02 ++#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D 0x1510b03 ++#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_D 0x1510b04 ++#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D 0x1510b05 ++#define ixPSX81_WRP_PCIE_PORT_IS_SB_D 0x1510b13 ++#define ixPSX81_WRP_PCIE_HOLD_TRAINING_E 0x1510c00 ++#define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E 0x1510c01 ++#define ixPSX81_WRP_BIF_STRAP_ASPM_E 0x1510c02 ++#define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E 0x1510c03 ++#define ixPSX81_WRP_BIF_STRAP_MISC_PORT_E 0x1510c04 ++#define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E 0x1510c05 ++#define ixPSX81_WRP_PCIE_PORT_IS_SB_E 0x1510c13 ++#define ixPSX81_WRP_LNCNT_CONTROL 0x1518030 ++#define ixPSX81_WRP_CFG_LNC_WINDOW 0x1518031 ++#define ixPSX81_WRP_LNCNT_QUAN_THRD 0x1518032 ++#define ixPSX81_WRP_LNCNT_WEIGHT 0x1518033 ++#define ixPSX81_WRP_LNC_TOTAL_WACC 0x1518034 ++#define ixPSX81_WRP_LNC_BW_WACC 0x1518035 ++#define ixPSX81_WRP_LNC_CMN_WACC 0x1518036 ++#define ixPSX81_WRP_PCIE_EFUSE 0x151fff0 ++#define ixPSX81_WRP_PCIE_EFUSE2 0x151fff1 ++#define ixPSX81_WRP_PCIE_EFUSE3 0x151fff2 ++#define ixPSX81_WRP_PCIE_EFUSE4 0x151fff3 ++#define ixPSX81_WRP_PCIE_EFUSE5 0x151fff4 ++#define ixPSX81_WRP_PCIE_EFUSE6 0x151fff5 ++#define ixPSX81_WRP_PCIE_EFUSE7 0x151fff6 ++#define ixPSX81_WRP_PCIE_WRAP_SCRATCH1 0x1318001 ++#define ixPSX81_WRP_PCIE_WRAP_SCRATCH2 0x1318002 ++#define ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC 0x1318005 ++#define ixPSX81_WRP_PCIE_WRAP_DTM_MISC 0x1318006 ++#define ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1318007 ++#define ixPSX81_WRP_PCIE_WRAP_MISC 0x1318008 ++#define ixPSX81_WRP_PCIE_WRAP_PIF_MISC 0x1318009 ++#define ixPSX81_WRP_PCIE_RXDET_OVERRIDE 0x131800a ++#define ixPSX81_WRP_IMPCTL_CNTL_PIF0 0x1318070 ++#define ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL 0x1318090 ++#define ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL 0x1318096 ++#define ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL 0x1318097 ++#define ixPSX81_WRP_REG_ADAPT_pif0_CONTROL 0x1318098 ++#define ixPSX81_WRP_BIOSTIMER_CMD 0x13180f0 ++#define ixPSX81_WRP_BIOSTIMER_CNTL 0x13180f1 ++#define ixPSX81_WRP_BIOSTIMER_DEBUG 0x13180f2 ++#define ixPSX81_WRP_DTM_RX_BP_CNTL 0x131ffe0 ++#define ixPSX81_WRP_DTM_CNTL 0x131ffe1 ++#define ixPSX81_WRP_DTM_CNTL_LEGACY 0x131ffe2 ++#define ixPSX81_WRP_DTM_STI_LCLK_CTRL 0x131ffe3 ++#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x 0x131ffe4 ++#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt 0x131ffe5 ++#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x 0x131ffe6 ++#define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt 0x131ffe7 ++#define ixPSX81_WRP_DELAYLINE_COMMAND 0x131ffd0 ++#define ixPSX81_WRP_DELAYLINE_STATUS 0x131ffd1 ++#define ixRFE_WARMRST_CNTL 0x1085164 ++#define ixRFE_SOFTRST_CNTL 0x1080001 ++#define ixRFE_IMPRST_CNTL 0x1085160 ++#define ixRFE_CLIENT_SOFTRST_TRIGGER 0x1080004 ++#define ixRFE_MASTER_SOFTRST_TRIGGER 0x1080005 ++#define ixRFE_PWDN_COMMAND 0x1080010 ++#define ixRFE_PWDN_STATUS 0x1080011 ++#define ixRFE_MST_PCIEW0_CMDSTATUS 0x1080020 ++#define ixRFE_MST_PCIEW1_CMDSTATUS 0x1080021 ++#define ixRFE_MST_RWREG_RFEWRC_CMDSTATUS 0x1080022 ++#define ixRFE_MST_TMOUT_STATUS 0x108003f ++#define ixRFE_IMPARBH_STATUS 0x1085140 ++#define ixRFE_IMPARBH_CONTROL 0x1080083 ++#define ixPSX80_BIF_PCIE_RESERVED 0x1400000 ++#define ixPSX80_BIF_PCIE_SCRATCH 0x1400001 ++#define ixPSX80_BIF_PCIE_HW_DEBUG 0x1400002 ++#define ixPSX80_BIF_PCIE_RX_NUM_NAK 0x140000e ++#define ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED 0x140000f ++#define ixPSX80_BIF_PCIE_CNTL 0x1400010 ++#define ixPSX80_BIF_PCIE_CONFIG_CNTL 0x1400011 ++#define ixPSX80_BIF_PCIE_DEBUG_CNTL 0x1400012 ++#define ixPSX80_BIF_PCIE_CNTL2 0x140001c ++#define ixPSX80_BIF_PCIE_RX_CNTL2 0x140001d ++#define ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL 0x140001e ++#define ixPSX80_BIF_PCIE_CI_CNTL 0x1400020 ++#define ixPSX80_BIF_PCIE_BUS_CNTL 0x1400021 ++#define ixPSX80_BIF_PCIE_LC_STATE6 0x1400022 ++#define ixPSX80_BIF_PCIE_LC_STATE7 0x1400023 ++#define ixPSX80_BIF_PCIE_LC_STATE8 0x1400024 ++#define ixPSX80_BIF_PCIE_LC_STATE9 0x1400025 ++#define ixPSX80_BIF_PCIE_LC_STATE10 0x1400026 ++#define ixPSX80_BIF_PCIE_LC_STATE11 0x1400027 ++#define ixPSX80_BIF_PCIE_LC_STATUS1 0x1400028 ++#define ixPSX80_BIF_PCIE_LC_STATUS2 0x1400029 ++#define ixPSX80_BIF_PCIE_WPR_CNTL 0x1400030 ++#define ixPSX80_BIF_PCIE_RX_LAST_TLP0 0x1400031 ++#define ixPSX80_BIF_PCIE_RX_LAST_TLP1 0x1400032 ++#define ixPSX80_BIF_PCIE_RX_LAST_TLP2 0x1400033 ++#define ixPSX80_BIF_PCIE_RX_LAST_TLP3 0x1400034 ++#define ixPSX80_BIF_PCIE_TX_LAST_TLP0 0x1400035 ++#define ixPSX80_BIF_PCIE_TX_LAST_TLP1 0x1400036 ++#define ixPSX80_BIF_PCIE_TX_LAST_TLP2 0x1400037 ++#define ixPSX80_BIF_PCIE_TX_LAST_TLP3 0x1400038 ++#define ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND 0x140003a ++#define ixPSX80_BIF_PCIE_I2C_REG_DATA 0x140003b ++#define ixPSX80_BIF_PCIE_CFG_CNTL 0x140003c ++#define ixPSX80_BIF_PCIE_LC_PM_CNTL 0x140003d ++#define ixPSX80_BIF_PCIE_P_CNTL 0x1400040 ++#define ixPSX80_BIF_PCIE_P_BUF_STATUS 0x1400041 ++#define ixPSX80_BIF_PCIE_P_DECODER_STATUS 0x1400042 ++#define ixPSX80_BIF_PCIE_P_MISC_STATUS 0x1400043 ++#define ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET 0x1400050 ++#define ixPSX80_BIF_PCIE_PERF_COUNT_CNTL 0x1400080 ++#define ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK 0x1400081 ++#define ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK 0x1400082 ++#define ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK 0x1400083 ++#define ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK 0x1400084 ++#define ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK 0x1400085 ++#define ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK 0x1400086 ++#define ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK 0x1400087 ++#define ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK 0x1400088 ++#define ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK 0x1400089 ++#define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK 0x140008a ++#define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK 0x140008b ++#define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK 0x140008c ++#define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d ++#define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e ++#define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f ++#define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 ++#define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 ++#define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 ++#define ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 ++#define ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 ++#define ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2 0x1400095 ++#define ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2 0x1400096 ++#define ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2 0x1400097 ++#define ixPSX80_BIF_PCIE_STRAP_F0 0x14000b0 ++#define ixPSX80_BIF_PCIE_STRAP_MISC 0x14000c0 ++#define ixPSX80_BIF_PCIE_STRAP_MISC2 0x14000c1 ++#define ixPSX80_BIF_PCIE_STRAP_PI 0x14000c2 ++#define ixPSX80_BIF_PCIE_STRAP_I2C_BD 0x14000c4 ++#define ixPSX80_BIF_PCIE_PRBS_CLR 0x14000c8 ++#define ixPSX80_BIF_PCIE_PRBS_STATUS1 0x14000c9 ++#define ixPSX80_BIF_PCIE_PRBS_STATUS2 0x14000ca ++#define ixPSX80_BIF_PCIE_PRBS_FREERUN 0x14000cb ++#define ixPSX80_BIF_PCIE_PRBS_MISC 0x14000cc ++#define ixPSX80_BIF_PCIE_PRBS_USER_PATTERN 0x14000cd ++#define ixPSX80_BIF_PCIE_PRBS_LO_BITCNT 0x14000ce ++#define ixPSX80_BIF_PCIE_PRBS_HI_BITCNT 0x14000cf ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_0 0x14000d0 ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_1 0x14000d1 ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_2 0x14000d2 ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_3 0x14000d3 ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_4 0x14000d4 ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_5 0x14000d5 ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_6 0x14000d6 ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_7 0x14000d7 ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_8 0x14000d8 ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_9 0x14000d9 ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_10 0x14000da ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_11 0x14000db ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_12 0x14000dc ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_13 0x14000dd ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_14 0x14000de ++#define ixPSX80_BIF_PCIE_PRBS_ERRCNT_15 0x14000df ++#define ixPSX80_BIF_SWRST_COMMAND_STATUS 0x1400100 ++#define ixPSX80_BIF_SWRST_GENERAL_CONTROL 0x1400101 ++#define ixPSX80_BIF_SWRST_COMMAND_0 0x1400102 ++#define ixPSX80_BIF_SWRST_COMMAND_1 0x1400103 ++#define ixPSX80_BIF_SWRST_CONTROL_0 0x1400104 ++#define ixPSX80_BIF_SWRST_CONTROL_1 0x1400105 ++#define ixPSX80_BIF_SWRST_CONTROL_2 0x1400106 ++#define ixPSX80_BIF_SWRST_CONTROL_3 0x1400107 ++#define ixPSX80_BIF_SWRST_CONTROL_4 0x1400108 ++#define ixPSX80_BIF_SWRST_CONTROL_5 0x1400109 ++#define ixPSX80_BIF_SWRST_CONTROL_6 0x140010a ++#define ixPSX80_BIF_CPM_CONTROL 0x1400118 ++#define ixPSX80_BIF_LM_CONTROL 0x1400120 ++#define ixPSX80_BIF_LM_PCIETXMUX0 0x1400121 ++#define ixPSX80_BIF_LM_PCIETXMUX1 0x1400122 ++#define ixPSX80_BIF_LM_PCIETXMUX2 0x1400123 ++#define ixPSX80_BIF_LM_PCIETXMUX3 0x1400124 ++#define ixPSX80_BIF_LM_PCIERXMUX0 0x1400125 ++#define ixPSX80_BIF_LM_PCIERXMUX1 0x1400126 ++#define ixPSX80_BIF_LM_PCIERXMUX2 0x1400127 ++#define ixPSX80_BIF_LM_PCIERXMUX3 0x1400128 ++#define ixPSX80_BIF_LM_LANEENABLE 0x1400129 ++#define ixPSX80_BIF_LM_PRBSCONTROL 0x140012a ++#define ixPSX80_BIF_LM_POWERCONTROL 0x140012b ++#define ixPSX80_BIF_LM_POWERCONTROL1 0x140012c ++#define ixPSX80_BIF_LM_POWERCONTROL2 0x140012d ++#define ixPSX80_BIF_LM_POWERCONTROL3 0x140012e ++#define ixPSX80_BIF_LM_POWERCONTROL4 0x140012f ++#define ixPSX81_BIF_PCIE_RESERVED 0x1410000 ++#define ixPSX81_BIF_PCIE_SCRATCH 0x1410001 ++#define ixPSX81_BIF_PCIE_HW_DEBUG 0x1410002 ++#define ixPSX81_BIF_PCIE_RX_NUM_NAK 0x141000e ++#define ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED 0x141000f ++#define ixPSX81_BIF_PCIE_CNTL 0x1410010 ++#define ixPSX81_BIF_PCIE_CONFIG_CNTL 0x1410011 ++#define ixPSX81_BIF_PCIE_DEBUG_CNTL 0x1410012 ++#define ixPSX81_BIF_PCIE_CNTL2 0x141001c ++#define ixPSX81_BIF_PCIE_RX_CNTL2 0x141001d ++#define ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL 0x141001e ++#define ixPSX81_BIF_PCIE_CI_CNTL 0x1410020 ++#define ixPSX81_BIF_PCIE_BUS_CNTL 0x1410021 ++#define ixPSX81_BIF_PCIE_LC_STATE6 0x1410022 ++#define ixPSX81_BIF_PCIE_LC_STATE7 0x1410023 ++#define ixPSX81_BIF_PCIE_LC_STATE8 0x1410024 ++#define ixPSX81_BIF_PCIE_LC_STATE9 0x1410025 ++#define ixPSX81_BIF_PCIE_LC_STATE10 0x1410026 ++#define ixPSX81_BIF_PCIE_LC_STATE11 0x1410027 ++#define ixPSX81_BIF_PCIE_LC_STATUS1 0x1410028 ++#define ixPSX81_BIF_PCIE_LC_STATUS2 0x1410029 ++#define ixPSX81_BIF_PCIE_WPR_CNTL 0x1410030 ++#define ixPSX81_BIF_PCIE_RX_LAST_TLP0 0x1410031 ++#define ixPSX81_BIF_PCIE_RX_LAST_TLP1 0x1410032 ++#define ixPSX81_BIF_PCIE_RX_LAST_TLP2 0x1410033 ++#define ixPSX81_BIF_PCIE_RX_LAST_TLP3 0x1410034 ++#define ixPSX81_BIF_PCIE_TX_LAST_TLP0 0x1410035 ++#define ixPSX81_BIF_PCIE_TX_LAST_TLP1 0x1410036 ++#define ixPSX81_BIF_PCIE_TX_LAST_TLP2 0x1410037 ++#define ixPSX81_BIF_PCIE_TX_LAST_TLP3 0x1410038 ++#define ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND 0x141003a ++#define ixPSX81_BIF_PCIE_I2C_REG_DATA 0x141003b ++#define ixPSX81_BIF_PCIE_CFG_CNTL 0x141003c ++#define ixPSX81_BIF_PCIE_LC_PM_CNTL 0x141003d ++#define ixPSX81_BIF_PCIE_P_CNTL 0x1410040 ++#define ixPSX81_BIF_PCIE_P_BUF_STATUS 0x1410041 ++#define ixPSX81_BIF_PCIE_P_DECODER_STATUS 0x1410042 ++#define ixPSX81_BIF_PCIE_P_MISC_STATUS 0x1410043 ++#define ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET 0x1410050 ++#define ixPSX81_BIF_PCIE_PERF_COUNT_CNTL 0x1410080 ++#define ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK 0x1410081 ++#define ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK 0x1410082 ++#define ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK 0x1410083 ++#define ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK 0x1410084 ++#define ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK 0x1410085 ++#define ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK 0x1410086 ++#define ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK 0x1410087 ++#define ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK 0x1410088 ++#define ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK 0x1410089 ++#define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK 0x141008a ++#define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK 0x141008b ++#define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK 0x141008c ++#define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK 0x141008d ++#define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK 0x141008e ++#define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK 0x141008f ++#define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK 0x1410090 ++#define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1410091 ++#define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1410092 ++#define ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1410093 ++#define ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1410094 ++#define ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2 0x1410095 ++#define ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2 0x1410096 ++#define ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2 0x1410097 ++#define ixPSX81_BIF_PCIE_STRAP_F0 0x14100b0 ++#define ixPSX81_BIF_PCIE_STRAP_MISC 0x14100c0 ++#define ixPSX81_BIF_PCIE_STRAP_MISC2 0x14100c1 ++#define ixPSX81_BIF_PCIE_STRAP_PI 0x14100c2 ++#define ixPSX81_BIF_PCIE_STRAP_I2C_BD 0x14100c4 ++#define ixPSX81_BIF_PCIE_PRBS_CLR 0x14100c8 ++#define ixPSX81_BIF_PCIE_PRBS_STATUS1 0x14100c9 ++#define ixPSX81_BIF_PCIE_PRBS_STATUS2 0x14100ca ++#define ixPSX81_BIF_PCIE_PRBS_FREERUN 0x14100cb ++#define ixPSX81_BIF_PCIE_PRBS_MISC 0x14100cc ++#define ixPSX81_BIF_PCIE_PRBS_USER_PATTERN 0x14100cd ++#define ixPSX81_BIF_PCIE_PRBS_LO_BITCNT 0x14100ce ++#define ixPSX81_BIF_PCIE_PRBS_HI_BITCNT 0x14100cf ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_0 0x14100d0 ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_1 0x14100d1 ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_2 0x14100d2 ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_3 0x14100d3 ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_4 0x14100d4 ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_5 0x14100d5 ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_6 0x14100d6 ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_7 0x14100d7 ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_8 0x14100d8 ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_9 0x14100d9 ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_10 0x14100da ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_11 0x14100db ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_12 0x14100dc ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_13 0x14100dd ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_14 0x14100de ++#define ixPSX81_BIF_PCIE_PRBS_ERRCNT_15 0x14100df ++#define ixPSX81_BIF_SWRST_COMMAND_STATUS 0x1410100 ++#define ixPSX81_BIF_SWRST_GENERAL_CONTROL 0x1410101 ++#define ixPSX81_BIF_SWRST_COMMAND_0 0x1410102 ++#define ixPSX81_BIF_SWRST_COMMAND_1 0x1410103 ++#define ixPSX81_BIF_SWRST_CONTROL_0 0x1410104 ++#define ixPSX81_BIF_SWRST_CONTROL_1 0x1410105 ++#define ixPSX81_BIF_SWRST_CONTROL_2 0x1410106 ++#define ixPSX81_BIF_SWRST_CONTROL_3 0x1410107 ++#define ixPSX81_BIF_SWRST_CONTROL_4 0x1410108 ++#define ixPSX81_BIF_SWRST_CONTROL_5 0x1410109 ++#define ixPSX81_BIF_SWRST_CONTROL_6 0x141010a ++#define ixPSX81_BIF_CPM_CONTROL 0x1410118 ++#define ixPSX81_BIF_LM_CONTROL 0x1410120 ++#define ixPSX81_BIF_LM_PCIETXMUX0 0x1410121 ++#define ixPSX81_BIF_LM_PCIETXMUX1 0x1410122 ++#define ixPSX81_BIF_LM_PCIETXMUX2 0x1410123 ++#define ixPSX81_BIF_LM_PCIETXMUX3 0x1410124 ++#define ixPSX81_BIF_LM_PCIERXMUX0 0x1410125 ++#define ixPSX81_BIF_LM_PCIERXMUX1 0x1410126 ++#define ixPSX81_BIF_LM_PCIERXMUX2 0x1410127 ++#define ixPSX81_BIF_LM_PCIERXMUX3 0x1410128 ++#define ixPSX81_BIF_LM_LANEENABLE 0x1410129 ++#define ixPSX81_BIF_LM_PRBSCONTROL 0x141012a ++#define ixPSX81_BIF_LM_POWERCONTROL 0x141012b ++#define ixPSX81_BIF_LM_POWERCONTROL1 0x141012c ++#define ixPSX81_BIF_LM_POWERCONTROL2 0x141012d ++#define ixPSX81_BIF_LM_POWERCONTROL3 0x141012e ++#define ixPSX81_BIF_LM_POWERCONTROL4 0x141012f ++#define ixPSX80_PHY0_COM_COMMON_FUSE1 0x1206200 ++#define ixPSX80_PHY0_COM_COMMON_FUSE2 0x1206201 ++#define ixPSX80_PHY0_COM_COMMON_FUSE3 0x1206202 ++#define ixPSX80_PHY0_COM_COMMON_ELECIDLE 0x1206204 ++#define ixPSX80_PHY0_COM_COMMON_DFX 0x1206205 ++#define ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM 0x1206206 ++#define ixPSX80_PHY0_COM_COMMON_SELDEEMPH35 0x1206207 ++#define ixPSX80_PHY0_COM_COMMON_SELDEEMPH60 0x1206208 ++#define ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT 0x1206209 ++#define ixPSX80_PHY0_COM_COMMON_ADAPTCTL1 0x120620a ++#define ixPSX80_PHY0_COM_COMMON_ADAPTCTL2 0x120620b ++#define ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL 0x120620c ++#define ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1 0x120620d ++#define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL 0x120620e ++#define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1 0x120620f ++#define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1 0x1206210 ++#define ixPSX80_PHY0_COM_COMMON_LNCNTRL 0x1206211 ++#define ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG 0x1206212 ++#define ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG 0x1206213 ++#define ixPSX80_PHY0_COM_COMMON_CDR_PHCTL 0x1206214 ++#define ixPSX80_PHY0_COM_COMMON_CDR_FRCTL 0x1206215 ++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST 0x120fe00 ++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0 0x1200000 ++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1 0x1200100 ++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2 0x1200200 ++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3 0x1200300 ++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4 0x1200400 ++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5 0x1200500 ++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6 0x1200600 ++#define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7 0x1200700 ++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST 0x120fe01 ++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0 0x1200001 ++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1 0x1200101 ++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2 0x1200201 ++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3 0x1200301 ++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4 0x1200401 ++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5 0x1200501 ++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6 0x1200601 ++#define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7 0x1200701 ++#define ixPSX80_PHY0_RX_RX_CTL_BROADCAST 0x120fe02 ++#define ixPSX80_PHY0_RX_RX_CTL_LANE0 0x1200002 ++#define ixPSX80_PHY0_RX_RX_CTL_LANE1 0x1200102 ++#define ixPSX80_PHY0_RX_RX_CTL_LANE2 0x1200202 ++#define ixPSX80_PHY0_RX_RX_CTL_LANE3 0x1200302 ++#define ixPSX80_PHY0_RX_RX_CTL_LANE4 0x1200402 ++#define ixPSX80_PHY0_RX_RX_CTL_LANE5 0x1200502 ++#define ixPSX80_PHY0_RX_RX_CTL_LANE6 0x1200602 ++#define ixPSX80_PHY0_RX_RX_CTL_LANE7 0x1200702 ++#define ixPSX80_PHY0_RX_DLL_CTL_BROADCAST 0x120fe03 ++#define ixPSX80_PHY0_RX_DLL_CTL_LANE0 0x1200003 ++#define ixPSX80_PHY0_RX_DLL_CTL_LANE1 0x1200103 ++#define ixPSX80_PHY0_RX_DLL_CTL_LANE2 0x1200203 ++#define ixPSX80_PHY0_RX_DLL_CTL_LANE3 0x1200303 ++#define ixPSX80_PHY0_RX_DLL_CTL_LANE4 0x1200403 ++#define ixPSX80_PHY0_RX_DLL_CTL_LANE5 0x1200503 ++#define ixPSX80_PHY0_RX_DLL_CTL_LANE6 0x1200603 ++#define ixPSX80_PHY0_RX_DLL_CTL_LANE7 0x1200703 ++#define ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST 0x120fe04 ++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE0 0x1200004 ++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE1 0x1200104 ++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE2 0x1200204 ++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE3 0x1200304 ++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE4 0x1200404 ++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE5 0x1200504 ++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE6 0x1200604 ++#define ixPSX80_PHY0_RX_RXTEST_REGS_LANE7 0x1200704 ++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST 0x120fe05 ++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0 0x1200005 ++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1 0x1200105 ++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2 0x1200205 ++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3 0x1200305 ++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4 0x1200405 ++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5 0x1200505 ++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6 0x1200605 ++#define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7 0x1200705 ++#define ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST 0x120fe0a ++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE0 0x120000a ++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE1 0x120010a ++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE2 0x120020a ++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE3 0x120030a ++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE4 0x120040a ++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE5 0x120050a ++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE6 0x120060a ++#define ixPSX80_PHY0_RX_ADAPTCTL_LANE7 0x120070a ++#define ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST 0x120fe0b ++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE0 0x120000b ++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE1 0x120010b ++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE2 0x120020b ++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE3 0x120030b ++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE4 0x120040b ++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE5 0x120050b ++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE6 0x120060b ++#define ixPSX80_PHY0_RX_FOMCALCCTL_LANE7 0x120070b ++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST 0x120fe0c ++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0 0x120000c ++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1 0x120010c ++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2 0x120020c ++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3 0x120030c ++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4 0x120040c ++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5 0x120050c ++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6 0x120060c ++#define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7 0x120070c ++#define ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST 0x120fe0d ++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0 0x120000d ++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1 0x120010d ++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2 0x120020d ++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3 0x120030d ++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4 0x120040d ++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5 0x120050d ++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6 0x120060d ++#define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7 0x120070d ++#define ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST 0x120fe0e ++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE0 0x120000e ++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE1 0x120010e ++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE2 0x120020e ++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE3 0x120030e ++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE4 0x120040e ++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE5 0x120050e ++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE6 0x120060e ++#define ixPSX80_PHY0_RX_ADAPTDBG1_LANE7 0x120070e ++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST 0x120ff00 ++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0 0x1202000 ++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1 0x1202100 ++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2 0x1202200 ++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3 0x1202300 ++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4 0x1202400 ++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5 0x1202500 ++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6 0x1202600 ++#define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7 0x1202700 ++#define ixPSX80_PHY0_TX_DFX_BROADCAST 0x120ff01 ++#define ixPSX80_PHY0_TX_DFX_LANE0 0x1202001 ++#define ixPSX80_PHY0_TX_DFX_LANE1 0x1202101 ++#define ixPSX80_PHY0_TX_DFX_LANE2 0x1202201 ++#define ixPSX80_PHY0_TX_DFX_LANE3 0x1202301 ++#define ixPSX80_PHY0_TX_DFX_LANE4 0x1202401 ++#define ixPSX80_PHY0_TX_DFX_LANE5 0x1202501 ++#define ixPSX80_PHY0_TX_DFX_LANE6 0x1202601 ++#define ixPSX80_PHY0_TX_DFX_LANE7 0x1202701 ++#define ixPSX80_PHY0_TX_DEEMPH_BROADCAST 0x120ff02 ++#define ixPSX80_PHY0_TX_DEEMPH_LANE0 0x1202002 ++#define ixPSX80_PHY0_TX_DEEMPH_LANE1 0x1202102 ++#define ixPSX80_PHY0_TX_DEEMPH_LANE2 0x1202202 ++#define ixPSX80_PHY0_TX_DEEMPH_LANE3 0x1202302 ++#define ixPSX80_PHY0_TX_DEEMPH_LANE4 0x1202402 ++#define ixPSX80_PHY0_TX_DEEMPH_LANE5 0x1202502 ++#define ixPSX80_PHY0_TX_DEEMPH_LANE6 0x1202602 ++#define ixPSX80_PHY0_TX_DEEMPH_LANE7 0x1202702 ++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST 0x120ff03 ++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0 0x1202003 ++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1 0x1202103 ++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2 0x1202203 ++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3 0x1202303 ++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4 0x1202403 ++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5 0x1202503 ++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6 0x1202603 ++#define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7 0x1202703 ++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST 0x120ff04 ++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0 0x1202004 ++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1 0x1202104 ++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2 0x1202204 ++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3 0x1202304 ++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4 0x1202404 ++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5 0x1202504 ++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6 0x1202604 ++#define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7 0x1202704 ++#define ixPSX80_PHY0_TX_TXCNTRL_BROADCAST 0x120ff06 ++#define ixPSX80_PHY0_TX_TXCNTRL_LANE0 0x1202006 ++#define ixPSX80_PHY0_TX_TXCNTRL_LANE1 0x1202106 ++#define ixPSX80_PHY0_TX_TXCNTRL_LANE2 0x1202206 ++#define ixPSX80_PHY0_TX_TXCNTRL_LANE3 0x1202306 ++#define ixPSX80_PHY0_TX_TXCNTRL_LANE4 0x1202406 ++#define ixPSX80_PHY0_TX_TXCNTRL_LANE5 0x1202506 ++#define ixPSX80_PHY0_TX_TXCNTRL_LANE6 0x1202606 ++#define ixPSX80_PHY0_TX_TXCNTRL_LANE7 0x1202706 ++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST 0x120ff07 ++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x1202007 ++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x1202107 ++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x1202207 ++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x1202307 ++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4 0x1202407 ++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5 0x1202507 ++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6 0x1202607 ++#define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7 0x1202707 ++#define ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn 0x1204180 ++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt 0x1204101 ++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl 0x1204102 ++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1 0x1204103 ++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2 0x1204104 ++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode 0x1204105 ++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl 0x1204108 ++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3 0x1204109 ++#define ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess 0x120410a ++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4 0x120410b ++#define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5 0x120410c ++#define ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn 0x1204080 ++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt 0x1204001 ++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl 0x1204002 ++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1 0x1204003 ++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2 0x1204004 ++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode 0x1204005 ++#define ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl 0x1204007 ++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl 0x1204008 ++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3 0x1204009 ++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4 0x120400b ++#define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5 0x120400c ++#define ixPSX81_PHY0_COM_COMMON_FUSE1 0x1216200 ++#define ixPSX81_PHY0_COM_COMMON_FUSE2 0x1216201 ++#define ixPSX81_PHY0_COM_COMMON_FUSE3 0x1216202 ++#define ixPSX81_PHY0_COM_COMMON_ELECIDLE 0x1216204 ++#define ixPSX81_PHY0_COM_COMMON_DFX 0x1216205 ++#define ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM 0x1216206 ++#define ixPSX81_PHY0_COM_COMMON_SELDEEMPH35 0x1216207 ++#define ixPSX81_PHY0_COM_COMMON_SELDEEMPH60 0x1216208 ++#define ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT 0x1216209 ++#define ixPSX81_PHY0_COM_COMMON_ADAPTCTL1 0x121620a ++#define ixPSX81_PHY0_COM_COMMON_ADAPTCTL2 0x121620b ++#define ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL 0x121620c ++#define ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1 0x121620d ++#define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL 0x121620e ++#define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1 0x121620f ++#define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1 0x1216210 ++#define ixPSX81_PHY0_COM_COMMON_LNCNTRL 0x1216211 ++#define ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG 0x1216212 ++#define ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG 0x1216213 ++#define ixPSX81_PHY0_COM_COMMON_CDR_PHCTL 0x1216214 ++#define ixPSX81_PHY0_COM_COMMON_CDR_FRCTL 0x1216215 ++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST 0x121fe00 ++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0 0x1210000 ++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1 0x1210100 ++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2 0x1210200 ++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3 0x1210300 ++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4 0x1210400 ++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5 0x1210500 ++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6 0x1210600 ++#define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7 0x1210700 ++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST 0x121fe01 ++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0 0x1210001 ++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1 0x1210101 ++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2 0x1210201 ++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3 0x1210301 ++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4 0x1210401 ++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5 0x1210501 ++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6 0x1210601 ++#define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7 0x1210701 ++#define ixPSX81_PHY0_RX_RX_CTL_BROADCAST 0x121fe02 ++#define ixPSX81_PHY0_RX_RX_CTL_LANE0 0x1210002 ++#define ixPSX81_PHY0_RX_RX_CTL_LANE1 0x1210102 ++#define ixPSX81_PHY0_RX_RX_CTL_LANE2 0x1210202 ++#define ixPSX81_PHY0_RX_RX_CTL_LANE3 0x1210302 ++#define ixPSX81_PHY0_RX_RX_CTL_LANE4 0x1210402 ++#define ixPSX81_PHY0_RX_RX_CTL_LANE5 0x1210502 ++#define ixPSX81_PHY0_RX_RX_CTL_LANE6 0x1210602 ++#define ixPSX81_PHY0_RX_RX_CTL_LANE7 0x1210702 ++#define ixPSX81_PHY0_RX_DLL_CTL_BROADCAST 0x121fe03 ++#define ixPSX81_PHY0_RX_DLL_CTL_LANE0 0x1210003 ++#define ixPSX81_PHY0_RX_DLL_CTL_LANE1 0x1210103 ++#define ixPSX81_PHY0_RX_DLL_CTL_LANE2 0x1210203 ++#define ixPSX81_PHY0_RX_DLL_CTL_LANE3 0x1210303 ++#define ixPSX81_PHY0_RX_DLL_CTL_LANE4 0x1210403 ++#define ixPSX81_PHY0_RX_DLL_CTL_LANE5 0x1210503 ++#define ixPSX81_PHY0_RX_DLL_CTL_LANE6 0x1210603 ++#define ixPSX81_PHY0_RX_DLL_CTL_LANE7 0x1210703 ++#define ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST 0x121fe04 ++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE0 0x1210004 ++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE1 0x1210104 ++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE2 0x1210204 ++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE3 0x1210304 ++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE4 0x1210404 ++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE5 0x1210504 ++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE6 0x1210604 ++#define ixPSX81_PHY0_RX_RXTEST_REGS_LANE7 0x1210704 ++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST 0x121fe05 ++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0 0x1210005 ++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1 0x1210105 ++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2 0x1210205 ++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3 0x1210305 ++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4 0x1210405 ++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5 0x1210505 ++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6 0x1210605 ++#define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7 0x1210705 ++#define ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST 0x121fe0a ++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE0 0x121000a ++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE1 0x121010a ++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE2 0x121020a ++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE3 0x121030a ++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE4 0x121040a ++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE5 0x121050a ++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE6 0x121060a ++#define ixPSX81_PHY0_RX_ADAPTCTL_LANE7 0x121070a ++#define ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST 0x121fe0b ++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE0 0x121000b ++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE1 0x121010b ++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE2 0x121020b ++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE3 0x121030b ++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE4 0x121040b ++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE5 0x121050b ++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE6 0x121060b ++#define ixPSX81_PHY0_RX_FOMCALCCTL_LANE7 0x121070b ++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST 0x121fe0c ++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0 0x121000c ++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1 0x121010c ++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2 0x121020c ++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3 0x121030c ++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4 0x121040c ++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5 0x121050c ++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6 0x121060c ++#define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7 0x121070c ++#define ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST 0x121fe0d ++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0 0x121000d ++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1 0x121010d ++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2 0x121020d ++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3 0x121030d ++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4 0x121040d ++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5 0x121050d ++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6 0x121060d ++#define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7 0x121070d ++#define ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST 0x121fe0e ++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE0 0x121000e ++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE1 0x121010e ++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE2 0x121020e ++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE3 0x121030e ++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE4 0x121040e ++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE5 0x121050e ++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE6 0x121060e ++#define ixPSX81_PHY0_RX_ADAPTDBG1_LANE7 0x121070e ++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST 0x121ff00 ++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0 0x1212000 ++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1 0x1212100 ++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2 0x1212200 ++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3 0x1212300 ++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4 0x1212400 ++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5 0x1212500 ++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6 0x1212600 ++#define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7 0x1212700 ++#define ixPSX81_PHY0_TX_DFX_BROADCAST 0x121ff01 ++#define ixPSX81_PHY0_TX_DFX_LANE0 0x1212001 ++#define ixPSX81_PHY0_TX_DFX_LANE1 0x1212101 ++#define ixPSX81_PHY0_TX_DFX_LANE2 0x1212201 ++#define ixPSX81_PHY0_TX_DFX_LANE3 0x1212301 ++#define ixPSX81_PHY0_TX_DFX_LANE4 0x1212401 ++#define ixPSX81_PHY0_TX_DFX_LANE5 0x1212501 ++#define ixPSX81_PHY0_TX_DFX_LANE6 0x1212601 ++#define ixPSX81_PHY0_TX_DFX_LANE7 0x1212701 ++#define ixPSX81_PHY0_TX_DEEMPH_BROADCAST 0x121ff02 ++#define ixPSX81_PHY0_TX_DEEMPH_LANE0 0x1212002 ++#define ixPSX81_PHY0_TX_DEEMPH_LANE1 0x1212102 ++#define ixPSX81_PHY0_TX_DEEMPH_LANE2 0x1212202 ++#define ixPSX81_PHY0_TX_DEEMPH_LANE3 0x1212302 ++#define ixPSX81_PHY0_TX_DEEMPH_LANE4 0x1212402 ++#define ixPSX81_PHY0_TX_DEEMPH_LANE5 0x1212502 ++#define ixPSX81_PHY0_TX_DEEMPH_LANE6 0x1212602 ++#define ixPSX81_PHY0_TX_DEEMPH_LANE7 0x1212702 ++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST 0x121ff03 ++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0 0x1212003 ++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1 0x1212103 ++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2 0x1212203 ++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3 0x1212303 ++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4 0x1212403 ++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5 0x1212503 ++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6 0x1212603 ++#define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7 0x1212703 ++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST 0x121ff04 ++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0 0x1212004 ++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1 0x1212104 ++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2 0x1212204 ++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3 0x1212304 ++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4 0x1212404 ++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5 0x1212504 ++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6 0x1212604 ++#define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7 0x1212704 ++#define ixPSX81_PHY0_TX_TXCNTRL_BROADCAST 0x121ff06 ++#define ixPSX81_PHY0_TX_TXCNTRL_LANE0 0x1212006 ++#define ixPSX81_PHY0_TX_TXCNTRL_LANE1 0x1212106 ++#define ixPSX81_PHY0_TX_TXCNTRL_LANE2 0x1212206 ++#define ixPSX81_PHY0_TX_TXCNTRL_LANE3 0x1212306 ++#define ixPSX81_PHY0_TX_TXCNTRL_LANE4 0x1212406 ++#define ixPSX81_PHY0_TX_TXCNTRL_LANE5 0x1212506 ++#define ixPSX81_PHY0_TX_TXCNTRL_LANE6 0x1212606 ++#define ixPSX81_PHY0_TX_TXCNTRL_LANE7 0x1212706 ++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST 0x121ff07 ++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x1212007 ++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x1212107 ++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x1212207 ++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x1212307 ++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4 0x1212407 ++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5 0x1212507 ++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6 0x1212607 ++#define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7 0x1212707 ++#define ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn 0x1214180 ++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt 0x1214101 ++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl 0x1214102 ++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1 0x1214103 ++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2 0x1214104 ++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode 0x1214105 ++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl 0x1214108 ++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3 0x1214109 ++#define ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess 0x121410a ++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4 0x121410b ++#define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5 0x121410c ++#define ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn 0x1214080 ++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt 0x1214001 ++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl 0x1214002 ++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1 0x1214003 ++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2 0x1214004 ++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode 0x1214005 ++#define ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl 0x1214007 ++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl 0x1214008 ++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3 0x1214009 ++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4 0x121400b ++#define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5 0x121400c ++#define ixPSX80_PIF0_SCRATCH 0x1100001 ++#define ixPSX80_PIF0_HW_DEBUG 0x1100002 ++#define ixPSX80_PIF0_STRAP_0 0x1100003 ++#define ixPSX80_PIF0_CTRL 0x1100004 ++#define ixPSX80_PIF0_TX_CTRL 0x1100008 ++#define ixPSX80_PIF0_TX_CTRL2 0x1100009 ++#define ixPSX80_PIF0_RX_CTRL 0x110000a ++#define ixPSX80_PIF0_RX_CTRL2 0x110000b ++#define ixPSX80_PIF0_GLB_OVRD 0x110000c ++#define ixPSX80_PIF0_GLB_OVRD2 0x110000d ++#define ixPSX80_PIF0_BIF_CMD_STATUS 0x1100010 ++#define ixPSX80_PIF0_CMD_BUS_CTRL 0x1100011 ++#define ixPSX80_PIF0_CMD_BUS_GLB_OVRD 0x1100013 ++#define ixPSX80_PIF0_LANE0_OVRD 0x1100014 ++#define ixPSX80_PIF0_LANE0_OVRD2 0x1100015 ++#define ixPSX80_PIF0_LANE1_OVRD 0x1100016 ++#define ixPSX80_PIF0_LANE1_OVRD2 0x1100017 ++#define ixPSX80_PIF0_LANE2_OVRD 0x1100018 ++#define ixPSX80_PIF0_LANE2_OVRD2 0x1100019 ++#define ixPSX80_PIF0_LANE3_OVRD 0x110001a ++#define ixPSX80_PIF0_LANE3_OVRD2 0x110001b ++#define ixPSX80_PIF0_LANE4_OVRD 0x110001c ++#define ixPSX80_PIF0_LANE4_OVRD2 0x110001d ++#define ixPSX80_PIF0_LANE5_OVRD 0x110001e ++#define ixPSX80_PIF0_LANE5_OVRD2 0x110001f ++#define ixPSX80_PIF0_LANE6_OVRD 0x1100020 ++#define ixPSX80_PIF0_LANE6_OVRD2 0x1100021 ++#define ixPSX80_PIF0_LANE7_OVRD 0x1100022 ++#define ixPSX80_PIF0_LANE7_OVRD2 0x1100023 ++#define ixPSX81_PIF0_SCRATCH 0x1110001 ++#define ixPSX81_PIF0_HW_DEBUG 0x1110002 ++#define ixPSX81_PIF0_STRAP_0 0x1110003 ++#define ixPSX81_PIF0_CTRL 0x1110004 ++#define ixPSX81_PIF0_TX_CTRL 0x1110008 ++#define ixPSX81_PIF0_TX_CTRL2 0x1110009 ++#define ixPSX81_PIF0_RX_CTRL 0x111000a ++#define ixPSX81_PIF0_RX_CTRL2 0x111000b ++#define ixPSX81_PIF0_GLB_OVRD 0x111000c ++#define ixPSX81_PIF0_GLB_OVRD2 0x111000d ++#define ixPSX81_PIF0_BIF_CMD_STATUS 0x1110010 ++#define ixPSX81_PIF0_CMD_BUS_CTRL 0x1110011 ++#define ixPSX81_PIF0_CMD_BUS_GLB_OVRD 0x1110013 ++#define ixPSX81_PIF0_LANE0_OVRD 0x1110014 ++#define ixPSX81_PIF0_LANE0_OVRD2 0x1110015 ++#define ixPSX81_PIF0_LANE1_OVRD 0x1110016 ++#define ixPSX81_PIF0_LANE1_OVRD2 0x1110017 ++#define ixPSX81_PIF0_LANE2_OVRD 0x1110018 ++#define ixPSX81_PIF0_LANE2_OVRD2 0x1110019 ++#define ixPSX81_PIF0_LANE3_OVRD 0x111001a ++#define ixPSX81_PIF0_LANE3_OVRD2 0x111001b ++#define ixPSX81_PIF0_LANE4_OVRD 0x111001c ++#define ixPSX81_PIF0_LANE4_OVRD2 0x111001d ++#define ixPSX81_PIF0_LANE5_OVRD 0x111001e ++#define ixPSX81_PIF0_LANE5_OVRD2 0x111001f ++#define ixPSX81_PIF0_LANE6_OVRD 0x1110020 ++#define ixPSX81_PIF0_LANE6_OVRD2 0x1110021 ++#define ixPSX81_PIF0_LANE7_OVRD 0x1110022 ++#define ixPSX81_PIF0_LANE7_OVRD2 0x1110023 ++ ++#endif /* BIF_5_1_D_H */ +diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h +new file mode 100644 +index 0000000..d8d5ae0 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h +@@ -0,0 +1,1068 @@ ++/* ++ * BIF_5_1 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef BIF_5_1_ENUM_H ++#define BIF_5_1_ENUM_H ++ ++typedef enum DebugBlockId { ++ DBG_BLOCK_ID_RESERVED = 0x0, ++ DBG_BLOCK_ID_DBG = 0x1, ++ DBG_BLOCK_ID_VMC = 0x2, ++ DBG_BLOCK_ID_PDMA = 0x3, ++ DBG_BLOCK_ID_CG = 0x4, ++ DBG_BLOCK_ID_SRBM = 0x5, ++ DBG_BLOCK_ID_GRBM = 0x6, ++ DBG_BLOCK_ID_RLC = 0x7, ++ DBG_BLOCK_ID_CSC = 0x8, ++ DBG_BLOCK_ID_SEM = 0x9, ++ DBG_BLOCK_ID_IH = 0xa, ++ DBG_BLOCK_ID_SC = 0xb, ++ DBG_BLOCK_ID_SQ = 0xc, ++ DBG_BLOCK_ID_UVDU = 0xd, ++ DBG_BLOCK_ID_SQA = 0xe, ++ DBG_BLOCK_ID_SDMA0 = 0xf, ++ DBG_BLOCK_ID_SDMA1 = 0x10, ++ DBG_BLOCK_ID_SPIM = 0x11, ++ DBG_BLOCK_ID_GDS = 0x12, ++ DBG_BLOCK_ID_VC0 = 0x13, ++ DBG_BLOCK_ID_VC1 = 0x14, ++ DBG_BLOCK_ID_PA0 = 0x15, ++ DBG_BLOCK_ID_PA1 = 0x16, ++ DBG_BLOCK_ID_CP0 = 0x17, ++ DBG_BLOCK_ID_CP1 = 0x18, ++ DBG_BLOCK_ID_CP2 = 0x19, ++ DBG_BLOCK_ID_XBR = 0x1a, ++ DBG_BLOCK_ID_UVDM = 0x1b, ++ DBG_BLOCK_ID_VGT0 = 0x1c, ++ DBG_BLOCK_ID_VGT1 = 0x1d, ++ DBG_BLOCK_ID_IA = 0x1e, ++ DBG_BLOCK_ID_SXM0 = 0x1f, ++ DBG_BLOCK_ID_SXM1 = 0x20, ++ DBG_BLOCK_ID_SCT0 = 0x21, ++ DBG_BLOCK_ID_SCT1 = 0x22, ++ DBG_BLOCK_ID_SPM0 = 0x23, ++ DBG_BLOCK_ID_SPM1 = 0x24, ++ DBG_BLOCK_ID_UNUSED0 = 0x25, ++ DBG_BLOCK_ID_UNUSED1 = 0x26, ++ DBG_BLOCK_ID_TCAA = 0x27, ++ DBG_BLOCK_ID_TCAB = 0x28, ++ DBG_BLOCK_ID_TCCA = 0x29, ++ DBG_BLOCK_ID_TCCB = 0x2a, ++ DBG_BLOCK_ID_MCC0 = 0x2b, ++ DBG_BLOCK_ID_MCC1 = 0x2c, ++ DBG_BLOCK_ID_MCC2 = 0x2d, ++ DBG_BLOCK_ID_MCC3 = 0x2e, ++ DBG_BLOCK_ID_SXS0 = 0x2f, ++ DBG_BLOCK_ID_SXS1 = 0x30, ++ DBG_BLOCK_ID_SXS2 = 0x31, ++ DBG_BLOCK_ID_SXS3 = 0x32, ++ DBG_BLOCK_ID_SXS4 = 0x33, ++ DBG_BLOCK_ID_SXS5 = 0x34, ++ DBG_BLOCK_ID_SXS6 = 0x35, ++ DBG_BLOCK_ID_SXS7 = 0x36, ++ DBG_BLOCK_ID_SXS8 = 0x37, ++ DBG_BLOCK_ID_SXS9 = 0x38, ++ DBG_BLOCK_ID_BCI0 = 0x39, ++ DBG_BLOCK_ID_BCI1 = 0x3a, ++ DBG_BLOCK_ID_BCI2 = 0x3b, ++ DBG_BLOCK_ID_BCI3 = 0x3c, ++ DBG_BLOCK_ID_MCB = 0x3d, ++ DBG_BLOCK_ID_UNUSED6 = 0x3e, ++ DBG_BLOCK_ID_SQA00 = 0x3f, ++ DBG_BLOCK_ID_SQA01 = 0x40, ++ DBG_BLOCK_ID_SQA02 = 0x41, ++ DBG_BLOCK_ID_SQA10 = 0x42, ++ DBG_BLOCK_ID_SQA11 = 0x43, ++ DBG_BLOCK_ID_SQA12 = 0x44, ++ DBG_BLOCK_ID_UNUSED7 = 0x45, ++ DBG_BLOCK_ID_UNUSED8 = 0x46, ++ DBG_BLOCK_ID_SQB00 = 0x47, ++ DBG_BLOCK_ID_SQB01 = 0x48, ++ DBG_BLOCK_ID_SQB10 = 0x49, ++ DBG_BLOCK_ID_SQB11 = 0x4a, ++ DBG_BLOCK_ID_SQ00 = 0x4b, ++ DBG_BLOCK_ID_SQ01 = 0x4c, ++ DBG_BLOCK_ID_SQ10 = 0x4d, ++ DBG_BLOCK_ID_SQ11 = 0x4e, ++ DBG_BLOCK_ID_CB00 = 0x4f, ++ DBG_BLOCK_ID_CB01 = 0x50, ++ DBG_BLOCK_ID_CB02 = 0x51, ++ DBG_BLOCK_ID_CB03 = 0x52, ++ DBG_BLOCK_ID_CB04 = 0x53, ++ DBG_BLOCK_ID_UNUSED9 = 0x54, ++ DBG_BLOCK_ID_UNUSED10 = 0x55, ++ DBG_BLOCK_ID_UNUSED11 = 0x56, ++ DBG_BLOCK_ID_CB10 = 0x57, ++ DBG_BLOCK_ID_CB11 = 0x58, ++ DBG_BLOCK_ID_CB12 = 0x59, ++ DBG_BLOCK_ID_CB13 = 0x5a, ++ DBG_BLOCK_ID_CB14 = 0x5b, ++ DBG_BLOCK_ID_UNUSED12 = 0x5c, ++ DBG_BLOCK_ID_UNUSED13 = 0x5d, ++ DBG_BLOCK_ID_UNUSED14 = 0x5e, ++ DBG_BLOCK_ID_TCP0 = 0x5f, ++ DBG_BLOCK_ID_TCP1 = 0x60, ++ DBG_BLOCK_ID_TCP2 = 0x61, ++ DBG_BLOCK_ID_TCP3 = 0x62, ++ DBG_BLOCK_ID_TCP4 = 0x63, ++ DBG_BLOCK_ID_TCP5 = 0x64, ++ DBG_BLOCK_ID_TCP6 = 0x65, ++ DBG_BLOCK_ID_TCP7 = 0x66, ++ DBG_BLOCK_ID_TCP8 = 0x67, ++ DBG_BLOCK_ID_TCP9 = 0x68, ++ DBG_BLOCK_ID_TCP10 = 0x69, ++ DBG_BLOCK_ID_TCP11 = 0x6a, ++ DBG_BLOCK_ID_TCP12 = 0x6b, ++ DBG_BLOCK_ID_TCP13 = 0x6c, ++ DBG_BLOCK_ID_TCP14 = 0x6d, ++ DBG_BLOCK_ID_TCP15 = 0x6e, ++ DBG_BLOCK_ID_TCP16 = 0x6f, ++ DBG_BLOCK_ID_TCP17 = 0x70, ++ DBG_BLOCK_ID_TCP18 = 0x71, ++ DBG_BLOCK_ID_TCP19 = 0x72, ++ DBG_BLOCK_ID_TCP20 = 0x73, ++ DBG_BLOCK_ID_TCP21 = 0x74, ++ DBG_BLOCK_ID_TCP22 = 0x75, ++ DBG_BLOCK_ID_TCP23 = 0x76, ++ DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, ++ DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, ++ DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, ++ DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, ++ DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, ++ DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, ++ DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, ++ DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, ++ DBG_BLOCK_ID_DB00 = 0x7f, ++ DBG_BLOCK_ID_DB01 = 0x80, ++ DBG_BLOCK_ID_DB02 = 0x81, ++ DBG_BLOCK_ID_DB03 = 0x82, ++ DBG_BLOCK_ID_DB04 = 0x83, ++ DBG_BLOCK_ID_UNUSED15 = 0x84, ++ DBG_BLOCK_ID_UNUSED16 = 0x85, ++ DBG_BLOCK_ID_UNUSED17 = 0x86, ++ DBG_BLOCK_ID_DB10 = 0x87, ++ DBG_BLOCK_ID_DB11 = 0x88, ++ DBG_BLOCK_ID_DB12 = 0x89, ++ DBG_BLOCK_ID_DB13 = 0x8a, ++ DBG_BLOCK_ID_DB14 = 0x8b, ++ DBG_BLOCK_ID_UNUSED18 = 0x8c, ++ DBG_BLOCK_ID_UNUSED19 = 0x8d, ++ DBG_BLOCK_ID_UNUSED20 = 0x8e, ++ DBG_BLOCK_ID_TCC0 = 0x8f, ++ DBG_BLOCK_ID_TCC1 = 0x90, ++ DBG_BLOCK_ID_TCC2 = 0x91, ++ DBG_BLOCK_ID_TCC3 = 0x92, ++ DBG_BLOCK_ID_TCC4 = 0x93, ++ DBG_BLOCK_ID_TCC5 = 0x94, ++ DBG_BLOCK_ID_TCC6 = 0x95, ++ DBG_BLOCK_ID_TCC7 = 0x96, ++ DBG_BLOCK_ID_SPS00 = 0x97, ++ DBG_BLOCK_ID_SPS01 = 0x98, ++ DBG_BLOCK_ID_SPS02 = 0x99, ++ DBG_BLOCK_ID_SPS10 = 0x9a, ++ DBG_BLOCK_ID_SPS11 = 0x9b, ++ DBG_BLOCK_ID_SPS12 = 0x9c, ++ DBG_BLOCK_ID_UNUSED21 = 0x9d, ++ DBG_BLOCK_ID_UNUSED22 = 0x9e, ++ DBG_BLOCK_ID_TA00 = 0x9f, ++ DBG_BLOCK_ID_TA01 = 0xa0, ++ DBG_BLOCK_ID_TA02 = 0xa1, ++ DBG_BLOCK_ID_TA03 = 0xa2, ++ DBG_BLOCK_ID_TA04 = 0xa3, ++ DBG_BLOCK_ID_TA05 = 0xa4, ++ DBG_BLOCK_ID_TA06 = 0xa5, ++ DBG_BLOCK_ID_TA07 = 0xa6, ++ DBG_BLOCK_ID_TA08 = 0xa7, ++ DBG_BLOCK_ID_TA09 = 0xa8, ++ DBG_BLOCK_ID_TA0A = 0xa9, ++ DBG_BLOCK_ID_TA0B = 0xaa, ++ DBG_BLOCK_ID_UNUSED23 = 0xab, ++ DBG_BLOCK_ID_UNUSED24 = 0xac, ++ DBG_BLOCK_ID_UNUSED25 = 0xad, ++ DBG_BLOCK_ID_UNUSED26 = 0xae, ++ DBG_BLOCK_ID_TA10 = 0xaf, ++ DBG_BLOCK_ID_TA11 = 0xb0, ++ DBG_BLOCK_ID_TA12 = 0xb1, ++ DBG_BLOCK_ID_TA13 = 0xb2, ++ DBG_BLOCK_ID_TA14 = 0xb3, ++ DBG_BLOCK_ID_TA15 = 0xb4, ++ DBG_BLOCK_ID_TA16 = 0xb5, ++ DBG_BLOCK_ID_TA17 = 0xb6, ++ DBG_BLOCK_ID_TA18 = 0xb7, ++ DBG_BLOCK_ID_TA19 = 0xb8, ++ DBG_BLOCK_ID_TA1A = 0xb9, ++ DBG_BLOCK_ID_TA1B = 0xba, ++ DBG_BLOCK_ID_UNUSED27 = 0xbb, ++ DBG_BLOCK_ID_UNUSED28 = 0xbc, ++ DBG_BLOCK_ID_UNUSED29 = 0xbd, ++ DBG_BLOCK_ID_UNUSED30 = 0xbe, ++ DBG_BLOCK_ID_TD00 = 0xbf, ++ DBG_BLOCK_ID_TD01 = 0xc0, ++ DBG_BLOCK_ID_TD02 = 0xc1, ++ DBG_BLOCK_ID_TD03 = 0xc2, ++ DBG_BLOCK_ID_TD04 = 0xc3, ++ DBG_BLOCK_ID_TD05 = 0xc4, ++ DBG_BLOCK_ID_TD06 = 0xc5, ++ DBG_BLOCK_ID_TD07 = 0xc6, ++ DBG_BLOCK_ID_TD08 = 0xc7, ++ DBG_BLOCK_ID_TD09 = 0xc8, ++ DBG_BLOCK_ID_TD0A = 0xc9, ++ DBG_BLOCK_ID_TD0B = 0xca, ++ DBG_BLOCK_ID_UNUSED31 = 0xcb, ++ DBG_BLOCK_ID_UNUSED32 = 0xcc, ++ DBG_BLOCK_ID_UNUSED33 = 0xcd, ++ DBG_BLOCK_ID_UNUSED34 = 0xce, ++ DBG_BLOCK_ID_TD10 = 0xcf, ++ DBG_BLOCK_ID_TD11 = 0xd0, ++ DBG_BLOCK_ID_TD12 = 0xd1, ++ DBG_BLOCK_ID_TD13 = 0xd2, ++ DBG_BLOCK_ID_TD14 = 0xd3, ++ DBG_BLOCK_ID_TD15 = 0xd4, ++ DBG_BLOCK_ID_TD16 = 0xd5, ++ DBG_BLOCK_ID_TD17 = 0xd6, ++ DBG_BLOCK_ID_TD18 = 0xd7, ++ DBG_BLOCK_ID_TD19 = 0xd8, ++ DBG_BLOCK_ID_TD1A = 0xd9, ++ DBG_BLOCK_ID_TD1B = 0xda, ++ DBG_BLOCK_ID_UNUSED35 = 0xdb, ++ DBG_BLOCK_ID_UNUSED36 = 0xdc, ++ DBG_BLOCK_ID_UNUSED37 = 0xdd, ++ DBG_BLOCK_ID_UNUSED38 = 0xde, ++ DBG_BLOCK_ID_LDS00 = 0xdf, ++ DBG_BLOCK_ID_LDS01 = 0xe0, ++ DBG_BLOCK_ID_LDS02 = 0xe1, ++ DBG_BLOCK_ID_LDS03 = 0xe2, ++ DBG_BLOCK_ID_LDS04 = 0xe3, ++ DBG_BLOCK_ID_LDS05 = 0xe4, ++ DBG_BLOCK_ID_LDS06 = 0xe5, ++ DBG_BLOCK_ID_LDS07 = 0xe6, ++ DBG_BLOCK_ID_LDS08 = 0xe7, ++ DBG_BLOCK_ID_LDS09 = 0xe8, ++ DBG_BLOCK_ID_LDS0A = 0xe9, ++ DBG_BLOCK_ID_LDS0B = 0xea, ++ DBG_BLOCK_ID_UNUSED39 = 0xeb, ++ DBG_BLOCK_ID_UNUSED40 = 0xec, ++ DBG_BLOCK_ID_UNUSED41 = 0xed, ++ DBG_BLOCK_ID_UNUSED42 = 0xee, ++ DBG_BLOCK_ID_LDS10 = 0xef, ++ DBG_BLOCK_ID_LDS11 = 0xf0, ++ DBG_BLOCK_ID_LDS12 = 0xf1, ++ DBG_BLOCK_ID_LDS13 = 0xf2, ++ DBG_BLOCK_ID_LDS14 = 0xf3, ++ DBG_BLOCK_ID_LDS15 = 0xf4, ++ DBG_BLOCK_ID_LDS16 = 0xf5, ++ DBG_BLOCK_ID_LDS17 = 0xf6, ++ DBG_BLOCK_ID_LDS18 = 0xf7, ++ DBG_BLOCK_ID_LDS19 = 0xf8, ++ DBG_BLOCK_ID_LDS1A = 0xf9, ++ DBG_BLOCK_ID_LDS1B = 0xfa, ++ DBG_BLOCK_ID_UNUSED43 = 0xfb, ++ DBG_BLOCK_ID_UNUSED44 = 0xfc, ++ DBG_BLOCK_ID_UNUSED45 = 0xfd, ++ DBG_BLOCK_ID_UNUSED46 = 0xfe, ++} DebugBlockId; ++typedef enum DebugBlockId_BY2 { ++ DBG_BLOCK_ID_RESERVED_BY2 = 0x0, ++ DBG_BLOCK_ID_VMC_BY2 = 0x1, ++ DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, ++ DBG_BLOCK_ID_GRBM_BY2 = 0x3, ++ DBG_BLOCK_ID_CSC_BY2 = 0x4, ++ DBG_BLOCK_ID_IH_BY2 = 0x5, ++ DBG_BLOCK_ID_SQ_BY2 = 0x6, ++ DBG_BLOCK_ID_UVD_BY2 = 0x7, ++ DBG_BLOCK_ID_SDMA0_BY2 = 0x8, ++ DBG_BLOCK_ID_SPIM_BY2 = 0x9, ++ DBG_BLOCK_ID_VC0_BY2 = 0xa, ++ DBG_BLOCK_ID_PA_BY2 = 0xb, ++ DBG_BLOCK_ID_CP0_BY2 = 0xc, ++ DBG_BLOCK_ID_CP2_BY2 = 0xd, ++ DBG_BLOCK_ID_PC0_BY2 = 0xe, ++ DBG_BLOCK_ID_BCI0_BY2 = 0xf, ++ DBG_BLOCK_ID_SXM0_BY2 = 0x10, ++ DBG_BLOCK_ID_SCT0_BY2 = 0x11, ++ DBG_BLOCK_ID_SPM0_BY2 = 0x12, ++ DBG_BLOCK_ID_BCI2_BY2 = 0x13, ++ DBG_BLOCK_ID_TCA_BY2 = 0x14, ++ DBG_BLOCK_ID_TCCA_BY2 = 0x15, ++ DBG_BLOCK_ID_MCC_BY2 = 0x16, ++ DBG_BLOCK_ID_MCC2_BY2 = 0x17, ++ DBG_BLOCK_ID_MCD_BY2 = 0x18, ++ DBG_BLOCK_ID_MCD2_BY2 = 0x19, ++ DBG_BLOCK_ID_MCD4_BY2 = 0x1a, ++ DBG_BLOCK_ID_MCB_BY2 = 0x1b, ++ DBG_BLOCK_ID_SQA_BY2 = 0x1c, ++ DBG_BLOCK_ID_SQA02_BY2 = 0x1d, ++ DBG_BLOCK_ID_SQA11_BY2 = 0x1e, ++ DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, ++ DBG_BLOCK_ID_SQB_BY2 = 0x20, ++ DBG_BLOCK_ID_SQB10_BY2 = 0x21, ++ DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, ++ DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, ++ DBG_BLOCK_ID_CB_BY2 = 0x24, ++ DBG_BLOCK_ID_CB02_BY2 = 0x25, ++ DBG_BLOCK_ID_CB10_BY2 = 0x26, ++ DBG_BLOCK_ID_CB12_BY2 = 0x27, ++ DBG_BLOCK_ID_SXS_BY2 = 0x28, ++ DBG_BLOCK_ID_SXS2_BY2 = 0x29, ++ DBG_BLOCK_ID_SXS4_BY2 = 0x2a, ++ DBG_BLOCK_ID_SXS6_BY2 = 0x2b, ++ DBG_BLOCK_ID_DB_BY2 = 0x2c, ++ DBG_BLOCK_ID_DB02_BY2 = 0x2d, ++ DBG_BLOCK_ID_DB10_BY2 = 0x2e, ++ DBG_BLOCK_ID_DB12_BY2 = 0x2f, ++ DBG_BLOCK_ID_TCP_BY2 = 0x30, ++ DBG_BLOCK_ID_TCP2_BY2 = 0x31, ++ DBG_BLOCK_ID_TCP4_BY2 = 0x32, ++ DBG_BLOCK_ID_TCP6_BY2 = 0x33, ++ DBG_BLOCK_ID_TCP8_BY2 = 0x34, ++ DBG_BLOCK_ID_TCP10_BY2 = 0x35, ++ DBG_BLOCK_ID_TCP12_BY2 = 0x36, ++ DBG_BLOCK_ID_TCP14_BY2 = 0x37, ++ DBG_BLOCK_ID_TCP16_BY2 = 0x38, ++ DBG_BLOCK_ID_TCP18_BY2 = 0x39, ++ DBG_BLOCK_ID_TCP20_BY2 = 0x3a, ++ DBG_BLOCK_ID_TCP22_BY2 = 0x3b, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, ++ DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, ++ DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, ++ DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, ++ DBG_BLOCK_ID_TCC_BY2 = 0x40, ++ DBG_BLOCK_ID_TCC2_BY2 = 0x41, ++ DBG_BLOCK_ID_TCC4_BY2 = 0x42, ++ DBG_BLOCK_ID_TCC6_BY2 = 0x43, ++ DBG_BLOCK_ID_SPS_BY2 = 0x44, ++ DBG_BLOCK_ID_SPS02_BY2 = 0x45, ++ DBG_BLOCK_ID_SPS11_BY2 = 0x46, ++ DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, ++ DBG_BLOCK_ID_TA_BY2 = 0x48, ++ DBG_BLOCK_ID_TA02_BY2 = 0x49, ++ DBG_BLOCK_ID_TA04_BY2 = 0x4a, ++ DBG_BLOCK_ID_TA06_BY2 = 0x4b, ++ DBG_BLOCK_ID_TA08_BY2 = 0x4c, ++ DBG_BLOCK_ID_TA0A_BY2 = 0x4d, ++ DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, ++ DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, ++ DBG_BLOCK_ID_TA10_BY2 = 0x50, ++ DBG_BLOCK_ID_TA12_BY2 = 0x51, ++ DBG_BLOCK_ID_TA14_BY2 = 0x52, ++ DBG_BLOCK_ID_TA16_BY2 = 0x53, ++ DBG_BLOCK_ID_TA18_BY2 = 0x54, ++ DBG_BLOCK_ID_TA1A_BY2 = 0x55, ++ DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, ++ DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, ++ DBG_BLOCK_ID_TD_BY2 = 0x58, ++ DBG_BLOCK_ID_TD02_BY2 = 0x59, ++ DBG_BLOCK_ID_TD04_BY2 = 0x5a, ++ DBG_BLOCK_ID_TD06_BY2 = 0x5b, ++ DBG_BLOCK_ID_TD08_BY2 = 0x5c, ++ DBG_BLOCK_ID_TD0A_BY2 = 0x5d, ++ DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, ++ DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, ++ DBG_BLOCK_ID_TD10_BY2 = 0x60, ++ DBG_BLOCK_ID_TD12_BY2 = 0x61, ++ DBG_BLOCK_ID_TD14_BY2 = 0x62, ++ DBG_BLOCK_ID_TD16_BY2 = 0x63, ++ DBG_BLOCK_ID_TD18_BY2 = 0x64, ++ DBG_BLOCK_ID_TD1A_BY2 = 0x65, ++ DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, ++ DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, ++ DBG_BLOCK_ID_LDS_BY2 = 0x68, ++ DBG_BLOCK_ID_LDS02_BY2 = 0x69, ++ DBG_BLOCK_ID_LDS04_BY2 = 0x6a, ++ DBG_BLOCK_ID_LDS06_BY2 = 0x6b, ++ DBG_BLOCK_ID_LDS08_BY2 = 0x6c, ++ DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, ++ DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, ++ DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, ++ DBG_BLOCK_ID_LDS10_BY2 = 0x70, ++ DBG_BLOCK_ID_LDS12_BY2 = 0x71, ++ DBG_BLOCK_ID_LDS14_BY2 = 0x72, ++ DBG_BLOCK_ID_LDS16_BY2 = 0x73, ++ DBG_BLOCK_ID_LDS18_BY2 = 0x74, ++ DBG_BLOCK_ID_LDS1A_BY2 = 0x75, ++ DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, ++ DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, ++} DebugBlockId_BY2; ++typedef enum DebugBlockId_BY4 { ++ DBG_BLOCK_ID_RESERVED_BY4 = 0x0, ++ DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, ++ DBG_BLOCK_ID_CSC_BY4 = 0x2, ++ DBG_BLOCK_ID_SQ_BY4 = 0x3, ++ DBG_BLOCK_ID_SDMA0_BY4 = 0x4, ++ DBG_BLOCK_ID_VC0_BY4 = 0x5, ++ DBG_BLOCK_ID_CP0_BY4 = 0x6, ++ DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, ++ DBG_BLOCK_ID_SXM0_BY4 = 0x8, ++ DBG_BLOCK_ID_SPM0_BY4 = 0x9, ++ DBG_BLOCK_ID_TCAA_BY4 = 0xa, ++ DBG_BLOCK_ID_MCC_BY4 = 0xb, ++ DBG_BLOCK_ID_MCD_BY4 = 0xc, ++ DBG_BLOCK_ID_MCD4_BY4 = 0xd, ++ DBG_BLOCK_ID_SQA_BY4 = 0xe, ++ DBG_BLOCK_ID_SQA11_BY4 = 0xf, ++ DBG_BLOCK_ID_SQB_BY4 = 0x10, ++ DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, ++ DBG_BLOCK_ID_CB_BY4 = 0x12, ++ DBG_BLOCK_ID_CB10_BY4 = 0x13, ++ DBG_BLOCK_ID_SXS_BY4 = 0x14, ++ DBG_BLOCK_ID_SXS4_BY4 = 0x15, ++ DBG_BLOCK_ID_DB_BY4 = 0x16, ++ DBG_BLOCK_ID_DB10_BY4 = 0x17, ++ DBG_BLOCK_ID_TCP_BY4 = 0x18, ++ DBG_BLOCK_ID_TCP4_BY4 = 0x19, ++ DBG_BLOCK_ID_TCP8_BY4 = 0x1a, ++ DBG_BLOCK_ID_TCP12_BY4 = 0x1b, ++ DBG_BLOCK_ID_TCP16_BY4 = 0x1c, ++ DBG_BLOCK_ID_TCP20_BY4 = 0x1d, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, ++ DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, ++ DBG_BLOCK_ID_TCC_BY4 = 0x20, ++ DBG_BLOCK_ID_TCC4_BY4 = 0x21, ++ DBG_BLOCK_ID_SPS_BY4 = 0x22, ++ DBG_BLOCK_ID_SPS11_BY4 = 0x23, ++ DBG_BLOCK_ID_TA_BY4 = 0x24, ++ DBG_BLOCK_ID_TA04_BY4 = 0x25, ++ DBG_BLOCK_ID_TA08_BY4 = 0x26, ++ DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, ++ DBG_BLOCK_ID_TA10_BY4 = 0x28, ++ DBG_BLOCK_ID_TA14_BY4 = 0x29, ++ DBG_BLOCK_ID_TA18_BY4 = 0x2a, ++ DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, ++ DBG_BLOCK_ID_TD_BY4 = 0x2c, ++ DBG_BLOCK_ID_TD04_BY4 = 0x2d, ++ DBG_BLOCK_ID_TD08_BY4 = 0x2e, ++ DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, ++ DBG_BLOCK_ID_TD10_BY4 = 0x30, ++ DBG_BLOCK_ID_TD14_BY4 = 0x31, ++ DBG_BLOCK_ID_TD18_BY4 = 0x32, ++ DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, ++ DBG_BLOCK_ID_LDS_BY4 = 0x34, ++ DBG_BLOCK_ID_LDS04_BY4 = 0x35, ++ DBG_BLOCK_ID_LDS08_BY4 = 0x36, ++ DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, ++ DBG_BLOCK_ID_LDS10_BY4 = 0x38, ++ DBG_BLOCK_ID_LDS14_BY4 = 0x39, ++ DBG_BLOCK_ID_LDS18_BY4 = 0x3a, ++ DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, ++} DebugBlockId_BY4; ++typedef enum DebugBlockId_BY8 { ++ DBG_BLOCK_ID_RESERVED_BY8 = 0x0, ++ DBG_BLOCK_ID_CSC_BY8 = 0x1, ++ DBG_BLOCK_ID_SDMA0_BY8 = 0x2, ++ DBG_BLOCK_ID_CP0_BY8 = 0x3, ++ DBG_BLOCK_ID_SXM0_BY8 = 0x4, ++ DBG_BLOCK_ID_TCA_BY8 = 0x5, ++ DBG_BLOCK_ID_MCD_BY8 = 0x6, ++ DBG_BLOCK_ID_SQA_BY8 = 0x7, ++ DBG_BLOCK_ID_SQB_BY8 = 0x8, ++ DBG_BLOCK_ID_CB_BY8 = 0x9, ++ DBG_BLOCK_ID_SXS_BY8 = 0xa, ++ DBG_BLOCK_ID_DB_BY8 = 0xb, ++ DBG_BLOCK_ID_TCP_BY8 = 0xc, ++ DBG_BLOCK_ID_TCP8_BY8 = 0xd, ++ DBG_BLOCK_ID_TCP16_BY8 = 0xe, ++ DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, ++ DBG_BLOCK_ID_TCC_BY8 = 0x10, ++ DBG_BLOCK_ID_SPS_BY8 = 0x11, ++ DBG_BLOCK_ID_TA_BY8 = 0x12, ++ DBG_BLOCK_ID_TA08_BY8 = 0x13, ++ DBG_BLOCK_ID_TA10_BY8 = 0x14, ++ DBG_BLOCK_ID_TA18_BY8 = 0x15, ++ DBG_BLOCK_ID_TD_BY8 = 0x16, ++ DBG_BLOCK_ID_TD08_BY8 = 0x17, ++ DBG_BLOCK_ID_TD10_BY8 = 0x18, ++ DBG_BLOCK_ID_TD18_BY8 = 0x19, ++ DBG_BLOCK_ID_LDS_BY8 = 0x1a, ++ DBG_BLOCK_ID_LDS08_BY8 = 0x1b, ++ DBG_BLOCK_ID_LDS10_BY8 = 0x1c, ++ DBG_BLOCK_ID_LDS18_BY8 = 0x1d, ++} DebugBlockId_BY8; ++typedef enum DebugBlockId_BY16 { ++ DBG_BLOCK_ID_RESERVED_BY16 = 0x0, ++ DBG_BLOCK_ID_SDMA0_BY16 = 0x1, ++ DBG_BLOCK_ID_SXM_BY16 = 0x2, ++ DBG_BLOCK_ID_MCD_BY16 = 0x3, ++ DBG_BLOCK_ID_SQB_BY16 = 0x4, ++ DBG_BLOCK_ID_SXS_BY16 = 0x5, ++ DBG_BLOCK_ID_TCP_BY16 = 0x6, ++ DBG_BLOCK_ID_TCP16_BY16 = 0x7, ++ DBG_BLOCK_ID_TCC_BY16 = 0x8, ++ DBG_BLOCK_ID_TA_BY16 = 0x9, ++ DBG_BLOCK_ID_TA10_BY16 = 0xa, ++ DBG_BLOCK_ID_TD_BY16 = 0xb, ++ DBG_BLOCK_ID_TD10_BY16 = 0xc, ++ DBG_BLOCK_ID_LDS_BY16 = 0xd, ++ DBG_BLOCK_ID_LDS10_BY16 = 0xe, ++} DebugBlockId_BY16; ++typedef enum SurfaceEndian { ++ ENDIAN_NONE = 0x0, ++ ENDIAN_8IN16 = 0x1, ++ ENDIAN_8IN32 = 0x2, ++ ENDIAN_8IN64 = 0x3, ++} SurfaceEndian; ++typedef enum ArrayMode { ++ ARRAY_LINEAR_GENERAL = 0x0, ++ ARRAY_LINEAR_ALIGNED = 0x1, ++ ARRAY_1D_TILED_THIN1 = 0x2, ++ ARRAY_1D_TILED_THICK = 0x3, ++ ARRAY_2D_TILED_THIN1 = 0x4, ++ ARRAY_PRT_TILED_THIN1 = 0x5, ++ ARRAY_PRT_2D_TILED_THIN1 = 0x6, ++ ARRAY_2D_TILED_THICK = 0x7, ++ ARRAY_2D_TILED_XTHICK = 0x8, ++ ARRAY_PRT_TILED_THICK = 0x9, ++ ARRAY_PRT_2D_TILED_THICK = 0xa, ++ ARRAY_PRT_3D_TILED_THIN1 = 0xb, ++ ARRAY_3D_TILED_THIN1 = 0xc, ++ ARRAY_3D_TILED_THICK = 0xd, ++ ARRAY_3D_TILED_XTHICK = 0xe, ++ ARRAY_PRT_3D_TILED_THICK = 0xf, ++} ArrayMode; ++typedef enum PipeTiling { ++ CONFIG_1_PIPE = 0x0, ++ CONFIG_2_PIPE = 0x1, ++ CONFIG_4_PIPE = 0x2, ++ CONFIG_8_PIPE = 0x3, ++} PipeTiling; ++typedef enum BankTiling { ++ CONFIG_4_BANK = 0x0, ++ CONFIG_8_BANK = 0x1, ++} BankTiling; ++typedef enum GroupInterleave { ++ CONFIG_256B_GROUP = 0x0, ++ CONFIG_512B_GROUP = 0x1, ++} GroupInterleave; ++typedef enum RowTiling { ++ CONFIG_1KB_ROW = 0x0, ++ CONFIG_2KB_ROW = 0x1, ++ CONFIG_4KB_ROW = 0x2, ++ CONFIG_8KB_ROW = 0x3, ++ CONFIG_1KB_ROW_OPT = 0x4, ++ CONFIG_2KB_ROW_OPT = 0x5, ++ CONFIG_4KB_ROW_OPT = 0x6, ++ CONFIG_8KB_ROW_OPT = 0x7, ++} RowTiling; ++typedef enum BankSwapBytes { ++ CONFIG_128B_SWAPS = 0x0, ++ CONFIG_256B_SWAPS = 0x1, ++ CONFIG_512B_SWAPS = 0x2, ++ CONFIG_1KB_SWAPS = 0x3, ++} BankSwapBytes; ++typedef enum SampleSplitBytes { ++ CONFIG_1KB_SPLIT = 0x0, ++ CONFIG_2KB_SPLIT = 0x1, ++ CONFIG_4KB_SPLIT = 0x2, ++ CONFIG_8KB_SPLIT = 0x3, ++} SampleSplitBytes; ++typedef enum NumPipes { ++ ADDR_CONFIG_1_PIPE = 0x0, ++ ADDR_CONFIG_2_PIPE = 0x1, ++ ADDR_CONFIG_4_PIPE = 0x2, ++ ADDR_CONFIG_8_PIPE = 0x3, ++} NumPipes; ++typedef enum PipeInterleaveSize { ++ ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, ++ ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, ++} PipeInterleaveSize; ++typedef enum BankInterleaveSize { ++ ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, ++ ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, ++ ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, ++ ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, ++} BankInterleaveSize; ++typedef enum NumShaderEngines { ++ ADDR_CONFIG_1_SHADER_ENGINE = 0x0, ++ ADDR_CONFIG_2_SHADER_ENGINE = 0x1, ++} NumShaderEngines; ++typedef enum ShaderEngineTileSize { ++ ADDR_CONFIG_SE_TILE_16 = 0x0, ++ ADDR_CONFIG_SE_TILE_32 = 0x1, ++} ShaderEngineTileSize; ++typedef enum NumGPUs { ++ ADDR_CONFIG_1_GPU = 0x0, ++ ADDR_CONFIG_2_GPU = 0x1, ++ ADDR_CONFIG_4_GPU = 0x2, ++} NumGPUs; ++typedef enum MultiGPUTileSize { ++ ADDR_CONFIG_GPU_TILE_16 = 0x0, ++ ADDR_CONFIG_GPU_TILE_32 = 0x1, ++ ADDR_CONFIG_GPU_TILE_64 = 0x2, ++ ADDR_CONFIG_GPU_TILE_128 = 0x3, ++} MultiGPUTileSize; ++typedef enum RowSize { ++ ADDR_CONFIG_1KB_ROW = 0x0, ++ ADDR_CONFIG_2KB_ROW = 0x1, ++ ADDR_CONFIG_4KB_ROW = 0x2, ++} RowSize; ++typedef enum NumLowerPipes { ++ ADDR_CONFIG_1_LOWER_PIPES = 0x0, ++ ADDR_CONFIG_2_LOWER_PIPES = 0x1, ++} NumLowerPipes; ++typedef enum ColorTransform { ++ DCC_CT_AUTO = 0x0, ++ DCC_CT_NONE = 0x1, ++ ABGR_TO_A_BG_G_RB = 0x2, ++ BGRA_TO_BG_G_RB_A = 0x3, ++} ColorTransform; ++typedef enum CompareRef { ++ REF_NEVER = 0x0, ++ REF_LESS = 0x1, ++ REF_EQUAL = 0x2, ++ REF_LEQUAL = 0x3, ++ REF_GREATER = 0x4, ++ REF_NOTEQUAL = 0x5, ++ REF_GEQUAL = 0x6, ++ REF_ALWAYS = 0x7, ++} CompareRef; ++typedef enum ReadSize { ++ READ_256_BITS = 0x0, ++ READ_512_BITS = 0x1, ++} ReadSize; ++typedef enum DepthFormat { ++ DEPTH_INVALID = 0x0, ++ DEPTH_16 = 0x1, ++ DEPTH_X8_24 = 0x2, ++ DEPTH_8_24 = 0x3, ++ DEPTH_X8_24_FLOAT = 0x4, ++ DEPTH_8_24_FLOAT = 0x5, ++ DEPTH_32_FLOAT = 0x6, ++ DEPTH_X24_8_32_FLOAT = 0x7, ++} DepthFormat; ++typedef enum ZFormat { ++ Z_INVALID = 0x0, ++ Z_16 = 0x1, ++ Z_24 = 0x2, ++ Z_32_FLOAT = 0x3, ++} ZFormat; ++typedef enum StencilFormat { ++ STENCIL_INVALID = 0x0, ++ STENCIL_8 = 0x1, ++} StencilFormat; ++typedef enum CmaskMode { ++ CMASK_CLEAR_NONE = 0x0, ++ CMASK_CLEAR_ONE = 0x1, ++ CMASK_CLEAR_ALL = 0x2, ++ CMASK_ANY_EXPANDED = 0x3, ++ CMASK_ALPHA0_FRAG1 = 0x4, ++ CMASK_ALPHA0_FRAG2 = 0x5, ++ CMASK_ALPHA0_FRAG4 = 0x6, ++ CMASK_ALPHA0_FRAGS = 0x7, ++ CMASK_ALPHA1_FRAG1 = 0x8, ++ CMASK_ALPHA1_FRAG2 = 0x9, ++ CMASK_ALPHA1_FRAG4 = 0xa, ++ CMASK_ALPHA1_FRAGS = 0xb, ++ CMASK_ALPHAX_FRAG1 = 0xc, ++ CMASK_ALPHAX_FRAG2 = 0xd, ++ CMASK_ALPHAX_FRAG4 = 0xe, ++ CMASK_ALPHAX_FRAGS = 0xf, ++} CmaskMode; ++typedef enum QuadExportFormat { ++ EXPORT_UNUSED = 0x0, ++ EXPORT_32_R = 0x1, ++ EXPORT_32_GR = 0x2, ++ EXPORT_32_AR = 0x3, ++ EXPORT_FP16_ABGR = 0x4, ++ EXPORT_UNSIGNED16_ABGR = 0x5, ++ EXPORT_SIGNED16_ABGR = 0x6, ++ EXPORT_32_ABGR = 0x7, ++} QuadExportFormat; ++typedef enum QuadExportFormatOld { ++ EXPORT_4P_32BPC_ABGR = 0x0, ++ EXPORT_4P_16BPC_ABGR = 0x1, ++ EXPORT_4P_32BPC_GR = 0x2, ++ EXPORT_4P_32BPC_AR = 0x3, ++ EXPORT_2P_32BPC_ABGR = 0x4, ++ EXPORT_8P_32BPC_R = 0x5, ++} QuadExportFormatOld; ++typedef enum ColorFormat { ++ COLOR_INVALID = 0x0, ++ COLOR_8 = 0x1, ++ COLOR_16 = 0x2, ++ COLOR_8_8 = 0x3, ++ COLOR_32 = 0x4, ++ COLOR_16_16 = 0x5, ++ COLOR_10_11_11 = 0x6, ++ COLOR_11_11_10 = 0x7, ++ COLOR_10_10_10_2 = 0x8, ++ COLOR_2_10_10_10 = 0x9, ++ COLOR_8_8_8_8 = 0xa, ++ COLOR_32_32 = 0xb, ++ COLOR_16_16_16_16 = 0xc, ++ COLOR_RESERVED_13 = 0xd, ++ COLOR_32_32_32_32 = 0xe, ++ COLOR_RESERVED_15 = 0xf, ++ COLOR_5_6_5 = 0x10, ++ COLOR_1_5_5_5 = 0x11, ++ COLOR_5_5_5_1 = 0x12, ++ COLOR_4_4_4_4 = 0x13, ++ COLOR_8_24 = 0x14, ++ COLOR_24_8 = 0x15, ++ COLOR_X24_8_32_FLOAT = 0x16, ++ COLOR_RESERVED_23 = 0x17, ++} ColorFormat; ++typedef enum SurfaceFormat { ++ FMT_INVALID = 0x0, ++ FMT_8 = 0x1, ++ FMT_16 = 0x2, ++ FMT_8_8 = 0x3, ++ FMT_32 = 0x4, ++ FMT_16_16 = 0x5, ++ FMT_10_11_11 = 0x6, ++ FMT_11_11_10 = 0x7, ++ FMT_10_10_10_2 = 0x8, ++ FMT_2_10_10_10 = 0x9, ++ FMT_8_8_8_8 = 0xa, ++ FMT_32_32 = 0xb, ++ FMT_16_16_16_16 = 0xc, ++ FMT_32_32_32 = 0xd, ++ FMT_32_32_32_32 = 0xe, ++ FMT_RESERVED_4 = 0xf, ++ FMT_5_6_5 = 0x10, ++ FMT_1_5_5_5 = 0x11, ++ FMT_5_5_5_1 = 0x12, ++ FMT_4_4_4_4 = 0x13, ++ FMT_8_24 = 0x14, ++ FMT_24_8 = 0x15, ++ FMT_X24_8_32_FLOAT = 0x16, ++ FMT_RESERVED_33 = 0x17, ++ FMT_11_11_10_FLOAT = 0x18, ++ FMT_16_FLOAT = 0x19, ++ FMT_32_FLOAT = 0x1a, ++ FMT_16_16_FLOAT = 0x1b, ++ FMT_8_24_FLOAT = 0x1c, ++ FMT_24_8_FLOAT = 0x1d, ++ FMT_32_32_FLOAT = 0x1e, ++ FMT_10_11_11_FLOAT = 0x1f, ++ FMT_16_16_16_16_FLOAT = 0x20, ++ FMT_3_3_2 = 0x21, ++ FMT_6_5_5 = 0x22, ++ FMT_32_32_32_32_FLOAT = 0x23, ++ FMT_RESERVED_36 = 0x24, ++ FMT_1 = 0x25, ++ FMT_1_REVERSED = 0x26, ++ FMT_GB_GR = 0x27, ++ FMT_BG_RG = 0x28, ++ FMT_32_AS_8 = 0x29, ++ FMT_32_AS_8_8 = 0x2a, ++ FMT_5_9_9_9_SHAREDEXP = 0x2b, ++ FMT_8_8_8 = 0x2c, ++ FMT_16_16_16 = 0x2d, ++ FMT_16_16_16_FLOAT = 0x2e, ++ FMT_4_4 = 0x2f, ++ FMT_32_32_32_FLOAT = 0x30, ++ FMT_BC1 = 0x31, ++ FMT_BC2 = 0x32, ++ FMT_BC3 = 0x33, ++ FMT_BC4 = 0x34, ++ FMT_BC5 = 0x35, ++ FMT_BC6 = 0x36, ++ FMT_BC7 = 0x37, ++ FMT_32_AS_32_32_32_32 = 0x38, ++ FMT_APC3 = 0x39, ++ FMT_APC4 = 0x3a, ++ FMT_APC5 = 0x3b, ++ FMT_APC6 = 0x3c, ++ FMT_APC7 = 0x3d, ++ FMT_CTX1 = 0x3e, ++ FMT_RESERVED_63 = 0x3f, ++} SurfaceFormat; ++typedef enum BUF_DATA_FORMAT { ++ BUF_DATA_FORMAT_INVALID = 0x0, ++ BUF_DATA_FORMAT_8 = 0x1, ++ BUF_DATA_FORMAT_16 = 0x2, ++ BUF_DATA_FORMAT_8_8 = 0x3, ++ BUF_DATA_FORMAT_32 = 0x4, ++ BUF_DATA_FORMAT_16_16 = 0x5, ++ BUF_DATA_FORMAT_10_11_11 = 0x6, ++ BUF_DATA_FORMAT_11_11_10 = 0x7, ++ BUF_DATA_FORMAT_10_10_10_2 = 0x8, ++ BUF_DATA_FORMAT_2_10_10_10 = 0x9, ++ BUF_DATA_FORMAT_8_8_8_8 = 0xa, ++ BUF_DATA_FORMAT_32_32 = 0xb, ++ BUF_DATA_FORMAT_16_16_16_16 = 0xc, ++ BUF_DATA_FORMAT_32_32_32 = 0xd, ++ BUF_DATA_FORMAT_32_32_32_32 = 0xe, ++ BUF_DATA_FORMAT_RESERVED_15 = 0xf, ++} BUF_DATA_FORMAT; ++typedef enum IMG_DATA_FORMAT { ++ IMG_DATA_FORMAT_INVALID = 0x0, ++ IMG_DATA_FORMAT_8 = 0x1, ++ IMG_DATA_FORMAT_16 = 0x2, ++ IMG_DATA_FORMAT_8_8 = 0x3, ++ IMG_DATA_FORMAT_32 = 0x4, ++ IMG_DATA_FORMAT_16_16 = 0x5, ++ IMG_DATA_FORMAT_10_11_11 = 0x6, ++ IMG_DATA_FORMAT_11_11_10 = 0x7, ++ IMG_DATA_FORMAT_10_10_10_2 = 0x8, ++ IMG_DATA_FORMAT_2_10_10_10 = 0x9, ++ IMG_DATA_FORMAT_8_8_8_8 = 0xa, ++ IMG_DATA_FORMAT_32_32 = 0xb, ++ IMG_DATA_FORMAT_16_16_16_16 = 0xc, ++ IMG_DATA_FORMAT_32_32_32 = 0xd, ++ IMG_DATA_FORMAT_32_32_32_32 = 0xe, ++ IMG_DATA_FORMAT_RESERVED_15 = 0xf, ++ IMG_DATA_FORMAT_5_6_5 = 0x10, ++ IMG_DATA_FORMAT_1_5_5_5 = 0x11, ++ IMG_DATA_FORMAT_5_5_5_1 = 0x12, ++ IMG_DATA_FORMAT_4_4_4_4 = 0x13, ++ IMG_DATA_FORMAT_8_24 = 0x14, ++ IMG_DATA_FORMAT_24_8 = 0x15, ++ IMG_DATA_FORMAT_X24_8_32 = 0x16, ++ IMG_DATA_FORMAT_RESERVED_23 = 0x17, ++ IMG_DATA_FORMAT_RESERVED_24 = 0x18, ++ IMG_DATA_FORMAT_RESERVED_25 = 0x19, ++ IMG_DATA_FORMAT_RESERVED_26 = 0x1a, ++ IMG_DATA_FORMAT_RESERVED_27 = 0x1b, ++ IMG_DATA_FORMAT_RESERVED_28 = 0x1c, ++ IMG_DATA_FORMAT_RESERVED_29 = 0x1d, ++ IMG_DATA_FORMAT_RESERVED_30 = 0x1e, ++ IMG_DATA_FORMAT_RESERVED_31 = 0x1f, ++ IMG_DATA_FORMAT_GB_GR = 0x20, ++ IMG_DATA_FORMAT_BG_RG = 0x21, ++ IMG_DATA_FORMAT_5_9_9_9 = 0x22, ++ IMG_DATA_FORMAT_BC1 = 0x23, ++ IMG_DATA_FORMAT_BC2 = 0x24, ++ IMG_DATA_FORMAT_BC3 = 0x25, ++ IMG_DATA_FORMAT_BC4 = 0x26, ++ IMG_DATA_FORMAT_BC5 = 0x27, ++ IMG_DATA_FORMAT_BC6 = 0x28, ++ IMG_DATA_FORMAT_BC7 = 0x29, ++ IMG_DATA_FORMAT_RESERVED_42 = 0x2a, ++ IMG_DATA_FORMAT_RESERVED_43 = 0x2b, ++ IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, ++ IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, ++ IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, ++ IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, ++ IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, ++ IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, ++ IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, ++ IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, ++ IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, ++ IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, ++ IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, ++ IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, ++ IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, ++ IMG_DATA_FORMAT_4_4 = 0x39, ++ IMG_DATA_FORMAT_6_5_5 = 0x3a, ++ IMG_DATA_FORMAT_1 = 0x3b, ++ IMG_DATA_FORMAT_1_REVERSED = 0x3c, ++ IMG_DATA_FORMAT_32_AS_8 = 0x3d, ++ IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, ++ IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, ++} IMG_DATA_FORMAT; ++typedef enum BUF_NUM_FORMAT { ++ BUF_NUM_FORMAT_UNORM = 0x0, ++ BUF_NUM_FORMAT_SNORM = 0x1, ++ BUF_NUM_FORMAT_USCALED = 0x2, ++ BUF_NUM_FORMAT_SSCALED = 0x3, ++ BUF_NUM_FORMAT_UINT = 0x4, ++ BUF_NUM_FORMAT_SINT = 0x5, ++ BUF_NUM_FORMAT_RESERVED_6 = 0x6, ++ BUF_NUM_FORMAT_FLOAT = 0x7, ++} BUF_NUM_FORMAT; ++typedef enum IMG_NUM_FORMAT { ++ IMG_NUM_FORMAT_UNORM = 0x0, ++ IMG_NUM_FORMAT_SNORM = 0x1, ++ IMG_NUM_FORMAT_USCALED = 0x2, ++ IMG_NUM_FORMAT_SSCALED = 0x3, ++ IMG_NUM_FORMAT_UINT = 0x4, ++ IMG_NUM_FORMAT_SINT = 0x5, ++ IMG_NUM_FORMAT_RESERVED_6 = 0x6, ++ IMG_NUM_FORMAT_FLOAT = 0x7, ++ IMG_NUM_FORMAT_RESERVED_8 = 0x8, ++ IMG_NUM_FORMAT_SRGB = 0x9, ++ IMG_NUM_FORMAT_RESERVED_10 = 0xa, ++ IMG_NUM_FORMAT_RESERVED_11 = 0xb, ++ IMG_NUM_FORMAT_RESERVED_12 = 0xc, ++ IMG_NUM_FORMAT_RESERVED_13 = 0xd, ++ IMG_NUM_FORMAT_RESERVED_14 = 0xe, ++ IMG_NUM_FORMAT_RESERVED_15 = 0xf, ++} IMG_NUM_FORMAT; ++typedef enum TileType { ++ ARRAY_COLOR_TILE = 0x0, ++ ARRAY_DEPTH_TILE = 0x1, ++} TileType; ++typedef enum NonDispTilingOrder { ++ ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, ++ ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, ++} NonDispTilingOrder; ++typedef enum MicroTileMode { ++ ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, ++ ADDR_SURF_THIN_MICRO_TILING = 0x1, ++ ADDR_SURF_DEPTH_MICRO_TILING = 0x2, ++ ADDR_SURF_ROTATED_MICRO_TILING = 0x3, ++ ADDR_SURF_THICK_MICRO_TILING = 0x4, ++} MicroTileMode; ++typedef enum TileSplit { ++ ADDR_SURF_TILE_SPLIT_64B = 0x0, ++ ADDR_SURF_TILE_SPLIT_128B = 0x1, ++ ADDR_SURF_TILE_SPLIT_256B = 0x2, ++ ADDR_SURF_TILE_SPLIT_512B = 0x3, ++ ADDR_SURF_TILE_SPLIT_1KB = 0x4, ++ ADDR_SURF_TILE_SPLIT_2KB = 0x5, ++ ADDR_SURF_TILE_SPLIT_4KB = 0x6, ++} TileSplit; ++typedef enum SampleSplit { ++ ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, ++ ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, ++ ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, ++ ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, ++} SampleSplit; ++typedef enum PipeConfig { ++ ADDR_SURF_P2 = 0x0, ++ ADDR_SURF_P2_RESERVED0 = 0x1, ++ ADDR_SURF_P2_RESERVED1 = 0x2, ++ ADDR_SURF_P2_RESERVED2 = 0x3, ++ ADDR_SURF_P4_8x16 = 0x4, ++ ADDR_SURF_P4_16x16 = 0x5, ++ ADDR_SURF_P4_16x32 = 0x6, ++ ADDR_SURF_P4_32x32 = 0x7, ++ ADDR_SURF_P8_16x16_8x16 = 0x8, ++ ADDR_SURF_P8_16x32_8x16 = 0x9, ++ ADDR_SURF_P8_32x32_8x16 = 0xa, ++ ADDR_SURF_P8_16x32_16x16 = 0xb, ++ ADDR_SURF_P8_32x32_16x16 = 0xc, ++ ADDR_SURF_P8_32x32_16x32 = 0xd, ++ ADDR_SURF_P8_32x64_32x32 = 0xe, ++ ADDR_SURF_P8_RESERVED0 = 0xf, ++ ADDR_SURF_P16_32x32_8x16 = 0x10, ++ ADDR_SURF_P16_32x32_16x16 = 0x11, ++} PipeConfig; ++typedef enum NumBanks { ++ ADDR_SURF_2_BANK = 0x0, ++ ADDR_SURF_4_BANK = 0x1, ++ ADDR_SURF_8_BANK = 0x2, ++ ADDR_SURF_16_BANK = 0x3, ++} NumBanks; ++typedef enum BankWidth { ++ ADDR_SURF_BANK_WIDTH_1 = 0x0, ++ ADDR_SURF_BANK_WIDTH_2 = 0x1, ++ ADDR_SURF_BANK_WIDTH_4 = 0x2, ++ ADDR_SURF_BANK_WIDTH_8 = 0x3, ++} BankWidth; ++typedef enum BankHeight { ++ ADDR_SURF_BANK_HEIGHT_1 = 0x0, ++ ADDR_SURF_BANK_HEIGHT_2 = 0x1, ++ ADDR_SURF_BANK_HEIGHT_4 = 0x2, ++ ADDR_SURF_BANK_HEIGHT_8 = 0x3, ++} BankHeight; ++typedef enum BankWidthHeight { ++ ADDR_SURF_BANK_WH_1 = 0x0, ++ ADDR_SURF_BANK_WH_2 = 0x1, ++ ADDR_SURF_BANK_WH_4 = 0x2, ++ ADDR_SURF_BANK_WH_8 = 0x3, ++} BankWidthHeight; ++typedef enum MacroTileAspect { ++ ADDR_SURF_MACRO_ASPECT_1 = 0x0, ++ ADDR_SURF_MACRO_ASPECT_2 = 0x1, ++ ADDR_SURF_MACRO_ASPECT_4 = 0x2, ++ ADDR_SURF_MACRO_ASPECT_8 = 0x3, ++} MacroTileAspect; ++typedef enum GATCL1RequestType { ++ GATCL1_TYPE_NORMAL = 0x0, ++ GATCL1_TYPE_SHOOTDOWN = 0x1, ++ GATCL1_TYPE_BYPASS = 0x2, ++} GATCL1RequestType; ++typedef enum TCC_CACHE_POLICIES { ++ TCC_CACHE_POLICY_LRU = 0x0, ++ TCC_CACHE_POLICY_STREAM = 0x1, ++} TCC_CACHE_POLICIES; ++typedef enum MTYPE { ++ MTYPE_NC_NV = 0x0, ++ MTYPE_NC = 0x1, ++ MTYPE_CC = 0x2, ++ MTYPE_UC = 0x3, ++} MTYPE; ++typedef enum PERFMON_COUNTER_MODE { ++ PERFMON_COUNTER_MODE_ACCUM = 0x0, ++ PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, ++ PERFMON_COUNTER_MODE_MAX = 0x2, ++ PERFMON_COUNTER_MODE_DIRTY = 0x3, ++ PERFMON_COUNTER_MODE_SAMPLE = 0x4, ++ PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, ++ PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, ++ PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, ++ PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, ++ PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, ++ PERFMON_COUNTER_MODE_RESERVED = 0xf, ++} PERFMON_COUNTER_MODE; ++typedef enum PERFMON_SPM_MODE { ++ PERFMON_SPM_MODE_OFF = 0x0, ++ PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, ++ PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, ++ PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, ++ PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, ++ PERFMON_SPM_MODE_RESERVED_5 = 0x5, ++ PERFMON_SPM_MODE_RESERVED_6 = 0x6, ++ PERFMON_SPM_MODE_RESERVED_7 = 0x7, ++ PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, ++ PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, ++ PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, ++} PERFMON_SPM_MODE; ++typedef enum SurfaceTiling { ++ ARRAY_LINEAR = 0x0, ++ ARRAY_TILED = 0x1, ++} SurfaceTiling; ++typedef enum SurfaceArray { ++ ARRAY_1D = 0x0, ++ ARRAY_2D = 0x1, ++ ARRAY_3D = 0x2, ++ ARRAY_3D_SLICE = 0x3, ++} SurfaceArray; ++typedef enum ColorArray { ++ ARRAY_2D_ALT_COLOR = 0x0, ++ ARRAY_2D_COLOR = 0x1, ++ ARRAY_3D_SLICE_COLOR = 0x3, ++} ColorArray; ++typedef enum DepthArray { ++ ARRAY_2D_ALT_DEPTH = 0x0, ++ ARRAY_2D_DEPTH = 0x1, ++} DepthArray; ++typedef enum ENUM_NUM_SIMD_PER_CU { ++ NUM_SIMD_PER_CU = 0x4, ++} ENUM_NUM_SIMD_PER_CU; ++typedef enum MEM_PWR_FORCE_CTRL { ++ NO_FORCE_REQUEST = 0x0, ++ FORCE_LIGHT_SLEEP_REQUEST = 0x1, ++ FORCE_DEEP_SLEEP_REQUEST = 0x2, ++ FORCE_SHUT_DOWN_REQUEST = 0x3, ++} MEM_PWR_FORCE_CTRL; ++typedef enum MEM_PWR_FORCE_CTRL2 { ++ NO_FORCE_REQ = 0x0, ++ FORCE_LIGHT_SLEEP_REQ = 0x1, ++} MEM_PWR_FORCE_CTRL2; ++typedef enum MEM_PWR_DIS_CTRL { ++ ENABLE_MEM_PWR_CTRL = 0x0, ++ DISABLE_MEM_PWR_CTRL = 0x1, ++} MEM_PWR_DIS_CTRL; ++typedef enum MEM_PWR_SEL_CTRL { ++ DYNAMIC_SHUT_DOWN_ENABLE = 0x0, ++ DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, ++ DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, ++} MEM_PWR_SEL_CTRL; ++typedef enum MEM_PWR_SEL_CTRL2 { ++ DYNAMIC_DEEP_SLEEP_EN = 0x0, ++ DYNAMIC_LIGHT_SLEEP_EN = 0x1, ++} MEM_PWR_SEL_CTRL2; ++ ++#endif /* BIF_5_1_ENUM_H */ +diff --git a/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h +new file mode 100644 +index 0000000..ee1da0c +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h +@@ -0,0 +1,33080 @@ ++/* ++ * BIF_5_1 Register documentation ++ * ++ * Copyright (C) 2014 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef BIF_5_1_SH_MASK_H ++#define BIF_5_1_SH_MASK_H ++ ++#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff ++#define MM_INDEX__MM_OFFSET__SHIFT 0x0 ++#define MM_INDEX__MM_APER_MASK 0x80000000 ++#define MM_INDEX__MM_APER__SHIFT 0x1f ++#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff ++#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 ++#define MM_DATA__MM_DATA_MASK 0xffffffff ++#define MM_DATA__MM_DATA__SHIFT 0x0 ++#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2 ++#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 ++#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1 ++#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0 ++#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2 ++#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1 ++#define BUS_CNTL__PMI_IO_DIS_MASK 0x4 ++#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 ++#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8 ++#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 ++#define BUS_CNTL__PMI_BM_DIS_MASK 0x10 ++#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 ++#define BUS_CNTL__PMI_INT_DIS_MASK 0x20 ++#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5 ++#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40 ++#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 ++#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80 ++#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 ++#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100 ++#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8 ++#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00 ++#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa ++#define BUS_CNTL__SET_MC_TC_MASK 0xe000 ++#define BUS_CNTL__SET_MC_TC__SHIFT 0xd ++#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000 ++#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 ++#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000 ++#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 ++#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000 ++#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 ++#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1 ++#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 ++#define CONFIG_CNTL__VGA_DIS_MASK 0x2 ++#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1 ++#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4 ++#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 ++#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18 ++#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 ++#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff ++#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 ++#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff ++#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 ++#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff ++#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 ++#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff ++#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 ++#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff ++#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 ++#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff ++#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 ++#define BX_RESET_EN__COR_RESET_EN_MASK 0x1 ++#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 ++#define BX_RESET_EN__REG_RESET_EN_MASK 0x2 ++#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 ++#define BX_RESET_EN__STY_RESET_EN_MASK 0x4 ++#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 ++#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7 ++#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 ++#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8 ++#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3 ++#define HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define HW_DEBUG__HW_16_DEBUG_MASK 0x10000 ++#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10 ++#define HW_DEBUG__HW_17_DEBUG_MASK 0x20000 ++#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11 ++#define HW_DEBUG__HW_18_DEBUG_MASK 0x40000 ++#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12 ++#define HW_DEBUG__HW_19_DEBUG_MASK 0x80000 ++#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13 ++#define HW_DEBUG__HW_20_DEBUG_MASK 0x100000 ++#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14 ++#define HW_DEBUG__HW_21_DEBUG_MASK 0x200000 ++#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15 ++#define HW_DEBUG__HW_22_DEBUG_MASK 0x400000 ++#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16 ++#define HW_DEBUG__HW_23_DEBUG_MASK 0x800000 ++#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17 ++#define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000 ++#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18 ++#define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000 ++#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19 ++#define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000 ++#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a ++#define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000 ++#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b ++#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000 ++#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c ++#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000 ++#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d ++#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000 ++#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e ++#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000 ++#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f ++#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f ++#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0 ++#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000 ++#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10 ++#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f ++#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0 ++#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0 ++#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5 ++#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00 ++#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa ++#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000 ++#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf ++#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000 ++#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14 ++#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000 ++#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19 ++#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1 ++#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 ++#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1 ++#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 ++#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2 ++#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 ++#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8 ++#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 ++#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0 ++#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 ++#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100 ++#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 ++#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00 ++#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9 ++#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000 ++#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd ++#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000 ++#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf ++#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff ++#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 ++#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1 ++#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0 ++#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2 ++#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1 ++#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4 ++#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2 ++#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8 ++#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3 ++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10 ++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4 ++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20 ++#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5 ++#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40 ++#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6 ++#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80 ++#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7 ++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00 ++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8 ++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000 ++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10 ++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000 ++#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18 ++#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000 ++#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e ++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f ++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0 ++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00 ++#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8 ++#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff ++#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0 ++#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1 ++#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 ++#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1 ++#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A_MASK 0x1 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A__SHIFT 0x0 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x2 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL__SHIFT 0x1 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE_MASK 0x4 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x2 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE_MASK 0x18 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE__SHIFT 0x3 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0_MASK 0x20 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0__SHIFT 0x5 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1_MASK 0x40 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1__SHIFT 0x6 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2_MASK 0x80 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2__SHIFT 0x7 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x100 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3__SHIFT 0x8 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x200 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN__SHIFT 0x9 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE_MASK 0x400 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0xa ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN_MASK 0x800 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN__SHIFT 0xb ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN_MASK 0x1000 ++#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN__SHIFT 0xc ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A_MASK 0x1 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A__SHIFT 0x0 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x2 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL__SHIFT 0x1 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE_MASK 0x4 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x2 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE_MASK 0x18 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE__SHIFT 0x3 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0_MASK 0x20 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0__SHIFT 0x5 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1_MASK 0x40 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1__SHIFT 0x6 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2_MASK 0x80 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2__SHIFT 0x7 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x100 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3__SHIFT 0x8 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x200 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN__SHIFT 0x9 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE_MASK 0x400 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0xa ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN_MASK 0x800 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN__SHIFT 0xb ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN_MASK 0x1000 ++#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN__SHIFT 0xc ++#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff ++#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 ++#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000 ++#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f ++#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff ++#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 ++#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1 ++#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 ++#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2 ++#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 ++#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4 ++#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 ++#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8 ++#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 ++#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10 ++#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 ++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20 ++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 ++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40 ++#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 ++#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80 ++#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7 ++#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100 ++#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8 ++#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200 ++#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9 ++#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400 ++#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa ++#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800 ++#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb ++#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000 ++#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc ++#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1 ++#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 ++#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2 ++#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 ++#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4 ++#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 ++#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8 ++#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 ++#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x10 ++#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 ++#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x20 ++#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5 ++#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000 ++#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 ++#define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3 ++#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0 ++#define BIF_FB_EN__FB_READ_EN_MASK 0x1 ++#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 ++#define BIF_FB_EN__FB_WRITE_EN_MASK 0x2 ++#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 ++#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff ++#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 ++#define BIF_BUSNUM_LIST0__ID0_MASK 0xff ++#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0 ++#define BIF_BUSNUM_LIST0__ID1_MASK 0xff00 ++#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8 ++#define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000 ++#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10 ++#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000 ++#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18 ++#define BIF_BUSNUM_LIST1__ID4_MASK 0xff ++#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0 ++#define BIF_BUSNUM_LIST1__ID5_MASK 0xff00 ++#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8 ++#define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000 ++#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10 ++#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000 ++#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18 ++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff ++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 ++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100 ++#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 ++#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000 ++#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 ++#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000 ++#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 ++#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f ++#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 ++#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1 ++#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0 ++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2 ++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1 ++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4 ++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2 ++#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00 ++#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8 ++#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000 ++#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd ++#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff ++#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 ++#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff ++#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 ++#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe ++#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1 ++#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1 ++#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 ++#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2 ++#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 ++#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4 ++#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 ++#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8 ++#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 ++#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10 ++#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 ++#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20 ++#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 ++#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40 ++#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 ++#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80 ++#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 ++#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100 ++#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 ++#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200 ++#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 ++#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400 ++#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa ++#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800 ++#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb ++#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1 ++#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 ++#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2 ++#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 ++#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4 ++#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 ++#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8 ++#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 ++#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10 ++#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 ++#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20 ++#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 ++#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40 ++#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 ++#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80 ++#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 ++#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100 ++#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 ++#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200 ++#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 ++#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400 ++#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa ++#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800 ++#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb ++#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1 ++#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0 ++#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2 ++#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1 ++#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4 ++#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2 ++#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8 ++#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3 ++#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10 ++#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4 ++#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20 ++#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5 ++#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80 ++#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7 ++#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100 ++#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8 ++#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200 ++#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9 ++#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1 ++#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 ++#define HOST_BUSNUM__HOST_ID_MASK 0xffff ++#define HOST_BUSNUM__HOST_ID__SHIFT 0x0 ++#define PEER_REG_RANGE0__START_ADDR_MASK 0xffff ++#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 ++#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000 ++#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 ++#define PEER_REG_RANGE1__START_ADDR_MASK 0xffff ++#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 ++#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000 ++#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 ++#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff ++#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 ++#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff ++#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 ++#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000 ++#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f ++#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff ++#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 ++#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff ++#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 ++#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000 ++#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f ++#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff ++#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 ++#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff ++#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 ++#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000 ++#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f ++#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff ++#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 ++#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff ++#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 ++#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000 ++#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f ++#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1 ++#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0 ++#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD_MASK 0x1e ++#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD__SHIFT 0x1 ++#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff ++#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0 ++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff ++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 ++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00 ++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 ++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000 ++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 ++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000 ++#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 ++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff ++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 ++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00 ++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 ++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000 ++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 ++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000 ++#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 ++#define BACO_CNTL__BACO_EN_MASK 0x1 ++#define BACO_CNTL__BACO_EN__SHIFT 0x0 ++#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2 ++#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1 ++#define BACO_CNTL__BACO_ISO_DIS_MASK 0x4 ++#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2 ++#define BACO_CNTL__BACO_POWER_OFF_MASK 0x8 ++#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 ++#define BACO_CNTL__BACO_RESET_EN_MASK 0x10 ++#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4 ++#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20 ++#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5 ++#define BACO_CNTL__BACO_MODE_MASK 0x40 ++#define BACO_CNTL__BACO_MODE__SHIFT 0x6 ++#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80 ++#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7 ++#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100 ++#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8 ++#define BACO_CNTL__PWRGOOD_BF_MASK 0x200 ++#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9 ++#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400 ++#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa ++#define BACO_CNTL__PWRGOOD_MEM_MASK 0x800 ++#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb ++#define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000 ++#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc ++#define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000 ++#define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd ++#define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000 ++#define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10 ++#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000 ++#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11 ++#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1 ++#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0 ++#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2 ++#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1 ++#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1 ++#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 ++#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1 ++#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0 ++#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1 ++#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0 ++#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1 ++#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 ++#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2 ++#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 ++#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc ++#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2 ++#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x1 ++#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 ++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x1 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x2 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x10 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x20 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 ++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0xffc ++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 ++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000 ++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f ++#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0xffc ++#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 ++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0xffc ++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 ++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000 ++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f ++#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0xffc ++#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 ++#define BIF_SMU_INDEX__BIF_SMU_INDEX_MASK 0x7fffc ++#define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT 0x2 ++#define BIF_SMU_DATA__BIF_SMU_DATA_MASK 0x7fffc ++#define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT 0x2 ++#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1 ++#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0 ++#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1 ++#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0 ++#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2 ++#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1 ++#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4 ++#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2 ++#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8 ++#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3 ++#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10 ++#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4 ++#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20 ++#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5 ++#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40 ++#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6 ++#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80 ++#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7 ++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100 ++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8 ++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200 ++#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9 ++#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400 ++#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa ++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800 ++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb ++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000 ++#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc ++#define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000 ++#define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd ++#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000 ++#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe ++#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND_MASK 0x8000 ++#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND__SHIFT 0xf ++#define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000 ++#define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10 ++#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR_MASK 0x20000 ++#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR__SHIFT 0x11 ++#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR_MASK 0x40000 ++#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR__SHIFT 0x12 ++#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000 ++#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e ++#define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000 ++#define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f ++#define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1 ++#define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0 ++#define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2 ++#define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1 ++#define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1 ++#define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0 ++#define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2 ++#define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1 ++#define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1 ++#define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0 ++#define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2 ++#define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1 ++#define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1 ++#define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0 ++#define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2 ++#define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1 ++#define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1 ++#define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0 ++#define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2 ++#define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1 ++#define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1 ++#define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0 ++#define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2 ++#define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1 ++#define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1 ++#define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0 ++#define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2 ++#define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1 ++#define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1 ++#define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0 ++#define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2 ++#define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1 ++#define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2 ++#define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc ++#define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2 ++#define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1 ++#define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0 ++#define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1 ++#define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0 ++#define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2 ++#define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1 ++#define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4 ++#define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2 ++#define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8 ++#define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3 ++#define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10 ++#define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4 ++#define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20 ++#define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5 ++#define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40 ++#define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6 ++#define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80 ++#define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7 ++#define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100 ++#define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8 ++#define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200 ++#define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9 ++#define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400 ++#define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa ++#define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800 ++#define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb ++#define GPU_GARLIC_FLUSH_REQ__SDMA2_MASK 0x1000 ++#define GPU_GARLIC_FLUSH_REQ__SDMA2__SHIFT 0xc ++#define GPU_GARLIC_FLUSH_REQ__SDMA3_MASK 0x2000 ++#define GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT 0xd ++#define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1 ++#define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0 ++#define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2 ++#define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1 ++#define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4 ++#define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2 ++#define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8 ++#define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3 ++#define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10 ++#define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4 ++#define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20 ++#define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5 ++#define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40 ++#define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6 ++#define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80 ++#define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7 ++#define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100 ++#define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8 ++#define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200 ++#define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9 ++#define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400 ++#define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa ++#define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800 ++#define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb ++#define GPU_GARLIC_FLUSH_DONE__SDMA2_MASK 0x1000 ++#define GPU_GARLIC_FLUSH_DONE__SDMA2__SHIFT 0xc ++#define GPU_GARLIC_FLUSH_DONE__SDMA3_MASK 0x2000 ++#define GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT 0xd ++#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS__SHIFT 0x2 ++#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x7fffc ++#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 ++#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x7fffc ++#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 ++#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff ++#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 ++#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff ++#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 ++#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff ++#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 ++#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff ++#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 ++#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff ++#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 ++#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff ++#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 ++#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff ++#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 ++#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff ++#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 ++#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff ++#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 ++#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff ++#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 ++#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff ++#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 ++#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff ++#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 ++#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff ++#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 ++#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff ++#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 ++#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff ++#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 ++#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff ++#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 ++#define BIF_RB_CNTL__RB_ENABLE_MASK 0x1 ++#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define BIF_RB_CNTL__RB_SIZE_MASK 0x3e ++#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 ++#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 ++#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00 ++#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 ++#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x20000 ++#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 ++#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 ++#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f ++#define BIF_RB_BASE__ADDR_MASK 0xffffffff ++#define BIF_RB_BASE__ADDR__SHIFT 0x0 ++#define BIF_RB_RPTR__OFFSET_MASK 0x3fffc ++#define BIF_RB_RPTR__OFFSET__SHIFT 0x2 ++#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x1 ++#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 ++#define BIF_RB_WPTR__OFFSET_MASK 0x3fffc ++#define BIF_RB_WPTR__OFFSET__SHIFT 0x2 ++#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0xff ++#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc ++#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define VENDOR_ID__VENDOR_ID_MASK 0xffff ++#define VENDOR_ID__VENDOR_ID__SHIFT 0x0 ++#define DEVICE_ID__DEVICE_ID_MASK 0xffff ++#define DEVICE_ID__DEVICE_ID__SHIFT 0x0 ++#define COMMAND__IO_ACCESS_EN_MASK 0x1 ++#define COMMAND__IO_ACCESS_EN__SHIFT 0x0 ++#define COMMAND__MEM_ACCESS_EN_MASK 0x2 ++#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1 ++#define COMMAND__BUS_MASTER_EN_MASK 0x4 ++#define COMMAND__BUS_MASTER_EN__SHIFT 0x2 ++#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 ++#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 ++#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 ++#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 ++#define COMMAND__PAL_SNOOP_EN_MASK 0x20 ++#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5 ++#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 ++#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 ++#define COMMAND__AD_STEPPING_MASK 0x80 ++#define COMMAND__AD_STEPPING__SHIFT 0x7 ++#define COMMAND__SERR_EN_MASK 0x100 ++#define COMMAND__SERR_EN__SHIFT 0x8 ++#define COMMAND__FAST_B2B_EN_MASK 0x200 ++#define COMMAND__FAST_B2B_EN__SHIFT 0x9 ++#define COMMAND__INT_DIS_MASK 0x400 ++#define COMMAND__INT_DIS__SHIFT 0xa ++#define STATUS__INT_STATUS_MASK 0x8 ++#define STATUS__INT_STATUS__SHIFT 0x3 ++#define STATUS__CAP_LIST_MASK 0x10 ++#define STATUS__CAP_LIST__SHIFT 0x4 ++#define STATUS__PCI_66_EN_MASK 0x20 ++#define STATUS__PCI_66_EN__SHIFT 0x5 ++#define STATUS__FAST_BACK_CAPABLE_MASK 0x80 ++#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 ++#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100 ++#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 ++#define STATUS__DEVSEL_TIMING_MASK 0x600 ++#define STATUS__DEVSEL_TIMING__SHIFT 0x9 ++#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800 ++#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb ++#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000 ++#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc ++#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000 ++#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd ++#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000 ++#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe ++#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000 ++#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf ++#define REVISION_ID__MINOR_REV_ID_MASK 0xf ++#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0 ++#define REVISION_ID__MAJOR_REV_ID_MASK 0xf0 ++#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 ++#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff ++#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 ++#define SUB_CLASS__SUB_CLASS_MASK 0xff ++#define SUB_CLASS__SUB_CLASS__SHIFT 0x0 ++#define BASE_CLASS__BASE_CLASS_MASK 0xff ++#define BASE_CLASS__BASE_CLASS__SHIFT 0x0 ++#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff ++#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 ++#define LATENCY__LATENCY_TIMER_MASK 0xff ++#define LATENCY__LATENCY_TIMER__SHIFT 0x0 ++#define HEADER__HEADER_TYPE_MASK 0x7f ++#define HEADER__HEADER_TYPE__SHIFT 0x0 ++#define HEADER__DEVICE_TYPE_MASK 0x80 ++#define HEADER__DEVICE_TYPE__SHIFT 0x7 ++#define BIST__BIST_COMP_MASK 0xf ++#define BIST__BIST_COMP__SHIFT 0x0 ++#define BIST__BIST_STRT_MASK 0x40 ++#define BIST__BIST_STRT__SHIFT 0x6 ++#define BIST__BIST_CAP_MASK 0x80 ++#define BIST__BIST_CAP__SHIFT 0x7 ++#define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff ++#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 ++#define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff ++#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 ++#define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff ++#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 ++#define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff ++#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 ++#define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff ++#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 ++#define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff ++#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 ++#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff ++#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 ++#define CAP_PTR__CAP_PTR_MASK 0xff ++#define CAP_PTR__CAP_PTR__SHIFT 0x0 ++#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff ++#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 ++#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff ++#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 ++#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff ++#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000 ++#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 ++#define MIN_GRANT__MIN_GNT_MASK 0xff ++#define MIN_GRANT__MIN_GNT__SHIFT 0x0 ++#define MAX_LATENCY__MAX_LAT_MASK 0xff ++#define MAX_LATENCY__MAX_LAT__SHIFT 0x0 ++#define VENDOR_CAP_LIST__CAP_ID_MASK 0xff ++#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000 ++#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 ++#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff ++#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000 ++#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 ++#define PMI_CAP_LIST__CAP_ID_MASK 0xff ++#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define PMI_CAP__VERSION_MASK 0x7 ++#define PMI_CAP__VERSION__SHIFT 0x0 ++#define PMI_CAP__PME_CLOCK_MASK 0x8 ++#define PMI_CAP__PME_CLOCK__SHIFT 0x3 ++#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20 ++#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 ++#define PMI_CAP__AUX_CURRENT_MASK 0x1c0 ++#define PMI_CAP__AUX_CURRENT__SHIFT 0x6 ++#define PMI_CAP__D1_SUPPORT_MASK 0x200 ++#define PMI_CAP__D1_SUPPORT__SHIFT 0x9 ++#define PMI_CAP__D2_SUPPORT_MASK 0x400 ++#define PMI_CAP__D2_SUPPORT__SHIFT 0xa ++#define PMI_CAP__PME_SUPPORT_MASK 0xf800 ++#define PMI_CAP__PME_SUPPORT__SHIFT 0xb ++#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 ++#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 ++#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 ++#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 ++#define PMI_STATUS_CNTL__PME_EN_MASK 0x100 ++#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 ++#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 ++#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 ++#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 ++#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd ++#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 ++#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf ++#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 ++#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 ++#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 ++#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 ++#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 ++#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 ++#define PCIE_CAP_LIST__CAP_ID_MASK 0xff ++#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define PCIE_CAP__VERSION_MASK 0xf ++#define PCIE_CAP__VERSION__SHIFT 0x0 ++#define PCIE_CAP__DEVICE_TYPE_MASK 0xf0 ++#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 ++#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100 ++#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 ++#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00 ++#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 ++#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 ++#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 ++#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 ++#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 ++#define DEVICE_CAP__EXTENDED_TAG_MASK 0x20 ++#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 ++#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 ++#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 ++#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 ++#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 ++#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 ++#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf ++#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 ++#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 ++#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 ++#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a ++#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 ++#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c ++#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 ++#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 ++#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 ++#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 ++#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 ++#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 ++#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 ++#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 ++#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 ++#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 ++#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 ++#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 ++#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 ++#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 ++#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 ++#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 ++#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 ++#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa ++#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 ++#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb ++#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 ++#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc ++#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000 ++#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf ++#define DEVICE_STATUS__CORR_ERR_MASK 0x1 ++#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0 ++#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2 ++#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 ++#define DEVICE_STATUS__FATAL_ERR_MASK 0x4 ++#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 ++#define DEVICE_STATUS__USR_DETECTED_MASK 0x8 ++#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 ++#define DEVICE_STATUS__AUX_PWR_MASK 0x10 ++#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4 ++#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20 ++#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 ++#define LINK_CAP__LINK_SPEED_MASK 0xf ++#define LINK_CAP__LINK_SPEED__SHIFT 0x0 ++#define LINK_CAP__LINK_WIDTH_MASK 0x3f0 ++#define LINK_CAP__LINK_WIDTH__SHIFT 0x4 ++#define LINK_CAP__PM_SUPPORT_MASK 0xc00 ++#define LINK_CAP__PM_SUPPORT__SHIFT 0xa ++#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 ++#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc ++#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 ++#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf ++#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 ++#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 ++#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 ++#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 ++#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 ++#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 ++#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 ++#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 ++#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 ++#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 ++#define LINK_CAP__PORT_NUMBER_MASK 0xff000000 ++#define LINK_CAP__PORT_NUMBER__SHIFT 0x18 ++#define LINK_CNTL__PM_CONTROL_MASK 0x3 ++#define LINK_CNTL__PM_CONTROL__SHIFT 0x0 ++#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 ++#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 ++#define LINK_CNTL__LINK_DIS_MASK 0x10 ++#define LINK_CNTL__LINK_DIS__SHIFT 0x4 ++#define LINK_CNTL__RETRAIN_LINK_MASK 0x20 ++#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 ++#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 ++#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 ++#define LINK_CNTL__EXTENDED_SYNC_MASK 0x80 ++#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 ++#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 ++#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 ++#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 ++#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 ++#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 ++#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa ++#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 ++#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb ++#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf ++#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 ++#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0 ++#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 ++#define LINK_STATUS__LINK_TRAINING_MASK 0x800 ++#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb ++#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000 ++#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc ++#define LINK_STATUS__DL_ACTIVE_MASK 0x2000 ++#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd ++#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000 ++#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe ++#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000 ++#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf ++#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf ++#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 ++#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 ++#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 ++#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 ++#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 ++#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 ++#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa ++#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 ++#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb ++#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 ++#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc ++#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 ++#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 ++#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 ++#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 ++#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 ++#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 ++#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 ++#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 ++#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf ++#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 ++#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 ++#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 ++#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 ++#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 ++#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 ++#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 ++#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 ++#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 ++#define DEVICE_CNTL2__LTR_EN_MASK 0x400 ++#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa ++#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000 ++#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd ++#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 ++#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf ++#define DEVICE_STATUS2__RESERVED_MASK 0xffff ++#define DEVICE_STATUS2__RESERVED__SHIFT 0x0 ++#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe ++#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 ++#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 ++#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 ++#define LINK_CAP2__RESERVED_MASK 0xfffffe00 ++#define LINK_CAP2__RESERVED__SHIFT 0x9 ++#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf ++#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 ++#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 ++#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 ++#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 ++#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 ++#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 ++#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 ++#define LINK_CNTL2__XMIT_MARGIN_MASK 0x380 ++#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 ++#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 ++#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa ++#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 ++#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb ++#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 ++#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc ++#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1 ++#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 ++#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2 ++#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 ++#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4 ++#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 ++#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8 ++#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 ++#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10 ++#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 ++#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20 ++#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 ++#define MSI_CAP_LIST__CAP_ID_MASK 0xff ++#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define MSI_MSG_CNTL__MSI_EN_MASK 0x1 ++#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 ++#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe ++#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 ++#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70 ++#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 ++#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80 ++#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 ++#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc ++#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 ++#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff ++#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 ++#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff ++#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 ++#define MSI_MSG_DATA__MSI_DATA_MASK 0xffff ++#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff ++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 ++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 ++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 ++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 ++#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff ++#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff ++#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 ++#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 ++#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 ++#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 ++#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 ++#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 ++#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 ++#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 ++#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa ++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff ++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 ++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 ++#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 ++#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe ++#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 ++#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1 ++#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 ++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 ++#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 ++#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 ++#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 ++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1 ++#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 ++#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2 ++#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 ++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff ++#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 ++#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff ++#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 ++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 ++#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 ++#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 ++#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 ++#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 ++#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc ++#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 ++#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd ++#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 ++#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe ++#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 ++#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf ++#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 ++#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 ++#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 ++#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 ++#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 ++#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 ++#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 ++#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 ++#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 ++#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 ++#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 ++#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 ++#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 ++#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 ++#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 ++#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 ++#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 ++#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 ++#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 ++#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 ++#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 ++#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 ++#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 ++#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 ++#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 ++#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc ++#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 ++#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd ++#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 ++#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe ++#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 ++#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf ++#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 ++#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 ++#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 ++#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 ++#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 ++#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 ++#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 ++#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 ++#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 ++#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 ++#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 ++#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 ++#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 ++#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 ++#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 ++#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 ++#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 ++#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 ++#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 ++#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 ++#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 ++#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 ++#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 ++#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 ++#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 ++#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc ++#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 ++#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd ++#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 ++#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe ++#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 ++#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf ++#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 ++#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 ++#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 ++#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 ++#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 ++#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 ++#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 ++#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 ++#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 ++#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 ++#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 ++#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 ++#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 ++#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 ++#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 ++#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 ++#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 ++#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 ++#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 ++#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 ++#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 ++#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 ++#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 ++#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 ++#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 ++#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 ++#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 ++#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 ++#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 ++#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc ++#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 ++#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd ++#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 ++#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe ++#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 ++#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf ++#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 ++#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 ++#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 ++#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 ++#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 ++#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 ++#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 ++#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 ++#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 ++#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc ++#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 ++#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd ++#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 ++#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe ++#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 ++#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf ++#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f ++#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 ++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 ++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 ++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 ++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa ++#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 ++#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb ++#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff ++#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 ++#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff ++#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 ++#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff ++#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 ++#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff ++#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 ++#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff ++#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 ++#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff ++#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 ++#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff ++#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 ++#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff ++#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 ++#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 ++#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 ++#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7 ++#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 ++#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0 ++#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 ++#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00 ++#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 ++#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 ++#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 ++#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7 ++#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 ++#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0 ++#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 ++#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00 ++#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 ++#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 ++#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 ++#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7 ++#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 ++#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0 ++#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 ++#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00 ++#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 ++#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 ++#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 ++#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7 ++#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 ++#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0 ++#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 ++#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00 ++#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 ++#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 ++#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 ++#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7 ++#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 ++#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0 ++#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 ++#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00 ++#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 ++#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0 ++#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 ++#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7 ++#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 ++#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0 ++#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 ++#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00 ++#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 ++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff ++#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 ++#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff ++#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 ++#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300 ++#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 ++#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00 ++#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa ++#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000 ++#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd ++#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000 ++#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf ++#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000 ++#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 ++#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1 ++#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 ++#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f ++#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 ++#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 ++#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 ++#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 ++#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc ++#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 ++#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 ++#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 ++#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 ++#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff ++#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 ++#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f ++#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 ++#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100 ++#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 ++#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f ++#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 ++#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 ++#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 ++#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 ++#define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc ++#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 ++#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff ++#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 ++#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 ++#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 ++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 ++#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 ++#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 ++#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 ++#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 ++#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 ++#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 ++#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 ++#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 ++#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 ++#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 ++#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 ++#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 ++#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 ++#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 ++#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 ++#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1 ++#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 ++#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2 ++#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 ++#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4 ++#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 ++#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8 ++#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 ++#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10 ++#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 ++#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20 ++#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 ++#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40 ++#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 ++#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f ++#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 ++#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20 ++#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 ++#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40 ++#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 ++#define PCIE_ATS_CNTL__STU_MASK 0x1f ++#define PCIE_ATS_CNTL__STU__SHIFT 0x0 ++#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000 ++#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf ++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1 ++#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 ++#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2 ++#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 ++#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1 ++#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 ++#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2 ++#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 ++#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100 ++#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 ++#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000 ++#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf ++#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff ++#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 ++#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff ++#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 ++#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2 ++#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 ++#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4 ++#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 ++#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00 ++#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 ++#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1 ++#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 ++#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2 ++#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 ++#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4 ++#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 ++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 ++#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7 ++#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 ++#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300 ++#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 ++#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f ++#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 ++#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00 ++#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 ++#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 ++#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf ++#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f ++#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 ++#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000 ++#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf ++#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f ++#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 ++#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 ++#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc ++#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff ++#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 ++#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff ++#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 ++#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff ++#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 ++#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff ++#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 ++#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff ++#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 ++#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff ++#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 ++#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff ++#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 ++#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff ++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 ++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00 ++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa ++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000 ++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 ++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000 ++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a ++#define MM_INDEX_IND__MM_OFFSET_MASK 0x7fffffff ++#define MM_INDEX_IND__MM_OFFSET__SHIFT 0x0 ++#define MM_INDEX_IND__MM_APER_MASK 0x80000000 ++#define MM_INDEX_IND__MM_APER__SHIFT 0x1f ++#define MM_INDEX_HI_IND__MM_OFFSET_HI_MASK 0xffffffff ++#define MM_INDEX_HI_IND__MM_OFFSET_HI__SHIFT 0x0 ++#define MM_DATA_IND__MM_DATA_MASK 0xffffffff ++#define MM_DATA_IND__MM_DATA__SHIFT 0x0 ++#define BIF_MM_INDACCESS_CNTL_IND__MM_INDACCESS_DIS_MASK 0x2 ++#define BIF_MM_INDACCESS_CNTL_IND__MM_INDACCESS_DIS__SHIFT 0x1 ++#define BUS_CNTL_IND__BIOS_ROM_WRT_EN_MASK 0x1 ++#define BUS_CNTL_IND__BIOS_ROM_WRT_EN__SHIFT 0x0 ++#define BUS_CNTL_IND__BIOS_ROM_DIS_MASK 0x2 ++#define BUS_CNTL_IND__BIOS_ROM_DIS__SHIFT 0x1 ++#define BUS_CNTL_IND__PMI_IO_DIS_MASK 0x4 ++#define BUS_CNTL_IND__PMI_IO_DIS__SHIFT 0x2 ++#define BUS_CNTL_IND__PMI_MEM_DIS_MASK 0x8 ++#define BUS_CNTL_IND__PMI_MEM_DIS__SHIFT 0x3 ++#define BUS_CNTL_IND__PMI_BM_DIS_MASK 0x10 ++#define BUS_CNTL_IND__PMI_BM_DIS__SHIFT 0x4 ++#define BUS_CNTL_IND__PMI_INT_DIS_MASK 0x20 ++#define BUS_CNTL_IND__PMI_INT_DIS__SHIFT 0x5 ++#define BUS_CNTL_IND__VGA_REG_COHERENCY_DIS_MASK 0x40 ++#define BUS_CNTL_IND__VGA_REG_COHERENCY_DIS__SHIFT 0x6 ++#define BUS_CNTL_IND__VGA_MEM_COHERENCY_DIS_MASK 0x80 ++#define BUS_CNTL_IND__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 ++#define BUS_CNTL_IND__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100 ++#define BUS_CNTL_IND__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8 ++#define BUS_CNTL_IND__SET_AZ_TC_MASK 0x1c00 ++#define BUS_CNTL_IND__SET_AZ_TC__SHIFT 0xa ++#define BUS_CNTL_IND__SET_MC_TC_MASK 0xe000 ++#define BUS_CNTL_IND__SET_MC_TC__SHIFT 0xd ++#define BUS_CNTL_IND__ZERO_BE_WR_EN_MASK 0x10000 ++#define BUS_CNTL_IND__ZERO_BE_WR_EN__SHIFT 0x10 ++#define BUS_CNTL_IND__ZERO_BE_RD_EN_MASK 0x20000 ++#define BUS_CNTL_IND__ZERO_BE_RD_EN__SHIFT 0x11 ++#define BUS_CNTL_IND__RD_STALL_IO_WR_MASK 0x40000 ++#define BUS_CNTL_IND__RD_STALL_IO_WR__SHIFT 0x12 ++#define CONFIG_CNTL_IND__CFG_VGA_RAM_EN_MASK 0x1 ++#define CONFIG_CNTL_IND__CFG_VGA_RAM_EN__SHIFT 0x0 ++#define CONFIG_CNTL_IND__VGA_DIS_MASK 0x2 ++#define CONFIG_CNTL_IND__VGA_DIS__SHIFT 0x1 ++#define CONFIG_CNTL_IND__GENMO_MONO_ADDRESS_B_MASK 0x4 ++#define CONFIG_CNTL_IND__GENMO_MONO_ADDRESS_B__SHIFT 0x2 ++#define CONFIG_CNTL_IND__GRPH_ADRSEL_MASK 0x18 ++#define CONFIG_CNTL_IND__GRPH_ADRSEL__SHIFT 0x3 ++#define CONFIG_MEMSIZE_IND__CONFIG_MEMSIZE_MASK 0xffffffff ++#define CONFIG_MEMSIZE_IND__CONFIG_MEMSIZE__SHIFT 0x0 ++#define CONFIG_F0_BASE_IND__F0_BASE_MASK 0xffffffff ++#define CONFIG_F0_BASE_IND__F0_BASE__SHIFT 0x0 ++#define CONFIG_APER_SIZE_IND__APER_SIZE_MASK 0xffffffff ++#define CONFIG_APER_SIZE_IND__APER_SIZE__SHIFT 0x0 ++#define CONFIG_REG_APER_SIZE_IND__REG_APER_SIZE_MASK 0xfffff ++#define CONFIG_REG_APER_SIZE_IND__REG_APER_SIZE__SHIFT 0x0 ++#define BIF_SCRATCH0_IND__BIF_SCRATCH0_MASK 0xffffffff ++#define BIF_SCRATCH0_IND__BIF_SCRATCH0__SHIFT 0x0 ++#define BIF_SCRATCH1_IND__BIF_SCRATCH1_MASK 0xffffffff ++#define BIF_SCRATCH1_IND__BIF_SCRATCH1__SHIFT 0x0 ++#define BX_RESET_EN_IND__COR_RESET_EN_MASK 0x1 ++#define BX_RESET_EN_IND__COR_RESET_EN__SHIFT 0x0 ++#define BX_RESET_EN_IND__REG_RESET_EN_MASK 0x2 ++#define BX_RESET_EN_IND__REG_RESET_EN__SHIFT 0x1 ++#define BX_RESET_EN_IND__STY_RESET_EN_MASK 0x4 ++#define BX_RESET_EN_IND__STY_RESET_EN__SHIFT 0x2 ++#define MM_CFGREGS_CNTL_IND__MM_CFG_FUNC_SEL_MASK 0x7 ++#define MM_CFGREGS_CNTL_IND__MM_CFG_FUNC_SEL__SHIFT 0x0 ++#define MM_CFGREGS_CNTL_IND__MM_WR_TO_CFG_EN_MASK 0x8 ++#define MM_CFGREGS_CNTL_IND__MM_WR_TO_CFG_EN__SHIFT 0x3 ++#define HW_DEBUG_IND__HW_00_DEBUG_MASK 0x1 ++#define HW_DEBUG_IND__HW_00_DEBUG__SHIFT 0x0 ++#define HW_DEBUG_IND__HW_01_DEBUG_MASK 0x2 ++#define HW_DEBUG_IND__HW_01_DEBUG__SHIFT 0x1 ++#define HW_DEBUG_IND__HW_02_DEBUG_MASK 0x4 ++#define HW_DEBUG_IND__HW_02_DEBUG__SHIFT 0x2 ++#define HW_DEBUG_IND__HW_03_DEBUG_MASK 0x8 ++#define HW_DEBUG_IND__HW_03_DEBUG__SHIFT 0x3 ++#define HW_DEBUG_IND__HW_04_DEBUG_MASK 0x10 ++#define HW_DEBUG_IND__HW_04_DEBUG__SHIFT 0x4 ++#define HW_DEBUG_IND__HW_05_DEBUG_MASK 0x20 ++#define HW_DEBUG_IND__HW_05_DEBUG__SHIFT 0x5 ++#define HW_DEBUG_IND__HW_06_DEBUG_MASK 0x40 ++#define HW_DEBUG_IND__HW_06_DEBUG__SHIFT 0x6 ++#define HW_DEBUG_IND__HW_07_DEBUG_MASK 0x80 ++#define HW_DEBUG_IND__HW_07_DEBUG__SHIFT 0x7 ++#define HW_DEBUG_IND__HW_08_DEBUG_MASK 0x100 ++#define HW_DEBUG_IND__HW_08_DEBUG__SHIFT 0x8 ++#define HW_DEBUG_IND__HW_09_DEBUG_MASK 0x200 ++#define HW_DEBUG_IND__HW_09_DEBUG__SHIFT 0x9 ++#define HW_DEBUG_IND__HW_10_DEBUG_MASK 0x400 ++#define HW_DEBUG_IND__HW_10_DEBUG__SHIFT 0xa ++#define HW_DEBUG_IND__HW_11_DEBUG_MASK 0x800 ++#define HW_DEBUG_IND__HW_11_DEBUG__SHIFT 0xb ++#define HW_DEBUG_IND__HW_12_DEBUG_MASK 0x1000 ++#define HW_DEBUG_IND__HW_12_DEBUG__SHIFT 0xc ++#define HW_DEBUG_IND__HW_13_DEBUG_MASK 0x2000 ++#define HW_DEBUG_IND__HW_13_DEBUG__SHIFT 0xd ++#define HW_DEBUG_IND__HW_14_DEBUG_MASK 0x4000 ++#define HW_DEBUG_IND__HW_14_DEBUG__SHIFT 0xe ++#define HW_DEBUG_IND__HW_15_DEBUG_MASK 0x8000 ++#define HW_DEBUG_IND__HW_15_DEBUG__SHIFT 0xf ++#define HW_DEBUG_IND__HW_16_DEBUG_MASK 0x10000 ++#define HW_DEBUG_IND__HW_16_DEBUG__SHIFT 0x10 ++#define HW_DEBUG_IND__HW_17_DEBUG_MASK 0x20000 ++#define HW_DEBUG_IND__HW_17_DEBUG__SHIFT 0x11 ++#define HW_DEBUG_IND__HW_18_DEBUG_MASK 0x40000 ++#define HW_DEBUG_IND__HW_18_DEBUG__SHIFT 0x12 ++#define HW_DEBUG_IND__HW_19_DEBUG_MASK 0x80000 ++#define HW_DEBUG_IND__HW_19_DEBUG__SHIFT 0x13 ++#define HW_DEBUG_IND__HW_20_DEBUG_MASK 0x100000 ++#define HW_DEBUG_IND__HW_20_DEBUG__SHIFT 0x14 ++#define HW_DEBUG_IND__HW_21_DEBUG_MASK 0x200000 ++#define HW_DEBUG_IND__HW_21_DEBUG__SHIFT 0x15 ++#define HW_DEBUG_IND__HW_22_DEBUG_MASK 0x400000 ++#define HW_DEBUG_IND__HW_22_DEBUG__SHIFT 0x16 ++#define HW_DEBUG_IND__HW_23_DEBUG_MASK 0x800000 ++#define HW_DEBUG_IND__HW_23_DEBUG__SHIFT 0x17 ++#define HW_DEBUG_IND__HW_24_DEBUG_MASK 0x1000000 ++#define HW_DEBUG_IND__HW_24_DEBUG__SHIFT 0x18 ++#define HW_DEBUG_IND__HW_25_DEBUG_MASK 0x2000000 ++#define HW_DEBUG_IND__HW_25_DEBUG__SHIFT 0x19 ++#define HW_DEBUG_IND__HW_26_DEBUG_MASK 0x4000000 ++#define HW_DEBUG_IND__HW_26_DEBUG__SHIFT 0x1a ++#define HW_DEBUG_IND__HW_27_DEBUG_MASK 0x8000000 ++#define HW_DEBUG_IND__HW_27_DEBUG__SHIFT 0x1b ++#define HW_DEBUG_IND__HW_28_DEBUG_MASK 0x10000000 ++#define HW_DEBUG_IND__HW_28_DEBUG__SHIFT 0x1c ++#define HW_DEBUG_IND__HW_29_DEBUG_MASK 0x20000000 ++#define HW_DEBUG_IND__HW_29_DEBUG__SHIFT 0x1d ++#define HW_DEBUG_IND__HW_30_DEBUG_MASK 0x40000000 ++#define HW_DEBUG_IND__HW_30_DEBUG__SHIFT 0x1e ++#define HW_DEBUG_IND__HW_31_DEBUG_MASK 0x80000000 ++#define HW_DEBUG_IND__HW_31_DEBUG__SHIFT 0x1f ++#define MASTER_CREDIT_CNTL_IND__BIF_MC_RDRET_CREDIT_MASK 0x7f ++#define MASTER_CREDIT_CNTL_IND__BIF_MC_RDRET_CREDIT__SHIFT 0x0 ++#define MASTER_CREDIT_CNTL_IND__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000 ++#define MASTER_CREDIT_CNTL_IND__BIF_AZ_RDRET_CREDIT__SHIFT 0x10 ++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_SRBM_REQ_CREDIT_MASK 0x1f ++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_SRBM_REQ_CREDIT__SHIFT 0x0 ++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_VGA_REQ_CREDIT_MASK 0x1e0 ++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_VGA_REQ_CREDIT__SHIFT 0x5 ++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_HDP_REQ_CREDIT_MASK 0x7c00 ++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_HDP_REQ_CREDIT__SHIFT 0xa ++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_ROM_REQ_CREDIT_MASK 0x8000 ++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_ROM_REQ_CREDIT__SHIFT 0xf ++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_AZ_REQ_CREDIT_MASK 0x100000 ++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_AZ_REQ_CREDIT__SHIFT 0x14 ++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000 ++#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_XDMA_REQ_CREDIT__SHIFT 0x19 ++#define BX_RESET_CNTL_IND__LINK_TRAIN_EN_MASK 0x1 ++#define BX_RESET_CNTL_IND__LINK_TRAIN_EN__SHIFT 0x0 ++#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_OVERRIDE_MASK 0x1 ++#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 ++#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_EN_MASK 0x2 ++#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_EN__SHIFT 0x1 ++#define INTERRUPT_CNTL_IND__IH_REQ_NONSNOOP_EN_MASK 0x8 ++#define INTERRUPT_CNTL_IND__IH_REQ_NONSNOOP_EN__SHIFT 0x3 ++#define INTERRUPT_CNTL_IND__IH_INTR_DLY_CNTR_MASK 0xf0 ++#define INTERRUPT_CNTL_IND__IH_INTR_DLY_CNTR__SHIFT 0x4 ++#define INTERRUPT_CNTL_IND__GEN_IH_INT_EN_MASK 0x100 ++#define INTERRUPT_CNTL_IND__GEN_IH_INT_EN__SHIFT 0x8 ++#define INTERRUPT_CNTL_IND__GEN_GPIO_INT_EN_MASK 0x1e00 ++#define INTERRUPT_CNTL_IND__GEN_GPIO_INT_EN__SHIFT 0x9 ++#define INTERRUPT_CNTL_IND__SELECT_INT_GPIO_OUTPUT_MASK 0x6000 ++#define INTERRUPT_CNTL_IND__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd ++#define INTERRUPT_CNTL_IND__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000 ++#define INTERRUPT_CNTL_IND__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf ++#define INTERRUPT_CNTL2_IND__IH_DUMMY_RD_ADDR_MASK 0xffffffff ++#define INTERRUPT_CNTL2_IND__IH_DUMMY_RD_ADDR__SHIFT 0x0 ++#define BIF_DEBUG_CNTL_IND__DEBUG_EN_MASK 0x1 ++#define BIF_DEBUG_CNTL_IND__DEBUG_EN__SHIFT 0x0 ++#define BIF_DEBUG_CNTL_IND__DEBUG_MULTIBLOCKEN_MASK 0x2 ++#define BIF_DEBUG_CNTL_IND__DEBUG_MULTIBLOCKEN__SHIFT 0x1 ++#define BIF_DEBUG_CNTL_IND__DEBUG_OUT_EN_MASK 0x4 ++#define BIF_DEBUG_CNTL_IND__DEBUG_OUT_EN__SHIFT 0x2 ++#define BIF_DEBUG_CNTL_IND__DEBUG_PAD_SEL_MASK 0x8 ++#define BIF_DEBUG_CNTL_IND__DEBUG_PAD_SEL__SHIFT 0x3 ++#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK1_MASK 0x10 ++#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK1__SHIFT 0x4 ++#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK2_MASK 0x20 ++#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK2__SHIFT 0x5 ++#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_EN_MASK 0x40 ++#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_EN__SHIFT 0x6 ++#define BIF_DEBUG_CNTL_IND__DEBUG_SWAP_MASK 0x80 ++#define BIF_DEBUG_CNTL_IND__DEBUG_SWAP__SHIFT 0x7 ++#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK1_MASK 0x1f00 ++#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK1__SHIFT 0x8 ++#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK2_MASK 0x1f0000 ++#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK2__SHIFT 0x10 ++#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_XSP_MASK 0x1000000 ++#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_XSP__SHIFT 0x18 ++#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_CLKSEL_MASK 0xc0000000 ++#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_CLKSEL__SHIFT 0x1e ++#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK1_MASK 0x3f ++#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK1__SHIFT 0x0 ++#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK2_MASK 0x3f00 ++#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK2__SHIFT 0x8 ++#define BIF_DEBUG_OUT_IND__DEBUG_OUTPUT_MASK 0x1ffff ++#define BIF_DEBUG_OUT_IND__DEBUG_OUTPUT__SHIFT 0x0 ++#define HDP_REG_COHERENCY_FLUSH_CNTL_IND__HDP_REG_FLUSH_ADDR_MASK 0x1 ++#define HDP_REG_COHERENCY_FLUSH_CNTL_IND__HDP_REG_FLUSH_ADDR__SHIFT 0x0 ++#define HDP_MEM_COHERENCY_FLUSH_CNTL_IND__HDP_MEM_FLUSH_ADDR_MASK 0x1 ++#define HDP_MEM_COHERENCY_FLUSH_CNTL_IND__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_A_MASK 0x1 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_A__SHIFT 0x0 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SEL_MASK 0x2 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SEL__SHIFT 0x1 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_MODE_MASK 0x4 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_MODE__SHIFT 0x2 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SPARE_MASK 0x18 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SPARE__SHIFT 0x3 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN0_MASK 0x20 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN0__SHIFT 0x5 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN1_MASK 0x40 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN1__SHIFT 0x6 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN2_MASK 0x80 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN2__SHIFT 0x7 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN3_MASK 0x100 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN3__SHIFT 0x8 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SLEWN_MASK 0x200 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SLEWN__SHIFT 0x9 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_WAKE_MASK 0x400 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_WAKE__SHIFT 0xa ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SCHMEN_MASK 0x800 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SCHMEN__SHIFT 0xb ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_CNTL_EN_MASK 0x1000 ++#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_CNTL_EN__SHIFT 0xc ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_A_MASK 0x1 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_A__SHIFT 0x0 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SEL_MASK 0x2 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SEL__SHIFT 0x1 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_MODE_MASK 0x4 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_MODE__SHIFT 0x2 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SPARE_MASK 0x18 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SPARE__SHIFT 0x3 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN0_MASK 0x20 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN0__SHIFT 0x5 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN1_MASK 0x40 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN1__SHIFT 0x6 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN2_MASK 0x80 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN2__SHIFT 0x7 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN3_MASK 0x100 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN3__SHIFT 0x8 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SLEWN_MASK 0x200 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SLEWN__SHIFT 0x9 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_WAKE_MASK 0x400 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_WAKE__SHIFT 0xa ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SCHMEN_MASK 0x800 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SCHMEN__SHIFT 0xb ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_CNTL_EN_MASK 0x1000 ++#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_CNTL_EN__SHIFT 0xc ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_A_MASK 0x1 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_A__SHIFT 0x0 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SEL_MASK 0x2 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SEL__SHIFT 0x1 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_MODE_MASK 0x4 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_MODE__SHIFT 0x2 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SPARE_MASK 0x18 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SPARE__SHIFT 0x3 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN0_MASK 0x20 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN0__SHIFT 0x5 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN1_MASK 0x40 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN1__SHIFT 0x6 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN2_MASK 0x80 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN2__SHIFT 0x7 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN3_MASK 0x100 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN3__SHIFT 0x8 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SLEWN_MASK 0x200 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SLEWN__SHIFT 0x9 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_WAKE_MASK 0x400 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_WAKE__SHIFT 0xa ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SCHMEN_MASK 0x800 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SCHMEN__SHIFT 0xb ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_CNTL_EN_MASK 0x1000 ++#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_CNTL_EN__SHIFT 0xc ++#define BIF_XDMA_LO_IND__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff ++#define BIF_XDMA_LO_IND__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 ++#define BIF_XDMA_LO_IND__BIF_XDMA_APER_EN_MASK 0x80000000 ++#define BIF_XDMA_LO_IND__BIF_XDMA_APER_EN__SHIFT 0x1f ++#define BIF_XDMA_HI_IND__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff ++#define BIF_XDMA_HI_IND__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 ++#define BIF_FEATURES_CONTROL_MISC_IND__MST_BIF_REQ_EP_DIS_MASK 0x1 ++#define BIF_FEATURES_CONTROL_MISC_IND__MST_BIF_REQ_EP_DIS__SHIFT 0x0 ++#define BIF_FEATURES_CONTROL_MISC_IND__SLV_BIF_CPL_EP_DIS_MASK 0x2 ++#define BIF_FEATURES_CONTROL_MISC_IND__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 ++#define BIF_FEATURES_CONTROL_MISC_IND__BIF_SLV_REQ_EP_DIS_MASK 0x4 ++#define BIF_FEATURES_CONTROL_MISC_IND__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 ++#define BIF_FEATURES_CONTROL_MISC_IND__BIF_MST_CPL_EP_DIS_MASK 0x8 ++#define BIF_FEATURES_CONTROL_MISC_IND__BIF_MST_CPL_EP_DIS__SHIFT 0x3 ++#define BIF_FEATURES_CONTROL_MISC_IND__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10 ++#define BIF_FEATURES_CONTROL_MISC_IND__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 ++#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20 ++#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 ++#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40 ++#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 ++#define BIF_FEATURES_CONTROL_MISC_IND__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80 ++#define BIF_FEATURES_CONTROL_MISC_IND__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7 ++#define BIF_FEATURES_CONTROL_MISC_IND__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100 ++#define BIF_FEATURES_CONTROL_MISC_IND__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8 ++#define BIF_FEATURES_CONTROL_MISC_IND__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200 ++#define BIF_FEATURES_CONTROL_MISC_IND__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9 ++#define BIF_FEATURES_CONTROL_MISC_IND__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400 ++#define BIF_FEATURES_CONTROL_MISC_IND__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa ++#define BIF_FEATURES_CONTROL_MISC_IND__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800 ++#define BIF_FEATURES_CONTROL_MISC_IND__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb ++#define BIF_FEATURES_CONTROL_MISC_IND__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000 ++#define BIF_FEATURES_CONTROL_MISC_IND__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc ++#define BIF_DOORBELL_CNTL_IND__SELF_RING_DIS_MASK 0x1 ++#define BIF_DOORBELL_CNTL_IND__SELF_RING_DIS__SHIFT 0x0 ++#define BIF_DOORBELL_CNTL_IND__TRANS_CHECK_DIS_MASK 0x2 ++#define BIF_DOORBELL_CNTL_IND__TRANS_CHECK_DIS__SHIFT 0x1 ++#define BIF_DOORBELL_CNTL_IND__UNTRANS_LBACK_EN_MASK 0x4 ++#define BIF_DOORBELL_CNTL_IND__UNTRANS_LBACK_EN__SHIFT 0x2 ++#define BIF_DOORBELL_CNTL_IND__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8 ++#define BIF_DOORBELL_CNTL_IND__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 ++#define BIF_DOORBELL_CNTL_IND__DOORBELL_MONITOR_EN_MASK 0x10 ++#define BIF_DOORBELL_CNTL_IND__DOORBELL_MONITOR_EN__SHIFT 0x4 ++#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_STATUS_MASK 0x20 ++#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5 ++#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000 ++#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 ++#define BIF_SLVARB_MODE_IND__SLVARB_MODE_MASK 0x3 ++#define BIF_SLVARB_MODE_IND__SLVARB_MODE__SHIFT 0x0 ++#define BIF_FB_EN_IND__FB_READ_EN_MASK 0x1 ++#define BIF_FB_EN_IND__FB_READ_EN__SHIFT 0x0 ++#define BIF_FB_EN_IND__FB_WRITE_EN_MASK 0x2 ++#define BIF_FB_EN_IND__FB_WRITE_EN__SHIFT 0x1 ++#define BIF_BUSNUM_CNTL1_IND__ID_MASK_MASK 0xff ++#define BIF_BUSNUM_CNTL1_IND__ID_MASK__SHIFT 0x0 ++#define BIF_BUSNUM_LIST0_IND__ID0_MASK 0xff ++#define BIF_BUSNUM_LIST0_IND__ID0__SHIFT 0x0 ++#define BIF_BUSNUM_LIST0_IND__ID1_MASK 0xff00 ++#define BIF_BUSNUM_LIST0_IND__ID1__SHIFT 0x8 ++#define BIF_BUSNUM_LIST0_IND__ID2_MASK 0xff0000 ++#define BIF_BUSNUM_LIST0_IND__ID2__SHIFT 0x10 ++#define BIF_BUSNUM_LIST0_IND__ID3_MASK 0xff000000 ++#define BIF_BUSNUM_LIST0_IND__ID3__SHIFT 0x18 ++#define BIF_BUSNUM_LIST1_IND__ID4_MASK 0xff ++#define BIF_BUSNUM_LIST1_IND__ID4__SHIFT 0x0 ++#define BIF_BUSNUM_LIST1_IND__ID5_MASK 0xff00 ++#define BIF_BUSNUM_LIST1_IND__ID5__SHIFT 0x8 ++#define BIF_BUSNUM_LIST1_IND__ID6_MASK 0xff0000 ++#define BIF_BUSNUM_LIST1_IND__ID6__SHIFT 0x10 ++#define BIF_BUSNUM_LIST1_IND__ID7_MASK 0xff000000 ++#define BIF_BUSNUM_LIST1_IND__ID7__SHIFT 0x18 ++#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_SEL_MASK 0xff ++#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_SEL__SHIFT 0x0 ++#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_EN_MASK 0x100 ++#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_EN__SHIFT 0x8 ++#define BIF_BUSNUM_CNTL2_IND__HDPREG_CNTL_MASK 0x10000 ++#define BIF_BUSNUM_CNTL2_IND__HDPREG_CNTL__SHIFT 0x10 ++#define BIF_BUSNUM_CNTL2_IND__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000 ++#define BIF_BUSNUM_CNTL2_IND__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 ++#define BIF_BUSY_DELAY_CNTR_IND__DELAY_CNT_MASK 0x3f ++#define BIF_BUSY_DELAY_CNTR_IND__DELAY_CNT__SHIFT 0x0 ++#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_EN_MASK 0x1 ++#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_EN__SHIFT 0x0 ++#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET0_MASK 0x2 ++#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET0__SHIFT 0x1 ++#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET1_MASK 0x4 ++#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET1__SHIFT 0x2 ++#define BIF_PERFMON_CNTL_IND__PERF_SEL0_MASK 0x1f00 ++#define BIF_PERFMON_CNTL_IND__PERF_SEL0__SHIFT 0x8 ++#define BIF_PERFMON_CNTL_IND__PERF_SEL1_MASK 0x3e000 ++#define BIF_PERFMON_CNTL_IND__PERF_SEL1__SHIFT 0xd ++#define BIF_PERFCOUNTER0_RESULT_IND__PERFCOUNTER_RESULT_MASK 0xffffffff ++#define BIF_PERFCOUNTER0_RESULT_IND__PERFCOUNTER_RESULT__SHIFT 0x0 ++#define BIF_PERFCOUNTER1_RESULT_IND__PERFCOUNTER_RESULT_MASK 0xffffffff ++#define BIF_PERFCOUNTER1_RESULT_IND__PERFCOUNTER_RESULT__SHIFT 0x0 ++#define SLAVE_HANG_PROTECTION_CNTL_IND__HANG_PROTECTION_TIMER_SEL_MASK 0xe ++#define SLAVE_HANG_PROTECTION_CNTL_IND__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1 ++#define GPU_HDP_FLUSH_REQ_IND__CP0_MASK 0x1 ++#define GPU_HDP_FLUSH_REQ_IND__CP0__SHIFT 0x0 ++#define GPU_HDP_FLUSH_REQ_IND__CP1_MASK 0x2 ++#define GPU_HDP_FLUSH_REQ_IND__CP1__SHIFT 0x1 ++#define GPU_HDP_FLUSH_REQ_IND__CP2_MASK 0x4 ++#define GPU_HDP_FLUSH_REQ_IND__CP2__SHIFT 0x2 ++#define GPU_HDP_FLUSH_REQ_IND__CP3_MASK 0x8 ++#define GPU_HDP_FLUSH_REQ_IND__CP3__SHIFT 0x3 ++#define GPU_HDP_FLUSH_REQ_IND__CP4_MASK 0x10 ++#define GPU_HDP_FLUSH_REQ_IND__CP4__SHIFT 0x4 ++#define GPU_HDP_FLUSH_REQ_IND__CP5_MASK 0x20 ++#define GPU_HDP_FLUSH_REQ_IND__CP5__SHIFT 0x5 ++#define GPU_HDP_FLUSH_REQ_IND__CP6_MASK 0x40 ++#define GPU_HDP_FLUSH_REQ_IND__CP6__SHIFT 0x6 ++#define GPU_HDP_FLUSH_REQ_IND__CP7_MASK 0x80 ++#define GPU_HDP_FLUSH_REQ_IND__CP7__SHIFT 0x7 ++#define GPU_HDP_FLUSH_REQ_IND__CP8_MASK 0x100 ++#define GPU_HDP_FLUSH_REQ_IND__CP8__SHIFT 0x8 ++#define GPU_HDP_FLUSH_REQ_IND__CP9_MASK 0x200 ++#define GPU_HDP_FLUSH_REQ_IND__CP9__SHIFT 0x9 ++#define GPU_HDP_FLUSH_REQ_IND__SDMA0_MASK 0x400 ++#define GPU_HDP_FLUSH_REQ_IND__SDMA0__SHIFT 0xa ++#define GPU_HDP_FLUSH_REQ_IND__SDMA1_MASK 0x800 ++#define GPU_HDP_FLUSH_REQ_IND__SDMA1__SHIFT 0xb ++#define GPU_HDP_FLUSH_DONE_IND__CP0_MASK 0x1 ++#define GPU_HDP_FLUSH_DONE_IND__CP0__SHIFT 0x0 ++#define GPU_HDP_FLUSH_DONE_IND__CP1_MASK 0x2 ++#define GPU_HDP_FLUSH_DONE_IND__CP1__SHIFT 0x1 ++#define GPU_HDP_FLUSH_DONE_IND__CP2_MASK 0x4 ++#define GPU_HDP_FLUSH_DONE_IND__CP2__SHIFT 0x2 ++#define GPU_HDP_FLUSH_DONE_IND__CP3_MASK 0x8 ++#define GPU_HDP_FLUSH_DONE_IND__CP3__SHIFT 0x3 ++#define GPU_HDP_FLUSH_DONE_IND__CP4_MASK 0x10 ++#define GPU_HDP_FLUSH_DONE_IND__CP4__SHIFT 0x4 ++#define GPU_HDP_FLUSH_DONE_IND__CP5_MASK 0x20 ++#define GPU_HDP_FLUSH_DONE_IND__CP5__SHIFT 0x5 ++#define GPU_HDP_FLUSH_DONE_IND__CP6_MASK 0x40 ++#define GPU_HDP_FLUSH_DONE_IND__CP6__SHIFT 0x6 ++#define GPU_HDP_FLUSH_DONE_IND__CP7_MASK 0x80 ++#define GPU_HDP_FLUSH_DONE_IND__CP7__SHIFT 0x7 ++#define GPU_HDP_FLUSH_DONE_IND__CP8_MASK 0x100 ++#define GPU_HDP_FLUSH_DONE_IND__CP8__SHIFT 0x8 ++#define GPU_HDP_FLUSH_DONE_IND__CP9_MASK 0x200 ++#define GPU_HDP_FLUSH_DONE_IND__CP9__SHIFT 0x9 ++#define GPU_HDP_FLUSH_DONE_IND__SDMA0_MASK 0x400 ++#define GPU_HDP_FLUSH_DONE_IND__SDMA0__SHIFT 0xa ++#define GPU_HDP_FLUSH_DONE_IND__SDMA1_MASK 0x800 ++#define GPU_HDP_FLUSH_DONE_IND__SDMA1__SHIFT 0xb ++#define SLAVE_HANG_ERROR_IND__SRBM_HANG_ERROR_MASK 0x1 ++#define SLAVE_HANG_ERROR_IND__SRBM_HANG_ERROR__SHIFT 0x0 ++#define SLAVE_HANG_ERROR_IND__HDP_HANG_ERROR_MASK 0x2 ++#define SLAVE_HANG_ERROR_IND__HDP_HANG_ERROR__SHIFT 0x1 ++#define SLAVE_HANG_ERROR_IND__VGA_HANG_ERROR_MASK 0x4 ++#define SLAVE_HANG_ERROR_IND__VGA_HANG_ERROR__SHIFT 0x2 ++#define SLAVE_HANG_ERROR_IND__ROM_HANG_ERROR_MASK 0x8 ++#define SLAVE_HANG_ERROR_IND__ROM_HANG_ERROR__SHIFT 0x3 ++#define SLAVE_HANG_ERROR_IND__AUDIO_HANG_ERROR_MASK 0x10 ++#define SLAVE_HANG_ERROR_IND__AUDIO_HANG_ERROR__SHIFT 0x4 ++#define SLAVE_HANG_ERROR_IND__CEC_HANG_ERROR_MASK 0x20 ++#define SLAVE_HANG_ERROR_IND__CEC_HANG_ERROR__SHIFT 0x5 ++#define SLAVE_HANG_ERROR_IND__XDMA_HANG_ERROR_MASK 0x80 ++#define SLAVE_HANG_ERROR_IND__XDMA_HANG_ERROR__SHIFT 0x7 ++#define SLAVE_HANG_ERROR_IND__DOORBELL_HANG_ERROR_MASK 0x100 ++#define SLAVE_HANG_ERROR_IND__DOORBELL_HANG_ERROR__SHIFT 0x8 ++#define SLAVE_HANG_ERROR_IND__GARLIC_HANG_ERROR_MASK 0x200 ++#define SLAVE_HANG_ERROR_IND__GARLIC_HANG_ERROR__SHIFT 0x9 ++#define CAPTURE_HOST_BUSNUM_IND__CHECK_EN_MASK 0x1 ++#define CAPTURE_HOST_BUSNUM_IND__CHECK_EN__SHIFT 0x0 ++#define HOST_BUSNUM_IND__HOST_ID_MASK 0xffff ++#define HOST_BUSNUM_IND__HOST_ID__SHIFT 0x0 ++#define PEER_REG_RANGE0_IND__START_ADDR_MASK 0xffff ++#define PEER_REG_RANGE0_IND__START_ADDR__SHIFT 0x0 ++#define PEER_REG_RANGE0_IND__END_ADDR_MASK 0xffff0000 ++#define PEER_REG_RANGE0_IND__END_ADDR__SHIFT 0x10 ++#define PEER_REG_RANGE1_IND__START_ADDR_MASK 0xffff ++#define PEER_REG_RANGE1_IND__START_ADDR__SHIFT 0x0 ++#define PEER_REG_RANGE1_IND__END_ADDR_MASK 0xffff0000 ++#define PEER_REG_RANGE1_IND__END_ADDR__SHIFT 0x10 ++#define PEER0_FB_OFFSET_HI_IND__PEER0_FB_OFFSET_HI_MASK 0xfffff ++#define PEER0_FB_OFFSET_HI_IND__PEER0_FB_OFFSET_HI__SHIFT 0x0 ++#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_OFFSET_LO_MASK 0xfffff ++#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_OFFSET_LO__SHIFT 0x0 ++#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_EN_MASK 0x80000000 ++#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_EN__SHIFT 0x1f ++#define PEER1_FB_OFFSET_HI_IND__PEER1_FB_OFFSET_HI_MASK 0xfffff ++#define PEER1_FB_OFFSET_HI_IND__PEER1_FB_OFFSET_HI__SHIFT 0x0 ++#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_OFFSET_LO_MASK 0xfffff ++#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_OFFSET_LO__SHIFT 0x0 ++#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_EN_MASK 0x80000000 ++#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_EN__SHIFT 0x1f ++#define PEER2_FB_OFFSET_HI_IND__PEER2_FB_OFFSET_HI_MASK 0xfffff ++#define PEER2_FB_OFFSET_HI_IND__PEER2_FB_OFFSET_HI__SHIFT 0x0 ++#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_OFFSET_LO_MASK 0xfffff ++#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_OFFSET_LO__SHIFT 0x0 ++#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_EN_MASK 0x80000000 ++#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_EN__SHIFT 0x1f ++#define PEER3_FB_OFFSET_HI_IND__PEER3_FB_OFFSET_HI_MASK 0xfffff ++#define PEER3_FB_OFFSET_HI_IND__PEER3_FB_OFFSET_HI__SHIFT 0x0 ++#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_OFFSET_LO_MASK 0xfffff ++#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_OFFSET_LO__SHIFT 0x0 ++#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_EN_MASK 0x80000000 ++#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_EN__SHIFT 0x1f ++#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1 ++#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0 ++#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_APER_AD_MASK 0x1e ++#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_APER_AD__SHIFT 0x1 ++#define SMBUS_BACO_DUMMY_IND__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff ++#define SMBUS_BACO_DUMMY_IND__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0 ++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID0_MASK 0xff ++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID0__SHIFT 0x0 ++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID1_MASK 0xff00 ++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID1__SHIFT 0x8 ++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID2_MASK 0xff0000 ++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID2__SHIFT 0x10 ++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID3_MASK 0xff000000 ++#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID3__SHIFT 0x18 ++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID4_MASK 0xff ++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID4__SHIFT 0x0 ++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID5_MASK 0xff00 ++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID5__SHIFT 0x8 ++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID6_MASK 0xff0000 ++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID6__SHIFT 0x10 ++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID7_MASK 0xff000000 ++#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID7__SHIFT 0x18 ++#define BACO_CNTL_IND__BACO_EN_MASK 0x1 ++#define BACO_CNTL_IND__BACO_EN__SHIFT 0x0 ++#define BACO_CNTL_IND__BACO_BCLK_OFF_MASK 0x2 ++#define BACO_CNTL_IND__BACO_BCLK_OFF__SHIFT 0x1 ++#define BACO_CNTL_IND__BACO_ISO_DIS_MASK 0x4 ++#define BACO_CNTL_IND__BACO_ISO_DIS__SHIFT 0x2 ++#define BACO_CNTL_IND__BACO_POWER_OFF_MASK 0x8 ++#define BACO_CNTL_IND__BACO_POWER_OFF__SHIFT 0x3 ++#define BACO_CNTL_IND__BACO_RESET_EN_MASK 0x10 ++#define BACO_CNTL_IND__BACO_RESET_EN__SHIFT 0x4 ++#define BACO_CNTL_IND__BACO_HANG_PROTECTION_EN_MASK 0x20 ++#define BACO_CNTL_IND__BACO_HANG_PROTECTION_EN__SHIFT 0x5 ++#define BACO_CNTL_IND__BACO_MODE_MASK 0x40 ++#define BACO_CNTL_IND__BACO_MODE__SHIFT 0x6 ++#define BACO_CNTL_IND__BACO_ANA_ISO_DIS_MASK 0x80 ++#define BACO_CNTL_IND__BACO_ANA_ISO_DIS__SHIFT 0x7 ++#define BACO_CNTL_IND__RCU_BIF_CONFIG_DONE_MASK 0x100 ++#define BACO_CNTL_IND__RCU_BIF_CONFIG_DONE__SHIFT 0x8 ++#define BACO_CNTL_IND__PWRGOOD_BF_MASK 0x200 ++#define BACO_CNTL_IND__PWRGOOD_BF__SHIFT 0x9 ++#define BACO_CNTL_IND__PWRGOOD_GPIO_MASK 0x400 ++#define BACO_CNTL_IND__PWRGOOD_GPIO__SHIFT 0xa ++#define BACO_CNTL_IND__PWRGOOD_MEM_MASK 0x800 ++#define BACO_CNTL_IND__PWRGOOD_MEM__SHIFT 0xb ++#define BACO_CNTL_IND__PWRGOOD_DVO_MASK 0x1000 ++#define BACO_CNTL_IND__PWRGOOD_DVO__SHIFT 0xc ++#define BACO_CNTL_IND__PWRGOOD_IDSC_MASK 0x2000 ++#define BACO_CNTL_IND__PWRGOOD_IDSC__SHIFT 0xd ++#define BACO_CNTL_IND__BACO_POWER_OFF_DRAM_MASK 0x10000 ++#define BACO_CNTL_IND__BACO_POWER_OFF_DRAM__SHIFT 0x10 ++#define BACO_CNTL_IND__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000 ++#define BACO_CNTL_IND__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11 ++#define BF_ANA_ISO_CNTL_IND__BF_ANA_ISO_DIS_MASK_MASK 0x1 ++#define BF_ANA_ISO_CNTL_IND__BF_ANA_ISO_DIS_MASK__SHIFT 0x0 ++#define BF_ANA_ISO_CNTL_IND__BF_VDDC_ISO_DIS_MASK_MASK 0x2 ++#define BF_ANA_ISO_CNTL_IND__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1 ++#define MEM_TYPE_CNTL_IND__BF_MEM_PHY_G5_G3_MASK 0x1 ++#define MEM_TYPE_CNTL_IND__BF_MEM_PHY_G5_G3__SHIFT 0x0 ++#define BIF_BACO_DEBUG_IND__BIF_BACO_SCANDUMP_FLG_MASK 0x1 ++#define BIF_BACO_DEBUG_IND__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0 ++#define BIF_BACO_DEBUG_LATCH_IND__BIF_BACO_LATCH_FLG_MASK 0x1 ++#define BIF_BACO_DEBUG_LATCH_IND__BIF_BACO_LATCH_FLG__SHIFT 0x0 ++#define BACO_CNTL_MISC_IND__BIF_ROM_REQ_DIS_MASK 0x1 ++#define BACO_CNTL_MISC_IND__BIF_ROM_REQ_DIS__SHIFT 0x0 ++#define BACO_CNTL_MISC_IND__BIF_AZ_REQ_DIS_MASK 0x2 ++#define BACO_CNTL_MISC_IND__BIF_AZ_REQ_DIS__SHIFT 0x1 ++#define BACO_CNTL_MISC_IND__BACO_LINK_RST_WIDTH_SEL_MASK 0xc ++#define BACO_CNTL_MISC_IND__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2 ++#define SMU_BIF_VDDGFX_PWR_STATUS_IND__VDDGFX_GFX_PWR_OFF_MASK 0x1 ++#define SMU_BIF_VDDGFX_PWR_STATUS_IND__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 ++#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_GFX0_UPPER_IND__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX0_UPPER_IND__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_GFX1_UPPER_IND__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX1_UPPER_IND__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_GFX2_UPPER_IND__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX2_UPPER_IND__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_GFX3_UPPER_IND__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX3_UPPER_IND__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_GFX4_UPPER_IND__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX4_UPPER_IND__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_GFX5_UPPER_IND__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_GFX5_UPPER_IND__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_RSV1_UPPER_IND__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV1_UPPER_IND__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_RSV2_UPPER_IND__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV2_UPPER_IND__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_RSV3_UPPER_IND__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV3_UPPER_IND__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000 ++#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000 ++#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f ++#define BIF_VDDGFX_RSV4_UPPER_IND__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc ++#define BIF_VDDGFX_RSV4_UPPER_IND__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 ++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_CMP_EN_MASK 0x1 ++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 ++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_STALL_EN_MASK 0x2 ++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 ++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4 ++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 ++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8 ++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 ++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_CMP_EN_MASK 0x10 ++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 ++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_STALL_EN_MASK 0x20 ++#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 ++#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_LOWER_MASK 0xffc ++#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 ++#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_EN_MASK 0x80000000 ++#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_EN__SHIFT 0x1f ++#define BIF_DOORBELL_GBLAPER1_UPPER_IND__DOORBELL_GBLAPER1_UPPER_MASK 0xffc ++#define BIF_DOORBELL_GBLAPER1_UPPER_IND__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 ++#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_LOWER_MASK 0xffc ++#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 ++#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_EN_MASK 0x80000000 ++#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_EN__SHIFT 0x1f ++#define BIF_DOORBELL_GBLAPER2_UPPER_IND__DOORBELL_GBLAPER2_UPPER_MASK 0xffc ++#define BIF_DOORBELL_GBLAPER2_UPPER_IND__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 ++#define BIF_SMU_INDEX_IND__BIF_SMU_INDEX_MASK 0x7fffc ++#define BIF_SMU_INDEX_IND__BIF_SMU_INDEX__SHIFT 0x2 ++#define BIF_SMU_DATA_IND__BIF_SMU_DATA_MASK 0x7fffc ++#define BIF_SMU_DATA_IND__BIF_SMU_DATA__SHIFT 0x2 ++#define IMPCTL_RESET_IND__IMP_SW_RESET_MASK 0x1 ++#define IMPCTL_RESET_IND__IMP_SW_RESET__SHIFT 0x0 ++#define GARLIC_FLUSH_CNTL_IND__CP_RB0_WPTR_MASK 0x1 ++#define GARLIC_FLUSH_CNTL_IND__CP_RB0_WPTR__SHIFT 0x0 ++#define GARLIC_FLUSH_CNTL_IND__CP_RB1_WPTR_MASK 0x2 ++#define GARLIC_FLUSH_CNTL_IND__CP_RB1_WPTR__SHIFT 0x1 ++#define GARLIC_FLUSH_CNTL_IND__CP_RB2_WPTR_MASK 0x4 ++#define GARLIC_FLUSH_CNTL_IND__CP_RB2_WPTR__SHIFT 0x2 ++#define GARLIC_FLUSH_CNTL_IND__UVD_RBC_RB_WPTR_MASK 0x8 ++#define GARLIC_FLUSH_CNTL_IND__UVD_RBC_RB_WPTR__SHIFT 0x3 ++#define GARLIC_FLUSH_CNTL_IND__SDMA0_GFX_RB_WPTR_MASK 0x10 ++#define GARLIC_FLUSH_CNTL_IND__SDMA0_GFX_RB_WPTR__SHIFT 0x4 ++#define GARLIC_FLUSH_CNTL_IND__SDMA1_GFX_RB_WPTR_MASK 0x20 ++#define GARLIC_FLUSH_CNTL_IND__SDMA1_GFX_RB_WPTR__SHIFT 0x5 ++#define GARLIC_FLUSH_CNTL_IND__CP_DMA_ME_COMMAND_MASK 0x40 ++#define GARLIC_FLUSH_CNTL_IND__CP_DMA_ME_COMMAND__SHIFT 0x6 ++#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PFP_COMMAND_MASK 0x80 ++#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PFP_COMMAND__SHIFT 0x7 ++#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBI_WPTR_MASK 0x100 ++#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBI_WPTR__SHIFT 0x8 ++#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBO_WPTR_MASK 0x200 ++#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBO_WPTR__SHIFT 0x9 ++#define GARLIC_FLUSH_CNTL_IND__VCE_OUT_RB_WPTR_MASK 0x400 ++#define GARLIC_FLUSH_CNTL_IND__VCE_OUT_RB_WPTR__SHIFT 0xa ++#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR2_MASK 0x800 ++#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR2__SHIFT 0xb ++#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR_MASK 0x1000 ++#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR__SHIFT 0xc ++#define GARLIC_FLUSH_CNTL_IND__HOST_DOORBELL_MASK 0x2000 ++#define GARLIC_FLUSH_CNTL_IND__HOST_DOORBELL__SHIFT 0xd ++#define GARLIC_FLUSH_CNTL_IND__SELFRING_DOORBELL_MASK 0x4000 ++#define GARLIC_FLUSH_CNTL_IND__SELFRING_DOORBELL__SHIFT 0xe ++#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PIO_COMMAND_MASK 0x8000 ++#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PIO_COMMAND__SHIFT 0xf ++#define GARLIC_FLUSH_CNTL_IND__DISPLAY_MASK 0x10000 ++#define GARLIC_FLUSH_CNTL_IND__DISPLAY__SHIFT 0x10 ++#define GARLIC_FLUSH_CNTL_IND__SDMA2_GFX_RB_WPTR_MASK 0x20000 ++#define GARLIC_FLUSH_CNTL_IND__SDMA2_GFX_RB_WPTR__SHIFT 0x11 ++#define GARLIC_FLUSH_CNTL_IND__SDMA3_GFX_RB_WPTR_MASK 0x40000 ++#define GARLIC_FLUSH_CNTL_IND__SDMA3_GFX_RB_WPTR__SHIFT 0x12 ++#define GARLIC_FLUSH_CNTL_IND__IGNORE_MC_DISABLE_MASK 0x40000000 ++#define GARLIC_FLUSH_CNTL_IND__IGNORE_MC_DISABLE__SHIFT 0x1e ++#define GARLIC_FLUSH_CNTL_IND__DISABLE_ALL_MASK 0x80000000 ++#define GARLIC_FLUSH_CNTL_IND__DISABLE_ALL__SHIFT 0x1f ++#define GARLIC_FLUSH_REQ_IND__FLUSH_REQ_MASK 0x1 ++#define GARLIC_FLUSH_REQ_IND__FLUSH_REQ__SHIFT 0x0 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP0_MASK 0x1 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP0__SHIFT 0x0 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP1_MASK 0x2 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP1__SHIFT 0x1 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP2_MASK 0x4 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP2__SHIFT 0x2 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP3_MASK 0x8 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP3__SHIFT 0x3 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP4_MASK 0x10 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP4__SHIFT 0x4 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP5_MASK 0x20 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP5__SHIFT 0x5 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP6_MASK 0x40 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP6__SHIFT 0x6 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP7_MASK 0x80 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP7__SHIFT 0x7 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP8_MASK 0x100 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP8__SHIFT 0x8 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP9_MASK 0x200 ++#define GPU_GARLIC_FLUSH_REQ_IND__CP9__SHIFT 0x9 ++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA0_MASK 0x400 ++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA0__SHIFT 0xa ++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA1_MASK 0x800 ++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA1__SHIFT 0xb ++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA2_MASK 0x1000 ++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA2__SHIFT 0xc ++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA3_MASK 0x2000 ++#define GPU_GARLIC_FLUSH_REQ_IND__SDMA3__SHIFT 0xd ++#define GPU_GARLIC_FLUSH_DONE_IND__CP0_MASK 0x1 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP0__SHIFT 0x0 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP1_MASK 0x2 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP1__SHIFT 0x1 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP2_MASK 0x4 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP2__SHIFT 0x2 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP3_MASK 0x8 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP3__SHIFT 0x3 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP4_MASK 0x10 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP4__SHIFT 0x4 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP5_MASK 0x20 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP5__SHIFT 0x5 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP6_MASK 0x40 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP6__SHIFT 0x6 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP7_MASK 0x80 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP7__SHIFT 0x7 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP8_MASK 0x100 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP8__SHIFT 0x8 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP9_MASK 0x200 ++#define GPU_GARLIC_FLUSH_DONE_IND__CP9__SHIFT 0x9 ++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA0_MASK 0x400 ++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA0__SHIFT 0xa ++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA1_MASK 0x800 ++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA1__SHIFT 0xb ++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA2_MASK 0x1000 ++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA2__SHIFT 0xc ++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA3_MASK 0x2000 ++#define GPU_GARLIC_FLUSH_DONE_IND__SDMA3__SHIFT 0xd ++#define GARLIC_COHE_CP_RB0_WPTR_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_CP_RB0_WPTR_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_CP_RB1_WPTR_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_CP_RB1_WPTR_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_CP_RB2_WPTR_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_CP_RB2_WPTR_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_UVD_RBC_RB_WPTR_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_UVD_RBC_RB_WPTR_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_SDMA0_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_SDMA0_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_SDMA1_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_SDMA1_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_CP_DMA_ME_COMMAND_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_CP_DMA_ME_COMMAND_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_CP_DMA_PFP_COMMAND_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_CP_DMA_PFP_COMMAND_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_SAM_SAB_RBI_WPTR_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_SAM_SAB_RBI_WPTR_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_SAM_SAB_RBO_WPTR_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_SAM_SAB_RBO_WPTR_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_VCE_OUT_RB_WPTR_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_VCE_OUT_RB_WPTR_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_VCE_RB_WPTR2_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_VCE_RB_WPTR2_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_VCE_RB_WPTR_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_VCE_RB_WPTR_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_SDMA2_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_SDMA2_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_SDMA3_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_SDMA3_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_CP_DMA_PIO_COMMAND_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_CP_DMA_PIO_COMMAND_IND__ADDRESS__SHIFT 0x2 ++#define GARLIC_COHE_GARLIC_FLUSH_REQ_IND__ADDRESS_MASK 0x7fffc ++#define GARLIC_COHE_GARLIC_FLUSH_REQ_IND__ADDRESS__SHIFT 0x2 ++#define REMAP_HDP_MEM_FLUSH_CNTL_IND__ADDRESS_MASK 0x7fffc ++#define REMAP_HDP_MEM_FLUSH_CNTL_IND__ADDRESS__SHIFT 0x2 ++#define REMAP_HDP_REG_FLUSH_CNTL_IND__ADDRESS_MASK 0x7fffc ++#define REMAP_HDP_REG_FLUSH_CNTL_IND__ADDRESS__SHIFT 0x2 ++#define BIOS_SCRATCH_0_IND__BIOS_SCRATCH_0_MASK 0xffffffff ++#define BIOS_SCRATCH_0_IND__BIOS_SCRATCH_0__SHIFT 0x0 ++#define BIOS_SCRATCH_1_IND__BIOS_SCRATCH_1_MASK 0xffffffff ++#define BIOS_SCRATCH_1_IND__BIOS_SCRATCH_1__SHIFT 0x0 ++#define BIOS_SCRATCH_2_IND__BIOS_SCRATCH_2_MASK 0xffffffff ++#define BIOS_SCRATCH_2_IND__BIOS_SCRATCH_2__SHIFT 0x0 ++#define BIOS_SCRATCH_3_IND__BIOS_SCRATCH_3_MASK 0xffffffff ++#define BIOS_SCRATCH_3_IND__BIOS_SCRATCH_3__SHIFT 0x0 ++#define BIOS_SCRATCH_4_IND__BIOS_SCRATCH_4_MASK 0xffffffff ++#define BIOS_SCRATCH_4_IND__BIOS_SCRATCH_4__SHIFT 0x0 ++#define BIOS_SCRATCH_5_IND__BIOS_SCRATCH_5_MASK 0xffffffff ++#define BIOS_SCRATCH_5_IND__BIOS_SCRATCH_5__SHIFT 0x0 ++#define BIOS_SCRATCH_6_IND__BIOS_SCRATCH_6_MASK 0xffffffff ++#define BIOS_SCRATCH_6_IND__BIOS_SCRATCH_6__SHIFT 0x0 ++#define BIOS_SCRATCH_7_IND__BIOS_SCRATCH_7_MASK 0xffffffff ++#define BIOS_SCRATCH_7_IND__BIOS_SCRATCH_7__SHIFT 0x0 ++#define BIOS_SCRATCH_8_IND__BIOS_SCRATCH_8_MASK 0xffffffff ++#define BIOS_SCRATCH_8_IND__BIOS_SCRATCH_8__SHIFT 0x0 ++#define BIOS_SCRATCH_9_IND__BIOS_SCRATCH_9_MASK 0xffffffff ++#define BIOS_SCRATCH_9_IND__BIOS_SCRATCH_9__SHIFT 0x0 ++#define BIOS_SCRATCH_10_IND__BIOS_SCRATCH_10_MASK 0xffffffff ++#define BIOS_SCRATCH_10_IND__BIOS_SCRATCH_10__SHIFT 0x0 ++#define BIOS_SCRATCH_11_IND__BIOS_SCRATCH_11_MASK 0xffffffff ++#define BIOS_SCRATCH_11_IND__BIOS_SCRATCH_11__SHIFT 0x0 ++#define BIOS_SCRATCH_12_IND__BIOS_SCRATCH_12_MASK 0xffffffff ++#define BIOS_SCRATCH_12_IND__BIOS_SCRATCH_12__SHIFT 0x0 ++#define BIOS_SCRATCH_13_IND__BIOS_SCRATCH_13_MASK 0xffffffff ++#define BIOS_SCRATCH_13_IND__BIOS_SCRATCH_13__SHIFT 0x0 ++#define BIOS_SCRATCH_14_IND__BIOS_SCRATCH_14_MASK 0xffffffff ++#define BIOS_SCRATCH_14_IND__BIOS_SCRATCH_14__SHIFT 0x0 ++#define BIOS_SCRATCH_15_IND__BIOS_SCRATCH_15_MASK 0xffffffff ++#define BIOS_SCRATCH_15_IND__BIOS_SCRATCH_15__SHIFT 0x0 ++#define BIF_RB_CNTL_IND__RB_ENABLE_MASK 0x1 ++#define BIF_RB_CNTL_IND__RB_ENABLE__SHIFT 0x0 ++#define BIF_RB_CNTL_IND__RB_SIZE_MASK 0x3e ++#define BIF_RB_CNTL_IND__RB_SIZE__SHIFT 0x1 ++#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_ENABLE_MASK 0x100 ++#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 ++#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_TIMER_MASK 0x3e00 ++#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_TIMER__SHIFT 0x9 ++#define BIF_RB_CNTL_IND__BIF_RB_TRAN_MASK 0x20000 ++#define BIF_RB_CNTL_IND__BIF_RB_TRAN__SHIFT 0x11 ++#define BIF_RB_CNTL_IND__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 ++#define BIF_RB_CNTL_IND__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f ++#define BIF_RB_BASE_IND__ADDR_MASK 0xffffffff ++#define BIF_RB_BASE_IND__ADDR__SHIFT 0x0 ++#define BIF_RB_RPTR_IND__OFFSET_MASK 0x3fffc ++#define BIF_RB_RPTR_IND__OFFSET__SHIFT 0x2 ++#define BIF_RB_WPTR_IND__BIF_RB_OVERFLOW_MASK 0x1 ++#define BIF_RB_WPTR_IND__BIF_RB_OVERFLOW__SHIFT 0x0 ++#define BIF_RB_WPTR_IND__OFFSET_MASK 0x3fffc ++#define BIF_RB_WPTR_IND__OFFSET__SHIFT 0x2 ++#define BIF_RB_WPTR_ADDR_HI_IND__ADDR_MASK 0xff ++#define BIF_RB_WPTR_ADDR_HI_IND__ADDR__SHIFT 0x0 ++#define BIF_RB_WPTR_ADDR_LO_IND__ADDR_MASK 0xfffffffc ++#define BIF_RB_WPTR_ADDR_LO_IND__ADDR__SHIFT 0x2 ++#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR_MASK 0xffffffff ++#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR__SHIFT 0x0 ++#define NB_GBIF_DATA__NB_GBIF_DATA_MASK 0xffffffff ++#define NB_GBIF_DATA__NB_GBIF_DATA__SHIFT 0x0 ++#define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff ++#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 ++#define PCIE_DATA__PCIE_DATA_MASK 0xffffffff ++#define PCIE_DATA__PCIE_DATA__SHIFT 0x0 ++#define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff ++#define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0 ++#define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff ++#define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0 ++#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff ++#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 ++#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff ++#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 ++#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff ++#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 ++#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff ++#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 ++#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1 ++#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 ++#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe ++#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 ++#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80 ++#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 ++#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100 ++#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 ++#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200 ++#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 ++#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00 ++#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa ++#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000 ++#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf ++#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000 ++#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 ++#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000 ++#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 ++#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000 ++#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 ++#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000 ++#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 ++#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK 0x100000 ++#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT 0x14 ++#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000 ++#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 ++#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000 ++#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 ++#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000 ++#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 ++#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000 ++#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18 ++#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000 ++#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e ++#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000 ++#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f ++#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf ++#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 ++#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000 ++#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000 ++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 ++#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000 ++#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 ++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000 ++#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 ++#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000 ++#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 ++#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000 ++#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 ++#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff ++#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0 ++#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100 ++#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8 ++#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000 ++#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10 ++#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1 ++#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 ++#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2 ++#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 ++#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4 ++#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 ++#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8 ++#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 ++#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10 ++#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 ++#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40 ++#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 ++#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80 ++#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7 ++#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100 ++#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8 ++#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1 ++#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 ++#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2 ++#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 ++#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4 ++#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 ++#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8 ++#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 ++#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10 ++#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 ++#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40 ++#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 ++#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80 ++#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7 ++#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100 ++#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8 ++#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1 ++#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 ++#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e ++#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 ++#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0 ++#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 ++#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800 ++#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb ++#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 ++#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 ++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000 ++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 ++#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000 ++#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 ++#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000 ++#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 ++#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000 ++#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 ++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000 ++#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 ++#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000 ++#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 ++#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000 ++#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 ++#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000 ++#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 ++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1 ++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 ++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2 ++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 ++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4 ++#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 ++#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8 ++#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 ++#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10 ++#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 ++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20 ++#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 ++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100 ++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 ++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00 ++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 ++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000 ++#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3 ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30 ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0 ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300 ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00 ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000 ++#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000 ++#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c ++#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4 ++#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 ++#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8 ++#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 ++#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10 ++#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 ++#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0 ++#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 ++#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100 ++#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 ++#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200 ++#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 ++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400 ++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa ++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800 ++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb ++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000 ++#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc ++#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000 ++#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd ++#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40 ++#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 ++#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80 ++#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 ++#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000 ++#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc ++#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f ++#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 ++#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00 ++#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 ++#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000 ++#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 ++#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000 ++#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 ++#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f ++#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 ++#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00 ++#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 ++#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000 ++#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 ++#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000 ++#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 ++#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f ++#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 ++#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00 ++#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 ++#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000 ++#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 ++#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000 ++#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 ++#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f ++#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 ++#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00 ++#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 ++#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000 ++#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 ++#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000 ++#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 ++#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f ++#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 ++#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00 ++#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 ++#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000 ++#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 ++#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000 ++#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 ++#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f ++#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 ++#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00 ++#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 ++#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000 ++#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 ++#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000 ++#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 ++#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1 ++#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 ++#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2 ++#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 ++#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c ++#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 ++#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0 ++#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 ++#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff ++#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 ++#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000 ++#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 ++#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1 ++#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 ++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2 ++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 ++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4 ++#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 ++#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8 ++#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 ++#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10 ++#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 ++#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20 ++#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 ++#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40 ++#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 ++#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff ++#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 ++#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff ++#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 ++#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff ++#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 ++#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff ++#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 ++#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff ++#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 ++#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff ++#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 ++#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff ++#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 ++#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff ++#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 ++#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff ++#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 ++#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff ++#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 ++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1 ++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 ++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2 ++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 ++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4 ++#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 ++#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1 ++#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 ++#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2 ++#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 ++#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4 ++#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2 ++#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8 ++#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3 ++#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10 ++#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 ++#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20 ++#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 ++#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40 ++#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 ++#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80 ++#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 ++#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100 ++#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 ++#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000 ++#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc ++#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000 ++#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd ++#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000 ++#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe ++#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000 ++#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 ++#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff ++#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 ++#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000 ++#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 ++#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff ++#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 ++#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff ++#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 ++#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000 ++#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 ++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff ++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 ++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00 ++#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 ++#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1 ++#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0 ++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2 ++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1 ++#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4 ++#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2 ++#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8 ++#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3 ++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0 ++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4 ++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00 ++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8 ++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000 ++#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc ++#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000 ++#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10 ++#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000 ++#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11 ++#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000 ++#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12 ++#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000 ++#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14 ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7 ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38 ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40 ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380 ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00 ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000 ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000 ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000 ++#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf ++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1 ++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 ++#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2 ++#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 ++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4 ++#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 ++#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff ++#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0 ++#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00 ++#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8 ++#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff ++#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0 ++#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff ++#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0 ++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff ++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00 ++#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff ++#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0 ++#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff ++#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0 ++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff ++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00 ++#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff ++#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0 ++#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff ++#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0 ++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff ++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00 ++#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff ++#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0 ++#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff ++#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0 ++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff ++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00 ++#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff ++#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0 ++#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff ++#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0 ++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff ++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00 ++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff ++#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0 ++#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff ++#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0 ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0 ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0 ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4 ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00 ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8 ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000 ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000 ++#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18 ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0 ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0 ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4 ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00 ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8 ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000 ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000 ++#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18 ++#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff ++#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 ++#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00 ++#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 ++#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000 ++#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 ++#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000 ++#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 ++#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff ++#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 ++#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff ++#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 ++#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1 ++#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 ++#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2 ++#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 ++#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4 ++#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2 ++#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8 ++#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3 ++#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10 ++#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4 ++#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20 ++#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5 ++#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40 ++#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6 ++#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80 ++#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7 ++#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100 ++#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8 ++#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200 ++#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9 ++#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400 ++#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa ++#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800 ++#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb ++#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000 ++#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc ++#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000 ++#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd ++#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000 ++#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe ++#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000 ++#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf ++#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000 ++#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 ++#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000 ++#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 ++#define PCIE_STRAP_F1__STRAP_F1_EN_MASK 0x1 ++#define PCIE_STRAP_F1__STRAP_F1_EN__SHIFT 0x0 ++#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2 ++#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 ++#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4 ++#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2 ++#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8 ++#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3 ++#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10 ++#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4 ++#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20 ++#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5 ++#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40 ++#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6 ++#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80 ++#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7 ++#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100 ++#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8 ++#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200 ++#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9 ++#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400 ++#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa ++#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800 ++#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb ++#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000 ++#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc ++#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000 ++#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd ++#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000 ++#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe ++#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000 ++#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf ++#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000 ++#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 ++#define PCIE_STRAP_F2__STRAP_F2_EN_MASK 0x1 ++#define PCIE_STRAP_F2__STRAP_F2_EN__SHIFT 0x0 ++#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2 ++#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 ++#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4 ++#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2 ++#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8 ++#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3 ++#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10 ++#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4 ++#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20 ++#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5 ++#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40 ++#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6 ++#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80 ++#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7 ++#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100 ++#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8 ++#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200 ++#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9 ++#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400 ++#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa ++#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800 ++#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb ++#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000 ++#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc ++#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000 ++#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd ++#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000 ++#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe ++#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000 ++#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf ++#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000 ++#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 ++#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff ++#define PCIE_STRAP_F3__RESERVED__SHIFT 0x0 ++#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff ++#define PCIE_STRAP_F4__RESERVED__SHIFT 0x0 ++#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff ++#define PCIE_STRAP_F5__RESERVED__SHIFT 0x0 ++#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff ++#define PCIE_STRAP_F6__RESERVED__SHIFT 0x0 ++#define PCIE_STRAP_F7__RESERVED_MASK 0xffffffff ++#define PCIE_STRAP_F7__RESERVED__SHIFT 0x0 ++#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK 0xf ++#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT 0x0 ++#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10 ++#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4 ++#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00 ++#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8 ++#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000 ++#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd ++#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000 ++#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe ++#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000 ++#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf ++#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000 ++#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 ++#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000 ++#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19 ++#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000 ++#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a ++#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000 ++#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c ++#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000 ++#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d ++#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000 ++#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e ++#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000 ++#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f ++#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2 ++#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1 ++#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4 ++#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 ++#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8 ++#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3 ++#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10 ++#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 ++#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1 ++#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0 ++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000 ++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c ++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000 ++#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d ++#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f ++#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0 ++#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80 ++#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7 ++#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff ++#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 ++#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000 ++#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10 ++#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff ++#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 ++#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000 ++#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 ++#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff ++#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 ++#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff ++#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 ++#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1 ++#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 ++#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x6 ++#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 ++#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x8 ++#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x3 ++#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x10 ++#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x4 ++#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x60 ++#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x5 ++#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0xf80 ++#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x7 ++#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000 ++#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe ++#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000 ++#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 ++#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff ++#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 ++#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff ++#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 ++#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff ++#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 ++#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff ++#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 ++#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300 ++#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 ++#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000 ++#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc ++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000 ++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 ++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000 ++#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 ++#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff ++#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 ++#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f ++#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff ++#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 ++#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff ++#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 ++#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 ++#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 ++#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 ++#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 ++#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 ++#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 ++#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 ++#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 ++#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 ++#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 ++#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 ++#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 ++#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 ++#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 ++#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 ++#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 ++#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 ++#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 ++#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 ++#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 ++#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa ++#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 ++#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc ++#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 ++#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe ++#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 ++#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf ++#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 ++#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 ++#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 ++#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 ++#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 ++#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 ++#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 ++#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 ++#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x1000000 ++#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 ++#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x2000000 ++#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 ++#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x4000000 ++#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a ++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 ++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 ++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 ++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 ++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 ++#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 ++#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff ++#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 ++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 ++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 ++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 ++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e ++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 ++#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f ++#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff ++#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 ++#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 ++#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 ++#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 ++#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 ++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 ++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf ++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 ++#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 ++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff ++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 ++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 ++#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc ++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff ++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 ++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 ++#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 ++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff ++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 ++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 ++#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 ++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff ++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 ++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 ++#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 ++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff ++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 ++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 ++#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 ++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff ++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 ++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 ++#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 ++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff ++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 ++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 ++#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 ++#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 ++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 ++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 ++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 ++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 ++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 ++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 ++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 ++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 ++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 ++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 ++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 ++#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 ++#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 ++#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 ++#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e ++#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 ++#define PCIE_FC_P__PD_CREDITS_MASK 0xff ++#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0 ++#define PCIE_FC_P__PH_CREDITS_MASK 0xff00 ++#define PCIE_FC_P__PH_CREDITS__SHIFT 0x8 ++#define PCIE_FC_NP__NPD_CREDITS_MASK 0xff ++#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 ++#define PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 ++#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 ++#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff ++#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 ++#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 ++#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 ++#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 ++#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 ++#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 ++#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 ++#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 ++#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 ++#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 ++#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 ++#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 ++#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 ++#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 ++#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 ++#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 ++#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 ++#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 ++#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 ++#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 ++#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb ++#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x1000 ++#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc ++#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x2000 ++#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd ++#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 ++#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe ++#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 ++#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf ++#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 ++#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 ++#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 ++#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 ++#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 ++#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 ++#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 ++#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 ++#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 ++#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 ++#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 ++#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 ++#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 ++#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 ++#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 ++#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 ++#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 ++#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 ++#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 ++#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 ++#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 ++#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 ++#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 ++#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 ++#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 ++#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa ++#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 ++#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb ++#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 ++#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc ++#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 ++#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd ++#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 ++#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe ++#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 ++#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf ++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 ++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 ++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 ++#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 ++#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 ++#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 ++#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 ++#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 ++#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 ++#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 ++#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 ++#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 ++#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 ++#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 ++#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 ++#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 ++#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff ++#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 ++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff ++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 ++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 ++#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 ++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 ++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 ++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 ++#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 ++#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 ++#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 ++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 ++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 ++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 ++#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 ++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff ++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 ++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 ++#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 ++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff ++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 ++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 ++#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 ++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff ++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 ++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 ++#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 ++#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 ++#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 ++#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 ++#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 ++#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 ++#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 ++#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 ++#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 ++#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 ++#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 ++#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 ++#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc ++#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 ++#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 ++#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 ++#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 ++#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 ++#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 ++#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 ++#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 ++#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 ++#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 ++#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 ++#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 ++#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 ++#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 ++#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 ++#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 ++#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 ++#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 ++#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 ++#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b ++#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 ++#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c ++#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 ++#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d ++#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 ++#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e ++#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 ++#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f ++#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f ++#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 ++#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 ++#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 ++#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 ++#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 ++#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 ++#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 ++#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 ++#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 ++#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 ++#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa ++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 ++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb ++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 ++#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc ++#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 ++#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd ++#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 ++#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe ++#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 ++#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 ++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 ++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 ++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 ++#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 ++#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 ++#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 ++#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 ++#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 ++#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 ++#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 ++#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 ++#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 ++#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 ++#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 ++#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 ++#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 ++#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 ++#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a ++#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 ++#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b ++#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 ++#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c ++#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 ++#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d ++#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 ++#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f ++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 ++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 ++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 ++#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 ++#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 ++#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 ++#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 ++#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 ++#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 ++#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 ++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 ++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 ++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 ++#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 ++#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 ++#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 ++#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 ++#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa ++#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 ++#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb ++#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 ++#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc ++#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 ++#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe ++#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 ++#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 ++#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 ++#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 ++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 ++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 ++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 ++#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 ++#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 ++#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 ++#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 ++#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 ++#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 ++#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 ++#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 ++#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 ++#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 ++#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a ++#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 ++#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e ++#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 ++#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f ++#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 ++#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 ++#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 ++#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 ++#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 ++#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 ++#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 ++#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 ++#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 ++#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 ++#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 ++#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 ++#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 ++#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa ++#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 ++#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb ++#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 ++#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc ++#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 ++#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd ++#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 ++#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe ++#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 ++#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf ++#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 ++#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 ++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 ++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 ++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 ++#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 ++#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 ++#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 ++#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 ++#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 ++#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 ++#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 ++#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 ++#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 ++#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 ++#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a ++#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f ++#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 ++#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 ++#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 ++#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 ++#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc ++#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 ++#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 ++#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa ++#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf ++#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 ++#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 ++#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 ++#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 ++#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 ++#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 ++#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 ++#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 ++#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 ++#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 ++#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 ++#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 ++#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb ++#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 ++#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc ++#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 ++#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd ++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 ++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 ++#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 ++#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 ++#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 ++#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 ++#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 ++#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 ++#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 ++#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 ++#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 ++#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 ++#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 ++#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 ++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 ++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 ++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 ++#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 ++#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 ++#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a ++#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 ++#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b ++#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 ++#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c ++#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 ++#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d ++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 ++#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 ++#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 ++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff ++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 ++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 ++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 ++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 ++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 ++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 ++#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 ++#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 ++#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 ++#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 ++#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 ++#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 ++#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 ++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 ++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 ++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 ++#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 ++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 ++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 ++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 ++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 ++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 ++#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 ++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 ++#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 ++#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 ++#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 ++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 ++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa ++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 ++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc ++#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 ++#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd ++#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 ++#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf ++#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 ++#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 ++#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 ++#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 ++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 ++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 ++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 ++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 ++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 ++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 ++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 ++#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 ++#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 ++#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 ++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 ++#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 ++#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 ++#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 ++#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 ++#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a ++#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 ++#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b ++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 ++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c ++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 ++#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d ++#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 ++#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e ++#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 ++#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f ++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff ++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 ++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 ++#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc ++#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 ++#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 ++#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff ++#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 ++#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 ++#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 ++#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 ++#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 ++#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e ++#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 ++#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 ++#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 ++#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 ++#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd ++#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 ++#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 ++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf ++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 ++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 ++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 ++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 ++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa ++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 ++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 ++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 ++#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 ++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 ++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 ++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e ++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 ++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 ++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 ++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 ++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd ++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 ++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 ++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 ++#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 ++#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f ++#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 ++#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 ++#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 ++#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 ++#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 ++#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 ++#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 ++#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f ++#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 ++#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 ++#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 ++#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 ++#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 ++#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 ++#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 ++#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f ++#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 ++#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 ++#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 ++#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 ++#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 ++#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 ++#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 ++#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f ++#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 ++#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 ++#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 ++#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 ++#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 ++#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 ++#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 ++#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f ++#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 ++#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 ++#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 ++#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 ++#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 ++#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 ++#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 ++#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f ++#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 ++#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 ++#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 ++#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 ++#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 ++#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 ++#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 ++#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 ++#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 ++#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc ++#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 ++#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 ++#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 ++#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 ++#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 ++#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 ++#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 ++#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 ++#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb ++#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 ++#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc ++#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 ++#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd ++#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 ++#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe ++#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 ++#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf ++#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 ++#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 ++#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 ++#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 ++#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 ++#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 ++#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 ++#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 ++#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 ++#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 ++#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 ++#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 ++#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 ++#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 ++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 ++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 ++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 ++#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 ++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK 0x1 ++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT 0x0 ++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2 ++#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT 0x1 ++#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1 ++#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0 ++#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff ++#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0 ++#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000 ++#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e ++#define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000 ++#define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f ++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWGBIF_rst_MASK 0x1 ++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWGBIF_rst__SHIFT 0x0 ++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWGBIF_rst_MASK 0x2 ++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWGBIF_rst__SHIFT 0x1 ++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWGBIF_rst_MASK 0x4 ++#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWGBIF_rst__SHIFT 0x2 ++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__FBU_rst_MASK 0x1 ++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__FBU_rst__SHIFT 0x0 ++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWGBIF_rst_MASK 0x2 ++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWGBIF_rst__SHIFT 0x1 ++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK 0x4 ++#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x2 ++#define BIF_PWDN_COMMAND__REG_FBU_pw_cmd_MASK 0x1 ++#define BIF_PWDN_COMMAND__REG_FBU_pw_cmd__SHIFT 0x0 ++#define BIF_PWDN_COMMAND__REG_RWREG_RFEWGBIF_pw_cmd_MASK 0x2 ++#define BIF_PWDN_COMMAND__REG_RWREG_RFEWGBIF_pw_cmd__SHIFT 0x1 ++#define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK 0x4 ++#define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x2 ++#define BIF_PWDN_STATUS__FBU_REG_pw_status_MASK 0x1 ++#define BIF_PWDN_STATUS__FBU_REG_pw_status__SHIFT 0x0 ++#define BIF_PWDN_STATUS__RWREG_RFEWGBIF_REG_pw_status_MASK 0x2 ++#define BIF_PWDN_STATUS__RWREG_RFEWGBIF_REG_pw_status__SHIFT 0x1 ++#define BIF_PWDN_STATUS__BX_REG_pw_status_MASK 0x4 ++#define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x2 ++#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkGate_timer_MASK 0xff ++#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkGate_timer__SHIFT 0x0 ++#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkSetup_timer_MASK 0xf00 ++#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkSetup_timer__SHIFT 0x8 ++#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_timeout_timer_MASK 0xff0000 ++#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_timeout_timer__SHIFT 0x10 ++#define BIF_RFE_MST_FBU_CMDSTATUS__FBU_RFE_mstTimeout_MASK 0x1000000 ++#define BIF_RFE_MST_FBU_CMDSTATUS__FBU_RFE_mstTimeout__SHIFT 0x18 ++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkGate_timer_MASK 0xff ++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkGate_timer__SHIFT 0x0 ++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkSetup_timer_MASK 0xf00 ++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkSetup_timer__SHIFT 0x8 ++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_timeout_timer_MASK 0xff0000 ++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_timeout_timer__SHIFT 0x10 ++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__RWREG_RFEWGBIF_RFE_mstTimeout_MASK 0x1000000 ++#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__RWREG_RFEWGBIF_RFE_mstTimeout__SHIFT 0x18 ++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK 0xff ++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT 0x0 ++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK 0xf00 ++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT 0x8 ++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK 0xff0000 ++#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT 0x10 ++#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK 0x1000000 ++#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT 0x18 ++#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1 ++#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0 ++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_WR_TO_CFG_EN_MASK 0x1 ++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_WR_TO_CFG_EN__SHIFT 0x0 ++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_CFG_FUNC_SEL_MASK 0xe ++#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_CFG_FUNC_SEL__SHIFT 0x1 ++#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_WR_TO_CFG_EN_MASK 0x10 ++#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_WR_TO_CFG_EN__SHIFT 0x4 ++#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_CFG_FUNC_SEL_MASK 0xe0 ++#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_CFG_FUNC_SEL__SHIFT 0x5 ++#define BIF_CLOCKS_BITS_IND__OBFF_XSL_FORCE_REFCLK_MASK 0x1 ++#define BIF_CLOCKS_BITS_IND__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0 ++#define BIF_LNCNT_RESET_IND__RESET_LNCNT_EN_MASK 0x1 ++#define BIF_LNCNT_RESET_IND__RESET_LNCNT_EN__SHIFT 0x0 ++#define LNCNT_CONTROL_IND__LNCNT_ACC_MODE_MASK 0x1 ++#define LNCNT_CONTROL_IND__LNCNT_ACC_MODE__SHIFT 0x0 ++#define LNCNT_CONTROL_IND__LNCNT_REF_TIMEBASE_MASK 0x6 ++#define LNCNT_CONTROL_IND__LNCNT_REF_TIMEBASE__SHIFT 0x1 ++#define NEW_REFCLKB_TIMER_IND__REG_STOP_REFCLK_EN_MASK 0x1 ++#define NEW_REFCLKB_TIMER_IND__REG_STOP_REFCLK_EN__SHIFT 0x0 ++#define NEW_REFCLKB_TIMER_IND__STOP_REFCLK_TIMER_MASK 0x1ffffe ++#define NEW_REFCLKB_TIMER_IND__STOP_REFCLK_TIMER__SHIFT 0x1 ++#define NEW_REFCLKB_TIMER_IND__REFCLK_ON_MASK 0x200000 ++#define NEW_REFCLKB_TIMER_IND__REFCLK_ON__SHIFT 0x15 ++#define NEW_REFCLKB_TIMER_1_IND__PHY_PLL_PDWN_TIMER_MASK 0x3ff ++#define NEW_REFCLKB_TIMER_1_IND__PHY_PLL_PDWN_TIMER__SHIFT 0x0 ++#define NEW_REFCLKB_TIMER_1_IND__PLL0_PDNB_EN_MASK 0x400 ++#define NEW_REFCLKB_TIMER_1_IND__PLL0_PDNB_EN__SHIFT 0xa ++#define BIF_CLK_PDWN_DELAY_TIMER_IND__TIMER_MASK 0x3ff ++#define BIF_CLK_PDWN_DELAY_TIMER_IND__TIMER__SHIFT 0x0 ++#define BIF_RESET_EN_IND__SOFT_RST_MODE_MASK 0x2 ++#define BIF_RESET_EN_IND__SOFT_RST_MODE__SHIFT 0x1 ++#define BIF_RESET_EN_IND__PHY_RESET_EN_MASK 0x4 ++#define BIF_RESET_EN_IND__PHY_RESET_EN__SHIFT 0x2 ++#define BIF_RESET_EN_IND__COR_RESET_EN_MASK 0x8 ++#define BIF_RESET_EN_IND__COR_RESET_EN__SHIFT 0x3 ++#define BIF_RESET_EN_IND__REG_RESET_EN_MASK 0x10 ++#define BIF_RESET_EN_IND__REG_RESET_EN__SHIFT 0x4 ++#define BIF_RESET_EN_IND__STY_RESET_EN_MASK 0x20 ++#define BIF_RESET_EN_IND__STY_RESET_EN__SHIFT 0x5 ++#define BIF_RESET_EN_IND__CFG_RESET_EN_MASK 0x40 ++#define BIF_RESET_EN_IND__CFG_RESET_EN__SHIFT 0x6 ++#define BIF_RESET_EN_IND__DRV_RESET_EN_MASK 0x80 ++#define BIF_RESET_EN_IND__DRV_RESET_EN__SHIFT 0x7 ++#define BIF_RESET_EN_IND__RESET_CFGREG_ONLY_EN_MASK 0x100 ++#define BIF_RESET_EN_IND__RESET_CFGREG_ONLY_EN__SHIFT 0x8 ++#define BIF_RESET_EN_IND__HOT_RESET_EN_MASK 0x200 ++#define BIF_RESET_EN_IND__HOT_RESET_EN__SHIFT 0x9 ++#define BIF_RESET_EN_IND__LINK_DISABLE_RESET_EN_MASK 0x400 ++#define BIF_RESET_EN_IND__LINK_DISABLE_RESET_EN__SHIFT 0xa ++#define BIF_RESET_EN_IND__LINK_DOWN_RESET_EN_MASK 0x800 ++#define BIF_RESET_EN_IND__LINK_DOWN_RESET_EN__SHIFT 0xb ++#define BIF_RESET_EN_IND__CFG_RESET_PULSE_WIDTH_MASK 0x3f000 ++#define BIF_RESET_EN_IND__CFG_RESET_PULSE_WIDTH__SHIFT 0xc ++#define BIF_RESET_EN_IND__DRV_RESET_DELAY_SEL_MASK 0xc0000 ++#define BIF_RESET_EN_IND__DRV_RESET_DELAY_SEL__SHIFT 0x12 ++#define BIF_RESET_EN_IND__PIF_RSTB_EN_MASK 0x100000 ++#define BIF_RESET_EN_IND__PIF_RSTB_EN__SHIFT 0x14 ++#define BIF_RESET_EN_IND__PIF_STRAP_ALLVALID_EN_MASK 0x200000 ++#define BIF_RESET_EN_IND__PIF_STRAP_ALLVALID_EN__SHIFT 0x15 ++#define BIF_RESET_EN_IND__BIF_COR_RESET_EN_MASK 0x400000 ++#define BIF_RESET_EN_IND__BIF_COR_RESET_EN__SHIFT 0x16 ++#define BIF_RESET_EN_IND__FUNC0_FLR_EN_MASK 0x800000 ++#define BIF_RESET_EN_IND__FUNC0_FLR_EN__SHIFT 0x17 ++#define BIF_RESET_EN_IND__FUNC1_FLR_EN_MASK 0x1000000 ++#define BIF_RESET_EN_IND__FUNC1_FLR_EN__SHIFT 0x18 ++#define BIF_RESET_EN_IND__FUNC2_FLR_EN_MASK 0x2000000 ++#define BIF_RESET_EN_IND__FUNC2_FLR_EN__SHIFT 0x19 ++#define BIF_RESET_EN_IND__FUNC0_RESET_DELAY_SEL_MASK 0xc000000 ++#define BIF_RESET_EN_IND__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a ++#define BIF_RESET_EN_IND__FUNC1_RESET_DELAY_SEL_MASK 0x30000000 ++#define BIF_RESET_EN_IND__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c ++#define BIF_RESET_EN_IND__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000 ++#define BIF_RESET_EN_IND__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e ++#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL0_ACK_TIMER_MASK 0x7 ++#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL0_ACK_TIMER__SHIFT 0x0 ++#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL1_ACK_TIMER_MASK 0x38 ++#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL1_ACK_TIMER__SHIFT 0x3 ++#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL_SWITCH_TIMER_MASK 0x3c0 ++#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL_SWITCH_TIMER__SHIFT 0x6 ++#define BIF_BACO_MSIC_IND__BIF_XTALIN_SEL_MASK 0x1 ++#define BIF_BACO_MSIC_IND__BIF_XTALIN_SEL__SHIFT 0x0 ++#define BIF_BACO_MSIC_IND__BACO_LINK_RST_SEL_MASK 0x6 ++#define BIF_BACO_MSIC_IND__BACO_LINK_RST_SEL__SHIFT 0x1 ++#define BIF_BACO_MSIC_IND__ACPI_BACO_MUX_DIS_MASK 0x10 ++#define BIF_BACO_MSIC_IND__ACPI_BACO_MUX_DIS__SHIFT 0x4 ++#define BIF_RESET_CNTL_IND__STRAP_EN_MASK 0x1 ++#define BIF_RESET_CNTL_IND__STRAP_EN__SHIFT 0x0 ++#define BIF_RESET_CNTL_IND__RST_DONE_MASK 0x2 ++#define BIF_RESET_CNTL_IND__RST_DONE__SHIFT 0x1 ++#define BIF_RESET_CNTL_IND__LINK_TRAIN_EN_MASK 0x4 ++#define BIF_RESET_CNTL_IND__LINK_TRAIN_EN__SHIFT 0x2 ++#define BIF_RESET_CNTL_IND__STRAP_ALL_VALID_MASK 0x8 ++#define BIF_RESET_CNTL_IND__STRAP_ALL_VALID__SHIFT 0x3 ++#define BIF_RESET_CNTL_IND__RECAP_STRAP_WARMRST_MASK 0x100 ++#define BIF_RESET_CNTL_IND__RECAP_STRAP_WARMRST__SHIFT 0x8 ++#define BIF_RESET_CNTL_IND__HOLD_LKTRN_WARMRST_DIS_MASK 0x200 ++#define BIF_RESET_CNTL_IND__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9 ++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif0_bu_reg_accessMode_MASK 0x1 ++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0 ++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif1_bu_reg_accessMode_MASK 0x2 ++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1 ++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4 ++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2 ++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8 ++#define BIF_RFE_CNTL_MISC_IND__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3 ++#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_EN_MASK 0x1 ++#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_EN__SHIFT 0x0 ++#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_TIMER_MASK 0xffff0000 ++#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_TIMER__SHIFT 0x10 ++#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR_MASK 0xffffffff ++#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR__SHIFT 0x0 ++#define NB_GBIF_DATA__NB_GBIF_DATA_MASK 0xffffffff ++#define NB_GBIF_DATA__NB_GBIF_DATA__SHIFT 0x0 ++#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK_MASK 0x1 ++#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0 ++#define BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK 0x1 ++#define BIF_LNCNT_RESET__RESET_LNCNT_EN__SHIFT 0x0 ++#define LNCNT_CONTROL__LNCNT_ACC_MODE_MASK 0x1 ++#define LNCNT_CONTROL__LNCNT_ACC_MODE__SHIFT 0x0 ++#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE_MASK 0x6 ++#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE__SHIFT 0x1 ++#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK 0x1 ++#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT 0x0 ++#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK 0x1ffffe ++#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT 0x1 ++#define NEW_REFCLKB_TIMER__REFCLK_ON_MASK 0x200000 ++#define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT 0x15 ++#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK 0x3ff ++#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT 0x0 ++#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK 0x400 ++#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT 0xa ++#define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x3ff ++#define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x0 ++#define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x2 ++#define BIF_RESET_EN__SOFT_RST_MODE__SHIFT 0x1 ++#define BIF_RESET_EN__PHY_RESET_EN_MASK 0x4 ++#define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x2 ++#define BIF_RESET_EN__COR_RESET_EN_MASK 0x8 ++#define BIF_RESET_EN__COR_RESET_EN__SHIFT 0x3 ++#define BIF_RESET_EN__REG_RESET_EN_MASK 0x10 ++#define BIF_RESET_EN__REG_RESET_EN__SHIFT 0x4 ++#define BIF_RESET_EN__STY_RESET_EN_MASK 0x20 ++#define BIF_RESET_EN__STY_RESET_EN__SHIFT 0x5 ++#define BIF_RESET_EN__CFG_RESET_EN_MASK 0x40 ++#define BIF_RESET_EN__CFG_RESET_EN__SHIFT 0x6 ++#define BIF_RESET_EN__DRV_RESET_EN_MASK 0x80 ++#define BIF_RESET_EN__DRV_RESET_EN__SHIFT 0x7 ++#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK 0x100 ++#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT 0x8 ++#define BIF_RESET_EN__HOT_RESET_EN_MASK 0x200 ++#define BIF_RESET_EN__HOT_RESET_EN__SHIFT 0x9 ++#define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK 0x400 ++#define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT 0xa ++#define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK 0x800 ++#define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT 0xb ++#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK 0x3f000 ++#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT 0xc ++#define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK 0xc0000 ++#define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT 0x12 ++#define BIF_RESET_EN__PIF_RSTB_EN_MASK 0x100000 ++#define BIF_RESET_EN__PIF_RSTB_EN__SHIFT 0x14 ++#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK 0x200000 ++#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT 0x15 ++#define BIF_RESET_EN__BIF_COR_RESET_EN_MASK 0x400000 ++#define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT 0x16 ++#define BIF_RESET_EN__FUNC0_FLR_EN_MASK 0x800000 ++#define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT 0x17 ++#define BIF_RESET_EN__FUNC1_FLR_EN_MASK 0x1000000 ++#define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT 0x18 ++#define BIF_RESET_EN__FUNC2_FLR_EN_MASK 0x2000000 ++#define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x19 ++#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK 0xc000000 ++#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a ++#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK 0x30000000 ++#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c ++#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000 ++#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e ++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK 0x7 ++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT 0x0 ++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK 0x38 ++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT 0x3 ++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK 0x3c0 ++#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT 0x6 ++#define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x1 ++#define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x0 ++#define BIF_BACO_MSIC__BACO_LINK_RST_SEL_MASK 0x6 ++#define BIF_BACO_MSIC__BACO_LINK_RST_SEL__SHIFT 0x1 ++#define BIF_BACO_MSIC__ACPI_BACO_MUX_DIS_MASK 0x10 ++#define BIF_BACO_MSIC__ACPI_BACO_MUX_DIS__SHIFT 0x4 ++#define BIF_RESET_CNTL__STRAP_EN_MASK 0x1 ++#define BIF_RESET_CNTL__STRAP_EN__SHIFT 0x0 ++#define BIF_RESET_CNTL__RST_DONE_MASK 0x2 ++#define BIF_RESET_CNTL__RST_DONE__SHIFT 0x1 ++#define BIF_RESET_CNTL__LINK_TRAIN_EN_MASK 0x4 ++#define BIF_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x2 ++#define BIF_RESET_CNTL__STRAP_ALL_VALID_MASK 0x8 ++#define BIF_RESET_CNTL__STRAP_ALL_VALID__SHIFT 0x3 ++#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST_MASK 0x100 ++#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST__SHIFT 0x8 ++#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS_MASK 0x200 ++#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9 ++#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode_MASK 0x1 ++#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0 ++#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode_MASK 0x2 ++#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1 ++#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4 ++#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2 ++#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8 ++#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3 ++#define BIF_MEM_PG_CNTL__BIF_MEM_SD_EN_MASK 0x1 ++#define BIF_MEM_PG_CNTL__BIF_MEM_SD_EN__SHIFT 0x0 ++#define BIF_MEM_PG_CNTL__BIF_MEM_SD_TIMER_MASK 0xffff0000 ++#define BIF_MEM_PG_CNTL__BIF_MEM_SD_TIMER__SHIFT 0x10 ++#define C_PCIE_P_INDEX__PCIE_INDEX_MASK 0xffffffff ++#define C_PCIE_P_INDEX__PCIE_INDEX__SHIFT 0x0 ++#define C_PCIE_P_DATA__PCIE_DATA_MASK 0xffffffff ++#define C_PCIE_P_DATA__PCIE_DATA__SHIFT 0x0 ++#define D2F1_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff ++#define D2F1_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 ++#define D2F1_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff ++#define D2F1_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 ++#define D2F1_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff ++#define D2F1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 ++#define D2F1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff ++#define D2F1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 ++#define D2F1_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define D2F1_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define D2F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define D2F1_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define D2F1_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define D2F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define D2F1_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define D2F1_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define D2F1_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define D2F1_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define D2F1_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define D2F1_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define D2F1_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define D2F1_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define D2F1_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define D2F1_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define D2F1_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define D2F1_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define D2F1_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define D2F1_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define D2F1_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define D2F1_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define D2F1_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define D2F1_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define D2F1_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define D2F1_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define D2F1_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define D2F1_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define D2F1_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define D2F1_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define D2F1_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define D2F1_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define D2F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 ++#define D2F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 ++#define D2F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 ++#define D2F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 ++#define D2F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 ++#define D2F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 ++#define D2F1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 ++#define D2F1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 ++#define D2F1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 ++#define D2F1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 ++#define D2F1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 ++#define D2F1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 ++#define D2F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 ++#define D2F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 ++#define D2F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 ++#define D2F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 ++#define D2F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 ++#define D2F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define D2F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 ++#define D2F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 ++#define D2F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 ++#define D2F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa ++#define D2F1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 ++#define D2F1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc ++#define D2F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 ++#define D2F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe ++#define D2F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 ++#define D2F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf ++#define D2F1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 ++#define D2F1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 ++#define D2F1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 ++#define D2F1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 ++#define D2F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 ++#define D2F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 ++#define D2F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 ++#define D2F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 ++#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 ++#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 ++#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 ++#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 ++#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 ++#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 ++#define D2F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff ++#define D2F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 ++#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 ++#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 ++#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 ++#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e ++#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 ++#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f ++#define D2F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff ++#define D2F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 ++#define D2F1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 ++#define D2F1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 ++#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 ++#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 ++#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 ++#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf ++#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 ++#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 ++#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff ++#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 ++#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 ++#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc ++#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff ++#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 ++#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 ++#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 ++#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff ++#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 ++#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 ++#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 ++#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff ++#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 ++#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 ++#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 ++#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff ++#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 ++#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 ++#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 ++#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff ++#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 ++#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 ++#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 ++#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff ++#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 ++#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 ++#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 ++#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 ++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 ++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 ++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 ++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 ++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 ++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 ++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 ++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 ++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 ++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 ++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 ++#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 ++#define D2F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 ++#define D2F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 ++#define D2F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e ++#define D2F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 ++#define D2F1_PCIE_FC_P__PD_CREDITS_MASK 0xff ++#define D2F1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 ++#define D2F1_PCIE_FC_P__PH_CREDITS_MASK 0xff00 ++#define D2F1_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 ++#define D2F1_PCIE_FC_NP__NPD_CREDITS_MASK 0xff ++#define D2F1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 ++#define D2F1_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 ++#define D2F1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 ++#define D2F1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff ++#define D2F1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 ++#define D2F1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 ++#define D2F1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 ++#define D2F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 ++#define D2F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 ++#define D2F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 ++#define D2F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 ++#define D2F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 ++#define D2F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 ++#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 ++#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 ++#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 ++#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 ++#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 ++#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 ++#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 ++#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 ++#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 ++#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 ++#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 ++#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb ++#define D2F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 ++#define D2F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe ++#define D2F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 ++#define D2F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf ++#define D2F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 ++#define D2F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 ++#define D2F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 ++#define D2F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 ++#define D2F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 ++#define D2F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc ++#define D2F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 ++#define D2F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd ++#define D2F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 ++#define D2F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe ++#define D2F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 ++#define D2F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf ++#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 ++#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 ++#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 ++#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 ++#define D2F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 ++#define D2F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 ++#define D2F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 ++#define D2F1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 ++#define D2F1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a ++#define D2F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 ++#define D2F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b ++#define D2F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff ++#define D2F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 ++#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff ++#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 ++#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 ++#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 ++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 ++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 ++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 ++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 ++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 ++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 ++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 ++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 ++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 ++#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 ++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff ++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 ++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 ++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 ++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff ++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 ++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 ++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 ++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff ++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 ++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 ++#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 ++#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 ++#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 ++#define D2F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 ++#define D2F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 ++#define D2F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 ++#define D2F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 ++#define D2F1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 ++#define D2F1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 ++#define D2F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 ++#define D2F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 ++#define D2F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 ++#define D2F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 ++#define D2F1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 ++#define D2F1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc ++#define D2F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 ++#define D2F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 ++#define D2F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 ++#define D2F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 ++#define D2F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 ++#define D2F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 ++#define D2F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 ++#define D2F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 ++#define D2F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 ++#define D2F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 ++#define D2F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 ++#define D2F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 ++#define D2F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 ++#define D2F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 ++#define D2F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 ++#define D2F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 ++#define D2F1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 ++#define D2F1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 ++#define D2F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 ++#define D2F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b ++#define D2F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 ++#define D2F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c ++#define D2F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 ++#define D2F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d ++#define D2F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 ++#define D2F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e ++#define D2F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 ++#define D2F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f ++#define D2F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f ++#define D2F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 ++#define D2F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 ++#define D2F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 ++#define D2F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 ++#define D2F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 ++#define D2F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 ++#define D2F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 ++#define D2F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 ++#define D2F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 ++#define D2F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 ++#define D2F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa ++#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 ++#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb ++#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 ++#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc ++#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 ++#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd ++#define D2F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 ++#define D2F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe ++#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 ++#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 ++#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 ++#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 ++#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 ++#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 ++#define D2F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 ++#define D2F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 ++#define D2F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 ++#define D2F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 ++#define D2F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 ++#define D2F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 ++#define D2F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 ++#define D2F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 ++#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 ++#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 ++#define D2F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 ++#define D2F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 ++#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 ++#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a ++#define D2F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 ++#define D2F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b ++#define D2F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 ++#define D2F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c ++#define D2F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 ++#define D2F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d ++#define D2F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 ++#define D2F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f ++#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 ++#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 ++#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 ++#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 ++#define D2F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 ++#define D2F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 ++#define D2F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 ++#define D2F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 ++#define D2F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 ++#define D2F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 ++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 ++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 ++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 ++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 ++#define D2F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 ++#define D2F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 ++#define D2F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 ++#define D2F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa ++#define D2F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 ++#define D2F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb ++#define D2F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 ++#define D2F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc ++#define D2F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 ++#define D2F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe ++#define D2F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 ++#define D2F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 ++#define D2F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 ++#define D2F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 ++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 ++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 ++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 ++#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 ++#define D2F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 ++#define D2F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 ++#define D2F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 ++#define D2F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 ++#define D2F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 ++#define D2F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 ++#define D2F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 ++#define D2F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 ++#define D2F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 ++#define D2F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a ++#define D2F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 ++#define D2F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e ++#define D2F1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 ++#define D2F1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f ++#define D2F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 ++#define D2F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 ++#define D2F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 ++#define D2F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 ++#define D2F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 ++#define D2F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 ++#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 ++#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 ++#define D2F1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 ++#define D2F1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 ++#define D2F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 ++#define D2F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 ++#define D2F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 ++#define D2F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 ++#define D2F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 ++#define D2F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 ++#define D2F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 ++#define D2F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa ++#define D2F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 ++#define D2F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb ++#define D2F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 ++#define D2F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc ++#define D2F1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 ++#define D2F1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd ++#define D2F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 ++#define D2F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe ++#define D2F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 ++#define D2F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf ++#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 ++#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 ++#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 ++#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 ++#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 ++#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 ++#define D2F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 ++#define D2F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 ++#define D2F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 ++#define D2F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 ++#define D2F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 ++#define D2F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 ++#define D2F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 ++#define D2F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 ++#define D2F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 ++#define D2F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a ++#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f ++#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 ++#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 ++#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 ++#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 ++#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc ++#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 ++#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 ++#define D2F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 ++#define D2F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 ++#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 ++#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 ++#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 ++#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 ++#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 ++#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 ++#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 ++#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 ++#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d ++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff ++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 ++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 ++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 ++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 ++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 ++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 ++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 ++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 ++#define D2F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 ++#define D2F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f ++#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff ++#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 ++#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 ++#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc ++#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 ++#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 ++#define D2F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff ++#define D2F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 ++#define D2F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 ++#define D2F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 ++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 ++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 ++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e ++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 ++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 ++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 ++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 ++#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd ++#define D2F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 ++#define D2F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 ++#define D2F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 ++#define D2F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 ++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf ++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 ++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 ++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 ++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 ++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa ++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 ++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 ++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 ++#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 ++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 ++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 ++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e ++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 ++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 ++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 ++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 ++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd ++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 ++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 ++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 ++#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 ++#define D2F1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f ++#define D2F1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 ++#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 ++#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 ++#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 ++#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 ++#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 ++#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 ++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f ++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 ++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 ++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 ++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 ++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 ++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 ++#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 ++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f ++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 ++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 ++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 ++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 ++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 ++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 ++#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 ++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f ++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 ++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 ++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 ++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 ++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 ++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 ++#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 ++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f ++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 ++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 ++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 ++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 ++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 ++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 ++#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 ++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f ++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 ++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 ++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 ++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 ++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 ++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 ++#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 ++#define D2F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 ++#define D2F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 ++#define D2F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc ++#define D2F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 ++#define D2F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 ++#define D2F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 ++#define D2F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 ++#define D2F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 ++#define D2F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 ++#define D2F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 ++#define D2F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 ++#define D2F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb ++#define D2F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 ++#define D2F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc ++#define D2F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 ++#define D2F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd ++#define D2F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 ++#define D2F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe ++#define D2F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 ++#define D2F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf ++#define D2F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 ++#define D2F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 ++#define D2F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 ++#define D2F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 ++#define D2F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 ++#define D2F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 ++#define D2F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 ++#define D2F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 ++#define D2F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 ++#define D2F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 ++#define D2F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 ++#define D2F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 ++#define D2F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 ++#define D2F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 ++#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 ++#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 ++#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 ++#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 ++#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 ++#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 ++#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 ++#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 ++#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 ++#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 ++#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 ++#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 ++#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 ++#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 ++#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 ++#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 ++#define D2F1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 ++#define D2F1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 ++#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 ++#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 ++#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 ++#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 ++#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 ++#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa ++#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 ++#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb ++#define D2F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 ++#define D2F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf ++#define D2F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 ++#define D2F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 ++#define D2F1_VENDOR_ID__VENDOR_ID_MASK 0xffff ++#define D2F1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 ++#define D2F1_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 ++#define D2F1_DEVICE_ID__DEVICE_ID__SHIFT 0x10 ++#define D2F1_COMMAND__IO_ACCESS_EN_MASK 0x1 ++#define D2F1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 ++#define D2F1_COMMAND__MEM_ACCESS_EN_MASK 0x2 ++#define D2F1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 ++#define D2F1_COMMAND__BUS_MASTER_EN_MASK 0x4 ++#define D2F1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 ++#define D2F1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 ++#define D2F1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 ++#define D2F1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 ++#define D2F1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 ++#define D2F1_COMMAND__PAL_SNOOP_EN_MASK 0x20 ++#define D2F1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 ++#define D2F1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 ++#define D2F1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 ++#define D2F1_COMMAND__AD_STEPPING_MASK 0x80 ++#define D2F1_COMMAND__AD_STEPPING__SHIFT 0x7 ++#define D2F1_COMMAND__SERR_EN_MASK 0x100 ++#define D2F1_COMMAND__SERR_EN__SHIFT 0x8 ++#define D2F1_COMMAND__FAST_B2B_EN_MASK 0x200 ++#define D2F1_COMMAND__FAST_B2B_EN__SHIFT 0x9 ++#define D2F1_COMMAND__INT_DIS_MASK 0x400 ++#define D2F1_COMMAND__INT_DIS__SHIFT 0xa ++#define D2F1_STATUS__INT_STATUS_MASK 0x80000 ++#define D2F1_STATUS__INT_STATUS__SHIFT 0x13 ++#define D2F1_STATUS__CAP_LIST_MASK 0x100000 ++#define D2F1_STATUS__CAP_LIST__SHIFT 0x14 ++#define D2F1_STATUS__PCI_66_EN_MASK 0x200000 ++#define D2F1_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D2F1_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D2F1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D2F1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D2F1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D2F1_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D2F1_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D2F1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D2F1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D2F1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D2F1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D2F1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D2F1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D2F1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 ++#define D2F1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e ++#define D2F1_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D2F1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D2F1_REVISION_ID__MINOR_REV_ID_MASK 0xf ++#define D2F1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 ++#define D2F1_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 ++#define D2F1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 ++#define D2F1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 ++#define D2F1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 ++#define D2F1_SUB_CLASS__SUB_CLASS_MASK 0xff0000 ++#define D2F1_SUB_CLASS__SUB_CLASS__SHIFT 0x10 ++#define D2F1_BASE_CLASS__BASE_CLASS_MASK 0xff000000 ++#define D2F1_BASE_CLASS__BASE_CLASS__SHIFT 0x18 ++#define D2F1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff ++#define D2F1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 ++#define D2F1_LATENCY__LATENCY_TIMER_MASK 0xff00 ++#define D2F1_LATENCY__LATENCY_TIMER__SHIFT 0x8 ++#define D2F1_HEADER__HEADER_TYPE_MASK 0x7f0000 ++#define D2F1_HEADER__HEADER_TYPE__SHIFT 0x10 ++#define D2F1_HEADER__DEVICE_TYPE_MASK 0x800000 ++#define D2F1_HEADER__DEVICE_TYPE__SHIFT 0x17 ++#define D2F1_BIST__BIST_COMP_MASK 0xf000000 ++#define D2F1_BIST__BIST_COMP__SHIFT 0x18 ++#define D2F1_BIST__BIST_STRT_MASK 0x40000000 ++#define D2F1_BIST__BIST_STRT__SHIFT 0x1e ++#define D2F1_BIST__BIST_CAP_MASK 0x80000000 ++#define D2F1_BIST__BIST_CAP__SHIFT 0x1f ++#define D2F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff ++#define D2F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 ++#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 ++#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 ++#define D2F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 ++#define D2F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 ++#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 ++#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 ++#define D2F1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf ++#define D2F1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 ++#define D2F1_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 ++#define D2F1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 ++#define D2F1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 ++#define D2F1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 ++#define D2F1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 ++#define D2F1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc ++#define D2F1_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 ++#define D2F1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 ++#define D2F1_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 ++#define D2F1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D2F1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D2F1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D2F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D2F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D2F1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D2F1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D2F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D2F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D2F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D2F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D2F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D2F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D2F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 ++#define D2F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e ++#define D2F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D2F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D2F1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf ++#define D2F1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 ++#define D2F1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 ++#define D2F1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 ++#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 ++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf ++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 ++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 ++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 ++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 ++#define D2F1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff ++#define D2F1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 ++#define D2F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff ++#define D2F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 ++#define D2F1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff ++#define D2F1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 ++#define D2F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 ++#define D2F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 ++#define D2F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 ++#define D2F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 ++#define D2F1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 ++#define D2F1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 ++#define D2F1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 ++#define D2F1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 ++#define D2F1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 ++#define D2F1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 ++#define D2F1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 ++#define D2F1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 ++#define D2F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 ++#define D2F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 ++#define D2F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 ++#define D2F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 ++#define D2F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 ++#define D2F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 ++#define D2F1_CAP_PTR__CAP_PTR_MASK 0xff ++#define D2F1_CAP_PTR__CAP_PTR__SHIFT 0x0 ++#define D2F1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff ++#define D2F1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 ++#define D2F1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 ++#define D2F1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 ++#define D2F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 ++#define D2F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 ++#define D2F1_PMI_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F1_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F1_PMI_CAP__VERSION_MASK 0x70000 ++#define D2F1_PMI_CAP__VERSION__SHIFT 0x10 ++#define D2F1_PMI_CAP__PME_CLOCK_MASK 0x80000 ++#define D2F1_PMI_CAP__PME_CLOCK__SHIFT 0x13 ++#define D2F1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 ++#define D2F1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 ++#define D2F1_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 ++#define D2F1_PMI_CAP__AUX_CURRENT__SHIFT 0x16 ++#define D2F1_PMI_CAP__D1_SUPPORT_MASK 0x2000000 ++#define D2F1_PMI_CAP__D1_SUPPORT__SHIFT 0x19 ++#define D2F1_PMI_CAP__D2_SUPPORT_MASK 0x4000000 ++#define D2F1_PMI_CAP__D2_SUPPORT__SHIFT 0x1a ++#define D2F1_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 ++#define D2F1_PMI_CAP__PME_SUPPORT__SHIFT 0x1b ++#define D2F1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 ++#define D2F1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 ++#define D2F1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 ++#define D2F1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 ++#define D2F1_PMI_STATUS_CNTL__PME_EN_MASK 0x100 ++#define D2F1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 ++#define D2F1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 ++#define D2F1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 ++#define D2F1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 ++#define D2F1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd ++#define D2F1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 ++#define D2F1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf ++#define D2F1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 ++#define D2F1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 ++#define D2F1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 ++#define D2F1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 ++#define D2F1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 ++#define D2F1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 ++#define D2F1_PCIE_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F1_PCIE_CAP__VERSION_MASK 0xf0000 ++#define D2F1_PCIE_CAP__VERSION__SHIFT 0x10 ++#define D2F1_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 ++#define D2F1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 ++#define D2F1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 ++#define D2F1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 ++#define D2F1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 ++#define D2F1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 ++#define D2F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 ++#define D2F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 ++#define D2F1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 ++#define D2F1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 ++#define D2F1_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 ++#define D2F1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 ++#define D2F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 ++#define D2F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 ++#define D2F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 ++#define D2F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 ++#define D2F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 ++#define D2F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf ++#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 ++#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 ++#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 ++#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a ++#define D2F1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 ++#define D2F1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c ++#define D2F1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 ++#define D2F1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 ++#define D2F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 ++#define D2F1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 ++#define D2F1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 ++#define D2F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 ++#define D2F1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 ++#define D2F1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 ++#define D2F1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 ++#define D2F1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 ++#define D2F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 ++#define D2F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 ++#define D2F1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 ++#define D2F1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 ++#define D2F1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 ++#define D2F1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 ++#define D2F1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 ++#define D2F1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa ++#define D2F1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 ++#define D2F1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb ++#define D2F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 ++#define D2F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc ++#define D2F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 ++#define D2F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf ++#define D2F1_DEVICE_STATUS__CORR_ERR_MASK 0x10000 ++#define D2F1_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 ++#define D2F1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 ++#define D2F1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 ++#define D2F1_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 ++#define D2F1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 ++#define D2F1_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 ++#define D2F1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 ++#define D2F1_DEVICE_STATUS__AUX_PWR_MASK 0x100000 ++#define D2F1_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 ++#define D2F1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 ++#define D2F1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 ++#define D2F1_LINK_CAP__LINK_SPEED_MASK 0xf ++#define D2F1_LINK_CAP__LINK_SPEED__SHIFT 0x0 ++#define D2F1_LINK_CAP__LINK_WIDTH_MASK 0x3f0 ++#define D2F1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 ++#define D2F1_LINK_CAP__PM_SUPPORT_MASK 0xc00 ++#define D2F1_LINK_CAP__PM_SUPPORT__SHIFT 0xa ++#define D2F1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 ++#define D2F1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc ++#define D2F1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 ++#define D2F1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf ++#define D2F1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 ++#define D2F1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 ++#define D2F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 ++#define D2F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 ++#define D2F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 ++#define D2F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 ++#define D2F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 ++#define D2F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 ++#define D2F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 ++#define D2F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 ++#define D2F1_LINK_CAP__PORT_NUMBER_MASK 0xff000000 ++#define D2F1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 ++#define D2F1_LINK_CNTL__PM_CONTROL_MASK 0x3 ++#define D2F1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 ++#define D2F1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 ++#define D2F1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 ++#define D2F1_LINK_CNTL__LINK_DIS_MASK 0x10 ++#define D2F1_LINK_CNTL__LINK_DIS__SHIFT 0x4 ++#define D2F1_LINK_CNTL__RETRAIN_LINK_MASK 0x20 ++#define D2F1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 ++#define D2F1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 ++#define D2F1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 ++#define D2F1_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 ++#define D2F1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 ++#define D2F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 ++#define D2F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 ++#define D2F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 ++#define D2F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 ++#define D2F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 ++#define D2F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa ++#define D2F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 ++#define D2F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb ++#define D2F1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 ++#define D2F1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 ++#define D2F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 ++#define D2F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 ++#define D2F1_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 ++#define D2F1_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b ++#define D2F1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 ++#define D2F1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c ++#define D2F1_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 ++#define D2F1_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d ++#define D2F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 ++#define D2F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e ++#define D2F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 ++#define D2F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f ++#define D2F1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 ++#define D2F1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 ++#define D2F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 ++#define D2F1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 ++#define D2F1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 ++#define D2F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 ++#define D2F1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 ++#define D2F1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 ++#define D2F1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 ++#define D2F1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 ++#define D2F1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 ++#define D2F1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 ++#define D2F1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 ++#define D2F1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 ++#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 ++#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 ++#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 ++#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf ++#define D2F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 ++#define D2F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 ++#define D2F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 ++#define D2F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 ++#define D2F1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 ++#define D2F1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 ++#define D2F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 ++#define D2F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 ++#define D2F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 ++#define D2F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 ++#define D2F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 ++#define D2F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 ++#define D2F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 ++#define D2F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 ++#define D2F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 ++#define D2F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 ++#define D2F1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 ++#define D2F1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 ++#define D2F1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 ++#define D2F1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 ++#define D2F1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 ++#define D2F1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 ++#define D2F1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 ++#define D2F1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa ++#define D2F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 ++#define D2F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb ++#define D2F1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 ++#define D2F1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc ++#define D2F1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 ++#define D2F1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 ++#define D2F1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 ++#define D2F1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 ++#define D2F1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 ++#define D2F1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 ++#define D2F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 ++#define D2F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 ++#define D2F1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 ++#define D2F1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 ++#define D2F1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 ++#define D2F1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 ++#define D2F1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 ++#define D2F1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 ++#define D2F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 ++#define D2F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 ++#define D2F1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 ++#define D2F1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 ++#define D2F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 ++#define D2F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 ++#define D2F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 ++#define D2F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 ++#define D2F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 ++#define D2F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 ++#define D2F1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 ++#define D2F1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 ++#define D2F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 ++#define D2F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 ++#define D2F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 ++#define D2F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 ++#define D2F1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff ++#define D2F1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 ++#define D2F1_ROOT_STATUS__PME_STATUS_MASK 0x10000 ++#define D2F1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 ++#define D2F1_ROOT_STATUS__PME_PENDING_MASK 0x20000 ++#define D2F1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 ++#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf ++#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 ++#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 ++#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 ++#define D2F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 ++#define D2F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 ++#define D2F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 ++#define D2F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 ++#define D2F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 ++#define D2F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 ++#define D2F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 ++#define D2F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 ++#define D2F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 ++#define D2F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 ++#define D2F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 ++#define D2F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa ++#define D2F1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 ++#define D2F1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb ++#define D2F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 ++#define D2F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc ++#define D2F1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 ++#define D2F1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 ++#define D2F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 ++#define D2F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 ++#define D2F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 ++#define D2F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 ++#define D2F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 ++#define D2F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 ++#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf ++#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 ++#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 ++#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 ++#define D2F1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 ++#define D2F1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 ++#define D2F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 ++#define D2F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 ++#define D2F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 ++#define D2F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 ++#define D2F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 ++#define D2F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 ++#define D2F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 ++#define D2F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 ++#define D2F1_DEVICE_CNTL2__LTR_EN_MASK 0x400 ++#define D2F1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa ++#define D2F1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 ++#define D2F1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd ++#define D2F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 ++#define D2F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf ++#define D2F1_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 ++#define D2F1_DEVICE_STATUS2__RESERVED__SHIFT 0x10 ++#define D2F1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe ++#define D2F1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 ++#define D2F1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 ++#define D2F1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 ++#define D2F1_LINK_CAP2__RESERVED_MASK 0xfffffe00 ++#define D2F1_LINK_CAP2__RESERVED__SHIFT 0x9 ++#define D2F1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf ++#define D2F1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 ++#define D2F1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 ++#define D2F1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 ++#define D2F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 ++#define D2F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 ++#define D2F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 ++#define D2F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 ++#define D2F1_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 ++#define D2F1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 ++#define D2F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 ++#define D2F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa ++#define D2F1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 ++#define D2F1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb ++#define D2F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 ++#define D2F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc ++#define D2F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 ++#define D2F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 ++#define D2F1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 ++#define D2F1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 ++#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 ++#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 ++#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 ++#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 ++#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 ++#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 ++#define D2F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 ++#define D2F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 ++#define D2F1_SLOT_CAP2__RESERVED_MASK 0xffffffff ++#define D2F1_SLOT_CAP2__RESERVED__SHIFT 0x0 ++#define D2F1_SLOT_CNTL2__RESERVED_MASK 0xffff ++#define D2F1_SLOT_CNTL2__RESERVED__SHIFT 0x0 ++#define D2F1_SLOT_STATUS2__RESERVED_MASK 0xffff0000 ++#define D2F1_SLOT_STATUS2__RESERVED__SHIFT 0x10 ++#define D2F1_MSI_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F1_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F1_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 ++#define D2F1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 ++#define D2F1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 ++#define D2F1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 ++#define D2F1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 ++#define D2F1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 ++#define D2F1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 ++#define D2F1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 ++#define D2F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 ++#define D2F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 ++#define D2F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc ++#define D2F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 ++#define D2F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff ++#define D2F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 ++#define D2F1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff ++#define D2F1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 ++#define D2F1_MSI_MSG_DATA__MSI_DATA_MASK 0xffff ++#define D2F1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 ++#define D2F1_SSID_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F1_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff ++#define D2F1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define D2F1_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 ++#define D2F1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 ++#define D2F1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F1_MSI_MAP_CAP__EN_MASK 0x10000 ++#define D2F1_MSI_MAP_CAP__EN__SHIFT 0x10 ++#define D2F1_MSI_MAP_CAP__FIXD_MASK 0x20000 ++#define D2F1_MSI_MAP_CAP__FIXD__SHIFT 0x11 ++#define D2F1_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 ++#define D2F1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b ++#define D2F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 ++#define D2F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 ++#define D2F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff ++#define D2F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 ++#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff ++#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 ++#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 ++#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 ++#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 ++#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 ++#define D2F1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff ++#define D2F1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 ++#define D2F1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff ++#define D2F1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 ++#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 ++#define D2F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 ++#define D2F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 ++#define D2F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 ++#define D2F1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 ++#define D2F1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 ++#define D2F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 ++#define D2F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa ++#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff ++#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 ++#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 ++#define D2F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 ++#define D2F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe ++#define D2F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 ++#define D2F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D2F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D2F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D2F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D2F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D2F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D2F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D2F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D2F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D2F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D2F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D2F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D2F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D2F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D2F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D2F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D2F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D2F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D2F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D2F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D2F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff ++#define D2F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 ++#define D2F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff ++#define D2F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 ++#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc ++#define D2F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd ++#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe ++#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf ++#define D2F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 ++#define D2F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 ++#define D2F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 ++#define D2F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 ++#define D2F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 ++#define D2F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 ++#define D2F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc ++#define D2F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd ++#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe ++#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf ++#define D2F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 ++#define D2F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 ++#define D2F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 ++#define D2F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 ++#define D2F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 ++#define D2F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 ++#define D2F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 ++#define D2F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 ++#define D2F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 ++#define D2F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 ++#define D2F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 ++#define D2F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 ++#define D2F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 ++#define D2F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 ++#define D2F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 ++#define D2F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 ++#define D2F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 ++#define D2F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 ++#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 ++#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 ++#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 ++#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc ++#define D2F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 ++#define D2F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd ++#define D2F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 ++#define D2F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe ++#define D2F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 ++#define D2F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf ++#define D2F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 ++#define D2F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 ++#define D2F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 ++#define D2F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 ++#define D2F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 ++#define D2F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 ++#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 ++#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 ++#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 ++#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc ++#define D2F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 ++#define D2F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd ++#define D2F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 ++#define D2F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe ++#define D2F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 ++#define D2F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 ++#define D2F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb ++#define D2F1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff ++#define D2F1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 ++#define D2F1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff ++#define D2F1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 ++#define D2F1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff ++#define D2F1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 ++#define D2F1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff ++#define D2F1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 ++#define D2F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 ++#define D2F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 ++#define D2F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 ++#define D2F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 ++#define D2F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 ++#define D2F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 ++#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 ++#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 ++#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 ++#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 ++#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 ++#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 ++#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 ++#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 ++#define D2F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 ++#define D2F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 ++#define D2F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 ++#define D2F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 ++#define D2F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 ++#define D2F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 ++#define D2F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 ++#define D2F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b ++#define D2F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff ++#define D2F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 ++#define D2F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 ++#define D2F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 ++#define D2F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff ++#define D2F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 ++#define D2F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff ++#define D2F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 ++#define D2F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff ++#define D2F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 ++#define D2F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff ++#define D2F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 ++#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 ++#define D2F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 ++#define D2F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 ++#define D2F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 ++#define D2F1_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc ++#define D2F1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 ++#define D2F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff ++#define D2F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 ++#define D2F1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 ++#define D2F1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 ++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 ++#define D2F1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 ++#define D2F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 ++#define D2F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 ++#define D2F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 ++#define D2F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 ++#define D2F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 ++#define D2F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 ++#define D2F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 ++#define D2F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 ++#define D2F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 ++#define D2F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 ++#define D2F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 ++#define D2F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 ++#define D2F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 ++#define D2F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 ++#define D2F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 ++#define D2F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 ++#define D2F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 ++#define D2F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 ++#define D2F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 ++#define D2F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 ++#define D2F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 ++#define D2F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 ++#define D2F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 ++#define D2F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 ++#define D2F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 ++#define D2F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 ++#define D2F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 ++#define D2F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 ++#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f ++#define D2F1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 ++#define D2F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 ++#define D2F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf ++#define D2F1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 ++#define D2F1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 ++#define D2F1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 ++#define D2F1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f ++#define D2F1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f ++#define D2F1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 ++#define D2F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 ++#define D2F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc ++#define D2F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff ++#define D2F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 ++#define D2F1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff ++#define D2F1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 ++#define D2F1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff ++#define D2F1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 ++#define D2F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff ++#define D2F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 ++#define D2F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff ++#define D2F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 ++#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff ++#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 ++#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff ++#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 ++#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f ++#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 ++#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 ++#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 ++#define D2F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff ++#define D2F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 ++#define D2F2_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff ++#define D2F2_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 ++#define D2F2_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff ++#define D2F2_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 ++#define D2F2_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff ++#define D2F2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 ++#define D2F2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff ++#define D2F2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 ++#define D2F2_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define D2F2_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define D2F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define D2F2_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define D2F2_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define D2F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define D2F2_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define D2F2_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define D2F2_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define D2F2_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define D2F2_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define D2F2_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define D2F2_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define D2F2_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define D2F2_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define D2F2_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define D2F2_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define D2F2_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define D2F2_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define D2F2_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define D2F2_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define D2F2_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define D2F2_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define D2F2_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define D2F2_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define D2F2_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define D2F2_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define D2F2_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define D2F2_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define D2F2_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define D2F2_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define D2F2_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define D2F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 ++#define D2F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 ++#define D2F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 ++#define D2F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 ++#define D2F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 ++#define D2F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 ++#define D2F2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 ++#define D2F2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 ++#define D2F2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 ++#define D2F2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 ++#define D2F2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 ++#define D2F2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 ++#define D2F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 ++#define D2F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 ++#define D2F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 ++#define D2F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 ++#define D2F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 ++#define D2F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define D2F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 ++#define D2F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 ++#define D2F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 ++#define D2F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa ++#define D2F2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 ++#define D2F2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc ++#define D2F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 ++#define D2F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe ++#define D2F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 ++#define D2F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf ++#define D2F2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 ++#define D2F2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 ++#define D2F2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 ++#define D2F2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 ++#define D2F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 ++#define D2F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 ++#define D2F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 ++#define D2F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 ++#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 ++#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 ++#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 ++#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 ++#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 ++#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 ++#define D2F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff ++#define D2F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 ++#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 ++#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 ++#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 ++#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e ++#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 ++#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f ++#define D2F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff ++#define D2F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 ++#define D2F2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 ++#define D2F2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 ++#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 ++#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 ++#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 ++#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf ++#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 ++#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 ++#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff ++#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 ++#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 ++#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc ++#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff ++#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 ++#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 ++#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 ++#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff ++#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 ++#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 ++#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 ++#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff ++#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 ++#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 ++#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 ++#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff ++#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 ++#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 ++#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 ++#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff ++#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 ++#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 ++#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 ++#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff ++#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 ++#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 ++#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 ++#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 ++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 ++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 ++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 ++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 ++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 ++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 ++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 ++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 ++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 ++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 ++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 ++#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 ++#define D2F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 ++#define D2F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 ++#define D2F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e ++#define D2F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 ++#define D2F2_PCIE_FC_P__PD_CREDITS_MASK 0xff ++#define D2F2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 ++#define D2F2_PCIE_FC_P__PH_CREDITS_MASK 0xff00 ++#define D2F2_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 ++#define D2F2_PCIE_FC_NP__NPD_CREDITS_MASK 0xff ++#define D2F2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 ++#define D2F2_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 ++#define D2F2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 ++#define D2F2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff ++#define D2F2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 ++#define D2F2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 ++#define D2F2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 ++#define D2F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 ++#define D2F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 ++#define D2F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 ++#define D2F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 ++#define D2F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 ++#define D2F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 ++#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 ++#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 ++#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 ++#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 ++#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 ++#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 ++#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 ++#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 ++#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 ++#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 ++#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 ++#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb ++#define D2F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 ++#define D2F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe ++#define D2F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 ++#define D2F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf ++#define D2F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 ++#define D2F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 ++#define D2F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 ++#define D2F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 ++#define D2F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 ++#define D2F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc ++#define D2F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 ++#define D2F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd ++#define D2F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 ++#define D2F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe ++#define D2F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 ++#define D2F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf ++#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 ++#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 ++#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 ++#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 ++#define D2F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 ++#define D2F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 ++#define D2F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 ++#define D2F2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 ++#define D2F2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a ++#define D2F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 ++#define D2F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b ++#define D2F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff ++#define D2F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 ++#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff ++#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 ++#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 ++#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 ++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 ++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 ++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 ++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 ++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 ++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 ++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 ++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 ++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 ++#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 ++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff ++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 ++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 ++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 ++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff ++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 ++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 ++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 ++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff ++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 ++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 ++#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 ++#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 ++#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 ++#define D2F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 ++#define D2F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 ++#define D2F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 ++#define D2F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 ++#define D2F2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 ++#define D2F2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 ++#define D2F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 ++#define D2F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 ++#define D2F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 ++#define D2F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 ++#define D2F2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 ++#define D2F2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc ++#define D2F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 ++#define D2F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 ++#define D2F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 ++#define D2F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 ++#define D2F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 ++#define D2F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 ++#define D2F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 ++#define D2F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 ++#define D2F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 ++#define D2F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 ++#define D2F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 ++#define D2F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 ++#define D2F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 ++#define D2F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 ++#define D2F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 ++#define D2F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 ++#define D2F2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 ++#define D2F2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 ++#define D2F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 ++#define D2F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b ++#define D2F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 ++#define D2F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c ++#define D2F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 ++#define D2F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d ++#define D2F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 ++#define D2F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e ++#define D2F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 ++#define D2F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f ++#define D2F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f ++#define D2F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 ++#define D2F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 ++#define D2F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 ++#define D2F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 ++#define D2F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 ++#define D2F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 ++#define D2F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 ++#define D2F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 ++#define D2F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 ++#define D2F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 ++#define D2F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa ++#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 ++#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb ++#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 ++#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc ++#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 ++#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd ++#define D2F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 ++#define D2F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe ++#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 ++#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 ++#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 ++#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 ++#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 ++#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 ++#define D2F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 ++#define D2F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 ++#define D2F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 ++#define D2F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 ++#define D2F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 ++#define D2F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 ++#define D2F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 ++#define D2F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 ++#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 ++#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 ++#define D2F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 ++#define D2F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 ++#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 ++#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a ++#define D2F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 ++#define D2F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b ++#define D2F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 ++#define D2F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c ++#define D2F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 ++#define D2F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d ++#define D2F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 ++#define D2F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f ++#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 ++#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 ++#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 ++#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 ++#define D2F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 ++#define D2F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 ++#define D2F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 ++#define D2F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 ++#define D2F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 ++#define D2F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 ++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 ++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 ++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 ++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 ++#define D2F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 ++#define D2F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 ++#define D2F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 ++#define D2F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa ++#define D2F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 ++#define D2F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb ++#define D2F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 ++#define D2F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc ++#define D2F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 ++#define D2F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe ++#define D2F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 ++#define D2F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 ++#define D2F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 ++#define D2F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 ++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 ++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 ++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 ++#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 ++#define D2F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 ++#define D2F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 ++#define D2F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 ++#define D2F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 ++#define D2F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 ++#define D2F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 ++#define D2F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 ++#define D2F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 ++#define D2F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 ++#define D2F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a ++#define D2F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 ++#define D2F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e ++#define D2F2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 ++#define D2F2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f ++#define D2F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 ++#define D2F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 ++#define D2F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 ++#define D2F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 ++#define D2F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 ++#define D2F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 ++#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 ++#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 ++#define D2F2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 ++#define D2F2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 ++#define D2F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 ++#define D2F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 ++#define D2F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 ++#define D2F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 ++#define D2F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 ++#define D2F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 ++#define D2F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 ++#define D2F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa ++#define D2F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 ++#define D2F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb ++#define D2F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 ++#define D2F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc ++#define D2F2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 ++#define D2F2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd ++#define D2F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 ++#define D2F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe ++#define D2F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 ++#define D2F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf ++#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 ++#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 ++#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 ++#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 ++#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 ++#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 ++#define D2F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 ++#define D2F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 ++#define D2F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 ++#define D2F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 ++#define D2F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 ++#define D2F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 ++#define D2F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 ++#define D2F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 ++#define D2F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 ++#define D2F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a ++#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f ++#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 ++#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 ++#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 ++#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 ++#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc ++#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 ++#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 ++#define D2F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 ++#define D2F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 ++#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 ++#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 ++#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 ++#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 ++#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 ++#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 ++#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 ++#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 ++#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d ++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff ++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 ++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 ++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 ++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 ++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 ++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 ++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 ++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 ++#define D2F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 ++#define D2F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f ++#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff ++#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 ++#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 ++#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc ++#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 ++#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 ++#define D2F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff ++#define D2F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 ++#define D2F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 ++#define D2F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 ++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 ++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 ++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e ++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 ++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 ++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 ++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 ++#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd ++#define D2F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 ++#define D2F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 ++#define D2F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 ++#define D2F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 ++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf ++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 ++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 ++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 ++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 ++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa ++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 ++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 ++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 ++#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 ++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 ++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 ++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e ++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 ++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 ++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 ++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 ++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd ++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 ++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 ++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 ++#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 ++#define D2F2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f ++#define D2F2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 ++#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 ++#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 ++#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 ++#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 ++#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 ++#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 ++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f ++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 ++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 ++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 ++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 ++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 ++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 ++#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 ++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f ++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 ++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 ++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 ++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 ++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 ++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 ++#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 ++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f ++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 ++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 ++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 ++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 ++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 ++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 ++#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 ++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f ++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 ++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 ++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 ++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 ++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 ++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 ++#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 ++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f ++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 ++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 ++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 ++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 ++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 ++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 ++#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 ++#define D2F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 ++#define D2F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 ++#define D2F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc ++#define D2F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 ++#define D2F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 ++#define D2F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 ++#define D2F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 ++#define D2F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 ++#define D2F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 ++#define D2F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 ++#define D2F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 ++#define D2F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb ++#define D2F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 ++#define D2F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc ++#define D2F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 ++#define D2F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd ++#define D2F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 ++#define D2F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe ++#define D2F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 ++#define D2F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf ++#define D2F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 ++#define D2F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 ++#define D2F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 ++#define D2F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 ++#define D2F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 ++#define D2F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 ++#define D2F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 ++#define D2F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 ++#define D2F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 ++#define D2F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 ++#define D2F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 ++#define D2F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 ++#define D2F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 ++#define D2F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 ++#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 ++#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 ++#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 ++#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 ++#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 ++#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 ++#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 ++#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 ++#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 ++#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 ++#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 ++#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 ++#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 ++#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 ++#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 ++#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 ++#define D2F2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 ++#define D2F2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 ++#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 ++#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 ++#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 ++#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 ++#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 ++#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa ++#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 ++#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb ++#define D2F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 ++#define D2F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf ++#define D2F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 ++#define D2F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 ++#define D2F2_VENDOR_ID__VENDOR_ID_MASK 0xffff ++#define D2F2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 ++#define D2F2_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 ++#define D2F2_DEVICE_ID__DEVICE_ID__SHIFT 0x10 ++#define D2F2_COMMAND__IO_ACCESS_EN_MASK 0x1 ++#define D2F2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 ++#define D2F2_COMMAND__MEM_ACCESS_EN_MASK 0x2 ++#define D2F2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 ++#define D2F2_COMMAND__BUS_MASTER_EN_MASK 0x4 ++#define D2F2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 ++#define D2F2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 ++#define D2F2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 ++#define D2F2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 ++#define D2F2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 ++#define D2F2_COMMAND__PAL_SNOOP_EN_MASK 0x20 ++#define D2F2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 ++#define D2F2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 ++#define D2F2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 ++#define D2F2_COMMAND__AD_STEPPING_MASK 0x80 ++#define D2F2_COMMAND__AD_STEPPING__SHIFT 0x7 ++#define D2F2_COMMAND__SERR_EN_MASK 0x100 ++#define D2F2_COMMAND__SERR_EN__SHIFT 0x8 ++#define D2F2_COMMAND__FAST_B2B_EN_MASK 0x200 ++#define D2F2_COMMAND__FAST_B2B_EN__SHIFT 0x9 ++#define D2F2_COMMAND__INT_DIS_MASK 0x400 ++#define D2F2_COMMAND__INT_DIS__SHIFT 0xa ++#define D2F2_STATUS__INT_STATUS_MASK 0x80000 ++#define D2F2_STATUS__INT_STATUS__SHIFT 0x13 ++#define D2F2_STATUS__CAP_LIST_MASK 0x100000 ++#define D2F2_STATUS__CAP_LIST__SHIFT 0x14 ++#define D2F2_STATUS__PCI_66_EN_MASK 0x200000 ++#define D2F2_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D2F2_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D2F2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D2F2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D2F2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D2F2_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D2F2_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D2F2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D2F2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D2F2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D2F2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D2F2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D2F2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D2F2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 ++#define D2F2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e ++#define D2F2_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D2F2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D2F2_REVISION_ID__MINOR_REV_ID_MASK 0xf ++#define D2F2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 ++#define D2F2_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 ++#define D2F2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 ++#define D2F2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 ++#define D2F2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 ++#define D2F2_SUB_CLASS__SUB_CLASS_MASK 0xff0000 ++#define D2F2_SUB_CLASS__SUB_CLASS__SHIFT 0x10 ++#define D2F2_BASE_CLASS__BASE_CLASS_MASK 0xff000000 ++#define D2F2_BASE_CLASS__BASE_CLASS__SHIFT 0x18 ++#define D2F2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff ++#define D2F2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 ++#define D2F2_LATENCY__LATENCY_TIMER_MASK 0xff00 ++#define D2F2_LATENCY__LATENCY_TIMER__SHIFT 0x8 ++#define D2F2_HEADER__HEADER_TYPE_MASK 0x7f0000 ++#define D2F2_HEADER__HEADER_TYPE__SHIFT 0x10 ++#define D2F2_HEADER__DEVICE_TYPE_MASK 0x800000 ++#define D2F2_HEADER__DEVICE_TYPE__SHIFT 0x17 ++#define D2F2_BIST__BIST_COMP_MASK 0xf000000 ++#define D2F2_BIST__BIST_COMP__SHIFT 0x18 ++#define D2F2_BIST__BIST_STRT_MASK 0x40000000 ++#define D2F2_BIST__BIST_STRT__SHIFT 0x1e ++#define D2F2_BIST__BIST_CAP_MASK 0x80000000 ++#define D2F2_BIST__BIST_CAP__SHIFT 0x1f ++#define D2F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff ++#define D2F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 ++#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 ++#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 ++#define D2F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 ++#define D2F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 ++#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 ++#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 ++#define D2F2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf ++#define D2F2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 ++#define D2F2_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 ++#define D2F2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 ++#define D2F2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 ++#define D2F2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 ++#define D2F2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 ++#define D2F2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc ++#define D2F2_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 ++#define D2F2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 ++#define D2F2_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 ++#define D2F2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D2F2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D2F2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D2F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D2F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D2F2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D2F2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D2F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D2F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D2F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D2F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D2F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D2F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D2F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 ++#define D2F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e ++#define D2F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D2F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D2F2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf ++#define D2F2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 ++#define D2F2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 ++#define D2F2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 ++#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 ++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf ++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 ++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 ++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 ++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 ++#define D2F2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff ++#define D2F2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 ++#define D2F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff ++#define D2F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 ++#define D2F2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff ++#define D2F2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 ++#define D2F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 ++#define D2F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 ++#define D2F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 ++#define D2F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 ++#define D2F2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 ++#define D2F2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 ++#define D2F2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 ++#define D2F2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 ++#define D2F2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 ++#define D2F2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 ++#define D2F2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 ++#define D2F2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 ++#define D2F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 ++#define D2F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 ++#define D2F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 ++#define D2F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 ++#define D2F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 ++#define D2F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 ++#define D2F2_CAP_PTR__CAP_PTR_MASK 0xff ++#define D2F2_CAP_PTR__CAP_PTR__SHIFT 0x0 ++#define D2F2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff ++#define D2F2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 ++#define D2F2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 ++#define D2F2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 ++#define D2F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 ++#define D2F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 ++#define D2F2_PMI_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F2_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F2_PMI_CAP__VERSION_MASK 0x70000 ++#define D2F2_PMI_CAP__VERSION__SHIFT 0x10 ++#define D2F2_PMI_CAP__PME_CLOCK_MASK 0x80000 ++#define D2F2_PMI_CAP__PME_CLOCK__SHIFT 0x13 ++#define D2F2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 ++#define D2F2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 ++#define D2F2_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 ++#define D2F2_PMI_CAP__AUX_CURRENT__SHIFT 0x16 ++#define D2F2_PMI_CAP__D1_SUPPORT_MASK 0x2000000 ++#define D2F2_PMI_CAP__D1_SUPPORT__SHIFT 0x19 ++#define D2F2_PMI_CAP__D2_SUPPORT_MASK 0x4000000 ++#define D2F2_PMI_CAP__D2_SUPPORT__SHIFT 0x1a ++#define D2F2_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 ++#define D2F2_PMI_CAP__PME_SUPPORT__SHIFT 0x1b ++#define D2F2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 ++#define D2F2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 ++#define D2F2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 ++#define D2F2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 ++#define D2F2_PMI_STATUS_CNTL__PME_EN_MASK 0x100 ++#define D2F2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 ++#define D2F2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 ++#define D2F2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 ++#define D2F2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 ++#define D2F2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd ++#define D2F2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 ++#define D2F2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf ++#define D2F2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 ++#define D2F2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 ++#define D2F2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 ++#define D2F2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 ++#define D2F2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 ++#define D2F2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 ++#define D2F2_PCIE_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F2_PCIE_CAP__VERSION_MASK 0xf0000 ++#define D2F2_PCIE_CAP__VERSION__SHIFT 0x10 ++#define D2F2_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 ++#define D2F2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 ++#define D2F2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 ++#define D2F2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 ++#define D2F2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 ++#define D2F2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 ++#define D2F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 ++#define D2F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 ++#define D2F2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 ++#define D2F2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 ++#define D2F2_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 ++#define D2F2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 ++#define D2F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 ++#define D2F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 ++#define D2F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 ++#define D2F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 ++#define D2F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 ++#define D2F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf ++#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 ++#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 ++#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 ++#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a ++#define D2F2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 ++#define D2F2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c ++#define D2F2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 ++#define D2F2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 ++#define D2F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 ++#define D2F2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 ++#define D2F2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 ++#define D2F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 ++#define D2F2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 ++#define D2F2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 ++#define D2F2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 ++#define D2F2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 ++#define D2F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 ++#define D2F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 ++#define D2F2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 ++#define D2F2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 ++#define D2F2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 ++#define D2F2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 ++#define D2F2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 ++#define D2F2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa ++#define D2F2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 ++#define D2F2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb ++#define D2F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 ++#define D2F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc ++#define D2F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 ++#define D2F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf ++#define D2F2_DEVICE_STATUS__CORR_ERR_MASK 0x10000 ++#define D2F2_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 ++#define D2F2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 ++#define D2F2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 ++#define D2F2_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 ++#define D2F2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 ++#define D2F2_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 ++#define D2F2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 ++#define D2F2_DEVICE_STATUS__AUX_PWR_MASK 0x100000 ++#define D2F2_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 ++#define D2F2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 ++#define D2F2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 ++#define D2F2_LINK_CAP__LINK_SPEED_MASK 0xf ++#define D2F2_LINK_CAP__LINK_SPEED__SHIFT 0x0 ++#define D2F2_LINK_CAP__LINK_WIDTH_MASK 0x3f0 ++#define D2F2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 ++#define D2F2_LINK_CAP__PM_SUPPORT_MASK 0xc00 ++#define D2F2_LINK_CAP__PM_SUPPORT__SHIFT 0xa ++#define D2F2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 ++#define D2F2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc ++#define D2F2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 ++#define D2F2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf ++#define D2F2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 ++#define D2F2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 ++#define D2F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 ++#define D2F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 ++#define D2F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 ++#define D2F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 ++#define D2F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 ++#define D2F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 ++#define D2F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 ++#define D2F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 ++#define D2F2_LINK_CAP__PORT_NUMBER_MASK 0xff000000 ++#define D2F2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 ++#define D2F2_LINK_CNTL__PM_CONTROL_MASK 0x3 ++#define D2F2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 ++#define D2F2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 ++#define D2F2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 ++#define D2F2_LINK_CNTL__LINK_DIS_MASK 0x10 ++#define D2F2_LINK_CNTL__LINK_DIS__SHIFT 0x4 ++#define D2F2_LINK_CNTL__RETRAIN_LINK_MASK 0x20 ++#define D2F2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 ++#define D2F2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 ++#define D2F2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 ++#define D2F2_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 ++#define D2F2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 ++#define D2F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 ++#define D2F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 ++#define D2F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 ++#define D2F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 ++#define D2F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 ++#define D2F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa ++#define D2F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 ++#define D2F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb ++#define D2F2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 ++#define D2F2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 ++#define D2F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 ++#define D2F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 ++#define D2F2_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 ++#define D2F2_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b ++#define D2F2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 ++#define D2F2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c ++#define D2F2_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 ++#define D2F2_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d ++#define D2F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 ++#define D2F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e ++#define D2F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 ++#define D2F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f ++#define D2F2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 ++#define D2F2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 ++#define D2F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 ++#define D2F2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 ++#define D2F2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 ++#define D2F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 ++#define D2F2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 ++#define D2F2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 ++#define D2F2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 ++#define D2F2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 ++#define D2F2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 ++#define D2F2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 ++#define D2F2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 ++#define D2F2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 ++#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 ++#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 ++#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 ++#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf ++#define D2F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 ++#define D2F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 ++#define D2F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 ++#define D2F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 ++#define D2F2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 ++#define D2F2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 ++#define D2F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 ++#define D2F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 ++#define D2F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 ++#define D2F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 ++#define D2F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 ++#define D2F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 ++#define D2F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 ++#define D2F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 ++#define D2F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 ++#define D2F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 ++#define D2F2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 ++#define D2F2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 ++#define D2F2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 ++#define D2F2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 ++#define D2F2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 ++#define D2F2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 ++#define D2F2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 ++#define D2F2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa ++#define D2F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 ++#define D2F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb ++#define D2F2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 ++#define D2F2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc ++#define D2F2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 ++#define D2F2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 ++#define D2F2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 ++#define D2F2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 ++#define D2F2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 ++#define D2F2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 ++#define D2F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 ++#define D2F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 ++#define D2F2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 ++#define D2F2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 ++#define D2F2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 ++#define D2F2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 ++#define D2F2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 ++#define D2F2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 ++#define D2F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 ++#define D2F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 ++#define D2F2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 ++#define D2F2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 ++#define D2F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 ++#define D2F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 ++#define D2F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 ++#define D2F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 ++#define D2F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 ++#define D2F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 ++#define D2F2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 ++#define D2F2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 ++#define D2F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 ++#define D2F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 ++#define D2F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 ++#define D2F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 ++#define D2F2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff ++#define D2F2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 ++#define D2F2_ROOT_STATUS__PME_STATUS_MASK 0x10000 ++#define D2F2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 ++#define D2F2_ROOT_STATUS__PME_PENDING_MASK 0x20000 ++#define D2F2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 ++#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf ++#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 ++#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 ++#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 ++#define D2F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 ++#define D2F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 ++#define D2F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 ++#define D2F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 ++#define D2F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 ++#define D2F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 ++#define D2F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 ++#define D2F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 ++#define D2F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 ++#define D2F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 ++#define D2F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 ++#define D2F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa ++#define D2F2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 ++#define D2F2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb ++#define D2F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 ++#define D2F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc ++#define D2F2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 ++#define D2F2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 ++#define D2F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 ++#define D2F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 ++#define D2F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 ++#define D2F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 ++#define D2F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 ++#define D2F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 ++#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf ++#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 ++#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 ++#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 ++#define D2F2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 ++#define D2F2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 ++#define D2F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 ++#define D2F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 ++#define D2F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 ++#define D2F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 ++#define D2F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 ++#define D2F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 ++#define D2F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 ++#define D2F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 ++#define D2F2_DEVICE_CNTL2__LTR_EN_MASK 0x400 ++#define D2F2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa ++#define D2F2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 ++#define D2F2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd ++#define D2F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 ++#define D2F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf ++#define D2F2_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 ++#define D2F2_DEVICE_STATUS2__RESERVED__SHIFT 0x10 ++#define D2F2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe ++#define D2F2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 ++#define D2F2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 ++#define D2F2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 ++#define D2F2_LINK_CAP2__RESERVED_MASK 0xfffffe00 ++#define D2F2_LINK_CAP2__RESERVED__SHIFT 0x9 ++#define D2F2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf ++#define D2F2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 ++#define D2F2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 ++#define D2F2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 ++#define D2F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 ++#define D2F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 ++#define D2F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 ++#define D2F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 ++#define D2F2_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 ++#define D2F2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 ++#define D2F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 ++#define D2F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa ++#define D2F2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 ++#define D2F2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb ++#define D2F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 ++#define D2F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc ++#define D2F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 ++#define D2F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 ++#define D2F2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 ++#define D2F2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 ++#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 ++#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 ++#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 ++#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 ++#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 ++#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 ++#define D2F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 ++#define D2F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 ++#define D2F2_SLOT_CAP2__RESERVED_MASK 0xffffffff ++#define D2F2_SLOT_CAP2__RESERVED__SHIFT 0x0 ++#define D2F2_SLOT_CNTL2__RESERVED_MASK 0xffff ++#define D2F2_SLOT_CNTL2__RESERVED__SHIFT 0x0 ++#define D2F2_SLOT_STATUS2__RESERVED_MASK 0xffff0000 ++#define D2F2_SLOT_STATUS2__RESERVED__SHIFT 0x10 ++#define D2F2_MSI_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F2_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F2_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 ++#define D2F2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 ++#define D2F2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 ++#define D2F2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 ++#define D2F2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 ++#define D2F2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 ++#define D2F2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 ++#define D2F2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 ++#define D2F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 ++#define D2F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 ++#define D2F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc ++#define D2F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 ++#define D2F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff ++#define D2F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 ++#define D2F2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff ++#define D2F2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 ++#define D2F2_MSI_MSG_DATA__MSI_DATA_MASK 0xffff ++#define D2F2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 ++#define D2F2_SSID_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F2_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff ++#define D2F2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define D2F2_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 ++#define D2F2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 ++#define D2F2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F2_MSI_MAP_CAP__EN_MASK 0x10000 ++#define D2F2_MSI_MAP_CAP__EN__SHIFT 0x10 ++#define D2F2_MSI_MAP_CAP__FIXD_MASK 0x20000 ++#define D2F2_MSI_MAP_CAP__FIXD__SHIFT 0x11 ++#define D2F2_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 ++#define D2F2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b ++#define D2F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 ++#define D2F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 ++#define D2F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff ++#define D2F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 ++#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff ++#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 ++#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 ++#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 ++#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 ++#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 ++#define D2F2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff ++#define D2F2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 ++#define D2F2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff ++#define D2F2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 ++#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 ++#define D2F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 ++#define D2F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 ++#define D2F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 ++#define D2F2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 ++#define D2F2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 ++#define D2F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 ++#define D2F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa ++#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff ++#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 ++#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 ++#define D2F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 ++#define D2F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe ++#define D2F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 ++#define D2F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D2F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D2F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D2F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D2F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D2F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D2F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D2F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D2F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D2F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D2F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D2F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D2F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D2F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D2F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D2F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D2F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D2F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D2F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D2F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D2F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff ++#define D2F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 ++#define D2F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff ++#define D2F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 ++#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc ++#define D2F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd ++#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe ++#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf ++#define D2F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 ++#define D2F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 ++#define D2F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 ++#define D2F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 ++#define D2F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 ++#define D2F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 ++#define D2F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc ++#define D2F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd ++#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe ++#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf ++#define D2F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 ++#define D2F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 ++#define D2F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 ++#define D2F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 ++#define D2F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 ++#define D2F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 ++#define D2F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 ++#define D2F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 ++#define D2F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 ++#define D2F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 ++#define D2F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 ++#define D2F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 ++#define D2F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 ++#define D2F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 ++#define D2F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 ++#define D2F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 ++#define D2F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 ++#define D2F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 ++#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 ++#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 ++#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 ++#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc ++#define D2F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 ++#define D2F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd ++#define D2F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 ++#define D2F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe ++#define D2F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 ++#define D2F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf ++#define D2F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 ++#define D2F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 ++#define D2F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 ++#define D2F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 ++#define D2F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 ++#define D2F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 ++#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 ++#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 ++#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 ++#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc ++#define D2F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 ++#define D2F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd ++#define D2F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 ++#define D2F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe ++#define D2F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 ++#define D2F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 ++#define D2F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb ++#define D2F2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff ++#define D2F2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 ++#define D2F2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff ++#define D2F2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 ++#define D2F2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff ++#define D2F2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 ++#define D2F2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff ++#define D2F2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 ++#define D2F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 ++#define D2F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 ++#define D2F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 ++#define D2F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 ++#define D2F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 ++#define D2F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 ++#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 ++#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 ++#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 ++#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 ++#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 ++#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 ++#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 ++#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 ++#define D2F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 ++#define D2F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 ++#define D2F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 ++#define D2F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 ++#define D2F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 ++#define D2F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 ++#define D2F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 ++#define D2F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b ++#define D2F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff ++#define D2F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 ++#define D2F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 ++#define D2F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 ++#define D2F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff ++#define D2F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 ++#define D2F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff ++#define D2F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 ++#define D2F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff ++#define D2F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 ++#define D2F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff ++#define D2F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 ++#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 ++#define D2F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 ++#define D2F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 ++#define D2F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 ++#define D2F2_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc ++#define D2F2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 ++#define D2F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff ++#define D2F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 ++#define D2F2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 ++#define D2F2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 ++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 ++#define D2F2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 ++#define D2F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 ++#define D2F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 ++#define D2F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 ++#define D2F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 ++#define D2F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 ++#define D2F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 ++#define D2F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 ++#define D2F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 ++#define D2F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 ++#define D2F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 ++#define D2F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 ++#define D2F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 ++#define D2F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 ++#define D2F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 ++#define D2F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 ++#define D2F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 ++#define D2F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 ++#define D2F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 ++#define D2F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 ++#define D2F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 ++#define D2F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 ++#define D2F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 ++#define D2F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 ++#define D2F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 ++#define D2F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 ++#define D2F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 ++#define D2F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 ++#define D2F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 ++#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f ++#define D2F2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 ++#define D2F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 ++#define D2F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf ++#define D2F2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 ++#define D2F2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 ++#define D2F2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 ++#define D2F2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f ++#define D2F2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f ++#define D2F2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 ++#define D2F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 ++#define D2F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc ++#define D2F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff ++#define D2F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 ++#define D2F2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff ++#define D2F2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 ++#define D2F2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff ++#define D2F2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 ++#define D2F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff ++#define D2F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 ++#define D2F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff ++#define D2F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 ++#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff ++#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 ++#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff ++#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 ++#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f ++#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 ++#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 ++#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 ++#define D2F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff ++#define D2F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 ++#define D2F3_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff ++#define D2F3_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 ++#define D2F3_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff ++#define D2F3_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 ++#define D2F3_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff ++#define D2F3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 ++#define D2F3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff ++#define D2F3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 ++#define D2F3_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define D2F3_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define D2F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define D2F3_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define D2F3_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define D2F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define D2F3_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define D2F3_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define D2F3_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define D2F3_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define D2F3_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define D2F3_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define D2F3_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define D2F3_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define D2F3_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define D2F3_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define D2F3_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define D2F3_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define D2F3_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define D2F3_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define D2F3_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define D2F3_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define D2F3_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define D2F3_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define D2F3_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define D2F3_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define D2F3_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define D2F3_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define D2F3_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define D2F3_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define D2F3_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define D2F3_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define D2F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 ++#define D2F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 ++#define D2F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 ++#define D2F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 ++#define D2F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 ++#define D2F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 ++#define D2F3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 ++#define D2F3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 ++#define D2F3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 ++#define D2F3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 ++#define D2F3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 ++#define D2F3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 ++#define D2F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 ++#define D2F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 ++#define D2F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 ++#define D2F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 ++#define D2F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 ++#define D2F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define D2F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 ++#define D2F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 ++#define D2F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 ++#define D2F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa ++#define D2F3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 ++#define D2F3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc ++#define D2F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 ++#define D2F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe ++#define D2F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 ++#define D2F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf ++#define D2F3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 ++#define D2F3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 ++#define D2F3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 ++#define D2F3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 ++#define D2F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 ++#define D2F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 ++#define D2F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 ++#define D2F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 ++#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 ++#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 ++#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 ++#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 ++#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 ++#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 ++#define D2F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff ++#define D2F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 ++#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 ++#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 ++#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 ++#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e ++#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 ++#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f ++#define D2F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff ++#define D2F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 ++#define D2F3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 ++#define D2F3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 ++#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 ++#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 ++#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 ++#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf ++#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 ++#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 ++#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff ++#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 ++#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 ++#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc ++#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff ++#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 ++#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 ++#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 ++#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff ++#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 ++#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 ++#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 ++#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff ++#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 ++#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 ++#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 ++#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff ++#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 ++#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 ++#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 ++#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff ++#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 ++#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 ++#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 ++#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff ++#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 ++#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 ++#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 ++#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 ++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 ++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 ++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 ++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 ++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 ++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 ++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 ++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 ++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 ++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 ++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 ++#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 ++#define D2F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 ++#define D2F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 ++#define D2F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e ++#define D2F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 ++#define D2F3_PCIE_FC_P__PD_CREDITS_MASK 0xff ++#define D2F3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 ++#define D2F3_PCIE_FC_P__PH_CREDITS_MASK 0xff00 ++#define D2F3_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 ++#define D2F3_PCIE_FC_NP__NPD_CREDITS_MASK 0xff ++#define D2F3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 ++#define D2F3_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 ++#define D2F3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 ++#define D2F3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff ++#define D2F3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 ++#define D2F3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 ++#define D2F3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 ++#define D2F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 ++#define D2F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 ++#define D2F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 ++#define D2F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 ++#define D2F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 ++#define D2F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 ++#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 ++#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 ++#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 ++#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 ++#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 ++#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 ++#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 ++#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 ++#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 ++#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 ++#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 ++#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb ++#define D2F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 ++#define D2F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe ++#define D2F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 ++#define D2F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf ++#define D2F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 ++#define D2F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 ++#define D2F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 ++#define D2F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 ++#define D2F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 ++#define D2F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc ++#define D2F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 ++#define D2F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd ++#define D2F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 ++#define D2F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe ++#define D2F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 ++#define D2F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf ++#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 ++#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 ++#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 ++#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 ++#define D2F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 ++#define D2F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 ++#define D2F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 ++#define D2F3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 ++#define D2F3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a ++#define D2F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 ++#define D2F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b ++#define D2F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff ++#define D2F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 ++#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff ++#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 ++#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 ++#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 ++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 ++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 ++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 ++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 ++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 ++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 ++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 ++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 ++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 ++#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 ++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff ++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 ++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 ++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 ++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff ++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 ++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 ++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 ++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff ++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 ++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 ++#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 ++#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 ++#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 ++#define D2F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 ++#define D2F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 ++#define D2F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 ++#define D2F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 ++#define D2F3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 ++#define D2F3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 ++#define D2F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 ++#define D2F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 ++#define D2F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 ++#define D2F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 ++#define D2F3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 ++#define D2F3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc ++#define D2F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 ++#define D2F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 ++#define D2F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 ++#define D2F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 ++#define D2F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 ++#define D2F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 ++#define D2F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 ++#define D2F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 ++#define D2F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 ++#define D2F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 ++#define D2F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 ++#define D2F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 ++#define D2F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 ++#define D2F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 ++#define D2F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 ++#define D2F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 ++#define D2F3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 ++#define D2F3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 ++#define D2F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 ++#define D2F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b ++#define D2F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 ++#define D2F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c ++#define D2F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 ++#define D2F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d ++#define D2F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 ++#define D2F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e ++#define D2F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 ++#define D2F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f ++#define D2F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f ++#define D2F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 ++#define D2F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 ++#define D2F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 ++#define D2F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 ++#define D2F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 ++#define D2F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 ++#define D2F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 ++#define D2F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 ++#define D2F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 ++#define D2F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 ++#define D2F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa ++#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 ++#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb ++#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 ++#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc ++#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 ++#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd ++#define D2F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 ++#define D2F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe ++#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 ++#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 ++#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 ++#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 ++#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 ++#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 ++#define D2F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 ++#define D2F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 ++#define D2F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 ++#define D2F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 ++#define D2F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 ++#define D2F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 ++#define D2F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 ++#define D2F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 ++#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 ++#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 ++#define D2F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 ++#define D2F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 ++#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 ++#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a ++#define D2F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 ++#define D2F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b ++#define D2F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 ++#define D2F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c ++#define D2F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 ++#define D2F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d ++#define D2F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 ++#define D2F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f ++#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 ++#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 ++#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 ++#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 ++#define D2F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 ++#define D2F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 ++#define D2F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 ++#define D2F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 ++#define D2F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 ++#define D2F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 ++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 ++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 ++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 ++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 ++#define D2F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 ++#define D2F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 ++#define D2F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 ++#define D2F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa ++#define D2F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 ++#define D2F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb ++#define D2F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 ++#define D2F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc ++#define D2F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 ++#define D2F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe ++#define D2F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 ++#define D2F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 ++#define D2F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 ++#define D2F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 ++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 ++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 ++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 ++#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 ++#define D2F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 ++#define D2F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 ++#define D2F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 ++#define D2F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 ++#define D2F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 ++#define D2F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 ++#define D2F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 ++#define D2F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 ++#define D2F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 ++#define D2F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a ++#define D2F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 ++#define D2F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e ++#define D2F3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 ++#define D2F3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f ++#define D2F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 ++#define D2F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 ++#define D2F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 ++#define D2F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 ++#define D2F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 ++#define D2F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 ++#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 ++#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 ++#define D2F3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 ++#define D2F3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 ++#define D2F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 ++#define D2F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 ++#define D2F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 ++#define D2F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 ++#define D2F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 ++#define D2F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 ++#define D2F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 ++#define D2F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa ++#define D2F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 ++#define D2F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb ++#define D2F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 ++#define D2F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc ++#define D2F3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 ++#define D2F3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd ++#define D2F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 ++#define D2F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe ++#define D2F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 ++#define D2F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf ++#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 ++#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 ++#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 ++#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 ++#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 ++#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 ++#define D2F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 ++#define D2F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 ++#define D2F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 ++#define D2F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 ++#define D2F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 ++#define D2F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 ++#define D2F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 ++#define D2F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 ++#define D2F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 ++#define D2F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a ++#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f ++#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 ++#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 ++#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 ++#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 ++#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc ++#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 ++#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 ++#define D2F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 ++#define D2F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 ++#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 ++#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 ++#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 ++#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 ++#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 ++#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 ++#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 ++#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 ++#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d ++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff ++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 ++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 ++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 ++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 ++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 ++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 ++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 ++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 ++#define D2F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 ++#define D2F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f ++#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff ++#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 ++#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 ++#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc ++#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 ++#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 ++#define D2F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff ++#define D2F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 ++#define D2F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 ++#define D2F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 ++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 ++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 ++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e ++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 ++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 ++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 ++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 ++#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd ++#define D2F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 ++#define D2F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 ++#define D2F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 ++#define D2F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 ++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf ++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 ++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 ++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 ++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 ++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa ++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 ++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 ++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 ++#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 ++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 ++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 ++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e ++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 ++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 ++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 ++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 ++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd ++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 ++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 ++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 ++#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 ++#define D2F3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f ++#define D2F3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 ++#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 ++#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 ++#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 ++#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 ++#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 ++#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 ++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f ++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 ++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 ++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 ++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 ++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 ++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 ++#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 ++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f ++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 ++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 ++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 ++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 ++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 ++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 ++#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 ++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f ++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 ++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 ++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 ++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 ++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 ++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 ++#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 ++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f ++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 ++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 ++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 ++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 ++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 ++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 ++#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 ++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f ++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 ++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 ++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 ++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 ++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 ++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 ++#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 ++#define D2F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 ++#define D2F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 ++#define D2F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc ++#define D2F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 ++#define D2F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 ++#define D2F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 ++#define D2F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 ++#define D2F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 ++#define D2F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 ++#define D2F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 ++#define D2F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 ++#define D2F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb ++#define D2F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 ++#define D2F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc ++#define D2F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 ++#define D2F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd ++#define D2F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 ++#define D2F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe ++#define D2F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 ++#define D2F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf ++#define D2F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 ++#define D2F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 ++#define D2F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 ++#define D2F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 ++#define D2F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 ++#define D2F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 ++#define D2F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 ++#define D2F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 ++#define D2F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 ++#define D2F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 ++#define D2F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 ++#define D2F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 ++#define D2F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 ++#define D2F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 ++#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 ++#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 ++#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 ++#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 ++#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 ++#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 ++#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 ++#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 ++#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 ++#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 ++#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 ++#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 ++#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 ++#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 ++#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 ++#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 ++#define D2F3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 ++#define D2F3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 ++#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 ++#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 ++#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 ++#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 ++#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 ++#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa ++#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 ++#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb ++#define D2F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 ++#define D2F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf ++#define D2F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 ++#define D2F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 ++#define D2F3_VENDOR_ID__VENDOR_ID_MASK 0xffff ++#define D2F3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 ++#define D2F3_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 ++#define D2F3_DEVICE_ID__DEVICE_ID__SHIFT 0x10 ++#define D2F3_COMMAND__IO_ACCESS_EN_MASK 0x1 ++#define D2F3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 ++#define D2F3_COMMAND__MEM_ACCESS_EN_MASK 0x2 ++#define D2F3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 ++#define D2F3_COMMAND__BUS_MASTER_EN_MASK 0x4 ++#define D2F3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 ++#define D2F3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 ++#define D2F3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 ++#define D2F3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 ++#define D2F3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 ++#define D2F3_COMMAND__PAL_SNOOP_EN_MASK 0x20 ++#define D2F3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 ++#define D2F3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 ++#define D2F3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 ++#define D2F3_COMMAND__AD_STEPPING_MASK 0x80 ++#define D2F3_COMMAND__AD_STEPPING__SHIFT 0x7 ++#define D2F3_COMMAND__SERR_EN_MASK 0x100 ++#define D2F3_COMMAND__SERR_EN__SHIFT 0x8 ++#define D2F3_COMMAND__FAST_B2B_EN_MASK 0x200 ++#define D2F3_COMMAND__FAST_B2B_EN__SHIFT 0x9 ++#define D2F3_COMMAND__INT_DIS_MASK 0x400 ++#define D2F3_COMMAND__INT_DIS__SHIFT 0xa ++#define D2F3_STATUS__INT_STATUS_MASK 0x80000 ++#define D2F3_STATUS__INT_STATUS__SHIFT 0x13 ++#define D2F3_STATUS__CAP_LIST_MASK 0x100000 ++#define D2F3_STATUS__CAP_LIST__SHIFT 0x14 ++#define D2F3_STATUS__PCI_66_EN_MASK 0x200000 ++#define D2F3_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D2F3_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D2F3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D2F3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D2F3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D2F3_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D2F3_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D2F3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D2F3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D2F3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D2F3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D2F3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D2F3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D2F3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 ++#define D2F3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e ++#define D2F3_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D2F3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D2F3_REVISION_ID__MINOR_REV_ID_MASK 0xf ++#define D2F3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 ++#define D2F3_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 ++#define D2F3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 ++#define D2F3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 ++#define D2F3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 ++#define D2F3_SUB_CLASS__SUB_CLASS_MASK 0xff0000 ++#define D2F3_SUB_CLASS__SUB_CLASS__SHIFT 0x10 ++#define D2F3_BASE_CLASS__BASE_CLASS_MASK 0xff000000 ++#define D2F3_BASE_CLASS__BASE_CLASS__SHIFT 0x18 ++#define D2F3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff ++#define D2F3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 ++#define D2F3_LATENCY__LATENCY_TIMER_MASK 0xff00 ++#define D2F3_LATENCY__LATENCY_TIMER__SHIFT 0x8 ++#define D2F3_HEADER__HEADER_TYPE_MASK 0x7f0000 ++#define D2F3_HEADER__HEADER_TYPE__SHIFT 0x10 ++#define D2F3_HEADER__DEVICE_TYPE_MASK 0x800000 ++#define D2F3_HEADER__DEVICE_TYPE__SHIFT 0x17 ++#define D2F3_BIST__BIST_COMP_MASK 0xf000000 ++#define D2F3_BIST__BIST_COMP__SHIFT 0x18 ++#define D2F3_BIST__BIST_STRT_MASK 0x40000000 ++#define D2F3_BIST__BIST_STRT__SHIFT 0x1e ++#define D2F3_BIST__BIST_CAP_MASK 0x80000000 ++#define D2F3_BIST__BIST_CAP__SHIFT 0x1f ++#define D2F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff ++#define D2F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 ++#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 ++#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 ++#define D2F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 ++#define D2F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 ++#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 ++#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 ++#define D2F3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf ++#define D2F3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 ++#define D2F3_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 ++#define D2F3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 ++#define D2F3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 ++#define D2F3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 ++#define D2F3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 ++#define D2F3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc ++#define D2F3_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 ++#define D2F3_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 ++#define D2F3_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 ++#define D2F3_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D2F3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D2F3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D2F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D2F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D2F3_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D2F3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D2F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D2F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D2F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D2F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D2F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D2F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D2F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 ++#define D2F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e ++#define D2F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D2F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D2F3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf ++#define D2F3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 ++#define D2F3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 ++#define D2F3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 ++#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 ++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf ++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 ++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 ++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 ++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 ++#define D2F3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff ++#define D2F3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 ++#define D2F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff ++#define D2F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 ++#define D2F3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff ++#define D2F3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 ++#define D2F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 ++#define D2F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 ++#define D2F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 ++#define D2F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 ++#define D2F3_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 ++#define D2F3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 ++#define D2F3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 ++#define D2F3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 ++#define D2F3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 ++#define D2F3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 ++#define D2F3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 ++#define D2F3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 ++#define D2F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 ++#define D2F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 ++#define D2F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 ++#define D2F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 ++#define D2F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 ++#define D2F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 ++#define D2F3_CAP_PTR__CAP_PTR_MASK 0xff ++#define D2F3_CAP_PTR__CAP_PTR__SHIFT 0x0 ++#define D2F3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff ++#define D2F3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 ++#define D2F3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 ++#define D2F3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 ++#define D2F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 ++#define D2F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 ++#define D2F3_PMI_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F3_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F3_PMI_CAP__VERSION_MASK 0x70000 ++#define D2F3_PMI_CAP__VERSION__SHIFT 0x10 ++#define D2F3_PMI_CAP__PME_CLOCK_MASK 0x80000 ++#define D2F3_PMI_CAP__PME_CLOCK__SHIFT 0x13 ++#define D2F3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 ++#define D2F3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 ++#define D2F3_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 ++#define D2F3_PMI_CAP__AUX_CURRENT__SHIFT 0x16 ++#define D2F3_PMI_CAP__D1_SUPPORT_MASK 0x2000000 ++#define D2F3_PMI_CAP__D1_SUPPORT__SHIFT 0x19 ++#define D2F3_PMI_CAP__D2_SUPPORT_MASK 0x4000000 ++#define D2F3_PMI_CAP__D2_SUPPORT__SHIFT 0x1a ++#define D2F3_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 ++#define D2F3_PMI_CAP__PME_SUPPORT__SHIFT 0x1b ++#define D2F3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 ++#define D2F3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 ++#define D2F3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 ++#define D2F3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 ++#define D2F3_PMI_STATUS_CNTL__PME_EN_MASK 0x100 ++#define D2F3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 ++#define D2F3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 ++#define D2F3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 ++#define D2F3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 ++#define D2F3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd ++#define D2F3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 ++#define D2F3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf ++#define D2F3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 ++#define D2F3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 ++#define D2F3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 ++#define D2F3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 ++#define D2F3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 ++#define D2F3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 ++#define D2F3_PCIE_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F3_PCIE_CAP__VERSION_MASK 0xf0000 ++#define D2F3_PCIE_CAP__VERSION__SHIFT 0x10 ++#define D2F3_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 ++#define D2F3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 ++#define D2F3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 ++#define D2F3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 ++#define D2F3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 ++#define D2F3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 ++#define D2F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 ++#define D2F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 ++#define D2F3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 ++#define D2F3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 ++#define D2F3_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 ++#define D2F3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 ++#define D2F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 ++#define D2F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 ++#define D2F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 ++#define D2F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 ++#define D2F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 ++#define D2F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf ++#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 ++#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 ++#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 ++#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a ++#define D2F3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 ++#define D2F3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c ++#define D2F3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 ++#define D2F3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 ++#define D2F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 ++#define D2F3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 ++#define D2F3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 ++#define D2F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 ++#define D2F3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 ++#define D2F3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 ++#define D2F3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 ++#define D2F3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 ++#define D2F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 ++#define D2F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 ++#define D2F3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 ++#define D2F3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 ++#define D2F3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 ++#define D2F3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 ++#define D2F3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 ++#define D2F3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa ++#define D2F3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 ++#define D2F3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb ++#define D2F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 ++#define D2F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc ++#define D2F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 ++#define D2F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf ++#define D2F3_DEVICE_STATUS__CORR_ERR_MASK 0x10000 ++#define D2F3_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 ++#define D2F3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 ++#define D2F3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 ++#define D2F3_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 ++#define D2F3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 ++#define D2F3_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 ++#define D2F3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 ++#define D2F3_DEVICE_STATUS__AUX_PWR_MASK 0x100000 ++#define D2F3_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 ++#define D2F3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 ++#define D2F3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 ++#define D2F3_LINK_CAP__LINK_SPEED_MASK 0xf ++#define D2F3_LINK_CAP__LINK_SPEED__SHIFT 0x0 ++#define D2F3_LINK_CAP__LINK_WIDTH_MASK 0x3f0 ++#define D2F3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 ++#define D2F3_LINK_CAP__PM_SUPPORT_MASK 0xc00 ++#define D2F3_LINK_CAP__PM_SUPPORT__SHIFT 0xa ++#define D2F3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 ++#define D2F3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc ++#define D2F3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 ++#define D2F3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf ++#define D2F3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 ++#define D2F3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 ++#define D2F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 ++#define D2F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 ++#define D2F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 ++#define D2F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 ++#define D2F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 ++#define D2F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 ++#define D2F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 ++#define D2F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 ++#define D2F3_LINK_CAP__PORT_NUMBER_MASK 0xff000000 ++#define D2F3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 ++#define D2F3_LINK_CNTL__PM_CONTROL_MASK 0x3 ++#define D2F3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 ++#define D2F3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 ++#define D2F3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 ++#define D2F3_LINK_CNTL__LINK_DIS_MASK 0x10 ++#define D2F3_LINK_CNTL__LINK_DIS__SHIFT 0x4 ++#define D2F3_LINK_CNTL__RETRAIN_LINK_MASK 0x20 ++#define D2F3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 ++#define D2F3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 ++#define D2F3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 ++#define D2F3_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 ++#define D2F3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 ++#define D2F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 ++#define D2F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 ++#define D2F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 ++#define D2F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 ++#define D2F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 ++#define D2F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa ++#define D2F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 ++#define D2F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb ++#define D2F3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 ++#define D2F3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 ++#define D2F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 ++#define D2F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 ++#define D2F3_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 ++#define D2F3_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b ++#define D2F3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 ++#define D2F3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c ++#define D2F3_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 ++#define D2F3_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d ++#define D2F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 ++#define D2F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e ++#define D2F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 ++#define D2F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f ++#define D2F3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 ++#define D2F3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 ++#define D2F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 ++#define D2F3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 ++#define D2F3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 ++#define D2F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 ++#define D2F3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 ++#define D2F3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 ++#define D2F3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 ++#define D2F3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 ++#define D2F3_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 ++#define D2F3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 ++#define D2F3_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 ++#define D2F3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 ++#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 ++#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 ++#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 ++#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf ++#define D2F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 ++#define D2F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 ++#define D2F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 ++#define D2F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 ++#define D2F3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 ++#define D2F3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 ++#define D2F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 ++#define D2F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 ++#define D2F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 ++#define D2F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 ++#define D2F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 ++#define D2F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 ++#define D2F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 ++#define D2F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 ++#define D2F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 ++#define D2F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 ++#define D2F3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 ++#define D2F3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 ++#define D2F3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 ++#define D2F3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 ++#define D2F3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 ++#define D2F3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 ++#define D2F3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 ++#define D2F3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa ++#define D2F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 ++#define D2F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb ++#define D2F3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 ++#define D2F3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc ++#define D2F3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 ++#define D2F3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 ++#define D2F3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 ++#define D2F3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 ++#define D2F3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 ++#define D2F3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 ++#define D2F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 ++#define D2F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 ++#define D2F3_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 ++#define D2F3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 ++#define D2F3_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 ++#define D2F3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 ++#define D2F3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 ++#define D2F3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 ++#define D2F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 ++#define D2F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 ++#define D2F3_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 ++#define D2F3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 ++#define D2F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 ++#define D2F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 ++#define D2F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 ++#define D2F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 ++#define D2F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 ++#define D2F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 ++#define D2F3_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 ++#define D2F3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 ++#define D2F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 ++#define D2F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 ++#define D2F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 ++#define D2F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 ++#define D2F3_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff ++#define D2F3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 ++#define D2F3_ROOT_STATUS__PME_STATUS_MASK 0x10000 ++#define D2F3_ROOT_STATUS__PME_STATUS__SHIFT 0x10 ++#define D2F3_ROOT_STATUS__PME_PENDING_MASK 0x20000 ++#define D2F3_ROOT_STATUS__PME_PENDING__SHIFT 0x11 ++#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf ++#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 ++#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 ++#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 ++#define D2F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 ++#define D2F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 ++#define D2F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 ++#define D2F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 ++#define D2F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 ++#define D2F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 ++#define D2F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 ++#define D2F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 ++#define D2F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 ++#define D2F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 ++#define D2F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 ++#define D2F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa ++#define D2F3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 ++#define D2F3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb ++#define D2F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 ++#define D2F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc ++#define D2F3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 ++#define D2F3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 ++#define D2F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 ++#define D2F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 ++#define D2F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 ++#define D2F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 ++#define D2F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 ++#define D2F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 ++#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf ++#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 ++#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 ++#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 ++#define D2F3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 ++#define D2F3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 ++#define D2F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 ++#define D2F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 ++#define D2F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 ++#define D2F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 ++#define D2F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 ++#define D2F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 ++#define D2F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 ++#define D2F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 ++#define D2F3_DEVICE_CNTL2__LTR_EN_MASK 0x400 ++#define D2F3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa ++#define D2F3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 ++#define D2F3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd ++#define D2F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 ++#define D2F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf ++#define D2F3_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 ++#define D2F3_DEVICE_STATUS2__RESERVED__SHIFT 0x10 ++#define D2F3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe ++#define D2F3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 ++#define D2F3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 ++#define D2F3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 ++#define D2F3_LINK_CAP2__RESERVED_MASK 0xfffffe00 ++#define D2F3_LINK_CAP2__RESERVED__SHIFT 0x9 ++#define D2F3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf ++#define D2F3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 ++#define D2F3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 ++#define D2F3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 ++#define D2F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 ++#define D2F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 ++#define D2F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 ++#define D2F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 ++#define D2F3_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 ++#define D2F3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 ++#define D2F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 ++#define D2F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa ++#define D2F3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 ++#define D2F3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb ++#define D2F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 ++#define D2F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc ++#define D2F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 ++#define D2F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 ++#define D2F3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 ++#define D2F3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 ++#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 ++#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 ++#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 ++#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 ++#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 ++#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 ++#define D2F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 ++#define D2F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 ++#define D2F3_SLOT_CAP2__RESERVED_MASK 0xffffffff ++#define D2F3_SLOT_CAP2__RESERVED__SHIFT 0x0 ++#define D2F3_SLOT_CNTL2__RESERVED_MASK 0xffff ++#define D2F3_SLOT_CNTL2__RESERVED__SHIFT 0x0 ++#define D2F3_SLOT_STATUS2__RESERVED_MASK 0xffff0000 ++#define D2F3_SLOT_STATUS2__RESERVED__SHIFT 0x10 ++#define D2F3_MSI_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F3_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F3_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 ++#define D2F3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 ++#define D2F3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 ++#define D2F3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 ++#define D2F3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 ++#define D2F3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 ++#define D2F3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 ++#define D2F3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 ++#define D2F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 ++#define D2F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 ++#define D2F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc ++#define D2F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 ++#define D2F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff ++#define D2F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 ++#define D2F3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff ++#define D2F3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 ++#define D2F3_MSI_MSG_DATA__MSI_DATA_MASK 0xffff ++#define D2F3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 ++#define D2F3_SSID_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F3_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F3_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F3_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff ++#define D2F3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define D2F3_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 ++#define D2F3_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 ++#define D2F3_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F3_MSI_MAP_CAP__EN_MASK 0x10000 ++#define D2F3_MSI_MAP_CAP__EN__SHIFT 0x10 ++#define D2F3_MSI_MAP_CAP__FIXD_MASK 0x20000 ++#define D2F3_MSI_MAP_CAP__FIXD__SHIFT 0x11 ++#define D2F3_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 ++#define D2F3_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b ++#define D2F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 ++#define D2F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 ++#define D2F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff ++#define D2F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 ++#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff ++#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 ++#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 ++#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 ++#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 ++#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 ++#define D2F3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff ++#define D2F3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 ++#define D2F3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff ++#define D2F3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 ++#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 ++#define D2F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 ++#define D2F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 ++#define D2F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 ++#define D2F3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 ++#define D2F3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 ++#define D2F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 ++#define D2F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa ++#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff ++#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 ++#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 ++#define D2F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 ++#define D2F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe ++#define D2F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 ++#define D2F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D2F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D2F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D2F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D2F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D2F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D2F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D2F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D2F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D2F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D2F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D2F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D2F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D2F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D2F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D2F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D2F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D2F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D2F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D2F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D2F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff ++#define D2F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 ++#define D2F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff ++#define D2F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 ++#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc ++#define D2F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd ++#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe ++#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf ++#define D2F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 ++#define D2F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 ++#define D2F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 ++#define D2F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 ++#define D2F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 ++#define D2F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 ++#define D2F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc ++#define D2F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd ++#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe ++#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf ++#define D2F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 ++#define D2F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 ++#define D2F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 ++#define D2F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 ++#define D2F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 ++#define D2F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 ++#define D2F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 ++#define D2F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 ++#define D2F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 ++#define D2F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 ++#define D2F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 ++#define D2F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 ++#define D2F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 ++#define D2F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 ++#define D2F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 ++#define D2F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 ++#define D2F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 ++#define D2F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 ++#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 ++#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 ++#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 ++#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc ++#define D2F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 ++#define D2F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd ++#define D2F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 ++#define D2F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe ++#define D2F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 ++#define D2F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf ++#define D2F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 ++#define D2F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 ++#define D2F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 ++#define D2F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 ++#define D2F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 ++#define D2F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 ++#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 ++#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 ++#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 ++#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc ++#define D2F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 ++#define D2F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd ++#define D2F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 ++#define D2F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe ++#define D2F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 ++#define D2F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 ++#define D2F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb ++#define D2F3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff ++#define D2F3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 ++#define D2F3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff ++#define D2F3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 ++#define D2F3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff ++#define D2F3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 ++#define D2F3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff ++#define D2F3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 ++#define D2F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 ++#define D2F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 ++#define D2F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 ++#define D2F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 ++#define D2F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 ++#define D2F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 ++#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 ++#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 ++#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 ++#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 ++#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 ++#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 ++#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 ++#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 ++#define D2F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 ++#define D2F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 ++#define D2F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 ++#define D2F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 ++#define D2F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 ++#define D2F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 ++#define D2F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 ++#define D2F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b ++#define D2F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff ++#define D2F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 ++#define D2F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 ++#define D2F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 ++#define D2F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff ++#define D2F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 ++#define D2F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff ++#define D2F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 ++#define D2F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff ++#define D2F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 ++#define D2F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff ++#define D2F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 ++#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 ++#define D2F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 ++#define D2F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 ++#define D2F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 ++#define D2F3_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc ++#define D2F3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 ++#define D2F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff ++#define D2F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 ++#define D2F3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 ++#define D2F3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 ++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 ++#define D2F3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 ++#define D2F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 ++#define D2F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 ++#define D2F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 ++#define D2F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 ++#define D2F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 ++#define D2F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 ++#define D2F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 ++#define D2F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 ++#define D2F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 ++#define D2F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 ++#define D2F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 ++#define D2F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 ++#define D2F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 ++#define D2F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 ++#define D2F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 ++#define D2F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 ++#define D2F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 ++#define D2F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 ++#define D2F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 ++#define D2F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 ++#define D2F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 ++#define D2F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 ++#define D2F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 ++#define D2F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 ++#define D2F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 ++#define D2F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 ++#define D2F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 ++#define D2F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 ++#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f ++#define D2F3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 ++#define D2F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 ++#define D2F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf ++#define D2F3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 ++#define D2F3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 ++#define D2F3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 ++#define D2F3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f ++#define D2F3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f ++#define D2F3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 ++#define D2F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 ++#define D2F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc ++#define D2F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff ++#define D2F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 ++#define D2F3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff ++#define D2F3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 ++#define D2F3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff ++#define D2F3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 ++#define D2F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff ++#define D2F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 ++#define D2F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff ++#define D2F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 ++#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff ++#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 ++#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff ++#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 ++#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f ++#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 ++#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 ++#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 ++#define D2F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff ++#define D2F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 ++#define D2F4_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff ++#define D2F4_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 ++#define D2F4_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff ++#define D2F4_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 ++#define D2F4_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff ++#define D2F4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 ++#define D2F4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff ++#define D2F4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 ++#define D2F4_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define D2F4_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define D2F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define D2F4_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define D2F4_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define D2F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define D2F4_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define D2F4_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define D2F4_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define D2F4_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define D2F4_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define D2F4_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define D2F4_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define D2F4_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define D2F4_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define D2F4_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define D2F4_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define D2F4_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define D2F4_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define D2F4_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define D2F4_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define D2F4_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define D2F4_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define D2F4_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define D2F4_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define D2F4_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define D2F4_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define D2F4_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define D2F4_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define D2F4_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define D2F4_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define D2F4_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define D2F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 ++#define D2F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 ++#define D2F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 ++#define D2F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 ++#define D2F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 ++#define D2F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 ++#define D2F4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 ++#define D2F4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 ++#define D2F4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 ++#define D2F4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 ++#define D2F4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 ++#define D2F4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 ++#define D2F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 ++#define D2F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 ++#define D2F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 ++#define D2F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 ++#define D2F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 ++#define D2F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define D2F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 ++#define D2F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 ++#define D2F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 ++#define D2F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa ++#define D2F4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 ++#define D2F4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc ++#define D2F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 ++#define D2F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe ++#define D2F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 ++#define D2F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf ++#define D2F4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 ++#define D2F4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 ++#define D2F4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 ++#define D2F4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 ++#define D2F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 ++#define D2F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 ++#define D2F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 ++#define D2F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 ++#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 ++#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 ++#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 ++#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 ++#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 ++#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 ++#define D2F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff ++#define D2F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 ++#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 ++#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 ++#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 ++#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e ++#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 ++#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f ++#define D2F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff ++#define D2F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 ++#define D2F4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 ++#define D2F4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 ++#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 ++#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 ++#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 ++#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf ++#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 ++#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 ++#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff ++#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 ++#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 ++#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc ++#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff ++#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 ++#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 ++#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 ++#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff ++#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 ++#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 ++#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 ++#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff ++#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 ++#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 ++#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 ++#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff ++#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 ++#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 ++#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 ++#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff ++#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 ++#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 ++#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 ++#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff ++#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 ++#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 ++#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 ++#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 ++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 ++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 ++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 ++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 ++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 ++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 ++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 ++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 ++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 ++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 ++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 ++#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 ++#define D2F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 ++#define D2F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 ++#define D2F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e ++#define D2F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 ++#define D2F4_PCIE_FC_P__PD_CREDITS_MASK 0xff ++#define D2F4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 ++#define D2F4_PCIE_FC_P__PH_CREDITS_MASK 0xff00 ++#define D2F4_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 ++#define D2F4_PCIE_FC_NP__NPD_CREDITS_MASK 0xff ++#define D2F4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 ++#define D2F4_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 ++#define D2F4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 ++#define D2F4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff ++#define D2F4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 ++#define D2F4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 ++#define D2F4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 ++#define D2F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 ++#define D2F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 ++#define D2F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 ++#define D2F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 ++#define D2F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 ++#define D2F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 ++#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 ++#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 ++#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 ++#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 ++#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 ++#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 ++#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 ++#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 ++#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 ++#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 ++#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 ++#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb ++#define D2F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 ++#define D2F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe ++#define D2F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 ++#define D2F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf ++#define D2F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 ++#define D2F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 ++#define D2F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 ++#define D2F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 ++#define D2F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 ++#define D2F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc ++#define D2F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 ++#define D2F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd ++#define D2F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 ++#define D2F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe ++#define D2F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 ++#define D2F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf ++#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 ++#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 ++#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 ++#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 ++#define D2F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 ++#define D2F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 ++#define D2F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 ++#define D2F4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 ++#define D2F4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a ++#define D2F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 ++#define D2F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b ++#define D2F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff ++#define D2F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 ++#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff ++#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 ++#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 ++#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 ++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 ++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 ++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 ++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 ++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 ++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 ++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 ++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 ++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 ++#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 ++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff ++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 ++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 ++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 ++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff ++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 ++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 ++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 ++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff ++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 ++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 ++#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 ++#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 ++#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 ++#define D2F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 ++#define D2F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 ++#define D2F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 ++#define D2F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 ++#define D2F4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 ++#define D2F4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 ++#define D2F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 ++#define D2F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 ++#define D2F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 ++#define D2F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 ++#define D2F4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 ++#define D2F4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc ++#define D2F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 ++#define D2F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 ++#define D2F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 ++#define D2F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 ++#define D2F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 ++#define D2F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 ++#define D2F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 ++#define D2F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 ++#define D2F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 ++#define D2F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 ++#define D2F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 ++#define D2F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 ++#define D2F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 ++#define D2F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 ++#define D2F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 ++#define D2F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 ++#define D2F4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 ++#define D2F4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 ++#define D2F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 ++#define D2F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b ++#define D2F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 ++#define D2F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c ++#define D2F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 ++#define D2F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d ++#define D2F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 ++#define D2F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e ++#define D2F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 ++#define D2F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f ++#define D2F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f ++#define D2F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 ++#define D2F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 ++#define D2F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 ++#define D2F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 ++#define D2F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 ++#define D2F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 ++#define D2F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 ++#define D2F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 ++#define D2F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 ++#define D2F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 ++#define D2F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa ++#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 ++#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb ++#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 ++#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc ++#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 ++#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd ++#define D2F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 ++#define D2F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe ++#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 ++#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 ++#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 ++#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 ++#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 ++#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 ++#define D2F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 ++#define D2F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 ++#define D2F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 ++#define D2F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 ++#define D2F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 ++#define D2F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 ++#define D2F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 ++#define D2F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 ++#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 ++#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 ++#define D2F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 ++#define D2F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 ++#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 ++#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a ++#define D2F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 ++#define D2F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b ++#define D2F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 ++#define D2F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c ++#define D2F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 ++#define D2F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d ++#define D2F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 ++#define D2F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f ++#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 ++#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 ++#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 ++#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 ++#define D2F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 ++#define D2F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 ++#define D2F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 ++#define D2F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 ++#define D2F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 ++#define D2F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 ++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 ++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 ++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 ++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 ++#define D2F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 ++#define D2F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 ++#define D2F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 ++#define D2F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa ++#define D2F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 ++#define D2F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb ++#define D2F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 ++#define D2F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc ++#define D2F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 ++#define D2F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe ++#define D2F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 ++#define D2F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 ++#define D2F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 ++#define D2F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 ++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 ++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 ++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 ++#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 ++#define D2F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 ++#define D2F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 ++#define D2F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 ++#define D2F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 ++#define D2F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 ++#define D2F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 ++#define D2F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 ++#define D2F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 ++#define D2F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 ++#define D2F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a ++#define D2F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 ++#define D2F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e ++#define D2F4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 ++#define D2F4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f ++#define D2F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 ++#define D2F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 ++#define D2F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 ++#define D2F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 ++#define D2F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 ++#define D2F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 ++#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 ++#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 ++#define D2F4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 ++#define D2F4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 ++#define D2F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 ++#define D2F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 ++#define D2F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 ++#define D2F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 ++#define D2F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 ++#define D2F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 ++#define D2F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 ++#define D2F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa ++#define D2F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 ++#define D2F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb ++#define D2F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 ++#define D2F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc ++#define D2F4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 ++#define D2F4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd ++#define D2F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 ++#define D2F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe ++#define D2F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 ++#define D2F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf ++#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 ++#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 ++#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 ++#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 ++#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 ++#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 ++#define D2F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 ++#define D2F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 ++#define D2F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 ++#define D2F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 ++#define D2F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 ++#define D2F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 ++#define D2F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 ++#define D2F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 ++#define D2F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 ++#define D2F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a ++#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f ++#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 ++#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 ++#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 ++#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 ++#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc ++#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 ++#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 ++#define D2F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 ++#define D2F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 ++#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 ++#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 ++#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 ++#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 ++#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 ++#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 ++#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 ++#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 ++#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d ++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff ++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 ++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 ++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 ++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 ++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 ++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 ++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 ++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 ++#define D2F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 ++#define D2F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f ++#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff ++#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 ++#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 ++#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc ++#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 ++#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 ++#define D2F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff ++#define D2F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 ++#define D2F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 ++#define D2F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 ++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 ++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 ++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e ++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 ++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 ++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 ++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 ++#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd ++#define D2F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 ++#define D2F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 ++#define D2F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 ++#define D2F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 ++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf ++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 ++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 ++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 ++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 ++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa ++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 ++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 ++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 ++#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 ++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 ++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 ++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e ++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 ++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 ++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 ++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 ++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd ++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 ++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 ++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 ++#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 ++#define D2F4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f ++#define D2F4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 ++#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 ++#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 ++#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 ++#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 ++#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 ++#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 ++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f ++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 ++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 ++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 ++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 ++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 ++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 ++#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 ++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f ++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 ++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 ++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 ++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 ++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 ++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 ++#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 ++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f ++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 ++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 ++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 ++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 ++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 ++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 ++#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 ++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f ++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 ++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 ++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 ++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 ++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 ++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 ++#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 ++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f ++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 ++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 ++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 ++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 ++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 ++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 ++#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 ++#define D2F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 ++#define D2F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 ++#define D2F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc ++#define D2F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 ++#define D2F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 ++#define D2F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 ++#define D2F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 ++#define D2F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 ++#define D2F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 ++#define D2F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 ++#define D2F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 ++#define D2F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb ++#define D2F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 ++#define D2F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc ++#define D2F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 ++#define D2F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd ++#define D2F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 ++#define D2F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe ++#define D2F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 ++#define D2F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf ++#define D2F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 ++#define D2F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 ++#define D2F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 ++#define D2F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 ++#define D2F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 ++#define D2F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 ++#define D2F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 ++#define D2F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 ++#define D2F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 ++#define D2F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 ++#define D2F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 ++#define D2F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 ++#define D2F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 ++#define D2F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 ++#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 ++#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 ++#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 ++#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 ++#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 ++#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 ++#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 ++#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 ++#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 ++#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 ++#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 ++#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 ++#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 ++#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 ++#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 ++#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 ++#define D2F4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 ++#define D2F4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 ++#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 ++#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 ++#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 ++#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 ++#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 ++#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa ++#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 ++#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb ++#define D2F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 ++#define D2F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf ++#define D2F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 ++#define D2F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 ++#define D2F4_VENDOR_ID__VENDOR_ID_MASK 0xffff ++#define D2F4_VENDOR_ID__VENDOR_ID__SHIFT 0x0 ++#define D2F4_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 ++#define D2F4_DEVICE_ID__DEVICE_ID__SHIFT 0x10 ++#define D2F4_COMMAND__IO_ACCESS_EN_MASK 0x1 ++#define D2F4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 ++#define D2F4_COMMAND__MEM_ACCESS_EN_MASK 0x2 ++#define D2F4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 ++#define D2F4_COMMAND__BUS_MASTER_EN_MASK 0x4 ++#define D2F4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 ++#define D2F4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 ++#define D2F4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 ++#define D2F4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 ++#define D2F4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 ++#define D2F4_COMMAND__PAL_SNOOP_EN_MASK 0x20 ++#define D2F4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 ++#define D2F4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 ++#define D2F4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 ++#define D2F4_COMMAND__AD_STEPPING_MASK 0x80 ++#define D2F4_COMMAND__AD_STEPPING__SHIFT 0x7 ++#define D2F4_COMMAND__SERR_EN_MASK 0x100 ++#define D2F4_COMMAND__SERR_EN__SHIFT 0x8 ++#define D2F4_COMMAND__FAST_B2B_EN_MASK 0x200 ++#define D2F4_COMMAND__FAST_B2B_EN__SHIFT 0x9 ++#define D2F4_COMMAND__INT_DIS_MASK 0x400 ++#define D2F4_COMMAND__INT_DIS__SHIFT 0xa ++#define D2F4_STATUS__INT_STATUS_MASK 0x80000 ++#define D2F4_STATUS__INT_STATUS__SHIFT 0x13 ++#define D2F4_STATUS__CAP_LIST_MASK 0x100000 ++#define D2F4_STATUS__CAP_LIST__SHIFT 0x14 ++#define D2F4_STATUS__PCI_66_EN_MASK 0x200000 ++#define D2F4_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D2F4_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D2F4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D2F4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D2F4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D2F4_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D2F4_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D2F4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D2F4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D2F4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D2F4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D2F4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D2F4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D2F4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 ++#define D2F4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e ++#define D2F4_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D2F4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D2F4_REVISION_ID__MINOR_REV_ID_MASK 0xf ++#define D2F4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 ++#define D2F4_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 ++#define D2F4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 ++#define D2F4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 ++#define D2F4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 ++#define D2F4_SUB_CLASS__SUB_CLASS_MASK 0xff0000 ++#define D2F4_SUB_CLASS__SUB_CLASS__SHIFT 0x10 ++#define D2F4_BASE_CLASS__BASE_CLASS_MASK 0xff000000 ++#define D2F4_BASE_CLASS__BASE_CLASS__SHIFT 0x18 ++#define D2F4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff ++#define D2F4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 ++#define D2F4_LATENCY__LATENCY_TIMER_MASK 0xff00 ++#define D2F4_LATENCY__LATENCY_TIMER__SHIFT 0x8 ++#define D2F4_HEADER__HEADER_TYPE_MASK 0x7f0000 ++#define D2F4_HEADER__HEADER_TYPE__SHIFT 0x10 ++#define D2F4_HEADER__DEVICE_TYPE_MASK 0x800000 ++#define D2F4_HEADER__DEVICE_TYPE__SHIFT 0x17 ++#define D2F4_BIST__BIST_COMP_MASK 0xf000000 ++#define D2F4_BIST__BIST_COMP__SHIFT 0x18 ++#define D2F4_BIST__BIST_STRT_MASK 0x40000000 ++#define D2F4_BIST__BIST_STRT__SHIFT 0x1e ++#define D2F4_BIST__BIST_CAP_MASK 0x80000000 ++#define D2F4_BIST__BIST_CAP__SHIFT 0x1f ++#define D2F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff ++#define D2F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 ++#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 ++#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 ++#define D2F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 ++#define D2F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 ++#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 ++#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 ++#define D2F4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf ++#define D2F4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 ++#define D2F4_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 ++#define D2F4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 ++#define D2F4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 ++#define D2F4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 ++#define D2F4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 ++#define D2F4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc ++#define D2F4_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 ++#define D2F4_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 ++#define D2F4_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 ++#define D2F4_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D2F4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D2F4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D2F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D2F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D2F4_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D2F4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D2F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D2F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D2F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D2F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D2F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D2F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D2F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 ++#define D2F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e ++#define D2F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D2F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D2F4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf ++#define D2F4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 ++#define D2F4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 ++#define D2F4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 ++#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 ++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf ++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 ++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 ++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 ++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 ++#define D2F4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff ++#define D2F4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 ++#define D2F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff ++#define D2F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 ++#define D2F4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff ++#define D2F4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 ++#define D2F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 ++#define D2F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 ++#define D2F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 ++#define D2F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 ++#define D2F4_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 ++#define D2F4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 ++#define D2F4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 ++#define D2F4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 ++#define D2F4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 ++#define D2F4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 ++#define D2F4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 ++#define D2F4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 ++#define D2F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 ++#define D2F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 ++#define D2F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 ++#define D2F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 ++#define D2F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 ++#define D2F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 ++#define D2F4_CAP_PTR__CAP_PTR_MASK 0xff ++#define D2F4_CAP_PTR__CAP_PTR__SHIFT 0x0 ++#define D2F4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff ++#define D2F4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 ++#define D2F4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 ++#define D2F4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 ++#define D2F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 ++#define D2F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 ++#define D2F4_PMI_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F4_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F4_PMI_CAP__VERSION_MASK 0x70000 ++#define D2F4_PMI_CAP__VERSION__SHIFT 0x10 ++#define D2F4_PMI_CAP__PME_CLOCK_MASK 0x80000 ++#define D2F4_PMI_CAP__PME_CLOCK__SHIFT 0x13 ++#define D2F4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 ++#define D2F4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 ++#define D2F4_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 ++#define D2F4_PMI_CAP__AUX_CURRENT__SHIFT 0x16 ++#define D2F4_PMI_CAP__D1_SUPPORT_MASK 0x2000000 ++#define D2F4_PMI_CAP__D1_SUPPORT__SHIFT 0x19 ++#define D2F4_PMI_CAP__D2_SUPPORT_MASK 0x4000000 ++#define D2F4_PMI_CAP__D2_SUPPORT__SHIFT 0x1a ++#define D2F4_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 ++#define D2F4_PMI_CAP__PME_SUPPORT__SHIFT 0x1b ++#define D2F4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 ++#define D2F4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 ++#define D2F4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 ++#define D2F4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 ++#define D2F4_PMI_STATUS_CNTL__PME_EN_MASK 0x100 ++#define D2F4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 ++#define D2F4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 ++#define D2F4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 ++#define D2F4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 ++#define D2F4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd ++#define D2F4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 ++#define D2F4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf ++#define D2F4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 ++#define D2F4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 ++#define D2F4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 ++#define D2F4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 ++#define D2F4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 ++#define D2F4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 ++#define D2F4_PCIE_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F4_PCIE_CAP__VERSION_MASK 0xf0000 ++#define D2F4_PCIE_CAP__VERSION__SHIFT 0x10 ++#define D2F4_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 ++#define D2F4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 ++#define D2F4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 ++#define D2F4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 ++#define D2F4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 ++#define D2F4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 ++#define D2F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 ++#define D2F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 ++#define D2F4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 ++#define D2F4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 ++#define D2F4_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 ++#define D2F4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 ++#define D2F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 ++#define D2F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 ++#define D2F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 ++#define D2F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 ++#define D2F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 ++#define D2F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf ++#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 ++#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 ++#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 ++#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a ++#define D2F4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 ++#define D2F4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c ++#define D2F4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 ++#define D2F4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 ++#define D2F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 ++#define D2F4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 ++#define D2F4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 ++#define D2F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 ++#define D2F4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 ++#define D2F4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 ++#define D2F4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 ++#define D2F4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 ++#define D2F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 ++#define D2F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 ++#define D2F4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 ++#define D2F4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 ++#define D2F4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 ++#define D2F4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 ++#define D2F4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 ++#define D2F4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa ++#define D2F4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 ++#define D2F4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb ++#define D2F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 ++#define D2F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc ++#define D2F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 ++#define D2F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf ++#define D2F4_DEVICE_STATUS__CORR_ERR_MASK 0x10000 ++#define D2F4_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 ++#define D2F4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 ++#define D2F4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 ++#define D2F4_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 ++#define D2F4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 ++#define D2F4_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 ++#define D2F4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 ++#define D2F4_DEVICE_STATUS__AUX_PWR_MASK 0x100000 ++#define D2F4_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 ++#define D2F4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 ++#define D2F4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 ++#define D2F4_LINK_CAP__LINK_SPEED_MASK 0xf ++#define D2F4_LINK_CAP__LINK_SPEED__SHIFT 0x0 ++#define D2F4_LINK_CAP__LINK_WIDTH_MASK 0x3f0 ++#define D2F4_LINK_CAP__LINK_WIDTH__SHIFT 0x4 ++#define D2F4_LINK_CAP__PM_SUPPORT_MASK 0xc00 ++#define D2F4_LINK_CAP__PM_SUPPORT__SHIFT 0xa ++#define D2F4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 ++#define D2F4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc ++#define D2F4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 ++#define D2F4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf ++#define D2F4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 ++#define D2F4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 ++#define D2F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 ++#define D2F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 ++#define D2F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 ++#define D2F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 ++#define D2F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 ++#define D2F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 ++#define D2F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 ++#define D2F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 ++#define D2F4_LINK_CAP__PORT_NUMBER_MASK 0xff000000 ++#define D2F4_LINK_CAP__PORT_NUMBER__SHIFT 0x18 ++#define D2F4_LINK_CNTL__PM_CONTROL_MASK 0x3 ++#define D2F4_LINK_CNTL__PM_CONTROL__SHIFT 0x0 ++#define D2F4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 ++#define D2F4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 ++#define D2F4_LINK_CNTL__LINK_DIS_MASK 0x10 ++#define D2F4_LINK_CNTL__LINK_DIS__SHIFT 0x4 ++#define D2F4_LINK_CNTL__RETRAIN_LINK_MASK 0x20 ++#define D2F4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 ++#define D2F4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 ++#define D2F4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 ++#define D2F4_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 ++#define D2F4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 ++#define D2F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 ++#define D2F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 ++#define D2F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 ++#define D2F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 ++#define D2F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 ++#define D2F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa ++#define D2F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 ++#define D2F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb ++#define D2F4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 ++#define D2F4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 ++#define D2F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 ++#define D2F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 ++#define D2F4_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 ++#define D2F4_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b ++#define D2F4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 ++#define D2F4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c ++#define D2F4_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 ++#define D2F4_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d ++#define D2F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 ++#define D2F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e ++#define D2F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 ++#define D2F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f ++#define D2F4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 ++#define D2F4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 ++#define D2F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 ++#define D2F4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 ++#define D2F4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 ++#define D2F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 ++#define D2F4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 ++#define D2F4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 ++#define D2F4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 ++#define D2F4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 ++#define D2F4_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 ++#define D2F4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 ++#define D2F4_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 ++#define D2F4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 ++#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 ++#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 ++#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 ++#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf ++#define D2F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 ++#define D2F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 ++#define D2F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 ++#define D2F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 ++#define D2F4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 ++#define D2F4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 ++#define D2F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 ++#define D2F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 ++#define D2F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 ++#define D2F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 ++#define D2F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 ++#define D2F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 ++#define D2F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 ++#define D2F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 ++#define D2F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 ++#define D2F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 ++#define D2F4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 ++#define D2F4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 ++#define D2F4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 ++#define D2F4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 ++#define D2F4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 ++#define D2F4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 ++#define D2F4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 ++#define D2F4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa ++#define D2F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 ++#define D2F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb ++#define D2F4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 ++#define D2F4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc ++#define D2F4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 ++#define D2F4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 ++#define D2F4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 ++#define D2F4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 ++#define D2F4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 ++#define D2F4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 ++#define D2F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 ++#define D2F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 ++#define D2F4_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 ++#define D2F4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 ++#define D2F4_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 ++#define D2F4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 ++#define D2F4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 ++#define D2F4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 ++#define D2F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 ++#define D2F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 ++#define D2F4_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 ++#define D2F4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 ++#define D2F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 ++#define D2F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 ++#define D2F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 ++#define D2F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 ++#define D2F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 ++#define D2F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 ++#define D2F4_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 ++#define D2F4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 ++#define D2F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 ++#define D2F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 ++#define D2F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 ++#define D2F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 ++#define D2F4_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff ++#define D2F4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 ++#define D2F4_ROOT_STATUS__PME_STATUS_MASK 0x10000 ++#define D2F4_ROOT_STATUS__PME_STATUS__SHIFT 0x10 ++#define D2F4_ROOT_STATUS__PME_PENDING_MASK 0x20000 ++#define D2F4_ROOT_STATUS__PME_PENDING__SHIFT 0x11 ++#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf ++#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 ++#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 ++#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 ++#define D2F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 ++#define D2F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 ++#define D2F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 ++#define D2F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 ++#define D2F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 ++#define D2F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 ++#define D2F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 ++#define D2F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 ++#define D2F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 ++#define D2F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 ++#define D2F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 ++#define D2F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa ++#define D2F4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 ++#define D2F4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb ++#define D2F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 ++#define D2F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc ++#define D2F4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 ++#define D2F4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 ++#define D2F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 ++#define D2F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 ++#define D2F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 ++#define D2F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 ++#define D2F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 ++#define D2F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 ++#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf ++#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 ++#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 ++#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 ++#define D2F4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 ++#define D2F4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 ++#define D2F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 ++#define D2F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 ++#define D2F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 ++#define D2F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 ++#define D2F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 ++#define D2F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 ++#define D2F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 ++#define D2F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 ++#define D2F4_DEVICE_CNTL2__LTR_EN_MASK 0x400 ++#define D2F4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa ++#define D2F4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 ++#define D2F4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd ++#define D2F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 ++#define D2F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf ++#define D2F4_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 ++#define D2F4_DEVICE_STATUS2__RESERVED__SHIFT 0x10 ++#define D2F4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe ++#define D2F4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 ++#define D2F4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 ++#define D2F4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 ++#define D2F4_LINK_CAP2__RESERVED_MASK 0xfffffe00 ++#define D2F4_LINK_CAP2__RESERVED__SHIFT 0x9 ++#define D2F4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf ++#define D2F4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 ++#define D2F4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 ++#define D2F4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 ++#define D2F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 ++#define D2F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 ++#define D2F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 ++#define D2F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 ++#define D2F4_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 ++#define D2F4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 ++#define D2F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 ++#define D2F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa ++#define D2F4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 ++#define D2F4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb ++#define D2F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 ++#define D2F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc ++#define D2F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 ++#define D2F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 ++#define D2F4_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 ++#define D2F4_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 ++#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 ++#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 ++#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 ++#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 ++#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 ++#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 ++#define D2F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 ++#define D2F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 ++#define D2F4_SLOT_CAP2__RESERVED_MASK 0xffffffff ++#define D2F4_SLOT_CAP2__RESERVED__SHIFT 0x0 ++#define D2F4_SLOT_CNTL2__RESERVED_MASK 0xffff ++#define D2F4_SLOT_CNTL2__RESERVED__SHIFT 0x0 ++#define D2F4_SLOT_STATUS2__RESERVED_MASK 0xffff0000 ++#define D2F4_SLOT_STATUS2__RESERVED__SHIFT 0x10 ++#define D2F4_MSI_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F4_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F4_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 ++#define D2F4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 ++#define D2F4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 ++#define D2F4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 ++#define D2F4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 ++#define D2F4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 ++#define D2F4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 ++#define D2F4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 ++#define D2F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 ++#define D2F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 ++#define D2F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc ++#define D2F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 ++#define D2F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff ++#define D2F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 ++#define D2F4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff ++#define D2F4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 ++#define D2F4_MSI_MSG_DATA__MSI_DATA_MASK 0xffff ++#define D2F4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 ++#define D2F4_SSID_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F4_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F4_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F4_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff ++#define D2F4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define D2F4_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 ++#define D2F4_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 ++#define D2F4_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F4_MSI_MAP_CAP__EN_MASK 0x10000 ++#define D2F4_MSI_MAP_CAP__EN__SHIFT 0x10 ++#define D2F4_MSI_MAP_CAP__FIXD_MASK 0x20000 ++#define D2F4_MSI_MAP_CAP__FIXD__SHIFT 0x11 ++#define D2F4_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 ++#define D2F4_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b ++#define D2F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 ++#define D2F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 ++#define D2F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff ++#define D2F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 ++#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff ++#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 ++#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 ++#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 ++#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 ++#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 ++#define D2F4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff ++#define D2F4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 ++#define D2F4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff ++#define D2F4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 ++#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 ++#define D2F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 ++#define D2F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 ++#define D2F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 ++#define D2F4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 ++#define D2F4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 ++#define D2F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 ++#define D2F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa ++#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff ++#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 ++#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 ++#define D2F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 ++#define D2F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe ++#define D2F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 ++#define D2F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D2F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D2F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D2F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D2F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D2F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D2F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D2F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D2F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D2F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D2F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D2F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D2F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D2F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D2F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D2F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D2F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D2F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D2F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D2F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D2F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff ++#define D2F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 ++#define D2F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff ++#define D2F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 ++#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc ++#define D2F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd ++#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe ++#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf ++#define D2F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 ++#define D2F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 ++#define D2F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 ++#define D2F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 ++#define D2F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 ++#define D2F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 ++#define D2F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc ++#define D2F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd ++#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe ++#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf ++#define D2F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 ++#define D2F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 ++#define D2F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 ++#define D2F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 ++#define D2F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 ++#define D2F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 ++#define D2F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 ++#define D2F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 ++#define D2F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 ++#define D2F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 ++#define D2F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 ++#define D2F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 ++#define D2F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 ++#define D2F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 ++#define D2F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 ++#define D2F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 ++#define D2F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 ++#define D2F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 ++#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 ++#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 ++#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 ++#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc ++#define D2F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 ++#define D2F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd ++#define D2F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 ++#define D2F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe ++#define D2F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 ++#define D2F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf ++#define D2F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 ++#define D2F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 ++#define D2F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 ++#define D2F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 ++#define D2F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 ++#define D2F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 ++#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 ++#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 ++#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 ++#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc ++#define D2F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 ++#define D2F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd ++#define D2F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 ++#define D2F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe ++#define D2F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 ++#define D2F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 ++#define D2F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb ++#define D2F4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff ++#define D2F4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 ++#define D2F4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff ++#define D2F4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 ++#define D2F4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff ++#define D2F4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 ++#define D2F4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff ++#define D2F4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 ++#define D2F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 ++#define D2F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 ++#define D2F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 ++#define D2F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 ++#define D2F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 ++#define D2F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 ++#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 ++#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 ++#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 ++#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 ++#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 ++#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 ++#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 ++#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 ++#define D2F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 ++#define D2F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 ++#define D2F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 ++#define D2F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 ++#define D2F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 ++#define D2F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 ++#define D2F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 ++#define D2F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b ++#define D2F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff ++#define D2F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 ++#define D2F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 ++#define D2F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 ++#define D2F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff ++#define D2F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 ++#define D2F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff ++#define D2F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 ++#define D2F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff ++#define D2F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 ++#define D2F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff ++#define D2F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 ++#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 ++#define D2F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 ++#define D2F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 ++#define D2F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 ++#define D2F4_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc ++#define D2F4_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 ++#define D2F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff ++#define D2F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 ++#define D2F4_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 ++#define D2F4_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 ++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 ++#define D2F4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 ++#define D2F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 ++#define D2F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 ++#define D2F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 ++#define D2F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 ++#define D2F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 ++#define D2F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 ++#define D2F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 ++#define D2F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 ++#define D2F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 ++#define D2F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 ++#define D2F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 ++#define D2F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 ++#define D2F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 ++#define D2F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 ++#define D2F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 ++#define D2F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 ++#define D2F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 ++#define D2F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 ++#define D2F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 ++#define D2F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 ++#define D2F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 ++#define D2F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 ++#define D2F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 ++#define D2F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 ++#define D2F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 ++#define D2F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 ++#define D2F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 ++#define D2F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 ++#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F4_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f ++#define D2F4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 ++#define D2F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 ++#define D2F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf ++#define D2F4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 ++#define D2F4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 ++#define D2F4_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 ++#define D2F4_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f ++#define D2F4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f ++#define D2F4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 ++#define D2F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 ++#define D2F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc ++#define D2F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff ++#define D2F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 ++#define D2F4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff ++#define D2F4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 ++#define D2F4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff ++#define D2F4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 ++#define D2F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff ++#define D2F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 ++#define D2F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff ++#define D2F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 ++#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff ++#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 ++#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff ++#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 ++#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f ++#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 ++#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 ++#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 ++#define D2F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff ++#define D2F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 ++#define D2F5_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff ++#define D2F5_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 ++#define D2F5_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff ++#define D2F5_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 ++#define D2F5_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff ++#define D2F5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 ++#define D2F5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff ++#define D2F5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 ++#define D2F5_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define D2F5_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define D2F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define D2F5_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define D2F5_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define D2F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define D2F5_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define D2F5_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define D2F5_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define D2F5_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define D2F5_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define D2F5_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define D2F5_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define D2F5_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define D2F5_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define D2F5_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define D2F5_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define D2F5_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define D2F5_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define D2F5_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define D2F5_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define D2F5_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define D2F5_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define D2F5_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define D2F5_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define D2F5_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define D2F5_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define D2F5_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define D2F5_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define D2F5_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define D2F5_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define D2F5_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define D2F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 ++#define D2F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 ++#define D2F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 ++#define D2F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 ++#define D2F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 ++#define D2F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 ++#define D2F5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 ++#define D2F5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 ++#define D2F5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 ++#define D2F5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 ++#define D2F5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 ++#define D2F5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 ++#define D2F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 ++#define D2F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 ++#define D2F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 ++#define D2F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 ++#define D2F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 ++#define D2F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define D2F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 ++#define D2F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 ++#define D2F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 ++#define D2F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa ++#define D2F5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 ++#define D2F5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc ++#define D2F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 ++#define D2F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe ++#define D2F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 ++#define D2F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf ++#define D2F5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 ++#define D2F5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 ++#define D2F5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 ++#define D2F5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 ++#define D2F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 ++#define D2F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 ++#define D2F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 ++#define D2F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 ++#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 ++#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 ++#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 ++#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 ++#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 ++#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 ++#define D2F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff ++#define D2F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 ++#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 ++#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 ++#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 ++#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e ++#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 ++#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f ++#define D2F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff ++#define D2F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 ++#define D2F5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 ++#define D2F5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 ++#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 ++#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 ++#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 ++#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf ++#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 ++#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 ++#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff ++#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 ++#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 ++#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc ++#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff ++#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 ++#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 ++#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 ++#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff ++#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 ++#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 ++#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 ++#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff ++#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 ++#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 ++#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 ++#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff ++#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 ++#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 ++#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 ++#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff ++#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 ++#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 ++#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 ++#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff ++#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 ++#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 ++#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 ++#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 ++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 ++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 ++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 ++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 ++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 ++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 ++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 ++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 ++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 ++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 ++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 ++#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 ++#define D2F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 ++#define D2F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 ++#define D2F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e ++#define D2F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 ++#define D2F5_PCIE_FC_P__PD_CREDITS_MASK 0xff ++#define D2F5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 ++#define D2F5_PCIE_FC_P__PH_CREDITS_MASK 0xff00 ++#define D2F5_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 ++#define D2F5_PCIE_FC_NP__NPD_CREDITS_MASK 0xff ++#define D2F5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 ++#define D2F5_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 ++#define D2F5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 ++#define D2F5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff ++#define D2F5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 ++#define D2F5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 ++#define D2F5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 ++#define D2F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 ++#define D2F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 ++#define D2F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 ++#define D2F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 ++#define D2F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 ++#define D2F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 ++#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 ++#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 ++#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 ++#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 ++#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 ++#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 ++#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 ++#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 ++#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 ++#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 ++#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 ++#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb ++#define D2F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 ++#define D2F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe ++#define D2F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 ++#define D2F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf ++#define D2F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 ++#define D2F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 ++#define D2F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 ++#define D2F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 ++#define D2F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 ++#define D2F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc ++#define D2F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 ++#define D2F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd ++#define D2F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 ++#define D2F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe ++#define D2F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 ++#define D2F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf ++#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 ++#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 ++#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 ++#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 ++#define D2F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 ++#define D2F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 ++#define D2F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 ++#define D2F5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 ++#define D2F5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a ++#define D2F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 ++#define D2F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b ++#define D2F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff ++#define D2F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 ++#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff ++#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 ++#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 ++#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 ++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 ++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 ++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 ++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 ++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 ++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 ++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 ++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 ++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 ++#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 ++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff ++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 ++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 ++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 ++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff ++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 ++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 ++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 ++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff ++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 ++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 ++#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 ++#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 ++#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 ++#define D2F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 ++#define D2F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 ++#define D2F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 ++#define D2F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 ++#define D2F5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 ++#define D2F5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 ++#define D2F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 ++#define D2F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 ++#define D2F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 ++#define D2F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 ++#define D2F5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 ++#define D2F5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc ++#define D2F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 ++#define D2F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 ++#define D2F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 ++#define D2F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 ++#define D2F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 ++#define D2F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 ++#define D2F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 ++#define D2F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 ++#define D2F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 ++#define D2F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 ++#define D2F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 ++#define D2F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 ++#define D2F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 ++#define D2F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 ++#define D2F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 ++#define D2F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 ++#define D2F5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 ++#define D2F5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 ++#define D2F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 ++#define D2F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b ++#define D2F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 ++#define D2F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c ++#define D2F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 ++#define D2F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d ++#define D2F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 ++#define D2F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e ++#define D2F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 ++#define D2F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f ++#define D2F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f ++#define D2F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 ++#define D2F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 ++#define D2F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 ++#define D2F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 ++#define D2F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 ++#define D2F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 ++#define D2F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 ++#define D2F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 ++#define D2F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 ++#define D2F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 ++#define D2F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa ++#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 ++#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb ++#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 ++#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc ++#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 ++#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd ++#define D2F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 ++#define D2F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe ++#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 ++#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 ++#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 ++#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 ++#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 ++#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 ++#define D2F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 ++#define D2F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 ++#define D2F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 ++#define D2F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 ++#define D2F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 ++#define D2F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 ++#define D2F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 ++#define D2F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 ++#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 ++#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 ++#define D2F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 ++#define D2F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 ++#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 ++#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a ++#define D2F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 ++#define D2F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b ++#define D2F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 ++#define D2F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c ++#define D2F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 ++#define D2F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d ++#define D2F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 ++#define D2F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f ++#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 ++#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 ++#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 ++#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 ++#define D2F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 ++#define D2F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 ++#define D2F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 ++#define D2F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 ++#define D2F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 ++#define D2F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 ++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 ++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 ++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 ++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 ++#define D2F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 ++#define D2F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 ++#define D2F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 ++#define D2F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa ++#define D2F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 ++#define D2F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb ++#define D2F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 ++#define D2F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc ++#define D2F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 ++#define D2F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe ++#define D2F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 ++#define D2F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 ++#define D2F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 ++#define D2F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 ++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 ++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 ++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 ++#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 ++#define D2F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 ++#define D2F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 ++#define D2F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 ++#define D2F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 ++#define D2F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 ++#define D2F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 ++#define D2F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 ++#define D2F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 ++#define D2F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 ++#define D2F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a ++#define D2F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 ++#define D2F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e ++#define D2F5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 ++#define D2F5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f ++#define D2F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 ++#define D2F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 ++#define D2F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 ++#define D2F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 ++#define D2F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 ++#define D2F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 ++#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 ++#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 ++#define D2F5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 ++#define D2F5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 ++#define D2F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 ++#define D2F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 ++#define D2F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 ++#define D2F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 ++#define D2F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 ++#define D2F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 ++#define D2F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 ++#define D2F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa ++#define D2F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 ++#define D2F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb ++#define D2F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 ++#define D2F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc ++#define D2F5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 ++#define D2F5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd ++#define D2F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 ++#define D2F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe ++#define D2F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 ++#define D2F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf ++#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 ++#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 ++#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 ++#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 ++#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 ++#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 ++#define D2F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 ++#define D2F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 ++#define D2F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 ++#define D2F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 ++#define D2F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 ++#define D2F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 ++#define D2F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 ++#define D2F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 ++#define D2F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 ++#define D2F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a ++#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f ++#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 ++#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 ++#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 ++#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 ++#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc ++#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 ++#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 ++#define D2F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 ++#define D2F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 ++#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 ++#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 ++#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 ++#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 ++#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 ++#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 ++#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 ++#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 ++#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d ++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff ++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 ++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 ++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 ++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 ++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 ++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 ++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 ++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 ++#define D2F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 ++#define D2F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f ++#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff ++#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 ++#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 ++#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc ++#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 ++#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 ++#define D2F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff ++#define D2F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 ++#define D2F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 ++#define D2F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 ++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 ++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 ++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e ++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 ++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 ++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 ++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 ++#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd ++#define D2F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 ++#define D2F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 ++#define D2F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 ++#define D2F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 ++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf ++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 ++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 ++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 ++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 ++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa ++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 ++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 ++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 ++#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 ++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 ++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 ++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e ++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 ++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 ++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 ++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 ++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd ++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 ++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 ++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 ++#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 ++#define D2F5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f ++#define D2F5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 ++#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 ++#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 ++#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 ++#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 ++#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 ++#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 ++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f ++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 ++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 ++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 ++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 ++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 ++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 ++#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 ++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f ++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 ++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 ++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 ++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 ++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 ++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 ++#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 ++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f ++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 ++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 ++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 ++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 ++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 ++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 ++#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 ++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f ++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 ++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 ++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 ++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 ++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 ++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 ++#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 ++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f ++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 ++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 ++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 ++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 ++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 ++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 ++#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 ++#define D2F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 ++#define D2F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 ++#define D2F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc ++#define D2F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 ++#define D2F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 ++#define D2F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 ++#define D2F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 ++#define D2F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 ++#define D2F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 ++#define D2F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 ++#define D2F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 ++#define D2F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb ++#define D2F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 ++#define D2F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc ++#define D2F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 ++#define D2F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd ++#define D2F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 ++#define D2F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe ++#define D2F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 ++#define D2F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf ++#define D2F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 ++#define D2F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 ++#define D2F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 ++#define D2F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 ++#define D2F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 ++#define D2F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 ++#define D2F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 ++#define D2F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 ++#define D2F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 ++#define D2F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 ++#define D2F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 ++#define D2F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 ++#define D2F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 ++#define D2F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 ++#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 ++#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 ++#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 ++#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 ++#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 ++#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 ++#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 ++#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 ++#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 ++#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 ++#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 ++#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 ++#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 ++#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 ++#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 ++#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 ++#define D2F5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 ++#define D2F5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 ++#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 ++#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 ++#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 ++#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 ++#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 ++#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa ++#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 ++#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb ++#define D2F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 ++#define D2F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf ++#define D2F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 ++#define D2F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 ++#define D2F5_VENDOR_ID__VENDOR_ID_MASK 0xffff ++#define D2F5_VENDOR_ID__VENDOR_ID__SHIFT 0x0 ++#define D2F5_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 ++#define D2F5_DEVICE_ID__DEVICE_ID__SHIFT 0x10 ++#define D2F5_COMMAND__IO_ACCESS_EN_MASK 0x1 ++#define D2F5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 ++#define D2F5_COMMAND__MEM_ACCESS_EN_MASK 0x2 ++#define D2F5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 ++#define D2F5_COMMAND__BUS_MASTER_EN_MASK 0x4 ++#define D2F5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 ++#define D2F5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 ++#define D2F5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 ++#define D2F5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 ++#define D2F5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 ++#define D2F5_COMMAND__PAL_SNOOP_EN_MASK 0x20 ++#define D2F5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 ++#define D2F5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 ++#define D2F5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 ++#define D2F5_COMMAND__AD_STEPPING_MASK 0x80 ++#define D2F5_COMMAND__AD_STEPPING__SHIFT 0x7 ++#define D2F5_COMMAND__SERR_EN_MASK 0x100 ++#define D2F5_COMMAND__SERR_EN__SHIFT 0x8 ++#define D2F5_COMMAND__FAST_B2B_EN_MASK 0x200 ++#define D2F5_COMMAND__FAST_B2B_EN__SHIFT 0x9 ++#define D2F5_COMMAND__INT_DIS_MASK 0x400 ++#define D2F5_COMMAND__INT_DIS__SHIFT 0xa ++#define D2F5_STATUS__INT_STATUS_MASK 0x80000 ++#define D2F5_STATUS__INT_STATUS__SHIFT 0x13 ++#define D2F5_STATUS__CAP_LIST_MASK 0x100000 ++#define D2F5_STATUS__CAP_LIST__SHIFT 0x14 ++#define D2F5_STATUS__PCI_66_EN_MASK 0x200000 ++#define D2F5_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D2F5_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D2F5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D2F5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D2F5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D2F5_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D2F5_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D2F5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D2F5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D2F5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D2F5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D2F5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D2F5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D2F5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 ++#define D2F5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e ++#define D2F5_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D2F5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D2F5_REVISION_ID__MINOR_REV_ID_MASK 0xf ++#define D2F5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 ++#define D2F5_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 ++#define D2F5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 ++#define D2F5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 ++#define D2F5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 ++#define D2F5_SUB_CLASS__SUB_CLASS_MASK 0xff0000 ++#define D2F5_SUB_CLASS__SUB_CLASS__SHIFT 0x10 ++#define D2F5_BASE_CLASS__BASE_CLASS_MASK 0xff000000 ++#define D2F5_BASE_CLASS__BASE_CLASS__SHIFT 0x18 ++#define D2F5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff ++#define D2F5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 ++#define D2F5_LATENCY__LATENCY_TIMER_MASK 0xff00 ++#define D2F5_LATENCY__LATENCY_TIMER__SHIFT 0x8 ++#define D2F5_HEADER__HEADER_TYPE_MASK 0x7f0000 ++#define D2F5_HEADER__HEADER_TYPE__SHIFT 0x10 ++#define D2F5_HEADER__DEVICE_TYPE_MASK 0x800000 ++#define D2F5_HEADER__DEVICE_TYPE__SHIFT 0x17 ++#define D2F5_BIST__BIST_COMP_MASK 0xf000000 ++#define D2F5_BIST__BIST_COMP__SHIFT 0x18 ++#define D2F5_BIST__BIST_STRT_MASK 0x40000000 ++#define D2F5_BIST__BIST_STRT__SHIFT 0x1e ++#define D2F5_BIST__BIST_CAP_MASK 0x80000000 ++#define D2F5_BIST__BIST_CAP__SHIFT 0x1f ++#define D2F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff ++#define D2F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 ++#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 ++#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 ++#define D2F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 ++#define D2F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 ++#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 ++#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 ++#define D2F5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf ++#define D2F5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 ++#define D2F5_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 ++#define D2F5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 ++#define D2F5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 ++#define D2F5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 ++#define D2F5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 ++#define D2F5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc ++#define D2F5_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 ++#define D2F5_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 ++#define D2F5_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 ++#define D2F5_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D2F5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D2F5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D2F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D2F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D2F5_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D2F5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D2F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D2F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D2F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D2F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D2F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D2F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D2F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 ++#define D2F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e ++#define D2F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D2F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D2F5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf ++#define D2F5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 ++#define D2F5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 ++#define D2F5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 ++#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 ++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf ++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 ++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 ++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 ++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 ++#define D2F5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff ++#define D2F5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 ++#define D2F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff ++#define D2F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 ++#define D2F5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff ++#define D2F5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 ++#define D2F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 ++#define D2F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 ++#define D2F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 ++#define D2F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 ++#define D2F5_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 ++#define D2F5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 ++#define D2F5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 ++#define D2F5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 ++#define D2F5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 ++#define D2F5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 ++#define D2F5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 ++#define D2F5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 ++#define D2F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 ++#define D2F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 ++#define D2F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 ++#define D2F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 ++#define D2F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 ++#define D2F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 ++#define D2F5_CAP_PTR__CAP_PTR_MASK 0xff ++#define D2F5_CAP_PTR__CAP_PTR__SHIFT 0x0 ++#define D2F5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff ++#define D2F5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 ++#define D2F5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 ++#define D2F5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 ++#define D2F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 ++#define D2F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 ++#define D2F5_PMI_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F5_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F5_PMI_CAP__VERSION_MASK 0x70000 ++#define D2F5_PMI_CAP__VERSION__SHIFT 0x10 ++#define D2F5_PMI_CAP__PME_CLOCK_MASK 0x80000 ++#define D2F5_PMI_CAP__PME_CLOCK__SHIFT 0x13 ++#define D2F5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 ++#define D2F5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 ++#define D2F5_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 ++#define D2F5_PMI_CAP__AUX_CURRENT__SHIFT 0x16 ++#define D2F5_PMI_CAP__D1_SUPPORT_MASK 0x2000000 ++#define D2F5_PMI_CAP__D1_SUPPORT__SHIFT 0x19 ++#define D2F5_PMI_CAP__D2_SUPPORT_MASK 0x4000000 ++#define D2F5_PMI_CAP__D2_SUPPORT__SHIFT 0x1a ++#define D2F5_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 ++#define D2F5_PMI_CAP__PME_SUPPORT__SHIFT 0x1b ++#define D2F5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 ++#define D2F5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 ++#define D2F5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 ++#define D2F5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 ++#define D2F5_PMI_STATUS_CNTL__PME_EN_MASK 0x100 ++#define D2F5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 ++#define D2F5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 ++#define D2F5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 ++#define D2F5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 ++#define D2F5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd ++#define D2F5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 ++#define D2F5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf ++#define D2F5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 ++#define D2F5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 ++#define D2F5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 ++#define D2F5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 ++#define D2F5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 ++#define D2F5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 ++#define D2F5_PCIE_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F5_PCIE_CAP__VERSION_MASK 0xf0000 ++#define D2F5_PCIE_CAP__VERSION__SHIFT 0x10 ++#define D2F5_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 ++#define D2F5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 ++#define D2F5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 ++#define D2F5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 ++#define D2F5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 ++#define D2F5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 ++#define D2F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 ++#define D2F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 ++#define D2F5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 ++#define D2F5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 ++#define D2F5_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 ++#define D2F5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 ++#define D2F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 ++#define D2F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 ++#define D2F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 ++#define D2F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 ++#define D2F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 ++#define D2F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf ++#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 ++#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 ++#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 ++#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a ++#define D2F5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 ++#define D2F5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c ++#define D2F5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 ++#define D2F5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 ++#define D2F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 ++#define D2F5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 ++#define D2F5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 ++#define D2F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 ++#define D2F5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 ++#define D2F5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 ++#define D2F5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 ++#define D2F5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 ++#define D2F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 ++#define D2F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 ++#define D2F5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 ++#define D2F5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 ++#define D2F5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 ++#define D2F5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 ++#define D2F5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 ++#define D2F5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa ++#define D2F5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 ++#define D2F5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb ++#define D2F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 ++#define D2F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc ++#define D2F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 ++#define D2F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf ++#define D2F5_DEVICE_STATUS__CORR_ERR_MASK 0x10000 ++#define D2F5_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 ++#define D2F5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 ++#define D2F5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 ++#define D2F5_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 ++#define D2F5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 ++#define D2F5_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 ++#define D2F5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 ++#define D2F5_DEVICE_STATUS__AUX_PWR_MASK 0x100000 ++#define D2F5_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 ++#define D2F5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 ++#define D2F5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 ++#define D2F5_LINK_CAP__LINK_SPEED_MASK 0xf ++#define D2F5_LINK_CAP__LINK_SPEED__SHIFT 0x0 ++#define D2F5_LINK_CAP__LINK_WIDTH_MASK 0x3f0 ++#define D2F5_LINK_CAP__LINK_WIDTH__SHIFT 0x4 ++#define D2F5_LINK_CAP__PM_SUPPORT_MASK 0xc00 ++#define D2F5_LINK_CAP__PM_SUPPORT__SHIFT 0xa ++#define D2F5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 ++#define D2F5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc ++#define D2F5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 ++#define D2F5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf ++#define D2F5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 ++#define D2F5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 ++#define D2F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 ++#define D2F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 ++#define D2F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 ++#define D2F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 ++#define D2F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 ++#define D2F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 ++#define D2F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 ++#define D2F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 ++#define D2F5_LINK_CAP__PORT_NUMBER_MASK 0xff000000 ++#define D2F5_LINK_CAP__PORT_NUMBER__SHIFT 0x18 ++#define D2F5_LINK_CNTL__PM_CONTROL_MASK 0x3 ++#define D2F5_LINK_CNTL__PM_CONTROL__SHIFT 0x0 ++#define D2F5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 ++#define D2F5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 ++#define D2F5_LINK_CNTL__LINK_DIS_MASK 0x10 ++#define D2F5_LINK_CNTL__LINK_DIS__SHIFT 0x4 ++#define D2F5_LINK_CNTL__RETRAIN_LINK_MASK 0x20 ++#define D2F5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 ++#define D2F5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 ++#define D2F5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 ++#define D2F5_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 ++#define D2F5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 ++#define D2F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 ++#define D2F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 ++#define D2F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 ++#define D2F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 ++#define D2F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 ++#define D2F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa ++#define D2F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 ++#define D2F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb ++#define D2F5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 ++#define D2F5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 ++#define D2F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 ++#define D2F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 ++#define D2F5_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 ++#define D2F5_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b ++#define D2F5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 ++#define D2F5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c ++#define D2F5_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 ++#define D2F5_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d ++#define D2F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 ++#define D2F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e ++#define D2F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 ++#define D2F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f ++#define D2F5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 ++#define D2F5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 ++#define D2F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 ++#define D2F5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 ++#define D2F5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 ++#define D2F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 ++#define D2F5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 ++#define D2F5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 ++#define D2F5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 ++#define D2F5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 ++#define D2F5_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 ++#define D2F5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 ++#define D2F5_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 ++#define D2F5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 ++#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 ++#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 ++#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 ++#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf ++#define D2F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 ++#define D2F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 ++#define D2F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 ++#define D2F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 ++#define D2F5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 ++#define D2F5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 ++#define D2F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 ++#define D2F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 ++#define D2F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 ++#define D2F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 ++#define D2F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 ++#define D2F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 ++#define D2F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 ++#define D2F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 ++#define D2F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 ++#define D2F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 ++#define D2F5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 ++#define D2F5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 ++#define D2F5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 ++#define D2F5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 ++#define D2F5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 ++#define D2F5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 ++#define D2F5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 ++#define D2F5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa ++#define D2F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 ++#define D2F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb ++#define D2F5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 ++#define D2F5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc ++#define D2F5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 ++#define D2F5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 ++#define D2F5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 ++#define D2F5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 ++#define D2F5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 ++#define D2F5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 ++#define D2F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 ++#define D2F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 ++#define D2F5_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 ++#define D2F5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 ++#define D2F5_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 ++#define D2F5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 ++#define D2F5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 ++#define D2F5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 ++#define D2F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 ++#define D2F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 ++#define D2F5_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 ++#define D2F5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 ++#define D2F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 ++#define D2F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 ++#define D2F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 ++#define D2F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 ++#define D2F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 ++#define D2F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 ++#define D2F5_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 ++#define D2F5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 ++#define D2F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 ++#define D2F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 ++#define D2F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 ++#define D2F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 ++#define D2F5_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff ++#define D2F5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 ++#define D2F5_ROOT_STATUS__PME_STATUS_MASK 0x10000 ++#define D2F5_ROOT_STATUS__PME_STATUS__SHIFT 0x10 ++#define D2F5_ROOT_STATUS__PME_PENDING_MASK 0x20000 ++#define D2F5_ROOT_STATUS__PME_PENDING__SHIFT 0x11 ++#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf ++#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 ++#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 ++#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 ++#define D2F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 ++#define D2F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 ++#define D2F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 ++#define D2F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 ++#define D2F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 ++#define D2F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 ++#define D2F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 ++#define D2F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 ++#define D2F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 ++#define D2F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 ++#define D2F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 ++#define D2F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa ++#define D2F5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 ++#define D2F5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb ++#define D2F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 ++#define D2F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc ++#define D2F5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 ++#define D2F5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 ++#define D2F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 ++#define D2F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 ++#define D2F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 ++#define D2F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 ++#define D2F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 ++#define D2F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 ++#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf ++#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 ++#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 ++#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 ++#define D2F5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 ++#define D2F5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 ++#define D2F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 ++#define D2F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 ++#define D2F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 ++#define D2F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 ++#define D2F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 ++#define D2F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 ++#define D2F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 ++#define D2F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 ++#define D2F5_DEVICE_CNTL2__LTR_EN_MASK 0x400 ++#define D2F5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa ++#define D2F5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 ++#define D2F5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd ++#define D2F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 ++#define D2F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf ++#define D2F5_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 ++#define D2F5_DEVICE_STATUS2__RESERVED__SHIFT 0x10 ++#define D2F5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe ++#define D2F5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 ++#define D2F5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 ++#define D2F5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 ++#define D2F5_LINK_CAP2__RESERVED_MASK 0xfffffe00 ++#define D2F5_LINK_CAP2__RESERVED__SHIFT 0x9 ++#define D2F5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf ++#define D2F5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 ++#define D2F5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 ++#define D2F5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 ++#define D2F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 ++#define D2F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 ++#define D2F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 ++#define D2F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 ++#define D2F5_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 ++#define D2F5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 ++#define D2F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 ++#define D2F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa ++#define D2F5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 ++#define D2F5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb ++#define D2F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 ++#define D2F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc ++#define D2F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 ++#define D2F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 ++#define D2F5_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 ++#define D2F5_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 ++#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 ++#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 ++#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 ++#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 ++#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 ++#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 ++#define D2F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 ++#define D2F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 ++#define D2F5_SLOT_CAP2__RESERVED_MASK 0xffffffff ++#define D2F5_SLOT_CAP2__RESERVED__SHIFT 0x0 ++#define D2F5_SLOT_CNTL2__RESERVED_MASK 0xffff ++#define D2F5_SLOT_CNTL2__RESERVED__SHIFT 0x0 ++#define D2F5_SLOT_STATUS2__RESERVED_MASK 0xffff0000 ++#define D2F5_SLOT_STATUS2__RESERVED__SHIFT 0x10 ++#define D2F5_MSI_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F5_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F5_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 ++#define D2F5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 ++#define D2F5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 ++#define D2F5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 ++#define D2F5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 ++#define D2F5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 ++#define D2F5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 ++#define D2F5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 ++#define D2F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 ++#define D2F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 ++#define D2F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc ++#define D2F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 ++#define D2F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff ++#define D2F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 ++#define D2F5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff ++#define D2F5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 ++#define D2F5_MSI_MSG_DATA__MSI_DATA_MASK 0xffff ++#define D2F5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 ++#define D2F5_SSID_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F5_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F5_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F5_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff ++#define D2F5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define D2F5_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 ++#define D2F5_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 ++#define D2F5_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff ++#define D2F5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D2F5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D2F5_MSI_MAP_CAP__EN_MASK 0x10000 ++#define D2F5_MSI_MAP_CAP__EN__SHIFT 0x10 ++#define D2F5_MSI_MAP_CAP__FIXD_MASK 0x20000 ++#define D2F5_MSI_MAP_CAP__FIXD__SHIFT 0x11 ++#define D2F5_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 ++#define D2F5_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b ++#define D2F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 ++#define D2F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 ++#define D2F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff ++#define D2F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 ++#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff ++#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 ++#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 ++#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 ++#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 ++#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 ++#define D2F5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff ++#define D2F5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 ++#define D2F5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff ++#define D2F5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 ++#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 ++#define D2F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 ++#define D2F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 ++#define D2F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 ++#define D2F5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 ++#define D2F5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 ++#define D2F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 ++#define D2F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa ++#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff ++#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 ++#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 ++#define D2F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 ++#define D2F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe ++#define D2F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 ++#define D2F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D2F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D2F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D2F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D2F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D2F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D2F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D2F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D2F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D2F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D2F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D2F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D2F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D2F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D2F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D2F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D2F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D2F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D2F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D2F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D2F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D2F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D2F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff ++#define D2F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 ++#define D2F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff ++#define D2F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 ++#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc ++#define D2F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd ++#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe ++#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf ++#define D2F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 ++#define D2F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 ++#define D2F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 ++#define D2F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 ++#define D2F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 ++#define D2F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 ++#define D2F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc ++#define D2F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd ++#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe ++#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf ++#define D2F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 ++#define D2F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 ++#define D2F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 ++#define D2F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 ++#define D2F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 ++#define D2F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 ++#define D2F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 ++#define D2F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 ++#define D2F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 ++#define D2F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 ++#define D2F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 ++#define D2F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 ++#define D2F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 ++#define D2F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 ++#define D2F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 ++#define D2F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 ++#define D2F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 ++#define D2F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 ++#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 ++#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 ++#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 ++#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc ++#define D2F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 ++#define D2F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd ++#define D2F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 ++#define D2F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe ++#define D2F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 ++#define D2F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf ++#define D2F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 ++#define D2F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 ++#define D2F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 ++#define D2F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 ++#define D2F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 ++#define D2F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 ++#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 ++#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 ++#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 ++#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc ++#define D2F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 ++#define D2F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd ++#define D2F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 ++#define D2F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe ++#define D2F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 ++#define D2F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 ++#define D2F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb ++#define D2F5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff ++#define D2F5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 ++#define D2F5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff ++#define D2F5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 ++#define D2F5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff ++#define D2F5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 ++#define D2F5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff ++#define D2F5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 ++#define D2F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 ++#define D2F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 ++#define D2F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 ++#define D2F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 ++#define D2F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 ++#define D2F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 ++#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 ++#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 ++#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 ++#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 ++#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 ++#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 ++#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 ++#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 ++#define D2F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 ++#define D2F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 ++#define D2F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 ++#define D2F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 ++#define D2F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 ++#define D2F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 ++#define D2F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 ++#define D2F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b ++#define D2F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff ++#define D2F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 ++#define D2F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 ++#define D2F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 ++#define D2F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff ++#define D2F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 ++#define D2F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff ++#define D2F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 ++#define D2F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff ++#define D2F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 ++#define D2F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff ++#define D2F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 ++#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 ++#define D2F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 ++#define D2F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 ++#define D2F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 ++#define D2F5_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc ++#define D2F5_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 ++#define D2F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff ++#define D2F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 ++#define D2F5_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 ++#define D2F5_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 ++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 ++#define D2F5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 ++#define D2F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 ++#define D2F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 ++#define D2F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 ++#define D2F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 ++#define D2F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 ++#define D2F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 ++#define D2F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 ++#define D2F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 ++#define D2F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 ++#define D2F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 ++#define D2F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 ++#define D2F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 ++#define D2F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 ++#define D2F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 ++#define D2F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 ++#define D2F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 ++#define D2F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 ++#define D2F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 ++#define D2F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 ++#define D2F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 ++#define D2F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 ++#define D2F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 ++#define D2F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 ++#define D2F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 ++#define D2F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 ++#define D2F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 ++#define D2F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 ++#define D2F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 ++#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D2F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D2F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D2F5_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f ++#define D2F5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 ++#define D2F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 ++#define D2F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf ++#define D2F5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 ++#define D2F5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 ++#define D2F5_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 ++#define D2F5_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f ++#define D2F5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f ++#define D2F5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 ++#define D2F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 ++#define D2F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc ++#define D2F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff ++#define D2F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 ++#define D2F5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff ++#define D2F5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 ++#define D2F5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff ++#define D2F5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 ++#define D2F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff ++#define D2F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 ++#define D2F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff ++#define D2F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 ++#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff ++#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 ++#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff ++#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 ++#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f ++#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 ++#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 ++#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 ++#define D2F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff ++#define D2F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 ++#define D3F1_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff ++#define D3F1_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 ++#define D3F1_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff ++#define D3F1_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 ++#define D3F1_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff ++#define D3F1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 ++#define D3F1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff ++#define D3F1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 ++#define D3F1_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define D3F1_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define D3F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define D3F1_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define D3F1_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define D3F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define D3F1_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define D3F1_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define D3F1_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define D3F1_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define D3F1_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define D3F1_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define D3F1_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define D3F1_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define D3F1_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define D3F1_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define D3F1_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define D3F1_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define D3F1_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define D3F1_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define D3F1_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define D3F1_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define D3F1_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define D3F1_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define D3F1_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define D3F1_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define D3F1_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define D3F1_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define D3F1_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define D3F1_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define D3F1_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define D3F1_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define D3F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 ++#define D3F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 ++#define D3F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 ++#define D3F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 ++#define D3F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 ++#define D3F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 ++#define D3F1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 ++#define D3F1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 ++#define D3F1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 ++#define D3F1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 ++#define D3F1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 ++#define D3F1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 ++#define D3F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 ++#define D3F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 ++#define D3F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 ++#define D3F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 ++#define D3F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 ++#define D3F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define D3F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 ++#define D3F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 ++#define D3F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 ++#define D3F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa ++#define D3F1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 ++#define D3F1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc ++#define D3F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 ++#define D3F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe ++#define D3F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 ++#define D3F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf ++#define D3F1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 ++#define D3F1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 ++#define D3F1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 ++#define D3F1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 ++#define D3F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 ++#define D3F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 ++#define D3F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 ++#define D3F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 ++#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 ++#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 ++#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 ++#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 ++#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 ++#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 ++#define D3F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff ++#define D3F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 ++#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 ++#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 ++#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 ++#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e ++#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 ++#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f ++#define D3F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff ++#define D3F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 ++#define D3F1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 ++#define D3F1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 ++#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 ++#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 ++#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 ++#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf ++#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 ++#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 ++#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff ++#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 ++#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 ++#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc ++#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff ++#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 ++#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 ++#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 ++#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff ++#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 ++#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 ++#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 ++#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff ++#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 ++#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 ++#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 ++#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff ++#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 ++#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 ++#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 ++#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff ++#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 ++#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 ++#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 ++#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff ++#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 ++#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 ++#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 ++#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 ++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 ++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 ++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 ++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 ++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 ++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 ++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 ++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 ++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 ++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 ++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 ++#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 ++#define D3F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 ++#define D3F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 ++#define D3F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e ++#define D3F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 ++#define D3F1_PCIE_FC_P__PD_CREDITS_MASK 0xff ++#define D3F1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 ++#define D3F1_PCIE_FC_P__PH_CREDITS_MASK 0xff00 ++#define D3F1_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 ++#define D3F1_PCIE_FC_NP__NPD_CREDITS_MASK 0xff ++#define D3F1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 ++#define D3F1_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 ++#define D3F1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 ++#define D3F1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff ++#define D3F1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 ++#define D3F1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 ++#define D3F1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 ++#define D3F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 ++#define D3F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 ++#define D3F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 ++#define D3F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 ++#define D3F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 ++#define D3F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 ++#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 ++#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 ++#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 ++#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 ++#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 ++#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 ++#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 ++#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 ++#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 ++#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 ++#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 ++#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb ++#define D3F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 ++#define D3F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe ++#define D3F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 ++#define D3F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf ++#define D3F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 ++#define D3F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 ++#define D3F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 ++#define D3F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 ++#define D3F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 ++#define D3F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc ++#define D3F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 ++#define D3F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd ++#define D3F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 ++#define D3F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe ++#define D3F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 ++#define D3F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf ++#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 ++#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 ++#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 ++#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 ++#define D3F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 ++#define D3F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 ++#define D3F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 ++#define D3F1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 ++#define D3F1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a ++#define D3F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 ++#define D3F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b ++#define D3F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff ++#define D3F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 ++#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff ++#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 ++#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 ++#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 ++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 ++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 ++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 ++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 ++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 ++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 ++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 ++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 ++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 ++#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 ++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff ++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 ++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 ++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 ++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff ++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 ++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 ++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 ++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff ++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 ++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 ++#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 ++#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 ++#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 ++#define D3F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 ++#define D3F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 ++#define D3F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 ++#define D3F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 ++#define D3F1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 ++#define D3F1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 ++#define D3F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 ++#define D3F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 ++#define D3F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 ++#define D3F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 ++#define D3F1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 ++#define D3F1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc ++#define D3F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 ++#define D3F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 ++#define D3F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 ++#define D3F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 ++#define D3F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 ++#define D3F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 ++#define D3F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 ++#define D3F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 ++#define D3F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 ++#define D3F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 ++#define D3F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 ++#define D3F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 ++#define D3F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 ++#define D3F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 ++#define D3F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 ++#define D3F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 ++#define D3F1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 ++#define D3F1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 ++#define D3F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 ++#define D3F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b ++#define D3F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 ++#define D3F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c ++#define D3F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 ++#define D3F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d ++#define D3F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 ++#define D3F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e ++#define D3F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 ++#define D3F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f ++#define D3F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f ++#define D3F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 ++#define D3F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 ++#define D3F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 ++#define D3F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 ++#define D3F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 ++#define D3F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 ++#define D3F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 ++#define D3F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 ++#define D3F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 ++#define D3F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 ++#define D3F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa ++#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 ++#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb ++#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 ++#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc ++#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 ++#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd ++#define D3F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 ++#define D3F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe ++#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 ++#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 ++#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 ++#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 ++#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 ++#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 ++#define D3F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 ++#define D3F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 ++#define D3F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 ++#define D3F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 ++#define D3F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 ++#define D3F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 ++#define D3F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 ++#define D3F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 ++#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 ++#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 ++#define D3F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 ++#define D3F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 ++#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 ++#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a ++#define D3F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 ++#define D3F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b ++#define D3F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 ++#define D3F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c ++#define D3F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 ++#define D3F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d ++#define D3F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 ++#define D3F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f ++#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 ++#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 ++#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 ++#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 ++#define D3F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 ++#define D3F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 ++#define D3F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 ++#define D3F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 ++#define D3F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 ++#define D3F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 ++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 ++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 ++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 ++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 ++#define D3F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 ++#define D3F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 ++#define D3F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 ++#define D3F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa ++#define D3F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 ++#define D3F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb ++#define D3F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 ++#define D3F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc ++#define D3F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 ++#define D3F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe ++#define D3F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 ++#define D3F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 ++#define D3F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 ++#define D3F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 ++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 ++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 ++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 ++#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 ++#define D3F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 ++#define D3F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 ++#define D3F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 ++#define D3F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 ++#define D3F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 ++#define D3F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 ++#define D3F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 ++#define D3F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 ++#define D3F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 ++#define D3F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a ++#define D3F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 ++#define D3F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e ++#define D3F1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 ++#define D3F1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f ++#define D3F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 ++#define D3F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 ++#define D3F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 ++#define D3F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 ++#define D3F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 ++#define D3F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 ++#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 ++#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 ++#define D3F1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 ++#define D3F1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 ++#define D3F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 ++#define D3F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 ++#define D3F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 ++#define D3F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 ++#define D3F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 ++#define D3F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 ++#define D3F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 ++#define D3F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa ++#define D3F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 ++#define D3F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb ++#define D3F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 ++#define D3F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc ++#define D3F1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 ++#define D3F1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd ++#define D3F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 ++#define D3F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe ++#define D3F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 ++#define D3F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf ++#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 ++#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 ++#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 ++#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 ++#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 ++#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 ++#define D3F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 ++#define D3F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 ++#define D3F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 ++#define D3F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 ++#define D3F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 ++#define D3F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 ++#define D3F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 ++#define D3F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 ++#define D3F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 ++#define D3F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a ++#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f ++#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 ++#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 ++#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 ++#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 ++#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc ++#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 ++#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 ++#define D3F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 ++#define D3F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 ++#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 ++#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 ++#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 ++#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 ++#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 ++#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 ++#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 ++#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 ++#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d ++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff ++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 ++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 ++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 ++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 ++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 ++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 ++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 ++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 ++#define D3F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 ++#define D3F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f ++#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff ++#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 ++#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 ++#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc ++#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 ++#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 ++#define D3F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff ++#define D3F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 ++#define D3F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 ++#define D3F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 ++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 ++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 ++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e ++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 ++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 ++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 ++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 ++#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd ++#define D3F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 ++#define D3F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 ++#define D3F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 ++#define D3F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 ++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf ++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 ++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 ++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 ++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 ++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa ++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 ++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 ++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 ++#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 ++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 ++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 ++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e ++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 ++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 ++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 ++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 ++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd ++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 ++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 ++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 ++#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 ++#define D3F1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f ++#define D3F1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 ++#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 ++#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 ++#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 ++#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 ++#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 ++#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 ++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f ++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 ++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 ++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 ++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 ++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 ++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 ++#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 ++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f ++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 ++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 ++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 ++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 ++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 ++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 ++#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 ++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f ++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 ++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 ++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 ++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 ++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 ++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 ++#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 ++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f ++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 ++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 ++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 ++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 ++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 ++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 ++#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 ++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f ++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 ++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 ++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 ++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 ++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 ++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 ++#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 ++#define D3F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 ++#define D3F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 ++#define D3F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc ++#define D3F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 ++#define D3F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 ++#define D3F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 ++#define D3F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 ++#define D3F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 ++#define D3F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 ++#define D3F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 ++#define D3F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 ++#define D3F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb ++#define D3F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 ++#define D3F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc ++#define D3F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 ++#define D3F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd ++#define D3F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 ++#define D3F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe ++#define D3F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 ++#define D3F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf ++#define D3F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 ++#define D3F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 ++#define D3F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 ++#define D3F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 ++#define D3F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 ++#define D3F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 ++#define D3F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 ++#define D3F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 ++#define D3F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 ++#define D3F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 ++#define D3F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 ++#define D3F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 ++#define D3F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 ++#define D3F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 ++#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 ++#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 ++#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 ++#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 ++#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 ++#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 ++#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 ++#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 ++#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 ++#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 ++#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 ++#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 ++#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 ++#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 ++#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 ++#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 ++#define D3F1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 ++#define D3F1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 ++#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 ++#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 ++#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 ++#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 ++#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 ++#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa ++#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 ++#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb ++#define D3F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 ++#define D3F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf ++#define D3F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 ++#define D3F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 ++#define D3F1_VENDOR_ID__VENDOR_ID_MASK 0xffff ++#define D3F1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 ++#define D3F1_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 ++#define D3F1_DEVICE_ID__DEVICE_ID__SHIFT 0x10 ++#define D3F1_COMMAND__IO_ACCESS_EN_MASK 0x1 ++#define D3F1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 ++#define D3F1_COMMAND__MEM_ACCESS_EN_MASK 0x2 ++#define D3F1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 ++#define D3F1_COMMAND__BUS_MASTER_EN_MASK 0x4 ++#define D3F1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 ++#define D3F1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 ++#define D3F1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 ++#define D3F1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 ++#define D3F1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 ++#define D3F1_COMMAND__PAL_SNOOP_EN_MASK 0x20 ++#define D3F1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 ++#define D3F1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 ++#define D3F1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 ++#define D3F1_COMMAND__AD_STEPPING_MASK 0x80 ++#define D3F1_COMMAND__AD_STEPPING__SHIFT 0x7 ++#define D3F1_COMMAND__SERR_EN_MASK 0x100 ++#define D3F1_COMMAND__SERR_EN__SHIFT 0x8 ++#define D3F1_COMMAND__FAST_B2B_EN_MASK 0x200 ++#define D3F1_COMMAND__FAST_B2B_EN__SHIFT 0x9 ++#define D3F1_COMMAND__INT_DIS_MASK 0x400 ++#define D3F1_COMMAND__INT_DIS__SHIFT 0xa ++#define D3F1_STATUS__INT_STATUS_MASK 0x80000 ++#define D3F1_STATUS__INT_STATUS__SHIFT 0x13 ++#define D3F1_STATUS__CAP_LIST_MASK 0x100000 ++#define D3F1_STATUS__CAP_LIST__SHIFT 0x14 ++#define D3F1_STATUS__PCI_66_EN_MASK 0x200000 ++#define D3F1_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D3F1_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D3F1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D3F1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D3F1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D3F1_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D3F1_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D3F1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D3F1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D3F1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D3F1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D3F1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D3F1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D3F1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 ++#define D3F1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e ++#define D3F1_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D3F1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D3F1_REVISION_ID__MINOR_REV_ID_MASK 0xf ++#define D3F1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 ++#define D3F1_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 ++#define D3F1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 ++#define D3F1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 ++#define D3F1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 ++#define D3F1_SUB_CLASS__SUB_CLASS_MASK 0xff0000 ++#define D3F1_SUB_CLASS__SUB_CLASS__SHIFT 0x10 ++#define D3F1_BASE_CLASS__BASE_CLASS_MASK 0xff000000 ++#define D3F1_BASE_CLASS__BASE_CLASS__SHIFT 0x18 ++#define D3F1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff ++#define D3F1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 ++#define D3F1_LATENCY__LATENCY_TIMER_MASK 0xff00 ++#define D3F1_LATENCY__LATENCY_TIMER__SHIFT 0x8 ++#define D3F1_HEADER__HEADER_TYPE_MASK 0x7f0000 ++#define D3F1_HEADER__HEADER_TYPE__SHIFT 0x10 ++#define D3F1_HEADER__DEVICE_TYPE_MASK 0x800000 ++#define D3F1_HEADER__DEVICE_TYPE__SHIFT 0x17 ++#define D3F1_BIST__BIST_COMP_MASK 0xf000000 ++#define D3F1_BIST__BIST_COMP__SHIFT 0x18 ++#define D3F1_BIST__BIST_STRT_MASK 0x40000000 ++#define D3F1_BIST__BIST_STRT__SHIFT 0x1e ++#define D3F1_BIST__BIST_CAP_MASK 0x80000000 ++#define D3F1_BIST__BIST_CAP__SHIFT 0x1f ++#define D3F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff ++#define D3F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 ++#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 ++#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 ++#define D3F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 ++#define D3F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 ++#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 ++#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 ++#define D3F1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf ++#define D3F1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 ++#define D3F1_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 ++#define D3F1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 ++#define D3F1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 ++#define D3F1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 ++#define D3F1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 ++#define D3F1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc ++#define D3F1_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 ++#define D3F1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 ++#define D3F1_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 ++#define D3F1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D3F1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D3F1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D3F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D3F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D3F1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D3F1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D3F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D3F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D3F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D3F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D3F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D3F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D3F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 ++#define D3F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e ++#define D3F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D3F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D3F1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf ++#define D3F1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 ++#define D3F1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 ++#define D3F1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 ++#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 ++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf ++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 ++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 ++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 ++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 ++#define D3F1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff ++#define D3F1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 ++#define D3F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff ++#define D3F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 ++#define D3F1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff ++#define D3F1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 ++#define D3F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 ++#define D3F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 ++#define D3F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 ++#define D3F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 ++#define D3F1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 ++#define D3F1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 ++#define D3F1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 ++#define D3F1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 ++#define D3F1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 ++#define D3F1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 ++#define D3F1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 ++#define D3F1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 ++#define D3F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 ++#define D3F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 ++#define D3F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 ++#define D3F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 ++#define D3F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 ++#define D3F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 ++#define D3F1_CAP_PTR__CAP_PTR_MASK 0xff ++#define D3F1_CAP_PTR__CAP_PTR__SHIFT 0x0 ++#define D3F1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff ++#define D3F1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 ++#define D3F1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 ++#define D3F1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 ++#define D3F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 ++#define D3F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 ++#define D3F1_PMI_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F1_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F1_PMI_CAP__VERSION_MASK 0x70000 ++#define D3F1_PMI_CAP__VERSION__SHIFT 0x10 ++#define D3F1_PMI_CAP__PME_CLOCK_MASK 0x80000 ++#define D3F1_PMI_CAP__PME_CLOCK__SHIFT 0x13 ++#define D3F1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 ++#define D3F1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 ++#define D3F1_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 ++#define D3F1_PMI_CAP__AUX_CURRENT__SHIFT 0x16 ++#define D3F1_PMI_CAP__D1_SUPPORT_MASK 0x2000000 ++#define D3F1_PMI_CAP__D1_SUPPORT__SHIFT 0x19 ++#define D3F1_PMI_CAP__D2_SUPPORT_MASK 0x4000000 ++#define D3F1_PMI_CAP__D2_SUPPORT__SHIFT 0x1a ++#define D3F1_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 ++#define D3F1_PMI_CAP__PME_SUPPORT__SHIFT 0x1b ++#define D3F1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 ++#define D3F1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 ++#define D3F1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 ++#define D3F1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 ++#define D3F1_PMI_STATUS_CNTL__PME_EN_MASK 0x100 ++#define D3F1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 ++#define D3F1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 ++#define D3F1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 ++#define D3F1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 ++#define D3F1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd ++#define D3F1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 ++#define D3F1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf ++#define D3F1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 ++#define D3F1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 ++#define D3F1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 ++#define D3F1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 ++#define D3F1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 ++#define D3F1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 ++#define D3F1_PCIE_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F1_PCIE_CAP__VERSION_MASK 0xf0000 ++#define D3F1_PCIE_CAP__VERSION__SHIFT 0x10 ++#define D3F1_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 ++#define D3F1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 ++#define D3F1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 ++#define D3F1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 ++#define D3F1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 ++#define D3F1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 ++#define D3F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 ++#define D3F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 ++#define D3F1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 ++#define D3F1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 ++#define D3F1_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 ++#define D3F1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 ++#define D3F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 ++#define D3F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 ++#define D3F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 ++#define D3F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 ++#define D3F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 ++#define D3F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf ++#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 ++#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 ++#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 ++#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a ++#define D3F1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 ++#define D3F1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c ++#define D3F1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 ++#define D3F1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 ++#define D3F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 ++#define D3F1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 ++#define D3F1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 ++#define D3F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 ++#define D3F1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 ++#define D3F1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 ++#define D3F1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 ++#define D3F1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 ++#define D3F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 ++#define D3F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 ++#define D3F1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 ++#define D3F1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 ++#define D3F1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 ++#define D3F1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 ++#define D3F1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 ++#define D3F1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa ++#define D3F1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 ++#define D3F1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb ++#define D3F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 ++#define D3F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc ++#define D3F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 ++#define D3F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf ++#define D3F1_DEVICE_STATUS__CORR_ERR_MASK 0x10000 ++#define D3F1_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 ++#define D3F1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 ++#define D3F1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 ++#define D3F1_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 ++#define D3F1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 ++#define D3F1_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 ++#define D3F1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 ++#define D3F1_DEVICE_STATUS__AUX_PWR_MASK 0x100000 ++#define D3F1_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 ++#define D3F1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 ++#define D3F1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 ++#define D3F1_LINK_CAP__LINK_SPEED_MASK 0xf ++#define D3F1_LINK_CAP__LINK_SPEED__SHIFT 0x0 ++#define D3F1_LINK_CAP__LINK_WIDTH_MASK 0x3f0 ++#define D3F1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 ++#define D3F1_LINK_CAP__PM_SUPPORT_MASK 0xc00 ++#define D3F1_LINK_CAP__PM_SUPPORT__SHIFT 0xa ++#define D3F1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 ++#define D3F1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc ++#define D3F1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 ++#define D3F1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf ++#define D3F1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 ++#define D3F1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 ++#define D3F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 ++#define D3F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 ++#define D3F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 ++#define D3F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 ++#define D3F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 ++#define D3F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 ++#define D3F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 ++#define D3F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 ++#define D3F1_LINK_CAP__PORT_NUMBER_MASK 0xff000000 ++#define D3F1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 ++#define D3F1_LINK_CNTL__PM_CONTROL_MASK 0x3 ++#define D3F1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 ++#define D3F1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 ++#define D3F1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 ++#define D3F1_LINK_CNTL__LINK_DIS_MASK 0x10 ++#define D3F1_LINK_CNTL__LINK_DIS__SHIFT 0x4 ++#define D3F1_LINK_CNTL__RETRAIN_LINK_MASK 0x20 ++#define D3F1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 ++#define D3F1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 ++#define D3F1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 ++#define D3F1_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 ++#define D3F1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 ++#define D3F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 ++#define D3F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 ++#define D3F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 ++#define D3F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 ++#define D3F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 ++#define D3F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa ++#define D3F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 ++#define D3F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb ++#define D3F1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 ++#define D3F1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 ++#define D3F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 ++#define D3F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 ++#define D3F1_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 ++#define D3F1_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b ++#define D3F1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 ++#define D3F1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c ++#define D3F1_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 ++#define D3F1_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d ++#define D3F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 ++#define D3F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e ++#define D3F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 ++#define D3F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f ++#define D3F1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 ++#define D3F1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 ++#define D3F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 ++#define D3F1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 ++#define D3F1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 ++#define D3F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 ++#define D3F1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 ++#define D3F1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 ++#define D3F1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 ++#define D3F1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 ++#define D3F1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 ++#define D3F1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 ++#define D3F1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 ++#define D3F1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 ++#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 ++#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 ++#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 ++#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf ++#define D3F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 ++#define D3F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 ++#define D3F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 ++#define D3F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 ++#define D3F1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 ++#define D3F1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 ++#define D3F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 ++#define D3F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 ++#define D3F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 ++#define D3F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 ++#define D3F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 ++#define D3F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 ++#define D3F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 ++#define D3F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 ++#define D3F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 ++#define D3F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 ++#define D3F1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 ++#define D3F1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 ++#define D3F1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 ++#define D3F1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 ++#define D3F1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 ++#define D3F1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 ++#define D3F1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 ++#define D3F1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa ++#define D3F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 ++#define D3F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb ++#define D3F1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 ++#define D3F1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc ++#define D3F1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 ++#define D3F1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 ++#define D3F1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 ++#define D3F1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 ++#define D3F1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 ++#define D3F1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 ++#define D3F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 ++#define D3F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 ++#define D3F1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 ++#define D3F1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 ++#define D3F1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 ++#define D3F1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 ++#define D3F1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 ++#define D3F1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 ++#define D3F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 ++#define D3F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 ++#define D3F1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 ++#define D3F1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 ++#define D3F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 ++#define D3F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 ++#define D3F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 ++#define D3F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 ++#define D3F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 ++#define D3F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 ++#define D3F1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 ++#define D3F1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 ++#define D3F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 ++#define D3F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 ++#define D3F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 ++#define D3F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 ++#define D3F1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff ++#define D3F1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 ++#define D3F1_ROOT_STATUS__PME_STATUS_MASK 0x10000 ++#define D3F1_ROOT_STATUS__PME_STATUS__SHIFT 0x10 ++#define D3F1_ROOT_STATUS__PME_PENDING_MASK 0x20000 ++#define D3F1_ROOT_STATUS__PME_PENDING__SHIFT 0x11 ++#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf ++#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 ++#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 ++#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 ++#define D3F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 ++#define D3F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 ++#define D3F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 ++#define D3F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 ++#define D3F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 ++#define D3F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 ++#define D3F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 ++#define D3F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 ++#define D3F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 ++#define D3F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 ++#define D3F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 ++#define D3F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa ++#define D3F1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 ++#define D3F1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb ++#define D3F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 ++#define D3F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc ++#define D3F1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 ++#define D3F1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 ++#define D3F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 ++#define D3F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 ++#define D3F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 ++#define D3F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 ++#define D3F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 ++#define D3F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 ++#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf ++#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 ++#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 ++#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 ++#define D3F1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 ++#define D3F1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 ++#define D3F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 ++#define D3F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 ++#define D3F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 ++#define D3F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 ++#define D3F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 ++#define D3F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 ++#define D3F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 ++#define D3F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 ++#define D3F1_DEVICE_CNTL2__LTR_EN_MASK 0x400 ++#define D3F1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa ++#define D3F1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 ++#define D3F1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd ++#define D3F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 ++#define D3F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf ++#define D3F1_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 ++#define D3F1_DEVICE_STATUS2__RESERVED__SHIFT 0x10 ++#define D3F1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe ++#define D3F1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 ++#define D3F1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 ++#define D3F1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 ++#define D3F1_LINK_CAP2__RESERVED_MASK 0xfffffe00 ++#define D3F1_LINK_CAP2__RESERVED__SHIFT 0x9 ++#define D3F1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf ++#define D3F1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 ++#define D3F1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 ++#define D3F1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 ++#define D3F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 ++#define D3F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 ++#define D3F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 ++#define D3F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 ++#define D3F1_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 ++#define D3F1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 ++#define D3F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 ++#define D3F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa ++#define D3F1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 ++#define D3F1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb ++#define D3F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 ++#define D3F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc ++#define D3F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 ++#define D3F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 ++#define D3F1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 ++#define D3F1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 ++#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 ++#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 ++#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 ++#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 ++#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 ++#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 ++#define D3F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 ++#define D3F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 ++#define D3F1_SLOT_CAP2__RESERVED_MASK 0xffffffff ++#define D3F1_SLOT_CAP2__RESERVED__SHIFT 0x0 ++#define D3F1_SLOT_CNTL2__RESERVED_MASK 0xffff ++#define D3F1_SLOT_CNTL2__RESERVED__SHIFT 0x0 ++#define D3F1_SLOT_STATUS2__RESERVED_MASK 0xffff0000 ++#define D3F1_SLOT_STATUS2__RESERVED__SHIFT 0x10 ++#define D3F1_MSI_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F1_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F1_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 ++#define D3F1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 ++#define D3F1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 ++#define D3F1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 ++#define D3F1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 ++#define D3F1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 ++#define D3F1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 ++#define D3F1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 ++#define D3F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 ++#define D3F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 ++#define D3F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc ++#define D3F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 ++#define D3F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff ++#define D3F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 ++#define D3F1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff ++#define D3F1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 ++#define D3F1_MSI_MSG_DATA__MSI_DATA_MASK 0xffff ++#define D3F1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 ++#define D3F1_SSID_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F1_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff ++#define D3F1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define D3F1_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 ++#define D3F1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 ++#define D3F1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F1_MSI_MAP_CAP__EN_MASK 0x10000 ++#define D3F1_MSI_MAP_CAP__EN__SHIFT 0x10 ++#define D3F1_MSI_MAP_CAP__FIXD_MASK 0x20000 ++#define D3F1_MSI_MAP_CAP__FIXD__SHIFT 0x11 ++#define D3F1_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 ++#define D3F1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b ++#define D3F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 ++#define D3F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 ++#define D3F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff ++#define D3F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 ++#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff ++#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 ++#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 ++#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 ++#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 ++#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 ++#define D3F1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff ++#define D3F1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 ++#define D3F1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff ++#define D3F1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 ++#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 ++#define D3F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 ++#define D3F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 ++#define D3F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 ++#define D3F1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 ++#define D3F1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 ++#define D3F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 ++#define D3F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa ++#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff ++#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 ++#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 ++#define D3F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 ++#define D3F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe ++#define D3F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 ++#define D3F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D3F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D3F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D3F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D3F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D3F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D3F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D3F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D3F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D3F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D3F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D3F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D3F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D3F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D3F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D3F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D3F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D3F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D3F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D3F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D3F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff ++#define D3F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 ++#define D3F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff ++#define D3F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 ++#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc ++#define D3F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd ++#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe ++#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf ++#define D3F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 ++#define D3F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 ++#define D3F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 ++#define D3F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 ++#define D3F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 ++#define D3F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 ++#define D3F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc ++#define D3F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd ++#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe ++#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf ++#define D3F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 ++#define D3F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 ++#define D3F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 ++#define D3F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 ++#define D3F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 ++#define D3F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 ++#define D3F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 ++#define D3F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 ++#define D3F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 ++#define D3F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 ++#define D3F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 ++#define D3F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 ++#define D3F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 ++#define D3F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 ++#define D3F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 ++#define D3F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 ++#define D3F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 ++#define D3F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 ++#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 ++#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 ++#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 ++#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc ++#define D3F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 ++#define D3F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd ++#define D3F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 ++#define D3F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe ++#define D3F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 ++#define D3F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf ++#define D3F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 ++#define D3F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 ++#define D3F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 ++#define D3F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 ++#define D3F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 ++#define D3F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 ++#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 ++#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 ++#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 ++#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc ++#define D3F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 ++#define D3F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd ++#define D3F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 ++#define D3F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe ++#define D3F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 ++#define D3F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 ++#define D3F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb ++#define D3F1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff ++#define D3F1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 ++#define D3F1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff ++#define D3F1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 ++#define D3F1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff ++#define D3F1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 ++#define D3F1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff ++#define D3F1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 ++#define D3F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 ++#define D3F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 ++#define D3F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 ++#define D3F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 ++#define D3F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 ++#define D3F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 ++#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 ++#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 ++#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 ++#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 ++#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 ++#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 ++#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 ++#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 ++#define D3F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 ++#define D3F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 ++#define D3F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 ++#define D3F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 ++#define D3F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 ++#define D3F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 ++#define D3F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 ++#define D3F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b ++#define D3F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff ++#define D3F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 ++#define D3F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 ++#define D3F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 ++#define D3F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff ++#define D3F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 ++#define D3F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff ++#define D3F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 ++#define D3F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff ++#define D3F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 ++#define D3F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff ++#define D3F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 ++#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 ++#define D3F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 ++#define D3F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 ++#define D3F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 ++#define D3F1_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc ++#define D3F1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 ++#define D3F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff ++#define D3F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 ++#define D3F1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 ++#define D3F1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 ++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 ++#define D3F1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 ++#define D3F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 ++#define D3F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 ++#define D3F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 ++#define D3F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 ++#define D3F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 ++#define D3F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 ++#define D3F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 ++#define D3F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 ++#define D3F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 ++#define D3F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 ++#define D3F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 ++#define D3F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 ++#define D3F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 ++#define D3F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 ++#define D3F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 ++#define D3F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 ++#define D3F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 ++#define D3F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 ++#define D3F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 ++#define D3F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 ++#define D3F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 ++#define D3F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 ++#define D3F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 ++#define D3F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 ++#define D3F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 ++#define D3F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 ++#define D3F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 ++#define D3F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 ++#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f ++#define D3F1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 ++#define D3F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 ++#define D3F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf ++#define D3F1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 ++#define D3F1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 ++#define D3F1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 ++#define D3F1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f ++#define D3F1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f ++#define D3F1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 ++#define D3F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 ++#define D3F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc ++#define D3F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff ++#define D3F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 ++#define D3F1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff ++#define D3F1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 ++#define D3F1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff ++#define D3F1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 ++#define D3F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff ++#define D3F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 ++#define D3F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff ++#define D3F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 ++#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff ++#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 ++#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff ++#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 ++#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f ++#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 ++#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 ++#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 ++#define D3F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff ++#define D3F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 ++#define D3F2_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff ++#define D3F2_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 ++#define D3F2_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff ++#define D3F2_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 ++#define D3F2_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff ++#define D3F2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 ++#define D3F2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff ++#define D3F2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 ++#define D3F2_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define D3F2_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define D3F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define D3F2_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define D3F2_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define D3F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define D3F2_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define D3F2_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define D3F2_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define D3F2_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define D3F2_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define D3F2_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define D3F2_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define D3F2_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define D3F2_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define D3F2_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define D3F2_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define D3F2_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define D3F2_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define D3F2_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define D3F2_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define D3F2_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define D3F2_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define D3F2_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define D3F2_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define D3F2_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define D3F2_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define D3F2_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define D3F2_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define D3F2_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define D3F2_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define D3F2_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define D3F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 ++#define D3F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 ++#define D3F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 ++#define D3F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 ++#define D3F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 ++#define D3F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 ++#define D3F2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 ++#define D3F2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 ++#define D3F2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 ++#define D3F2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 ++#define D3F2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 ++#define D3F2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 ++#define D3F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 ++#define D3F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 ++#define D3F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 ++#define D3F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 ++#define D3F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 ++#define D3F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define D3F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 ++#define D3F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 ++#define D3F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 ++#define D3F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa ++#define D3F2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 ++#define D3F2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc ++#define D3F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 ++#define D3F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe ++#define D3F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 ++#define D3F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf ++#define D3F2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 ++#define D3F2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 ++#define D3F2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 ++#define D3F2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 ++#define D3F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 ++#define D3F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 ++#define D3F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 ++#define D3F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 ++#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 ++#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 ++#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 ++#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 ++#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 ++#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 ++#define D3F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff ++#define D3F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 ++#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 ++#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 ++#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 ++#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e ++#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 ++#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f ++#define D3F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff ++#define D3F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 ++#define D3F2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 ++#define D3F2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 ++#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 ++#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 ++#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 ++#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf ++#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 ++#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 ++#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff ++#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 ++#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 ++#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc ++#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff ++#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 ++#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 ++#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 ++#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff ++#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 ++#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 ++#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 ++#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff ++#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 ++#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 ++#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 ++#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff ++#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 ++#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 ++#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 ++#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff ++#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 ++#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 ++#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 ++#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff ++#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 ++#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 ++#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 ++#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 ++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 ++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 ++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 ++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 ++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 ++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 ++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 ++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 ++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 ++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 ++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 ++#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 ++#define D3F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 ++#define D3F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 ++#define D3F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e ++#define D3F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 ++#define D3F2_PCIE_FC_P__PD_CREDITS_MASK 0xff ++#define D3F2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 ++#define D3F2_PCIE_FC_P__PH_CREDITS_MASK 0xff00 ++#define D3F2_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 ++#define D3F2_PCIE_FC_NP__NPD_CREDITS_MASK 0xff ++#define D3F2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 ++#define D3F2_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 ++#define D3F2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 ++#define D3F2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff ++#define D3F2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 ++#define D3F2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 ++#define D3F2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 ++#define D3F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 ++#define D3F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 ++#define D3F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 ++#define D3F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 ++#define D3F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 ++#define D3F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 ++#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 ++#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 ++#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 ++#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 ++#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 ++#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 ++#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 ++#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 ++#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 ++#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 ++#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 ++#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb ++#define D3F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 ++#define D3F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe ++#define D3F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 ++#define D3F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf ++#define D3F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 ++#define D3F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 ++#define D3F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 ++#define D3F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 ++#define D3F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 ++#define D3F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc ++#define D3F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 ++#define D3F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd ++#define D3F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 ++#define D3F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe ++#define D3F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 ++#define D3F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf ++#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 ++#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 ++#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 ++#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 ++#define D3F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 ++#define D3F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 ++#define D3F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 ++#define D3F2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 ++#define D3F2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a ++#define D3F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 ++#define D3F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b ++#define D3F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff ++#define D3F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 ++#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff ++#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 ++#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 ++#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 ++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 ++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 ++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 ++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 ++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 ++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 ++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 ++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 ++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 ++#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 ++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff ++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 ++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 ++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 ++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff ++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 ++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 ++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 ++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff ++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 ++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 ++#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 ++#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 ++#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 ++#define D3F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 ++#define D3F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 ++#define D3F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 ++#define D3F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 ++#define D3F2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 ++#define D3F2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 ++#define D3F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 ++#define D3F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 ++#define D3F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 ++#define D3F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 ++#define D3F2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 ++#define D3F2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc ++#define D3F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 ++#define D3F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 ++#define D3F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 ++#define D3F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 ++#define D3F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 ++#define D3F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 ++#define D3F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 ++#define D3F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 ++#define D3F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 ++#define D3F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 ++#define D3F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 ++#define D3F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 ++#define D3F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 ++#define D3F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 ++#define D3F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 ++#define D3F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 ++#define D3F2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 ++#define D3F2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 ++#define D3F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 ++#define D3F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b ++#define D3F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 ++#define D3F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c ++#define D3F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 ++#define D3F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d ++#define D3F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 ++#define D3F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e ++#define D3F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 ++#define D3F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f ++#define D3F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f ++#define D3F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 ++#define D3F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 ++#define D3F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 ++#define D3F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 ++#define D3F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 ++#define D3F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 ++#define D3F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 ++#define D3F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 ++#define D3F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 ++#define D3F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 ++#define D3F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa ++#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 ++#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb ++#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 ++#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc ++#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 ++#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd ++#define D3F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 ++#define D3F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe ++#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 ++#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 ++#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 ++#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 ++#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 ++#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 ++#define D3F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 ++#define D3F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 ++#define D3F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 ++#define D3F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 ++#define D3F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 ++#define D3F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 ++#define D3F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 ++#define D3F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 ++#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 ++#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 ++#define D3F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 ++#define D3F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 ++#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 ++#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a ++#define D3F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 ++#define D3F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b ++#define D3F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 ++#define D3F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c ++#define D3F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 ++#define D3F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d ++#define D3F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 ++#define D3F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f ++#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 ++#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 ++#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 ++#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 ++#define D3F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 ++#define D3F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 ++#define D3F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 ++#define D3F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 ++#define D3F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 ++#define D3F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 ++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 ++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 ++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 ++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 ++#define D3F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 ++#define D3F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 ++#define D3F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 ++#define D3F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa ++#define D3F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 ++#define D3F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb ++#define D3F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 ++#define D3F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc ++#define D3F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 ++#define D3F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe ++#define D3F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 ++#define D3F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 ++#define D3F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 ++#define D3F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 ++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 ++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 ++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 ++#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 ++#define D3F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 ++#define D3F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 ++#define D3F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 ++#define D3F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 ++#define D3F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 ++#define D3F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 ++#define D3F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 ++#define D3F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 ++#define D3F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 ++#define D3F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a ++#define D3F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 ++#define D3F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e ++#define D3F2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 ++#define D3F2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f ++#define D3F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 ++#define D3F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 ++#define D3F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 ++#define D3F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 ++#define D3F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 ++#define D3F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 ++#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 ++#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 ++#define D3F2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 ++#define D3F2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 ++#define D3F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 ++#define D3F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 ++#define D3F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 ++#define D3F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 ++#define D3F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 ++#define D3F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 ++#define D3F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 ++#define D3F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa ++#define D3F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 ++#define D3F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb ++#define D3F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 ++#define D3F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc ++#define D3F2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 ++#define D3F2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd ++#define D3F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 ++#define D3F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe ++#define D3F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 ++#define D3F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf ++#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 ++#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 ++#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 ++#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 ++#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 ++#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 ++#define D3F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 ++#define D3F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 ++#define D3F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 ++#define D3F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 ++#define D3F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 ++#define D3F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 ++#define D3F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 ++#define D3F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 ++#define D3F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 ++#define D3F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a ++#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f ++#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 ++#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 ++#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 ++#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 ++#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc ++#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 ++#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 ++#define D3F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 ++#define D3F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 ++#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 ++#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 ++#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 ++#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 ++#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 ++#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 ++#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 ++#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 ++#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d ++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff ++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 ++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 ++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 ++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 ++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 ++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 ++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 ++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 ++#define D3F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 ++#define D3F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f ++#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff ++#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 ++#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 ++#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc ++#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 ++#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 ++#define D3F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff ++#define D3F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 ++#define D3F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 ++#define D3F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 ++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 ++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 ++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e ++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 ++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 ++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 ++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 ++#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd ++#define D3F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 ++#define D3F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 ++#define D3F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 ++#define D3F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 ++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf ++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 ++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 ++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 ++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 ++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa ++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 ++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 ++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 ++#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 ++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 ++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 ++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e ++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 ++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 ++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 ++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 ++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd ++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 ++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 ++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 ++#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 ++#define D3F2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f ++#define D3F2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 ++#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 ++#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 ++#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 ++#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 ++#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 ++#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 ++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f ++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 ++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 ++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 ++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 ++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 ++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 ++#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 ++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f ++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 ++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 ++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 ++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 ++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 ++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 ++#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 ++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f ++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 ++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 ++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 ++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 ++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 ++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 ++#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 ++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f ++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 ++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 ++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 ++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 ++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 ++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 ++#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 ++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f ++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 ++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 ++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 ++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 ++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 ++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 ++#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 ++#define D3F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 ++#define D3F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 ++#define D3F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc ++#define D3F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 ++#define D3F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 ++#define D3F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 ++#define D3F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 ++#define D3F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 ++#define D3F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 ++#define D3F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 ++#define D3F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 ++#define D3F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb ++#define D3F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 ++#define D3F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc ++#define D3F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 ++#define D3F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd ++#define D3F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 ++#define D3F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe ++#define D3F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 ++#define D3F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf ++#define D3F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 ++#define D3F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 ++#define D3F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 ++#define D3F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 ++#define D3F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 ++#define D3F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 ++#define D3F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 ++#define D3F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 ++#define D3F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 ++#define D3F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 ++#define D3F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 ++#define D3F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 ++#define D3F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 ++#define D3F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 ++#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 ++#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 ++#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 ++#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 ++#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 ++#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 ++#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 ++#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 ++#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 ++#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 ++#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 ++#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 ++#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 ++#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 ++#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 ++#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 ++#define D3F2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 ++#define D3F2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 ++#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 ++#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 ++#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 ++#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 ++#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 ++#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa ++#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 ++#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb ++#define D3F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 ++#define D3F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf ++#define D3F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 ++#define D3F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 ++#define D3F2_VENDOR_ID__VENDOR_ID_MASK 0xffff ++#define D3F2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 ++#define D3F2_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 ++#define D3F2_DEVICE_ID__DEVICE_ID__SHIFT 0x10 ++#define D3F2_COMMAND__IO_ACCESS_EN_MASK 0x1 ++#define D3F2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 ++#define D3F2_COMMAND__MEM_ACCESS_EN_MASK 0x2 ++#define D3F2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 ++#define D3F2_COMMAND__BUS_MASTER_EN_MASK 0x4 ++#define D3F2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 ++#define D3F2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 ++#define D3F2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 ++#define D3F2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 ++#define D3F2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 ++#define D3F2_COMMAND__PAL_SNOOP_EN_MASK 0x20 ++#define D3F2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 ++#define D3F2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 ++#define D3F2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 ++#define D3F2_COMMAND__AD_STEPPING_MASK 0x80 ++#define D3F2_COMMAND__AD_STEPPING__SHIFT 0x7 ++#define D3F2_COMMAND__SERR_EN_MASK 0x100 ++#define D3F2_COMMAND__SERR_EN__SHIFT 0x8 ++#define D3F2_COMMAND__FAST_B2B_EN_MASK 0x200 ++#define D3F2_COMMAND__FAST_B2B_EN__SHIFT 0x9 ++#define D3F2_COMMAND__INT_DIS_MASK 0x400 ++#define D3F2_COMMAND__INT_DIS__SHIFT 0xa ++#define D3F2_STATUS__INT_STATUS_MASK 0x80000 ++#define D3F2_STATUS__INT_STATUS__SHIFT 0x13 ++#define D3F2_STATUS__CAP_LIST_MASK 0x100000 ++#define D3F2_STATUS__CAP_LIST__SHIFT 0x14 ++#define D3F2_STATUS__PCI_66_EN_MASK 0x200000 ++#define D3F2_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D3F2_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D3F2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D3F2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D3F2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D3F2_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D3F2_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D3F2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D3F2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D3F2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D3F2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D3F2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D3F2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D3F2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 ++#define D3F2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e ++#define D3F2_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D3F2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D3F2_REVISION_ID__MINOR_REV_ID_MASK 0xf ++#define D3F2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 ++#define D3F2_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 ++#define D3F2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 ++#define D3F2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 ++#define D3F2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 ++#define D3F2_SUB_CLASS__SUB_CLASS_MASK 0xff0000 ++#define D3F2_SUB_CLASS__SUB_CLASS__SHIFT 0x10 ++#define D3F2_BASE_CLASS__BASE_CLASS_MASK 0xff000000 ++#define D3F2_BASE_CLASS__BASE_CLASS__SHIFT 0x18 ++#define D3F2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff ++#define D3F2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 ++#define D3F2_LATENCY__LATENCY_TIMER_MASK 0xff00 ++#define D3F2_LATENCY__LATENCY_TIMER__SHIFT 0x8 ++#define D3F2_HEADER__HEADER_TYPE_MASK 0x7f0000 ++#define D3F2_HEADER__HEADER_TYPE__SHIFT 0x10 ++#define D3F2_HEADER__DEVICE_TYPE_MASK 0x800000 ++#define D3F2_HEADER__DEVICE_TYPE__SHIFT 0x17 ++#define D3F2_BIST__BIST_COMP_MASK 0xf000000 ++#define D3F2_BIST__BIST_COMP__SHIFT 0x18 ++#define D3F2_BIST__BIST_STRT_MASK 0x40000000 ++#define D3F2_BIST__BIST_STRT__SHIFT 0x1e ++#define D3F2_BIST__BIST_CAP_MASK 0x80000000 ++#define D3F2_BIST__BIST_CAP__SHIFT 0x1f ++#define D3F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff ++#define D3F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 ++#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 ++#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 ++#define D3F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 ++#define D3F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 ++#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 ++#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 ++#define D3F2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf ++#define D3F2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 ++#define D3F2_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 ++#define D3F2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 ++#define D3F2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 ++#define D3F2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 ++#define D3F2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 ++#define D3F2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc ++#define D3F2_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 ++#define D3F2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 ++#define D3F2_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 ++#define D3F2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D3F2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D3F2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D3F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D3F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D3F2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D3F2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D3F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D3F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D3F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D3F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D3F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D3F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D3F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 ++#define D3F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e ++#define D3F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D3F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D3F2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf ++#define D3F2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 ++#define D3F2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 ++#define D3F2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 ++#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 ++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf ++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 ++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 ++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 ++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 ++#define D3F2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff ++#define D3F2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 ++#define D3F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff ++#define D3F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 ++#define D3F2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff ++#define D3F2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 ++#define D3F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 ++#define D3F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 ++#define D3F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 ++#define D3F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 ++#define D3F2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 ++#define D3F2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 ++#define D3F2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 ++#define D3F2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 ++#define D3F2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 ++#define D3F2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 ++#define D3F2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 ++#define D3F2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 ++#define D3F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 ++#define D3F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 ++#define D3F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 ++#define D3F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 ++#define D3F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 ++#define D3F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 ++#define D3F2_CAP_PTR__CAP_PTR_MASK 0xff ++#define D3F2_CAP_PTR__CAP_PTR__SHIFT 0x0 ++#define D3F2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff ++#define D3F2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 ++#define D3F2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 ++#define D3F2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 ++#define D3F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 ++#define D3F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 ++#define D3F2_PMI_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F2_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F2_PMI_CAP__VERSION_MASK 0x70000 ++#define D3F2_PMI_CAP__VERSION__SHIFT 0x10 ++#define D3F2_PMI_CAP__PME_CLOCK_MASK 0x80000 ++#define D3F2_PMI_CAP__PME_CLOCK__SHIFT 0x13 ++#define D3F2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 ++#define D3F2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 ++#define D3F2_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 ++#define D3F2_PMI_CAP__AUX_CURRENT__SHIFT 0x16 ++#define D3F2_PMI_CAP__D1_SUPPORT_MASK 0x2000000 ++#define D3F2_PMI_CAP__D1_SUPPORT__SHIFT 0x19 ++#define D3F2_PMI_CAP__D2_SUPPORT_MASK 0x4000000 ++#define D3F2_PMI_CAP__D2_SUPPORT__SHIFT 0x1a ++#define D3F2_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 ++#define D3F2_PMI_CAP__PME_SUPPORT__SHIFT 0x1b ++#define D3F2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 ++#define D3F2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 ++#define D3F2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 ++#define D3F2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 ++#define D3F2_PMI_STATUS_CNTL__PME_EN_MASK 0x100 ++#define D3F2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 ++#define D3F2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 ++#define D3F2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 ++#define D3F2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 ++#define D3F2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd ++#define D3F2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 ++#define D3F2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf ++#define D3F2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 ++#define D3F2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 ++#define D3F2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 ++#define D3F2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 ++#define D3F2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 ++#define D3F2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 ++#define D3F2_PCIE_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F2_PCIE_CAP__VERSION_MASK 0xf0000 ++#define D3F2_PCIE_CAP__VERSION__SHIFT 0x10 ++#define D3F2_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 ++#define D3F2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 ++#define D3F2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 ++#define D3F2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 ++#define D3F2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 ++#define D3F2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 ++#define D3F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 ++#define D3F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 ++#define D3F2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 ++#define D3F2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 ++#define D3F2_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 ++#define D3F2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 ++#define D3F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 ++#define D3F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 ++#define D3F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 ++#define D3F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 ++#define D3F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 ++#define D3F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf ++#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 ++#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 ++#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 ++#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a ++#define D3F2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 ++#define D3F2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c ++#define D3F2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 ++#define D3F2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 ++#define D3F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 ++#define D3F2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 ++#define D3F2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 ++#define D3F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 ++#define D3F2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 ++#define D3F2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 ++#define D3F2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 ++#define D3F2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 ++#define D3F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 ++#define D3F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 ++#define D3F2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 ++#define D3F2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 ++#define D3F2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 ++#define D3F2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 ++#define D3F2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 ++#define D3F2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa ++#define D3F2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 ++#define D3F2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb ++#define D3F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 ++#define D3F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc ++#define D3F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 ++#define D3F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf ++#define D3F2_DEVICE_STATUS__CORR_ERR_MASK 0x10000 ++#define D3F2_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 ++#define D3F2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 ++#define D3F2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 ++#define D3F2_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 ++#define D3F2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 ++#define D3F2_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 ++#define D3F2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 ++#define D3F2_DEVICE_STATUS__AUX_PWR_MASK 0x100000 ++#define D3F2_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 ++#define D3F2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 ++#define D3F2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 ++#define D3F2_LINK_CAP__LINK_SPEED_MASK 0xf ++#define D3F2_LINK_CAP__LINK_SPEED__SHIFT 0x0 ++#define D3F2_LINK_CAP__LINK_WIDTH_MASK 0x3f0 ++#define D3F2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 ++#define D3F2_LINK_CAP__PM_SUPPORT_MASK 0xc00 ++#define D3F2_LINK_CAP__PM_SUPPORT__SHIFT 0xa ++#define D3F2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 ++#define D3F2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc ++#define D3F2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 ++#define D3F2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf ++#define D3F2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 ++#define D3F2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 ++#define D3F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 ++#define D3F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 ++#define D3F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 ++#define D3F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 ++#define D3F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 ++#define D3F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 ++#define D3F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 ++#define D3F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 ++#define D3F2_LINK_CAP__PORT_NUMBER_MASK 0xff000000 ++#define D3F2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 ++#define D3F2_LINK_CNTL__PM_CONTROL_MASK 0x3 ++#define D3F2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 ++#define D3F2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 ++#define D3F2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 ++#define D3F2_LINK_CNTL__LINK_DIS_MASK 0x10 ++#define D3F2_LINK_CNTL__LINK_DIS__SHIFT 0x4 ++#define D3F2_LINK_CNTL__RETRAIN_LINK_MASK 0x20 ++#define D3F2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 ++#define D3F2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 ++#define D3F2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 ++#define D3F2_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 ++#define D3F2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 ++#define D3F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 ++#define D3F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 ++#define D3F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 ++#define D3F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 ++#define D3F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 ++#define D3F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa ++#define D3F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 ++#define D3F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb ++#define D3F2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 ++#define D3F2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 ++#define D3F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 ++#define D3F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 ++#define D3F2_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 ++#define D3F2_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b ++#define D3F2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 ++#define D3F2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c ++#define D3F2_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 ++#define D3F2_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d ++#define D3F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 ++#define D3F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e ++#define D3F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 ++#define D3F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f ++#define D3F2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 ++#define D3F2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 ++#define D3F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 ++#define D3F2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 ++#define D3F2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 ++#define D3F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 ++#define D3F2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 ++#define D3F2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 ++#define D3F2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 ++#define D3F2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 ++#define D3F2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 ++#define D3F2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 ++#define D3F2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 ++#define D3F2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 ++#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 ++#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 ++#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 ++#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf ++#define D3F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 ++#define D3F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 ++#define D3F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 ++#define D3F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 ++#define D3F2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 ++#define D3F2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 ++#define D3F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 ++#define D3F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 ++#define D3F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 ++#define D3F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 ++#define D3F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 ++#define D3F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 ++#define D3F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 ++#define D3F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 ++#define D3F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 ++#define D3F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 ++#define D3F2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 ++#define D3F2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 ++#define D3F2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 ++#define D3F2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 ++#define D3F2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 ++#define D3F2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 ++#define D3F2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 ++#define D3F2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa ++#define D3F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 ++#define D3F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb ++#define D3F2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 ++#define D3F2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc ++#define D3F2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 ++#define D3F2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 ++#define D3F2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 ++#define D3F2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 ++#define D3F2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 ++#define D3F2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 ++#define D3F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 ++#define D3F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 ++#define D3F2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 ++#define D3F2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 ++#define D3F2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 ++#define D3F2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 ++#define D3F2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 ++#define D3F2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 ++#define D3F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 ++#define D3F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 ++#define D3F2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 ++#define D3F2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 ++#define D3F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 ++#define D3F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 ++#define D3F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 ++#define D3F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 ++#define D3F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 ++#define D3F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 ++#define D3F2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 ++#define D3F2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 ++#define D3F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 ++#define D3F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 ++#define D3F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 ++#define D3F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 ++#define D3F2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff ++#define D3F2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 ++#define D3F2_ROOT_STATUS__PME_STATUS_MASK 0x10000 ++#define D3F2_ROOT_STATUS__PME_STATUS__SHIFT 0x10 ++#define D3F2_ROOT_STATUS__PME_PENDING_MASK 0x20000 ++#define D3F2_ROOT_STATUS__PME_PENDING__SHIFT 0x11 ++#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf ++#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 ++#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 ++#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 ++#define D3F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 ++#define D3F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 ++#define D3F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 ++#define D3F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 ++#define D3F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 ++#define D3F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 ++#define D3F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 ++#define D3F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 ++#define D3F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 ++#define D3F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 ++#define D3F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 ++#define D3F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa ++#define D3F2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 ++#define D3F2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb ++#define D3F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 ++#define D3F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc ++#define D3F2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 ++#define D3F2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 ++#define D3F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 ++#define D3F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 ++#define D3F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 ++#define D3F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 ++#define D3F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 ++#define D3F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 ++#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf ++#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 ++#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 ++#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 ++#define D3F2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 ++#define D3F2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 ++#define D3F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 ++#define D3F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 ++#define D3F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 ++#define D3F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 ++#define D3F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 ++#define D3F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 ++#define D3F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 ++#define D3F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 ++#define D3F2_DEVICE_CNTL2__LTR_EN_MASK 0x400 ++#define D3F2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa ++#define D3F2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 ++#define D3F2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd ++#define D3F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 ++#define D3F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf ++#define D3F2_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 ++#define D3F2_DEVICE_STATUS2__RESERVED__SHIFT 0x10 ++#define D3F2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe ++#define D3F2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 ++#define D3F2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 ++#define D3F2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 ++#define D3F2_LINK_CAP2__RESERVED_MASK 0xfffffe00 ++#define D3F2_LINK_CAP2__RESERVED__SHIFT 0x9 ++#define D3F2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf ++#define D3F2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 ++#define D3F2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 ++#define D3F2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 ++#define D3F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 ++#define D3F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 ++#define D3F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 ++#define D3F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 ++#define D3F2_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 ++#define D3F2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 ++#define D3F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 ++#define D3F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa ++#define D3F2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 ++#define D3F2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb ++#define D3F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 ++#define D3F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc ++#define D3F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 ++#define D3F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 ++#define D3F2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 ++#define D3F2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 ++#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 ++#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 ++#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 ++#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 ++#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 ++#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 ++#define D3F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 ++#define D3F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 ++#define D3F2_SLOT_CAP2__RESERVED_MASK 0xffffffff ++#define D3F2_SLOT_CAP2__RESERVED__SHIFT 0x0 ++#define D3F2_SLOT_CNTL2__RESERVED_MASK 0xffff ++#define D3F2_SLOT_CNTL2__RESERVED__SHIFT 0x0 ++#define D3F2_SLOT_STATUS2__RESERVED_MASK 0xffff0000 ++#define D3F2_SLOT_STATUS2__RESERVED__SHIFT 0x10 ++#define D3F2_MSI_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F2_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F2_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 ++#define D3F2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 ++#define D3F2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 ++#define D3F2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 ++#define D3F2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 ++#define D3F2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 ++#define D3F2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 ++#define D3F2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 ++#define D3F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 ++#define D3F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 ++#define D3F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc ++#define D3F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 ++#define D3F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff ++#define D3F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 ++#define D3F2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff ++#define D3F2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 ++#define D3F2_MSI_MSG_DATA__MSI_DATA_MASK 0xffff ++#define D3F2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 ++#define D3F2_SSID_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F2_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff ++#define D3F2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define D3F2_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 ++#define D3F2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 ++#define D3F2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F2_MSI_MAP_CAP__EN_MASK 0x10000 ++#define D3F2_MSI_MAP_CAP__EN__SHIFT 0x10 ++#define D3F2_MSI_MAP_CAP__FIXD_MASK 0x20000 ++#define D3F2_MSI_MAP_CAP__FIXD__SHIFT 0x11 ++#define D3F2_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 ++#define D3F2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b ++#define D3F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 ++#define D3F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 ++#define D3F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff ++#define D3F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 ++#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff ++#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 ++#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 ++#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 ++#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 ++#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 ++#define D3F2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff ++#define D3F2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 ++#define D3F2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff ++#define D3F2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 ++#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 ++#define D3F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 ++#define D3F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 ++#define D3F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 ++#define D3F2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 ++#define D3F2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 ++#define D3F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 ++#define D3F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa ++#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff ++#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 ++#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 ++#define D3F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 ++#define D3F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe ++#define D3F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 ++#define D3F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D3F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D3F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D3F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D3F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D3F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D3F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D3F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D3F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D3F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D3F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D3F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D3F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D3F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D3F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D3F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D3F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D3F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D3F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D3F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D3F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff ++#define D3F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 ++#define D3F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff ++#define D3F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 ++#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc ++#define D3F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd ++#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe ++#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf ++#define D3F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 ++#define D3F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 ++#define D3F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 ++#define D3F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 ++#define D3F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 ++#define D3F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 ++#define D3F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc ++#define D3F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd ++#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe ++#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf ++#define D3F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 ++#define D3F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 ++#define D3F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 ++#define D3F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 ++#define D3F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 ++#define D3F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 ++#define D3F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 ++#define D3F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 ++#define D3F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 ++#define D3F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 ++#define D3F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 ++#define D3F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 ++#define D3F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 ++#define D3F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 ++#define D3F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 ++#define D3F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 ++#define D3F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 ++#define D3F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 ++#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 ++#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 ++#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 ++#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc ++#define D3F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 ++#define D3F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd ++#define D3F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 ++#define D3F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe ++#define D3F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 ++#define D3F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf ++#define D3F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 ++#define D3F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 ++#define D3F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 ++#define D3F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 ++#define D3F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 ++#define D3F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 ++#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 ++#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 ++#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 ++#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc ++#define D3F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 ++#define D3F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd ++#define D3F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 ++#define D3F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe ++#define D3F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 ++#define D3F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 ++#define D3F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb ++#define D3F2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff ++#define D3F2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 ++#define D3F2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff ++#define D3F2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 ++#define D3F2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff ++#define D3F2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 ++#define D3F2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff ++#define D3F2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 ++#define D3F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 ++#define D3F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 ++#define D3F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 ++#define D3F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 ++#define D3F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 ++#define D3F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 ++#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 ++#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 ++#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 ++#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 ++#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 ++#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 ++#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 ++#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 ++#define D3F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 ++#define D3F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 ++#define D3F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 ++#define D3F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 ++#define D3F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 ++#define D3F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 ++#define D3F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 ++#define D3F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b ++#define D3F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff ++#define D3F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 ++#define D3F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 ++#define D3F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 ++#define D3F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff ++#define D3F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 ++#define D3F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff ++#define D3F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 ++#define D3F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff ++#define D3F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 ++#define D3F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff ++#define D3F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 ++#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 ++#define D3F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 ++#define D3F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 ++#define D3F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 ++#define D3F2_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc ++#define D3F2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 ++#define D3F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff ++#define D3F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 ++#define D3F2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 ++#define D3F2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 ++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 ++#define D3F2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 ++#define D3F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 ++#define D3F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 ++#define D3F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 ++#define D3F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 ++#define D3F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 ++#define D3F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 ++#define D3F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 ++#define D3F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 ++#define D3F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 ++#define D3F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 ++#define D3F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 ++#define D3F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 ++#define D3F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 ++#define D3F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 ++#define D3F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 ++#define D3F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 ++#define D3F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 ++#define D3F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 ++#define D3F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 ++#define D3F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 ++#define D3F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 ++#define D3F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 ++#define D3F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 ++#define D3F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 ++#define D3F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 ++#define D3F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 ++#define D3F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 ++#define D3F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 ++#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f ++#define D3F2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 ++#define D3F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 ++#define D3F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf ++#define D3F2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 ++#define D3F2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 ++#define D3F2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 ++#define D3F2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f ++#define D3F2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f ++#define D3F2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 ++#define D3F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 ++#define D3F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc ++#define D3F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff ++#define D3F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 ++#define D3F2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff ++#define D3F2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 ++#define D3F2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff ++#define D3F2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 ++#define D3F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff ++#define D3F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 ++#define D3F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff ++#define D3F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 ++#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff ++#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 ++#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff ++#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 ++#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f ++#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 ++#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 ++#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 ++#define D3F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff ++#define D3F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 ++#define D3F3_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff ++#define D3F3_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 ++#define D3F3_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff ++#define D3F3_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 ++#define D3F3_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff ++#define D3F3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 ++#define D3F3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff ++#define D3F3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 ++#define D3F3_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define D3F3_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define D3F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define D3F3_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define D3F3_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define D3F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define D3F3_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define D3F3_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define D3F3_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define D3F3_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define D3F3_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define D3F3_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define D3F3_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define D3F3_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define D3F3_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define D3F3_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define D3F3_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define D3F3_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define D3F3_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define D3F3_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define D3F3_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define D3F3_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define D3F3_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define D3F3_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define D3F3_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define D3F3_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define D3F3_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define D3F3_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define D3F3_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define D3F3_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define D3F3_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define D3F3_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define D3F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 ++#define D3F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 ++#define D3F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 ++#define D3F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 ++#define D3F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 ++#define D3F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 ++#define D3F3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 ++#define D3F3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 ++#define D3F3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 ++#define D3F3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 ++#define D3F3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 ++#define D3F3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 ++#define D3F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 ++#define D3F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 ++#define D3F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 ++#define D3F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 ++#define D3F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 ++#define D3F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define D3F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 ++#define D3F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 ++#define D3F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 ++#define D3F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa ++#define D3F3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 ++#define D3F3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc ++#define D3F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 ++#define D3F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe ++#define D3F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 ++#define D3F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf ++#define D3F3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 ++#define D3F3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 ++#define D3F3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 ++#define D3F3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 ++#define D3F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 ++#define D3F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 ++#define D3F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 ++#define D3F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 ++#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 ++#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 ++#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 ++#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 ++#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 ++#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 ++#define D3F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff ++#define D3F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 ++#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 ++#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 ++#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 ++#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e ++#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 ++#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f ++#define D3F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff ++#define D3F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 ++#define D3F3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 ++#define D3F3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 ++#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 ++#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 ++#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 ++#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf ++#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 ++#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 ++#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff ++#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 ++#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 ++#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc ++#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff ++#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 ++#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 ++#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 ++#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff ++#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 ++#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 ++#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 ++#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff ++#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 ++#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 ++#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 ++#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff ++#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 ++#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 ++#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 ++#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff ++#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 ++#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 ++#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 ++#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff ++#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 ++#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 ++#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 ++#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 ++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 ++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 ++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 ++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 ++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 ++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 ++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 ++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 ++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 ++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 ++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 ++#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 ++#define D3F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 ++#define D3F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 ++#define D3F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e ++#define D3F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 ++#define D3F3_PCIE_FC_P__PD_CREDITS_MASK 0xff ++#define D3F3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 ++#define D3F3_PCIE_FC_P__PH_CREDITS_MASK 0xff00 ++#define D3F3_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 ++#define D3F3_PCIE_FC_NP__NPD_CREDITS_MASK 0xff ++#define D3F3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 ++#define D3F3_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 ++#define D3F3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 ++#define D3F3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff ++#define D3F3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 ++#define D3F3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 ++#define D3F3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 ++#define D3F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 ++#define D3F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 ++#define D3F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 ++#define D3F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 ++#define D3F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 ++#define D3F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 ++#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 ++#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 ++#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 ++#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 ++#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 ++#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 ++#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 ++#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 ++#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 ++#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 ++#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 ++#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb ++#define D3F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 ++#define D3F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe ++#define D3F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 ++#define D3F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf ++#define D3F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 ++#define D3F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 ++#define D3F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 ++#define D3F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 ++#define D3F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 ++#define D3F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc ++#define D3F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 ++#define D3F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd ++#define D3F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 ++#define D3F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe ++#define D3F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 ++#define D3F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf ++#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 ++#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 ++#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 ++#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 ++#define D3F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 ++#define D3F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 ++#define D3F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 ++#define D3F3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 ++#define D3F3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a ++#define D3F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 ++#define D3F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b ++#define D3F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff ++#define D3F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 ++#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff ++#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 ++#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 ++#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 ++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 ++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 ++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 ++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 ++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 ++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 ++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 ++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 ++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 ++#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 ++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff ++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 ++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 ++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 ++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff ++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 ++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 ++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 ++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff ++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 ++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 ++#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 ++#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 ++#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 ++#define D3F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 ++#define D3F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 ++#define D3F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 ++#define D3F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 ++#define D3F3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 ++#define D3F3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 ++#define D3F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 ++#define D3F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 ++#define D3F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 ++#define D3F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 ++#define D3F3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 ++#define D3F3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc ++#define D3F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 ++#define D3F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 ++#define D3F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 ++#define D3F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 ++#define D3F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 ++#define D3F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 ++#define D3F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 ++#define D3F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 ++#define D3F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 ++#define D3F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 ++#define D3F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 ++#define D3F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 ++#define D3F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 ++#define D3F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 ++#define D3F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 ++#define D3F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 ++#define D3F3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 ++#define D3F3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 ++#define D3F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 ++#define D3F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b ++#define D3F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 ++#define D3F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c ++#define D3F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 ++#define D3F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d ++#define D3F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 ++#define D3F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e ++#define D3F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 ++#define D3F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f ++#define D3F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f ++#define D3F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 ++#define D3F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 ++#define D3F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 ++#define D3F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 ++#define D3F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 ++#define D3F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 ++#define D3F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 ++#define D3F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 ++#define D3F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 ++#define D3F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 ++#define D3F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa ++#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 ++#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb ++#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 ++#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc ++#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 ++#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd ++#define D3F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 ++#define D3F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe ++#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 ++#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 ++#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 ++#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 ++#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 ++#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 ++#define D3F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 ++#define D3F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 ++#define D3F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 ++#define D3F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 ++#define D3F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 ++#define D3F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 ++#define D3F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 ++#define D3F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 ++#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 ++#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 ++#define D3F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 ++#define D3F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 ++#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 ++#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a ++#define D3F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 ++#define D3F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b ++#define D3F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 ++#define D3F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c ++#define D3F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 ++#define D3F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d ++#define D3F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 ++#define D3F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f ++#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 ++#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 ++#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 ++#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 ++#define D3F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 ++#define D3F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 ++#define D3F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 ++#define D3F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 ++#define D3F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 ++#define D3F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 ++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 ++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 ++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 ++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 ++#define D3F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 ++#define D3F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 ++#define D3F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 ++#define D3F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa ++#define D3F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 ++#define D3F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb ++#define D3F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 ++#define D3F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc ++#define D3F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 ++#define D3F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe ++#define D3F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 ++#define D3F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 ++#define D3F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 ++#define D3F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 ++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 ++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 ++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 ++#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 ++#define D3F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 ++#define D3F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 ++#define D3F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 ++#define D3F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 ++#define D3F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 ++#define D3F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 ++#define D3F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 ++#define D3F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 ++#define D3F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 ++#define D3F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a ++#define D3F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 ++#define D3F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e ++#define D3F3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 ++#define D3F3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f ++#define D3F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 ++#define D3F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 ++#define D3F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 ++#define D3F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 ++#define D3F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 ++#define D3F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 ++#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 ++#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 ++#define D3F3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 ++#define D3F3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 ++#define D3F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 ++#define D3F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 ++#define D3F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 ++#define D3F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 ++#define D3F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 ++#define D3F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 ++#define D3F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 ++#define D3F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa ++#define D3F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 ++#define D3F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb ++#define D3F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 ++#define D3F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc ++#define D3F3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 ++#define D3F3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd ++#define D3F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 ++#define D3F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe ++#define D3F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 ++#define D3F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf ++#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 ++#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 ++#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 ++#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 ++#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 ++#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 ++#define D3F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 ++#define D3F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 ++#define D3F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 ++#define D3F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 ++#define D3F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 ++#define D3F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 ++#define D3F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 ++#define D3F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 ++#define D3F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 ++#define D3F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a ++#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f ++#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 ++#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 ++#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 ++#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 ++#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc ++#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 ++#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 ++#define D3F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 ++#define D3F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 ++#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 ++#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 ++#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 ++#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 ++#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 ++#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 ++#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 ++#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 ++#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d ++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff ++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 ++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 ++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 ++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 ++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 ++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 ++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 ++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 ++#define D3F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 ++#define D3F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f ++#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff ++#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 ++#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 ++#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc ++#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 ++#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 ++#define D3F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff ++#define D3F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 ++#define D3F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 ++#define D3F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 ++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 ++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 ++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e ++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 ++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 ++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 ++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 ++#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd ++#define D3F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 ++#define D3F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 ++#define D3F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 ++#define D3F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 ++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf ++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 ++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 ++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 ++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 ++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa ++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 ++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 ++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 ++#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 ++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 ++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 ++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e ++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 ++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 ++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 ++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 ++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd ++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 ++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 ++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 ++#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 ++#define D3F3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f ++#define D3F3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 ++#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 ++#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 ++#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 ++#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 ++#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 ++#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 ++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f ++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 ++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 ++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 ++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 ++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 ++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 ++#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 ++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f ++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 ++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 ++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 ++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 ++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 ++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 ++#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 ++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f ++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 ++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 ++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 ++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 ++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 ++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 ++#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 ++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f ++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 ++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 ++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 ++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 ++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 ++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 ++#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 ++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f ++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 ++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 ++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 ++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 ++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 ++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 ++#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 ++#define D3F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 ++#define D3F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 ++#define D3F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc ++#define D3F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 ++#define D3F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 ++#define D3F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 ++#define D3F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 ++#define D3F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 ++#define D3F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 ++#define D3F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 ++#define D3F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 ++#define D3F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb ++#define D3F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 ++#define D3F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc ++#define D3F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 ++#define D3F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd ++#define D3F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 ++#define D3F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe ++#define D3F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 ++#define D3F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf ++#define D3F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 ++#define D3F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 ++#define D3F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 ++#define D3F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 ++#define D3F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 ++#define D3F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 ++#define D3F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 ++#define D3F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 ++#define D3F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 ++#define D3F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 ++#define D3F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 ++#define D3F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 ++#define D3F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 ++#define D3F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 ++#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 ++#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 ++#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 ++#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 ++#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 ++#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 ++#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 ++#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 ++#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 ++#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 ++#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 ++#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 ++#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 ++#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 ++#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 ++#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 ++#define D3F3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 ++#define D3F3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 ++#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 ++#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 ++#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 ++#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 ++#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 ++#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa ++#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 ++#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb ++#define D3F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 ++#define D3F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf ++#define D3F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 ++#define D3F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 ++#define D3F3_VENDOR_ID__VENDOR_ID_MASK 0xffff ++#define D3F3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 ++#define D3F3_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 ++#define D3F3_DEVICE_ID__DEVICE_ID__SHIFT 0x10 ++#define D3F3_COMMAND__IO_ACCESS_EN_MASK 0x1 ++#define D3F3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 ++#define D3F3_COMMAND__MEM_ACCESS_EN_MASK 0x2 ++#define D3F3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 ++#define D3F3_COMMAND__BUS_MASTER_EN_MASK 0x4 ++#define D3F3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 ++#define D3F3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 ++#define D3F3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 ++#define D3F3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 ++#define D3F3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 ++#define D3F3_COMMAND__PAL_SNOOP_EN_MASK 0x20 ++#define D3F3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 ++#define D3F3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 ++#define D3F3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 ++#define D3F3_COMMAND__AD_STEPPING_MASK 0x80 ++#define D3F3_COMMAND__AD_STEPPING__SHIFT 0x7 ++#define D3F3_COMMAND__SERR_EN_MASK 0x100 ++#define D3F3_COMMAND__SERR_EN__SHIFT 0x8 ++#define D3F3_COMMAND__FAST_B2B_EN_MASK 0x200 ++#define D3F3_COMMAND__FAST_B2B_EN__SHIFT 0x9 ++#define D3F3_COMMAND__INT_DIS_MASK 0x400 ++#define D3F3_COMMAND__INT_DIS__SHIFT 0xa ++#define D3F3_STATUS__INT_STATUS_MASK 0x80000 ++#define D3F3_STATUS__INT_STATUS__SHIFT 0x13 ++#define D3F3_STATUS__CAP_LIST_MASK 0x100000 ++#define D3F3_STATUS__CAP_LIST__SHIFT 0x14 ++#define D3F3_STATUS__PCI_66_EN_MASK 0x200000 ++#define D3F3_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D3F3_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D3F3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D3F3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D3F3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D3F3_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D3F3_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D3F3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D3F3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D3F3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D3F3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D3F3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D3F3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D3F3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 ++#define D3F3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e ++#define D3F3_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D3F3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D3F3_REVISION_ID__MINOR_REV_ID_MASK 0xf ++#define D3F3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 ++#define D3F3_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 ++#define D3F3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 ++#define D3F3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 ++#define D3F3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 ++#define D3F3_SUB_CLASS__SUB_CLASS_MASK 0xff0000 ++#define D3F3_SUB_CLASS__SUB_CLASS__SHIFT 0x10 ++#define D3F3_BASE_CLASS__BASE_CLASS_MASK 0xff000000 ++#define D3F3_BASE_CLASS__BASE_CLASS__SHIFT 0x18 ++#define D3F3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff ++#define D3F3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 ++#define D3F3_LATENCY__LATENCY_TIMER_MASK 0xff00 ++#define D3F3_LATENCY__LATENCY_TIMER__SHIFT 0x8 ++#define D3F3_HEADER__HEADER_TYPE_MASK 0x7f0000 ++#define D3F3_HEADER__HEADER_TYPE__SHIFT 0x10 ++#define D3F3_HEADER__DEVICE_TYPE_MASK 0x800000 ++#define D3F3_HEADER__DEVICE_TYPE__SHIFT 0x17 ++#define D3F3_BIST__BIST_COMP_MASK 0xf000000 ++#define D3F3_BIST__BIST_COMP__SHIFT 0x18 ++#define D3F3_BIST__BIST_STRT_MASK 0x40000000 ++#define D3F3_BIST__BIST_STRT__SHIFT 0x1e ++#define D3F3_BIST__BIST_CAP_MASK 0x80000000 ++#define D3F3_BIST__BIST_CAP__SHIFT 0x1f ++#define D3F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff ++#define D3F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 ++#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 ++#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 ++#define D3F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 ++#define D3F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 ++#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 ++#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 ++#define D3F3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf ++#define D3F3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 ++#define D3F3_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 ++#define D3F3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 ++#define D3F3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 ++#define D3F3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 ++#define D3F3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 ++#define D3F3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc ++#define D3F3_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 ++#define D3F3_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 ++#define D3F3_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 ++#define D3F3_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D3F3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D3F3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D3F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D3F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D3F3_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D3F3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D3F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D3F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D3F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D3F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D3F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D3F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D3F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 ++#define D3F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e ++#define D3F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D3F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D3F3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf ++#define D3F3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 ++#define D3F3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 ++#define D3F3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 ++#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 ++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf ++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 ++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 ++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 ++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 ++#define D3F3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff ++#define D3F3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 ++#define D3F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff ++#define D3F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 ++#define D3F3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff ++#define D3F3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 ++#define D3F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 ++#define D3F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 ++#define D3F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 ++#define D3F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 ++#define D3F3_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 ++#define D3F3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 ++#define D3F3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 ++#define D3F3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 ++#define D3F3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 ++#define D3F3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 ++#define D3F3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 ++#define D3F3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 ++#define D3F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 ++#define D3F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 ++#define D3F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 ++#define D3F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 ++#define D3F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 ++#define D3F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 ++#define D3F3_CAP_PTR__CAP_PTR_MASK 0xff ++#define D3F3_CAP_PTR__CAP_PTR__SHIFT 0x0 ++#define D3F3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff ++#define D3F3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 ++#define D3F3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 ++#define D3F3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 ++#define D3F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 ++#define D3F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 ++#define D3F3_PMI_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F3_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F3_PMI_CAP__VERSION_MASK 0x70000 ++#define D3F3_PMI_CAP__VERSION__SHIFT 0x10 ++#define D3F3_PMI_CAP__PME_CLOCK_MASK 0x80000 ++#define D3F3_PMI_CAP__PME_CLOCK__SHIFT 0x13 ++#define D3F3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 ++#define D3F3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 ++#define D3F3_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 ++#define D3F3_PMI_CAP__AUX_CURRENT__SHIFT 0x16 ++#define D3F3_PMI_CAP__D1_SUPPORT_MASK 0x2000000 ++#define D3F3_PMI_CAP__D1_SUPPORT__SHIFT 0x19 ++#define D3F3_PMI_CAP__D2_SUPPORT_MASK 0x4000000 ++#define D3F3_PMI_CAP__D2_SUPPORT__SHIFT 0x1a ++#define D3F3_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 ++#define D3F3_PMI_CAP__PME_SUPPORT__SHIFT 0x1b ++#define D3F3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 ++#define D3F3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 ++#define D3F3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 ++#define D3F3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 ++#define D3F3_PMI_STATUS_CNTL__PME_EN_MASK 0x100 ++#define D3F3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 ++#define D3F3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 ++#define D3F3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 ++#define D3F3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 ++#define D3F3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd ++#define D3F3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 ++#define D3F3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf ++#define D3F3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 ++#define D3F3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 ++#define D3F3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 ++#define D3F3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 ++#define D3F3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 ++#define D3F3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 ++#define D3F3_PCIE_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F3_PCIE_CAP__VERSION_MASK 0xf0000 ++#define D3F3_PCIE_CAP__VERSION__SHIFT 0x10 ++#define D3F3_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 ++#define D3F3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 ++#define D3F3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 ++#define D3F3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 ++#define D3F3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 ++#define D3F3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 ++#define D3F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 ++#define D3F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 ++#define D3F3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 ++#define D3F3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 ++#define D3F3_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 ++#define D3F3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 ++#define D3F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 ++#define D3F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 ++#define D3F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 ++#define D3F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 ++#define D3F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 ++#define D3F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf ++#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 ++#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 ++#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 ++#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a ++#define D3F3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 ++#define D3F3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c ++#define D3F3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 ++#define D3F3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 ++#define D3F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 ++#define D3F3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 ++#define D3F3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 ++#define D3F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 ++#define D3F3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 ++#define D3F3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 ++#define D3F3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 ++#define D3F3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 ++#define D3F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 ++#define D3F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 ++#define D3F3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 ++#define D3F3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 ++#define D3F3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 ++#define D3F3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 ++#define D3F3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 ++#define D3F3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa ++#define D3F3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 ++#define D3F3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb ++#define D3F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 ++#define D3F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc ++#define D3F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 ++#define D3F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf ++#define D3F3_DEVICE_STATUS__CORR_ERR_MASK 0x10000 ++#define D3F3_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 ++#define D3F3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 ++#define D3F3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 ++#define D3F3_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 ++#define D3F3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 ++#define D3F3_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 ++#define D3F3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 ++#define D3F3_DEVICE_STATUS__AUX_PWR_MASK 0x100000 ++#define D3F3_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 ++#define D3F3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 ++#define D3F3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 ++#define D3F3_LINK_CAP__LINK_SPEED_MASK 0xf ++#define D3F3_LINK_CAP__LINK_SPEED__SHIFT 0x0 ++#define D3F3_LINK_CAP__LINK_WIDTH_MASK 0x3f0 ++#define D3F3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 ++#define D3F3_LINK_CAP__PM_SUPPORT_MASK 0xc00 ++#define D3F3_LINK_CAP__PM_SUPPORT__SHIFT 0xa ++#define D3F3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 ++#define D3F3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc ++#define D3F3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 ++#define D3F3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf ++#define D3F3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 ++#define D3F3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 ++#define D3F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 ++#define D3F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 ++#define D3F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 ++#define D3F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 ++#define D3F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 ++#define D3F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 ++#define D3F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 ++#define D3F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 ++#define D3F3_LINK_CAP__PORT_NUMBER_MASK 0xff000000 ++#define D3F3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 ++#define D3F3_LINK_CNTL__PM_CONTROL_MASK 0x3 ++#define D3F3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 ++#define D3F3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 ++#define D3F3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 ++#define D3F3_LINK_CNTL__LINK_DIS_MASK 0x10 ++#define D3F3_LINK_CNTL__LINK_DIS__SHIFT 0x4 ++#define D3F3_LINK_CNTL__RETRAIN_LINK_MASK 0x20 ++#define D3F3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 ++#define D3F3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 ++#define D3F3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 ++#define D3F3_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 ++#define D3F3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 ++#define D3F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 ++#define D3F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 ++#define D3F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 ++#define D3F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 ++#define D3F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 ++#define D3F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa ++#define D3F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 ++#define D3F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb ++#define D3F3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 ++#define D3F3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 ++#define D3F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 ++#define D3F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 ++#define D3F3_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 ++#define D3F3_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b ++#define D3F3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 ++#define D3F3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c ++#define D3F3_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 ++#define D3F3_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d ++#define D3F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 ++#define D3F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e ++#define D3F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 ++#define D3F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f ++#define D3F3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 ++#define D3F3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 ++#define D3F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 ++#define D3F3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 ++#define D3F3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 ++#define D3F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 ++#define D3F3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 ++#define D3F3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 ++#define D3F3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 ++#define D3F3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 ++#define D3F3_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 ++#define D3F3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 ++#define D3F3_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 ++#define D3F3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 ++#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 ++#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 ++#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 ++#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf ++#define D3F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 ++#define D3F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 ++#define D3F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 ++#define D3F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 ++#define D3F3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 ++#define D3F3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 ++#define D3F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 ++#define D3F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 ++#define D3F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 ++#define D3F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 ++#define D3F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 ++#define D3F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 ++#define D3F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 ++#define D3F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 ++#define D3F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 ++#define D3F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 ++#define D3F3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 ++#define D3F3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 ++#define D3F3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 ++#define D3F3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 ++#define D3F3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 ++#define D3F3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 ++#define D3F3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 ++#define D3F3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa ++#define D3F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 ++#define D3F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb ++#define D3F3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 ++#define D3F3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc ++#define D3F3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 ++#define D3F3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 ++#define D3F3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 ++#define D3F3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 ++#define D3F3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 ++#define D3F3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 ++#define D3F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 ++#define D3F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 ++#define D3F3_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 ++#define D3F3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 ++#define D3F3_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 ++#define D3F3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 ++#define D3F3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 ++#define D3F3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 ++#define D3F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 ++#define D3F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 ++#define D3F3_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 ++#define D3F3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 ++#define D3F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 ++#define D3F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 ++#define D3F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 ++#define D3F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 ++#define D3F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 ++#define D3F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 ++#define D3F3_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 ++#define D3F3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 ++#define D3F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 ++#define D3F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 ++#define D3F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 ++#define D3F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 ++#define D3F3_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff ++#define D3F3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 ++#define D3F3_ROOT_STATUS__PME_STATUS_MASK 0x10000 ++#define D3F3_ROOT_STATUS__PME_STATUS__SHIFT 0x10 ++#define D3F3_ROOT_STATUS__PME_PENDING_MASK 0x20000 ++#define D3F3_ROOT_STATUS__PME_PENDING__SHIFT 0x11 ++#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf ++#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 ++#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 ++#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 ++#define D3F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 ++#define D3F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 ++#define D3F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 ++#define D3F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 ++#define D3F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 ++#define D3F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 ++#define D3F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 ++#define D3F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 ++#define D3F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 ++#define D3F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 ++#define D3F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 ++#define D3F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa ++#define D3F3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 ++#define D3F3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb ++#define D3F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 ++#define D3F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc ++#define D3F3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 ++#define D3F3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 ++#define D3F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 ++#define D3F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 ++#define D3F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 ++#define D3F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 ++#define D3F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 ++#define D3F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 ++#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf ++#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 ++#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 ++#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 ++#define D3F3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 ++#define D3F3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 ++#define D3F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 ++#define D3F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 ++#define D3F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 ++#define D3F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 ++#define D3F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 ++#define D3F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 ++#define D3F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 ++#define D3F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 ++#define D3F3_DEVICE_CNTL2__LTR_EN_MASK 0x400 ++#define D3F3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa ++#define D3F3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 ++#define D3F3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd ++#define D3F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 ++#define D3F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf ++#define D3F3_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 ++#define D3F3_DEVICE_STATUS2__RESERVED__SHIFT 0x10 ++#define D3F3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe ++#define D3F3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 ++#define D3F3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 ++#define D3F3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 ++#define D3F3_LINK_CAP2__RESERVED_MASK 0xfffffe00 ++#define D3F3_LINK_CAP2__RESERVED__SHIFT 0x9 ++#define D3F3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf ++#define D3F3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 ++#define D3F3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 ++#define D3F3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 ++#define D3F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 ++#define D3F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 ++#define D3F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 ++#define D3F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 ++#define D3F3_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 ++#define D3F3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 ++#define D3F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 ++#define D3F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa ++#define D3F3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 ++#define D3F3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb ++#define D3F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 ++#define D3F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc ++#define D3F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 ++#define D3F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 ++#define D3F3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 ++#define D3F3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 ++#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 ++#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 ++#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 ++#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 ++#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 ++#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 ++#define D3F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 ++#define D3F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 ++#define D3F3_SLOT_CAP2__RESERVED_MASK 0xffffffff ++#define D3F3_SLOT_CAP2__RESERVED__SHIFT 0x0 ++#define D3F3_SLOT_CNTL2__RESERVED_MASK 0xffff ++#define D3F3_SLOT_CNTL2__RESERVED__SHIFT 0x0 ++#define D3F3_SLOT_STATUS2__RESERVED_MASK 0xffff0000 ++#define D3F3_SLOT_STATUS2__RESERVED__SHIFT 0x10 ++#define D3F3_MSI_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F3_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F3_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 ++#define D3F3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 ++#define D3F3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 ++#define D3F3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 ++#define D3F3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 ++#define D3F3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 ++#define D3F3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 ++#define D3F3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 ++#define D3F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 ++#define D3F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 ++#define D3F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc ++#define D3F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 ++#define D3F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff ++#define D3F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 ++#define D3F3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff ++#define D3F3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 ++#define D3F3_MSI_MSG_DATA__MSI_DATA_MASK 0xffff ++#define D3F3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 ++#define D3F3_SSID_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F3_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F3_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F3_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff ++#define D3F3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define D3F3_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 ++#define D3F3_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 ++#define D3F3_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F3_MSI_MAP_CAP__EN_MASK 0x10000 ++#define D3F3_MSI_MAP_CAP__EN__SHIFT 0x10 ++#define D3F3_MSI_MAP_CAP__FIXD_MASK 0x20000 ++#define D3F3_MSI_MAP_CAP__FIXD__SHIFT 0x11 ++#define D3F3_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 ++#define D3F3_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b ++#define D3F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 ++#define D3F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 ++#define D3F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff ++#define D3F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 ++#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff ++#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 ++#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 ++#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 ++#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 ++#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 ++#define D3F3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff ++#define D3F3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 ++#define D3F3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff ++#define D3F3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 ++#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 ++#define D3F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 ++#define D3F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 ++#define D3F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 ++#define D3F3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 ++#define D3F3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 ++#define D3F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 ++#define D3F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa ++#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff ++#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 ++#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 ++#define D3F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 ++#define D3F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe ++#define D3F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 ++#define D3F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D3F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D3F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D3F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D3F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D3F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D3F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D3F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D3F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D3F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D3F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D3F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D3F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D3F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D3F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D3F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D3F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D3F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D3F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D3F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D3F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff ++#define D3F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 ++#define D3F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff ++#define D3F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 ++#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc ++#define D3F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd ++#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe ++#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf ++#define D3F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 ++#define D3F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 ++#define D3F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 ++#define D3F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 ++#define D3F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 ++#define D3F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 ++#define D3F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc ++#define D3F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd ++#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe ++#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf ++#define D3F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 ++#define D3F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 ++#define D3F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 ++#define D3F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 ++#define D3F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 ++#define D3F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 ++#define D3F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 ++#define D3F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 ++#define D3F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 ++#define D3F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 ++#define D3F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 ++#define D3F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 ++#define D3F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 ++#define D3F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 ++#define D3F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 ++#define D3F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 ++#define D3F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 ++#define D3F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 ++#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 ++#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 ++#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 ++#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc ++#define D3F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 ++#define D3F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd ++#define D3F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 ++#define D3F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe ++#define D3F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 ++#define D3F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf ++#define D3F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 ++#define D3F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 ++#define D3F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 ++#define D3F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 ++#define D3F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 ++#define D3F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 ++#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 ++#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 ++#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 ++#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc ++#define D3F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 ++#define D3F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd ++#define D3F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 ++#define D3F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe ++#define D3F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 ++#define D3F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 ++#define D3F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb ++#define D3F3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff ++#define D3F3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 ++#define D3F3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff ++#define D3F3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 ++#define D3F3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff ++#define D3F3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 ++#define D3F3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff ++#define D3F3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 ++#define D3F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 ++#define D3F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 ++#define D3F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 ++#define D3F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 ++#define D3F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 ++#define D3F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 ++#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 ++#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 ++#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 ++#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 ++#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 ++#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 ++#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 ++#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 ++#define D3F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 ++#define D3F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 ++#define D3F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 ++#define D3F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 ++#define D3F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 ++#define D3F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 ++#define D3F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 ++#define D3F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b ++#define D3F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff ++#define D3F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 ++#define D3F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 ++#define D3F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 ++#define D3F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff ++#define D3F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 ++#define D3F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff ++#define D3F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 ++#define D3F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff ++#define D3F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 ++#define D3F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff ++#define D3F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 ++#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 ++#define D3F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 ++#define D3F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 ++#define D3F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 ++#define D3F3_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc ++#define D3F3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 ++#define D3F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff ++#define D3F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 ++#define D3F3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 ++#define D3F3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 ++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 ++#define D3F3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 ++#define D3F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 ++#define D3F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 ++#define D3F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 ++#define D3F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 ++#define D3F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 ++#define D3F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 ++#define D3F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 ++#define D3F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 ++#define D3F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 ++#define D3F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 ++#define D3F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 ++#define D3F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 ++#define D3F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 ++#define D3F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 ++#define D3F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 ++#define D3F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 ++#define D3F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 ++#define D3F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 ++#define D3F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 ++#define D3F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 ++#define D3F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 ++#define D3F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 ++#define D3F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 ++#define D3F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 ++#define D3F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 ++#define D3F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 ++#define D3F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 ++#define D3F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 ++#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f ++#define D3F3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 ++#define D3F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 ++#define D3F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf ++#define D3F3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 ++#define D3F3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 ++#define D3F3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 ++#define D3F3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f ++#define D3F3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f ++#define D3F3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 ++#define D3F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 ++#define D3F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc ++#define D3F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff ++#define D3F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 ++#define D3F3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff ++#define D3F3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 ++#define D3F3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff ++#define D3F3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 ++#define D3F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff ++#define D3F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 ++#define D3F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff ++#define D3F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 ++#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff ++#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 ++#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff ++#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 ++#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f ++#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 ++#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 ++#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 ++#define D3F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff ++#define D3F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 ++#define D3F4_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff ++#define D3F4_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 ++#define D3F4_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff ++#define D3F4_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 ++#define D3F4_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff ++#define D3F4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 ++#define D3F4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff ++#define D3F4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 ++#define D3F4_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define D3F4_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define D3F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define D3F4_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define D3F4_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define D3F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define D3F4_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define D3F4_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define D3F4_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define D3F4_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define D3F4_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define D3F4_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define D3F4_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define D3F4_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define D3F4_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define D3F4_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define D3F4_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define D3F4_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define D3F4_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define D3F4_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define D3F4_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define D3F4_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define D3F4_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define D3F4_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define D3F4_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define D3F4_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define D3F4_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define D3F4_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define D3F4_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define D3F4_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define D3F4_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define D3F4_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define D3F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 ++#define D3F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 ++#define D3F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 ++#define D3F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 ++#define D3F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 ++#define D3F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 ++#define D3F4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 ++#define D3F4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 ++#define D3F4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 ++#define D3F4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 ++#define D3F4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 ++#define D3F4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 ++#define D3F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 ++#define D3F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 ++#define D3F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 ++#define D3F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 ++#define D3F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 ++#define D3F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define D3F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 ++#define D3F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 ++#define D3F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 ++#define D3F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa ++#define D3F4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 ++#define D3F4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc ++#define D3F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 ++#define D3F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe ++#define D3F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 ++#define D3F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf ++#define D3F4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 ++#define D3F4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 ++#define D3F4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 ++#define D3F4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 ++#define D3F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 ++#define D3F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 ++#define D3F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 ++#define D3F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 ++#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 ++#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 ++#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 ++#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 ++#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 ++#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 ++#define D3F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff ++#define D3F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 ++#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 ++#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 ++#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 ++#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e ++#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 ++#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f ++#define D3F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff ++#define D3F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 ++#define D3F4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 ++#define D3F4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 ++#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 ++#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 ++#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 ++#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf ++#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 ++#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 ++#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff ++#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 ++#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 ++#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc ++#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff ++#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 ++#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 ++#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 ++#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff ++#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 ++#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 ++#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 ++#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff ++#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 ++#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 ++#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 ++#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff ++#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 ++#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 ++#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 ++#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff ++#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 ++#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 ++#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 ++#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff ++#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 ++#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 ++#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 ++#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 ++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 ++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 ++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 ++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 ++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 ++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 ++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 ++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 ++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 ++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 ++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 ++#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 ++#define D3F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 ++#define D3F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 ++#define D3F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e ++#define D3F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 ++#define D3F4_PCIE_FC_P__PD_CREDITS_MASK 0xff ++#define D3F4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 ++#define D3F4_PCIE_FC_P__PH_CREDITS_MASK 0xff00 ++#define D3F4_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 ++#define D3F4_PCIE_FC_NP__NPD_CREDITS_MASK 0xff ++#define D3F4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 ++#define D3F4_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 ++#define D3F4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 ++#define D3F4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff ++#define D3F4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 ++#define D3F4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 ++#define D3F4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 ++#define D3F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 ++#define D3F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 ++#define D3F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 ++#define D3F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 ++#define D3F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 ++#define D3F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 ++#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 ++#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 ++#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 ++#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 ++#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 ++#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 ++#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 ++#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 ++#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 ++#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 ++#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 ++#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb ++#define D3F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 ++#define D3F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe ++#define D3F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 ++#define D3F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf ++#define D3F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 ++#define D3F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 ++#define D3F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 ++#define D3F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 ++#define D3F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 ++#define D3F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc ++#define D3F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 ++#define D3F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd ++#define D3F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 ++#define D3F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe ++#define D3F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 ++#define D3F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf ++#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 ++#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 ++#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 ++#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 ++#define D3F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 ++#define D3F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 ++#define D3F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 ++#define D3F4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 ++#define D3F4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a ++#define D3F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 ++#define D3F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b ++#define D3F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff ++#define D3F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 ++#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff ++#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 ++#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 ++#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 ++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 ++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 ++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 ++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 ++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 ++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 ++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 ++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 ++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 ++#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 ++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff ++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 ++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 ++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 ++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff ++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 ++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 ++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 ++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff ++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 ++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 ++#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 ++#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 ++#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 ++#define D3F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 ++#define D3F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 ++#define D3F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 ++#define D3F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 ++#define D3F4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 ++#define D3F4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 ++#define D3F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 ++#define D3F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 ++#define D3F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 ++#define D3F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 ++#define D3F4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 ++#define D3F4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc ++#define D3F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 ++#define D3F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 ++#define D3F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 ++#define D3F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 ++#define D3F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 ++#define D3F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 ++#define D3F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 ++#define D3F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 ++#define D3F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 ++#define D3F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 ++#define D3F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 ++#define D3F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 ++#define D3F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 ++#define D3F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 ++#define D3F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 ++#define D3F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 ++#define D3F4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 ++#define D3F4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 ++#define D3F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 ++#define D3F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b ++#define D3F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 ++#define D3F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c ++#define D3F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 ++#define D3F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d ++#define D3F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 ++#define D3F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e ++#define D3F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 ++#define D3F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f ++#define D3F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f ++#define D3F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 ++#define D3F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 ++#define D3F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 ++#define D3F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 ++#define D3F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 ++#define D3F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 ++#define D3F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 ++#define D3F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 ++#define D3F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 ++#define D3F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 ++#define D3F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa ++#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 ++#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb ++#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 ++#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc ++#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 ++#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd ++#define D3F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 ++#define D3F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe ++#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 ++#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 ++#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 ++#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 ++#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 ++#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 ++#define D3F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 ++#define D3F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 ++#define D3F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 ++#define D3F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 ++#define D3F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 ++#define D3F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 ++#define D3F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 ++#define D3F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 ++#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 ++#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 ++#define D3F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 ++#define D3F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 ++#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 ++#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a ++#define D3F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 ++#define D3F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b ++#define D3F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 ++#define D3F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c ++#define D3F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 ++#define D3F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d ++#define D3F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 ++#define D3F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f ++#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 ++#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 ++#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 ++#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 ++#define D3F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 ++#define D3F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 ++#define D3F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 ++#define D3F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 ++#define D3F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 ++#define D3F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 ++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 ++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 ++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 ++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 ++#define D3F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 ++#define D3F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 ++#define D3F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 ++#define D3F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa ++#define D3F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 ++#define D3F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb ++#define D3F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 ++#define D3F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc ++#define D3F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 ++#define D3F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe ++#define D3F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 ++#define D3F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 ++#define D3F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 ++#define D3F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 ++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 ++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 ++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 ++#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 ++#define D3F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 ++#define D3F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 ++#define D3F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 ++#define D3F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 ++#define D3F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 ++#define D3F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 ++#define D3F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 ++#define D3F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 ++#define D3F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 ++#define D3F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a ++#define D3F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 ++#define D3F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e ++#define D3F4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 ++#define D3F4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f ++#define D3F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 ++#define D3F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 ++#define D3F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 ++#define D3F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 ++#define D3F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 ++#define D3F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 ++#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 ++#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 ++#define D3F4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 ++#define D3F4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 ++#define D3F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 ++#define D3F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 ++#define D3F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 ++#define D3F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 ++#define D3F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 ++#define D3F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 ++#define D3F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 ++#define D3F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa ++#define D3F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 ++#define D3F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb ++#define D3F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 ++#define D3F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc ++#define D3F4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 ++#define D3F4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd ++#define D3F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 ++#define D3F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe ++#define D3F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 ++#define D3F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf ++#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 ++#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 ++#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 ++#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 ++#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 ++#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 ++#define D3F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 ++#define D3F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 ++#define D3F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 ++#define D3F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 ++#define D3F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 ++#define D3F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 ++#define D3F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 ++#define D3F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 ++#define D3F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 ++#define D3F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a ++#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f ++#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 ++#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 ++#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 ++#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 ++#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc ++#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 ++#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 ++#define D3F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 ++#define D3F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 ++#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 ++#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 ++#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 ++#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 ++#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 ++#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 ++#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 ++#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 ++#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d ++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff ++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 ++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 ++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 ++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 ++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 ++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 ++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 ++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 ++#define D3F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 ++#define D3F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f ++#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff ++#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 ++#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 ++#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc ++#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 ++#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 ++#define D3F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff ++#define D3F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 ++#define D3F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 ++#define D3F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 ++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 ++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 ++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e ++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 ++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 ++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 ++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 ++#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd ++#define D3F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 ++#define D3F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 ++#define D3F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 ++#define D3F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 ++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf ++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 ++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 ++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 ++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 ++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa ++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 ++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 ++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 ++#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 ++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 ++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 ++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e ++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 ++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 ++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 ++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 ++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd ++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 ++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 ++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 ++#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 ++#define D3F4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f ++#define D3F4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 ++#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 ++#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 ++#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 ++#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 ++#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 ++#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 ++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f ++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 ++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 ++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 ++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 ++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 ++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 ++#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 ++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f ++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 ++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 ++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 ++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 ++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 ++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 ++#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 ++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f ++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 ++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 ++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 ++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 ++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 ++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 ++#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 ++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f ++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 ++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 ++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 ++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 ++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 ++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 ++#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 ++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f ++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 ++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 ++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 ++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 ++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 ++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 ++#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 ++#define D3F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 ++#define D3F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 ++#define D3F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc ++#define D3F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 ++#define D3F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 ++#define D3F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 ++#define D3F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 ++#define D3F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 ++#define D3F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 ++#define D3F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 ++#define D3F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 ++#define D3F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb ++#define D3F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 ++#define D3F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc ++#define D3F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 ++#define D3F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd ++#define D3F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 ++#define D3F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe ++#define D3F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 ++#define D3F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf ++#define D3F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 ++#define D3F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 ++#define D3F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 ++#define D3F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 ++#define D3F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 ++#define D3F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 ++#define D3F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 ++#define D3F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 ++#define D3F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 ++#define D3F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 ++#define D3F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 ++#define D3F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 ++#define D3F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 ++#define D3F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 ++#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 ++#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 ++#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 ++#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 ++#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 ++#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 ++#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 ++#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 ++#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 ++#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 ++#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 ++#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 ++#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 ++#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 ++#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 ++#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 ++#define D3F4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 ++#define D3F4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 ++#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 ++#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 ++#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 ++#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 ++#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 ++#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa ++#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 ++#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb ++#define D3F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 ++#define D3F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf ++#define D3F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 ++#define D3F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 ++#define D3F4_VENDOR_ID__VENDOR_ID_MASK 0xffff ++#define D3F4_VENDOR_ID__VENDOR_ID__SHIFT 0x0 ++#define D3F4_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 ++#define D3F4_DEVICE_ID__DEVICE_ID__SHIFT 0x10 ++#define D3F4_COMMAND__IO_ACCESS_EN_MASK 0x1 ++#define D3F4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 ++#define D3F4_COMMAND__MEM_ACCESS_EN_MASK 0x2 ++#define D3F4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 ++#define D3F4_COMMAND__BUS_MASTER_EN_MASK 0x4 ++#define D3F4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 ++#define D3F4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 ++#define D3F4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 ++#define D3F4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 ++#define D3F4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 ++#define D3F4_COMMAND__PAL_SNOOP_EN_MASK 0x20 ++#define D3F4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 ++#define D3F4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 ++#define D3F4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 ++#define D3F4_COMMAND__AD_STEPPING_MASK 0x80 ++#define D3F4_COMMAND__AD_STEPPING__SHIFT 0x7 ++#define D3F4_COMMAND__SERR_EN_MASK 0x100 ++#define D3F4_COMMAND__SERR_EN__SHIFT 0x8 ++#define D3F4_COMMAND__FAST_B2B_EN_MASK 0x200 ++#define D3F4_COMMAND__FAST_B2B_EN__SHIFT 0x9 ++#define D3F4_COMMAND__INT_DIS_MASK 0x400 ++#define D3F4_COMMAND__INT_DIS__SHIFT 0xa ++#define D3F4_STATUS__INT_STATUS_MASK 0x80000 ++#define D3F4_STATUS__INT_STATUS__SHIFT 0x13 ++#define D3F4_STATUS__CAP_LIST_MASK 0x100000 ++#define D3F4_STATUS__CAP_LIST__SHIFT 0x14 ++#define D3F4_STATUS__PCI_66_EN_MASK 0x200000 ++#define D3F4_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D3F4_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D3F4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D3F4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D3F4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D3F4_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D3F4_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D3F4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D3F4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D3F4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D3F4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D3F4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D3F4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D3F4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 ++#define D3F4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e ++#define D3F4_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D3F4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D3F4_REVISION_ID__MINOR_REV_ID_MASK 0xf ++#define D3F4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 ++#define D3F4_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 ++#define D3F4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 ++#define D3F4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 ++#define D3F4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 ++#define D3F4_SUB_CLASS__SUB_CLASS_MASK 0xff0000 ++#define D3F4_SUB_CLASS__SUB_CLASS__SHIFT 0x10 ++#define D3F4_BASE_CLASS__BASE_CLASS_MASK 0xff000000 ++#define D3F4_BASE_CLASS__BASE_CLASS__SHIFT 0x18 ++#define D3F4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff ++#define D3F4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 ++#define D3F4_LATENCY__LATENCY_TIMER_MASK 0xff00 ++#define D3F4_LATENCY__LATENCY_TIMER__SHIFT 0x8 ++#define D3F4_HEADER__HEADER_TYPE_MASK 0x7f0000 ++#define D3F4_HEADER__HEADER_TYPE__SHIFT 0x10 ++#define D3F4_HEADER__DEVICE_TYPE_MASK 0x800000 ++#define D3F4_HEADER__DEVICE_TYPE__SHIFT 0x17 ++#define D3F4_BIST__BIST_COMP_MASK 0xf000000 ++#define D3F4_BIST__BIST_COMP__SHIFT 0x18 ++#define D3F4_BIST__BIST_STRT_MASK 0x40000000 ++#define D3F4_BIST__BIST_STRT__SHIFT 0x1e ++#define D3F4_BIST__BIST_CAP_MASK 0x80000000 ++#define D3F4_BIST__BIST_CAP__SHIFT 0x1f ++#define D3F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff ++#define D3F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 ++#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 ++#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 ++#define D3F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 ++#define D3F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 ++#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 ++#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 ++#define D3F4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf ++#define D3F4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 ++#define D3F4_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 ++#define D3F4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 ++#define D3F4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 ++#define D3F4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 ++#define D3F4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 ++#define D3F4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc ++#define D3F4_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 ++#define D3F4_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 ++#define D3F4_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 ++#define D3F4_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D3F4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D3F4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D3F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D3F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D3F4_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D3F4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D3F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D3F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D3F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D3F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D3F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D3F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D3F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 ++#define D3F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e ++#define D3F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D3F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D3F4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf ++#define D3F4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 ++#define D3F4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 ++#define D3F4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 ++#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 ++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf ++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 ++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 ++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 ++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 ++#define D3F4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff ++#define D3F4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 ++#define D3F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff ++#define D3F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 ++#define D3F4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff ++#define D3F4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 ++#define D3F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 ++#define D3F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 ++#define D3F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 ++#define D3F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 ++#define D3F4_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 ++#define D3F4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 ++#define D3F4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 ++#define D3F4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 ++#define D3F4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 ++#define D3F4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 ++#define D3F4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 ++#define D3F4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 ++#define D3F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 ++#define D3F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 ++#define D3F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 ++#define D3F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 ++#define D3F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 ++#define D3F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 ++#define D3F4_CAP_PTR__CAP_PTR_MASK 0xff ++#define D3F4_CAP_PTR__CAP_PTR__SHIFT 0x0 ++#define D3F4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff ++#define D3F4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 ++#define D3F4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 ++#define D3F4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 ++#define D3F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 ++#define D3F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 ++#define D3F4_PMI_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F4_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F4_PMI_CAP__VERSION_MASK 0x70000 ++#define D3F4_PMI_CAP__VERSION__SHIFT 0x10 ++#define D3F4_PMI_CAP__PME_CLOCK_MASK 0x80000 ++#define D3F4_PMI_CAP__PME_CLOCK__SHIFT 0x13 ++#define D3F4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 ++#define D3F4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 ++#define D3F4_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 ++#define D3F4_PMI_CAP__AUX_CURRENT__SHIFT 0x16 ++#define D3F4_PMI_CAP__D1_SUPPORT_MASK 0x2000000 ++#define D3F4_PMI_CAP__D1_SUPPORT__SHIFT 0x19 ++#define D3F4_PMI_CAP__D2_SUPPORT_MASK 0x4000000 ++#define D3F4_PMI_CAP__D2_SUPPORT__SHIFT 0x1a ++#define D3F4_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 ++#define D3F4_PMI_CAP__PME_SUPPORT__SHIFT 0x1b ++#define D3F4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 ++#define D3F4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 ++#define D3F4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 ++#define D3F4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 ++#define D3F4_PMI_STATUS_CNTL__PME_EN_MASK 0x100 ++#define D3F4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 ++#define D3F4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 ++#define D3F4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 ++#define D3F4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 ++#define D3F4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd ++#define D3F4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 ++#define D3F4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf ++#define D3F4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 ++#define D3F4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 ++#define D3F4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 ++#define D3F4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 ++#define D3F4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 ++#define D3F4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 ++#define D3F4_PCIE_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F4_PCIE_CAP__VERSION_MASK 0xf0000 ++#define D3F4_PCIE_CAP__VERSION__SHIFT 0x10 ++#define D3F4_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 ++#define D3F4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 ++#define D3F4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 ++#define D3F4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 ++#define D3F4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 ++#define D3F4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 ++#define D3F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 ++#define D3F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 ++#define D3F4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 ++#define D3F4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 ++#define D3F4_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 ++#define D3F4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 ++#define D3F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 ++#define D3F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 ++#define D3F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 ++#define D3F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 ++#define D3F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 ++#define D3F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf ++#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 ++#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 ++#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 ++#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a ++#define D3F4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 ++#define D3F4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c ++#define D3F4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 ++#define D3F4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 ++#define D3F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 ++#define D3F4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 ++#define D3F4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 ++#define D3F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 ++#define D3F4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 ++#define D3F4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 ++#define D3F4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 ++#define D3F4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 ++#define D3F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 ++#define D3F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 ++#define D3F4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 ++#define D3F4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 ++#define D3F4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 ++#define D3F4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 ++#define D3F4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 ++#define D3F4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa ++#define D3F4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 ++#define D3F4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb ++#define D3F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 ++#define D3F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc ++#define D3F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 ++#define D3F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf ++#define D3F4_DEVICE_STATUS__CORR_ERR_MASK 0x10000 ++#define D3F4_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 ++#define D3F4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 ++#define D3F4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 ++#define D3F4_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 ++#define D3F4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 ++#define D3F4_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 ++#define D3F4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 ++#define D3F4_DEVICE_STATUS__AUX_PWR_MASK 0x100000 ++#define D3F4_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 ++#define D3F4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 ++#define D3F4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 ++#define D3F4_LINK_CAP__LINK_SPEED_MASK 0xf ++#define D3F4_LINK_CAP__LINK_SPEED__SHIFT 0x0 ++#define D3F4_LINK_CAP__LINK_WIDTH_MASK 0x3f0 ++#define D3F4_LINK_CAP__LINK_WIDTH__SHIFT 0x4 ++#define D3F4_LINK_CAP__PM_SUPPORT_MASK 0xc00 ++#define D3F4_LINK_CAP__PM_SUPPORT__SHIFT 0xa ++#define D3F4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 ++#define D3F4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc ++#define D3F4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 ++#define D3F4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf ++#define D3F4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 ++#define D3F4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 ++#define D3F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 ++#define D3F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 ++#define D3F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 ++#define D3F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 ++#define D3F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 ++#define D3F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 ++#define D3F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 ++#define D3F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 ++#define D3F4_LINK_CAP__PORT_NUMBER_MASK 0xff000000 ++#define D3F4_LINK_CAP__PORT_NUMBER__SHIFT 0x18 ++#define D3F4_LINK_CNTL__PM_CONTROL_MASK 0x3 ++#define D3F4_LINK_CNTL__PM_CONTROL__SHIFT 0x0 ++#define D3F4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 ++#define D3F4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 ++#define D3F4_LINK_CNTL__LINK_DIS_MASK 0x10 ++#define D3F4_LINK_CNTL__LINK_DIS__SHIFT 0x4 ++#define D3F4_LINK_CNTL__RETRAIN_LINK_MASK 0x20 ++#define D3F4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 ++#define D3F4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 ++#define D3F4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 ++#define D3F4_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 ++#define D3F4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 ++#define D3F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 ++#define D3F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 ++#define D3F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 ++#define D3F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 ++#define D3F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 ++#define D3F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa ++#define D3F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 ++#define D3F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb ++#define D3F4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 ++#define D3F4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 ++#define D3F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 ++#define D3F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 ++#define D3F4_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 ++#define D3F4_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b ++#define D3F4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 ++#define D3F4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c ++#define D3F4_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 ++#define D3F4_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d ++#define D3F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 ++#define D3F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e ++#define D3F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 ++#define D3F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f ++#define D3F4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 ++#define D3F4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 ++#define D3F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 ++#define D3F4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 ++#define D3F4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 ++#define D3F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 ++#define D3F4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 ++#define D3F4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 ++#define D3F4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 ++#define D3F4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 ++#define D3F4_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 ++#define D3F4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 ++#define D3F4_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 ++#define D3F4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 ++#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 ++#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 ++#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 ++#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf ++#define D3F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 ++#define D3F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 ++#define D3F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 ++#define D3F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 ++#define D3F4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 ++#define D3F4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 ++#define D3F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 ++#define D3F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 ++#define D3F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 ++#define D3F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 ++#define D3F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 ++#define D3F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 ++#define D3F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 ++#define D3F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 ++#define D3F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 ++#define D3F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 ++#define D3F4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 ++#define D3F4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 ++#define D3F4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 ++#define D3F4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 ++#define D3F4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 ++#define D3F4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 ++#define D3F4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 ++#define D3F4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa ++#define D3F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 ++#define D3F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb ++#define D3F4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 ++#define D3F4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc ++#define D3F4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 ++#define D3F4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 ++#define D3F4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 ++#define D3F4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 ++#define D3F4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 ++#define D3F4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 ++#define D3F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 ++#define D3F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 ++#define D3F4_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 ++#define D3F4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 ++#define D3F4_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 ++#define D3F4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 ++#define D3F4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 ++#define D3F4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 ++#define D3F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 ++#define D3F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 ++#define D3F4_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 ++#define D3F4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 ++#define D3F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 ++#define D3F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 ++#define D3F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 ++#define D3F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 ++#define D3F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 ++#define D3F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 ++#define D3F4_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 ++#define D3F4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 ++#define D3F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 ++#define D3F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 ++#define D3F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 ++#define D3F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 ++#define D3F4_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff ++#define D3F4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 ++#define D3F4_ROOT_STATUS__PME_STATUS_MASK 0x10000 ++#define D3F4_ROOT_STATUS__PME_STATUS__SHIFT 0x10 ++#define D3F4_ROOT_STATUS__PME_PENDING_MASK 0x20000 ++#define D3F4_ROOT_STATUS__PME_PENDING__SHIFT 0x11 ++#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf ++#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 ++#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 ++#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 ++#define D3F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 ++#define D3F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 ++#define D3F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 ++#define D3F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 ++#define D3F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 ++#define D3F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 ++#define D3F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 ++#define D3F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 ++#define D3F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 ++#define D3F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 ++#define D3F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 ++#define D3F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa ++#define D3F4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 ++#define D3F4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb ++#define D3F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 ++#define D3F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc ++#define D3F4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 ++#define D3F4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 ++#define D3F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 ++#define D3F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 ++#define D3F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 ++#define D3F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 ++#define D3F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 ++#define D3F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 ++#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf ++#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 ++#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 ++#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 ++#define D3F4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 ++#define D3F4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 ++#define D3F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 ++#define D3F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 ++#define D3F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 ++#define D3F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 ++#define D3F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 ++#define D3F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 ++#define D3F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 ++#define D3F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 ++#define D3F4_DEVICE_CNTL2__LTR_EN_MASK 0x400 ++#define D3F4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa ++#define D3F4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 ++#define D3F4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd ++#define D3F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 ++#define D3F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf ++#define D3F4_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 ++#define D3F4_DEVICE_STATUS2__RESERVED__SHIFT 0x10 ++#define D3F4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe ++#define D3F4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 ++#define D3F4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 ++#define D3F4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 ++#define D3F4_LINK_CAP2__RESERVED_MASK 0xfffffe00 ++#define D3F4_LINK_CAP2__RESERVED__SHIFT 0x9 ++#define D3F4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf ++#define D3F4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 ++#define D3F4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 ++#define D3F4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 ++#define D3F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 ++#define D3F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 ++#define D3F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 ++#define D3F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 ++#define D3F4_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 ++#define D3F4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 ++#define D3F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 ++#define D3F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa ++#define D3F4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 ++#define D3F4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb ++#define D3F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 ++#define D3F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc ++#define D3F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 ++#define D3F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 ++#define D3F4_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 ++#define D3F4_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 ++#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 ++#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 ++#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 ++#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 ++#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 ++#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 ++#define D3F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 ++#define D3F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 ++#define D3F4_SLOT_CAP2__RESERVED_MASK 0xffffffff ++#define D3F4_SLOT_CAP2__RESERVED__SHIFT 0x0 ++#define D3F4_SLOT_CNTL2__RESERVED_MASK 0xffff ++#define D3F4_SLOT_CNTL2__RESERVED__SHIFT 0x0 ++#define D3F4_SLOT_STATUS2__RESERVED_MASK 0xffff0000 ++#define D3F4_SLOT_STATUS2__RESERVED__SHIFT 0x10 ++#define D3F4_MSI_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F4_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F4_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 ++#define D3F4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 ++#define D3F4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 ++#define D3F4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 ++#define D3F4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 ++#define D3F4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 ++#define D3F4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 ++#define D3F4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 ++#define D3F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 ++#define D3F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 ++#define D3F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc ++#define D3F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 ++#define D3F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff ++#define D3F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 ++#define D3F4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff ++#define D3F4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 ++#define D3F4_MSI_MSG_DATA__MSI_DATA_MASK 0xffff ++#define D3F4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 ++#define D3F4_SSID_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F4_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F4_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F4_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff ++#define D3F4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define D3F4_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 ++#define D3F4_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 ++#define D3F4_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F4_MSI_MAP_CAP__EN_MASK 0x10000 ++#define D3F4_MSI_MAP_CAP__EN__SHIFT 0x10 ++#define D3F4_MSI_MAP_CAP__FIXD_MASK 0x20000 ++#define D3F4_MSI_MAP_CAP__FIXD__SHIFT 0x11 ++#define D3F4_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 ++#define D3F4_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b ++#define D3F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 ++#define D3F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 ++#define D3F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff ++#define D3F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 ++#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff ++#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 ++#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 ++#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 ++#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 ++#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 ++#define D3F4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff ++#define D3F4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 ++#define D3F4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff ++#define D3F4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 ++#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 ++#define D3F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 ++#define D3F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 ++#define D3F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 ++#define D3F4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 ++#define D3F4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 ++#define D3F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 ++#define D3F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa ++#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff ++#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 ++#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 ++#define D3F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 ++#define D3F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe ++#define D3F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 ++#define D3F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D3F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D3F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D3F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D3F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D3F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D3F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D3F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D3F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D3F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D3F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D3F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D3F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D3F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D3F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D3F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D3F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D3F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D3F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D3F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D3F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff ++#define D3F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 ++#define D3F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff ++#define D3F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 ++#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc ++#define D3F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd ++#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe ++#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf ++#define D3F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 ++#define D3F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 ++#define D3F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 ++#define D3F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 ++#define D3F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 ++#define D3F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 ++#define D3F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc ++#define D3F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd ++#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe ++#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf ++#define D3F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 ++#define D3F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 ++#define D3F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 ++#define D3F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 ++#define D3F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 ++#define D3F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 ++#define D3F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 ++#define D3F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 ++#define D3F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 ++#define D3F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 ++#define D3F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 ++#define D3F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 ++#define D3F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 ++#define D3F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 ++#define D3F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 ++#define D3F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 ++#define D3F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 ++#define D3F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 ++#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 ++#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 ++#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 ++#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc ++#define D3F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 ++#define D3F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd ++#define D3F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 ++#define D3F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe ++#define D3F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 ++#define D3F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf ++#define D3F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 ++#define D3F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 ++#define D3F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 ++#define D3F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 ++#define D3F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 ++#define D3F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 ++#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 ++#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 ++#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 ++#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc ++#define D3F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 ++#define D3F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd ++#define D3F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 ++#define D3F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe ++#define D3F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 ++#define D3F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 ++#define D3F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb ++#define D3F4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff ++#define D3F4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 ++#define D3F4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff ++#define D3F4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 ++#define D3F4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff ++#define D3F4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 ++#define D3F4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff ++#define D3F4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 ++#define D3F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 ++#define D3F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 ++#define D3F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 ++#define D3F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 ++#define D3F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 ++#define D3F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 ++#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 ++#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 ++#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 ++#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 ++#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 ++#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 ++#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 ++#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 ++#define D3F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 ++#define D3F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 ++#define D3F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 ++#define D3F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 ++#define D3F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 ++#define D3F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 ++#define D3F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 ++#define D3F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b ++#define D3F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff ++#define D3F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 ++#define D3F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 ++#define D3F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 ++#define D3F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff ++#define D3F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 ++#define D3F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff ++#define D3F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 ++#define D3F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff ++#define D3F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 ++#define D3F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff ++#define D3F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 ++#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 ++#define D3F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 ++#define D3F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 ++#define D3F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 ++#define D3F4_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc ++#define D3F4_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 ++#define D3F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff ++#define D3F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 ++#define D3F4_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 ++#define D3F4_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 ++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 ++#define D3F4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 ++#define D3F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 ++#define D3F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 ++#define D3F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 ++#define D3F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 ++#define D3F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 ++#define D3F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 ++#define D3F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 ++#define D3F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 ++#define D3F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 ++#define D3F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 ++#define D3F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 ++#define D3F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 ++#define D3F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 ++#define D3F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 ++#define D3F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 ++#define D3F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 ++#define D3F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 ++#define D3F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 ++#define D3F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 ++#define D3F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 ++#define D3F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 ++#define D3F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 ++#define D3F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 ++#define D3F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 ++#define D3F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 ++#define D3F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 ++#define D3F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 ++#define D3F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 ++#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F4_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f ++#define D3F4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 ++#define D3F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 ++#define D3F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf ++#define D3F4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 ++#define D3F4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 ++#define D3F4_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 ++#define D3F4_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f ++#define D3F4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f ++#define D3F4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 ++#define D3F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 ++#define D3F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc ++#define D3F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff ++#define D3F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 ++#define D3F4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff ++#define D3F4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 ++#define D3F4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff ++#define D3F4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 ++#define D3F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff ++#define D3F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 ++#define D3F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff ++#define D3F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 ++#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff ++#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 ++#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff ++#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 ++#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f ++#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 ++#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 ++#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 ++#define D3F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff ++#define D3F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 ++#define D3F5_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff ++#define D3F5_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0 ++#define D3F5_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff ++#define D3F5_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0 ++#define D3F5_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff ++#define D3F5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 ++#define D3F5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff ++#define D3F5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 ++#define D3F5_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define D3F5_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define D3F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define D3F5_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define D3F5_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define D3F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define D3F5_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define D3F5_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define D3F5_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define D3F5_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define D3F5_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define D3F5_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define D3F5_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define D3F5_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define D3F5_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define D3F5_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define D3F5_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define D3F5_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define D3F5_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define D3F5_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define D3F5_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define D3F5_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define D3F5_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define D3F5_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define D3F5_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define D3F5_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define D3F5_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define D3F5_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define D3F5_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define D3F5_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define D3F5_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define D3F5_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define D3F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1 ++#define D3F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0 ++#define D3F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2 ++#define D3F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1 ++#define D3F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4 ++#define D3F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2 ++#define D3F5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8 ++#define D3F5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3 ++#define D3F5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10 ++#define D3F5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4 ++#define D3F5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20 ++#define D3F5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5 ++#define D3F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40 ++#define D3F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6 ++#define D3F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00 ++#define D3F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8 ++#define D3F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000 ++#define D3F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define D3F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000 ++#define D3F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12 ++#define D3F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00 ++#define D3F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa ++#define D3F5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000 ++#define D3F5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc ++#define D3F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000 ++#define D3F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe ++#define D3F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000 ++#define D3F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf ++#define D3F5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000 ++#define D3F5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14 ++#define D3F5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000 ++#define D3F5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15 ++#define D3F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000 ++#define D3F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16 ++#define D3F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000 ++#define D3F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17 ++#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7 ++#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 ++#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8 ++#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 ++#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00 ++#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 ++#define D3F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff ++#define D3F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0 ++#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000 ++#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18 ++#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000 ++#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e ++#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000 ++#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f ++#define D3F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff ++#define D3F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0 ++#define D3F5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000 ++#define D3F5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10 ++#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7 ++#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0 ++#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000 ++#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf ++#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000 ++#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10 ++#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff ++#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0 ++#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000 ++#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc ++#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff ++#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0 ++#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000 ++#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10 ++#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff ++#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0 ++#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000 ++#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10 ++#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff ++#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0 ++#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000 ++#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10 ++#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff ++#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0 ++#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000 ++#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10 ++#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff ++#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0 ++#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000 ++#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10 ++#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff ++#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0 ++#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000 ++#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000 ++#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15 ++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7 ++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0 ++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70 ++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4 ++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700 ++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8 ++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000 ++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10 ++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000 ++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14 ++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000 ++#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18 ++#define D3F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1 ++#define D3F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0 ++#define D3F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e ++#define D3F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 ++#define D3F5_PCIE_FC_P__PD_CREDITS_MASK 0xff ++#define D3F5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0 ++#define D3F5_PCIE_FC_P__PH_CREDITS_MASK 0xff00 ++#define D3F5_PCIE_FC_P__PH_CREDITS__SHIFT 0x8 ++#define D3F5_PCIE_FC_NP__NPD_CREDITS_MASK 0xff ++#define D3F5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0 ++#define D3F5_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00 ++#define D3F5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8 ++#define D3F5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff ++#define D3F5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0 ++#define D3F5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00 ++#define D3F5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8 ++#define D3F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1 ++#define D3F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 ++#define D3F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2 ++#define D3F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1 ++#define D3F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4 ++#define D3F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2 ++#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10 ++#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4 ++#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20 ++#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5 ++#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40 ++#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6 ++#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80 ++#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7 ++#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700 ++#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 ++#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800 ++#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb ++#define D3F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000 ++#define D3F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe ++#define D3F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000 ++#define D3F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf ++#define D3F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000 ++#define D3F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10 ++#define D3F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000 ++#define D3F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 ++#define D3F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000 ++#define D3F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc ++#define D3F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000 ++#define D3F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd ++#define D3F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000 ++#define D3F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe ++#define D3F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000 ++#define D3F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf ++#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000 ++#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10 ++#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000 ++#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13 ++#define D3F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000 ++#define D3F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000 ++#define D3F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 ++#define D3F5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000 ++#define D3F5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a ++#define D3F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000 ++#define D3F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b ++#define D3F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff ++#define D3F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0 ++#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff ++#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0 ++#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000 ++#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18 ++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1 ++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0 ++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2 ++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1 ++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4 ++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2 ++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8 ++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3 ++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10 ++#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4 ++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff ++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0 ++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000 ++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10 ++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff ++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0 ++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000 ++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10 ++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff ++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0 ++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000 ++#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000 ++#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000 ++#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12 ++#define D3F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2 ++#define D3F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1 ++#define D3F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4 ++#define D3F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2 ++#define D3F5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8 ++#define D3F5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3 ++#define D3F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0 ++#define D3F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4 ++#define D3F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00 ++#define D3F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8 ++#define D3F5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000 ++#define D3F5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc ++#define D3F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000 ++#define D3F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10 ++#define D3F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000 ++#define D3F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11 ++#define D3F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000 ++#define D3F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12 ++#define D3F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000 ++#define D3F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14 ++#define D3F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000 ++#define D3F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15 ++#define D3F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000 ++#define D3F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16 ++#define D3F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000 ++#define D3F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17 ++#define D3F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000 ++#define D3F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18 ++#define D3F5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000 ++#define D3F5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19 ++#define D3F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000 ++#define D3F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b ++#define D3F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000 ++#define D3F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c ++#define D3F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000 ++#define D3F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d ++#define D3F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000 ++#define D3F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e ++#define D3F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000 ++#define D3F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f ++#define D3F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f ++#define D3F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0 ++#define D3F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40 ++#define D3F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6 ++#define D3F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80 ++#define D3F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7 ++#define D3F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100 ++#define D3F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8 ++#define D3F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200 ++#define D3F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9 ++#define D3F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400 ++#define D3F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa ++#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800 ++#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb ++#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000 ++#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc ++#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000 ++#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd ++#define D3F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000 ++#define D3F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe ++#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000 ++#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10 ++#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000 ++#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11 ++#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000 ++#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12 ++#define D3F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000 ++#define D3F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13 ++#define D3F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000 ++#define D3F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14 ++#define D3F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000 ++#define D3F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15 ++#define D3F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000 ++#define D3F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16 ++#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000 ++#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17 ++#define D3F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000 ++#define D3F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19 ++#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000 ++#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a ++#define D3F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000 ++#define D3F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b ++#define D3F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000 ++#define D3F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c ++#define D3F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000 ++#define D3F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d ++#define D3F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000 ++#define D3F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f ++#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1 ++#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0 ++#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6 ++#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1 ++#define D3F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8 ++#define D3F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3 ++#define D3F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10 ++#define D3F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4 ++#define D3F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20 ++#define D3F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5 ++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0 ++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6 ++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100 ++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8 ++#define D3F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200 ++#define D3F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9 ++#define D3F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400 ++#define D3F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa ++#define D3F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800 ++#define D3F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb ++#define D3F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000 ++#define D3F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc ++#define D3F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000 ++#define D3F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe ++#define D3F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000 ++#define D3F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10 ++#define D3F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000 ++#define D3F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11 ++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000 ++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12 ++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000 ++#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13 ++#define D3F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000 ++#define D3F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15 ++#define D3F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000 ++#define D3F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16 ++#define D3F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000 ++#define D3F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17 ++#define D3F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000 ++#define D3F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18 ++#define D3F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000 ++#define D3F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a ++#define D3F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000 ++#define D3F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e ++#define D3F5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000 ++#define D3F5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f ++#define D3F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3 ++#define D3F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0 ++#define D3F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4 ++#define D3F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2 ++#define D3F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8 ++#define D3F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3 ++#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10 ++#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4 ++#define D3F5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20 ++#define D3F5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5 ++#define D3F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40 ++#define D3F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6 ++#define D3F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80 ++#define D3F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7 ++#define D3F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300 ++#define D3F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8 ++#define D3F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400 ++#define D3F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa ++#define D3F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800 ++#define D3F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb ++#define D3F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000 ++#define D3F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc ++#define D3F5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000 ++#define D3F5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd ++#define D3F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000 ++#define D3F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe ++#define D3F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000 ++#define D3F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf ++#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000 ++#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10 ++#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000 ++#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11 ++#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000 ++#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12 ++#define D3F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000 ++#define D3F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16 ++#define D3F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000 ++#define D3F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17 ++#define D3F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000 ++#define D3F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18 ++#define D3F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000 ++#define D3F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19 ++#define D3F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000 ++#define D3F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a ++#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f ++#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0 ++#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0 ++#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6 ++#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000 ++#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc ++#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000 ++#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12 ++#define D3F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000 ++#define D3F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18 ++#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1 ++#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0 ++#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4 ++#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2 ++#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10 ++#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400 ++#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000 ++#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000 ++#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d ++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff ++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0 ++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100 ++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8 ++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200 ++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9 ++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000 ++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10 ++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000 ++#define D3F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000 ++#define D3F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f ++#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff ++#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0 ++#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000 ++#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc ++#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000 ++#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18 ++#define D3F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff ++#define D3F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0 ++#define D3F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000 ++#define D3F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10 ++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1 ++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0 ++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e ++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1 ++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80 ++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7 ++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000 ++#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd ++#define D3F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000 ++#define D3F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13 ++#define D3F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000 ++#define D3F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14 ++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf ++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0 ++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0 ++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4 ++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00 ++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa ++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000 ++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10 ++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000 ++#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16 ++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1 ++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0 ++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e ++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1 ++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80 ++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7 ++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000 ++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd ++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000 ++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13 ++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000 ++#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19 ++#define D3F5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f ++#define D3F5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0 ++#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00 ++#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8 ++#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000 ++#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10 ++#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000 ++#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18 ++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f ++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0 ++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00 ++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8 ++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000 ++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10 ++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000 ++#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18 ++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f ++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0 ++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00 ++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8 ++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000 ++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10 ++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000 ++#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18 ++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f ++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0 ++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00 ++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8 ++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000 ++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10 ++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000 ++#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18 ++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f ++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0 ++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00 ++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8 ++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000 ++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10 ++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000 ++#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18 ++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f ++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0 ++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00 ++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8 ++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000 ++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10 ++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000 ++#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18 ++#define D3F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3 ++#define D3F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0 ++#define D3F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc ++#define D3F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2 ++#define D3F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30 ++#define D3F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4 ++#define D3F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0 ++#define D3F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6 ++#define D3F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700 ++#define D3F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8 ++#define D3F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800 ++#define D3F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb ++#define D3F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000 ++#define D3F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc ++#define D3F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000 ++#define D3F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd ++#define D3F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000 ++#define D3F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe ++#define D3F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000 ++#define D3F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf ++#define D3F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000 ++#define D3F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10 ++#define D3F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1 ++#define D3F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0 ++#define D3F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2 ++#define D3F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1 ++#define D3F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4 ++#define D3F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2 ++#define D3F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18 ++#define D3F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3 ++#define D3F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20 ++#define D3F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5 ++#define D3F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1 ++#define D3F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0 ++#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00 ++#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8 ++#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000 ++#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10 ++#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8 ++#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3 ++#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40 ++#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6 ++#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1 ++#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0 ++#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2 ++#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1 ++#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4 ++#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2 ++#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8 ++#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3 ++#define D3F5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80 ++#define D3F5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7 ++#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100 ++#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8 ++#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200 ++#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9 ++#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400 ++#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa ++#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800 ++#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb ++#define D3F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000 ++#define D3F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf ++#define D3F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000 ++#define D3F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10 ++#define D3F5_VENDOR_ID__VENDOR_ID_MASK 0xffff ++#define D3F5_VENDOR_ID__VENDOR_ID__SHIFT 0x0 ++#define D3F5_DEVICE_ID__DEVICE_ID_MASK 0xffff0000 ++#define D3F5_DEVICE_ID__DEVICE_ID__SHIFT 0x10 ++#define D3F5_COMMAND__IO_ACCESS_EN_MASK 0x1 ++#define D3F5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 ++#define D3F5_COMMAND__MEM_ACCESS_EN_MASK 0x2 ++#define D3F5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 ++#define D3F5_COMMAND__BUS_MASTER_EN_MASK 0x4 ++#define D3F5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 ++#define D3F5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8 ++#define D3F5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 ++#define D3F5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10 ++#define D3F5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 ++#define D3F5_COMMAND__PAL_SNOOP_EN_MASK 0x20 ++#define D3F5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 ++#define D3F5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40 ++#define D3F5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 ++#define D3F5_COMMAND__AD_STEPPING_MASK 0x80 ++#define D3F5_COMMAND__AD_STEPPING__SHIFT 0x7 ++#define D3F5_COMMAND__SERR_EN_MASK 0x100 ++#define D3F5_COMMAND__SERR_EN__SHIFT 0x8 ++#define D3F5_COMMAND__FAST_B2B_EN_MASK 0x200 ++#define D3F5_COMMAND__FAST_B2B_EN__SHIFT 0x9 ++#define D3F5_COMMAND__INT_DIS_MASK 0x400 ++#define D3F5_COMMAND__INT_DIS__SHIFT 0xa ++#define D3F5_STATUS__INT_STATUS_MASK 0x80000 ++#define D3F5_STATUS__INT_STATUS__SHIFT 0x13 ++#define D3F5_STATUS__CAP_LIST_MASK 0x100000 ++#define D3F5_STATUS__CAP_LIST__SHIFT 0x14 ++#define D3F5_STATUS__PCI_66_EN_MASK 0x200000 ++#define D3F5_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D3F5_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D3F5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D3F5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D3F5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D3F5_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D3F5_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D3F5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D3F5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D3F5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D3F5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D3F5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D3F5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D3F5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000 ++#define D3F5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e ++#define D3F5_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D3F5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D3F5_REVISION_ID__MINOR_REV_ID_MASK 0xf ++#define D3F5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 ++#define D3F5_REVISION_ID__MAJOR_REV_ID_MASK 0xf0 ++#define D3F5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 ++#define D3F5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00 ++#define D3F5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8 ++#define D3F5_SUB_CLASS__SUB_CLASS_MASK 0xff0000 ++#define D3F5_SUB_CLASS__SUB_CLASS__SHIFT 0x10 ++#define D3F5_BASE_CLASS__BASE_CLASS_MASK 0xff000000 ++#define D3F5_BASE_CLASS__BASE_CLASS__SHIFT 0x18 ++#define D3F5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff ++#define D3F5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 ++#define D3F5_LATENCY__LATENCY_TIMER_MASK 0xff00 ++#define D3F5_LATENCY__LATENCY_TIMER__SHIFT 0x8 ++#define D3F5_HEADER__HEADER_TYPE_MASK 0x7f0000 ++#define D3F5_HEADER__HEADER_TYPE__SHIFT 0x10 ++#define D3F5_HEADER__DEVICE_TYPE_MASK 0x800000 ++#define D3F5_HEADER__DEVICE_TYPE__SHIFT 0x17 ++#define D3F5_BIST__BIST_COMP_MASK 0xf000000 ++#define D3F5_BIST__BIST_COMP__SHIFT 0x18 ++#define D3F5_BIST__BIST_STRT_MASK 0x40000000 ++#define D3F5_BIST__BIST_STRT__SHIFT 0x1e ++#define D3F5_BIST__BIST_CAP_MASK 0x80000000 ++#define D3F5_BIST__BIST_CAP__SHIFT 0x1f ++#define D3F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff ++#define D3F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 ++#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00 ++#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 ++#define D3F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000 ++#define D3F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 ++#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000 ++#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 ++#define D3F5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf ++#define D3F5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 ++#define D3F5_IO_BASE_LIMIT__IO_BASE_MASK 0xf0 ++#define D3F5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 ++#define D3F5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00 ++#define D3F5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 ++#define D3F5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000 ++#define D3F5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc ++#define D3F5_SECONDARY_STATUS__CAP_LIST_MASK 0x100000 ++#define D3F5_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14 ++#define D3F5_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000 ++#define D3F5_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15 ++#define D3F5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000 ++#define D3F5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17 ++#define D3F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000 ++#define D3F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18 ++#define D3F5_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000 ++#define D3F5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19 ++#define D3F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000 ++#define D3F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b ++#define D3F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000 ++#define D3F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c ++#define D3F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000 ++#define D3F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d ++#define D3F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000 ++#define D3F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e ++#define D3F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000 ++#define D3F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f ++#define D3F5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf ++#define D3F5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 ++#define D3F5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0 ++#define D3F5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 ++#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 ++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf ++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 ++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0 ++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 ++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000 ++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 ++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000 ++#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 ++#define D3F5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff ++#define D3F5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 ++#define D3F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff ++#define D3F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 ++#define D3F5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff ++#define D3F5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 ++#define D3F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000 ++#define D3F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 ++#define D3F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000 ++#define D3F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10 ++#define D3F5_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000 ++#define D3F5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11 ++#define D3F5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000 ++#define D3F5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12 ++#define D3F5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000 ++#define D3F5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13 ++#define D3F5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000 ++#define D3F5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14 ++#define D3F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000 ++#define D3F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15 ++#define D3F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000 ++#define D3F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16 ++#define D3F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000 ++#define D3F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17 ++#define D3F5_CAP_PTR__CAP_PTR_MASK 0xff ++#define D3F5_CAP_PTR__CAP_PTR__SHIFT 0x0 ++#define D3F5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff ++#define D3F5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 ++#define D3F5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00 ++#define D3F5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8 ++#define D3F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1 ++#define D3F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 ++#define D3F5_PMI_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F5_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F5_PMI_CAP__VERSION_MASK 0x70000 ++#define D3F5_PMI_CAP__VERSION__SHIFT 0x10 ++#define D3F5_PMI_CAP__PME_CLOCK_MASK 0x80000 ++#define D3F5_PMI_CAP__PME_CLOCK__SHIFT 0x13 ++#define D3F5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000 ++#define D3F5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15 ++#define D3F5_PMI_CAP__AUX_CURRENT_MASK 0x1c00000 ++#define D3F5_PMI_CAP__AUX_CURRENT__SHIFT 0x16 ++#define D3F5_PMI_CAP__D1_SUPPORT_MASK 0x2000000 ++#define D3F5_PMI_CAP__D1_SUPPORT__SHIFT 0x19 ++#define D3F5_PMI_CAP__D2_SUPPORT_MASK 0x4000000 ++#define D3F5_PMI_CAP__D2_SUPPORT__SHIFT 0x1a ++#define D3F5_PMI_CAP__PME_SUPPORT_MASK 0xf8000000 ++#define D3F5_PMI_CAP__PME_SUPPORT__SHIFT 0x1b ++#define D3F5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3 ++#define D3F5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 ++#define D3F5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8 ++#define D3F5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 ++#define D3F5_PMI_STATUS_CNTL__PME_EN_MASK 0x100 ++#define D3F5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 ++#define D3F5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00 ++#define D3F5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 ++#define D3F5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000 ++#define D3F5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd ++#define D3F5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000 ++#define D3F5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf ++#define D3F5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000 ++#define D3F5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 ++#define D3F5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000 ++#define D3F5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 ++#define D3F5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000 ++#define D3F5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 ++#define D3F5_PCIE_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F5_PCIE_CAP__VERSION_MASK 0xf0000 ++#define D3F5_PCIE_CAP__VERSION__SHIFT 0x10 ++#define D3F5_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000 ++#define D3F5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14 ++#define D3F5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000 ++#define D3F5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18 ++#define D3F5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000 ++#define D3F5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19 ++#define D3F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7 ++#define D3F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 ++#define D3F5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18 ++#define D3F5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 ++#define D3F5_DEVICE_CAP__EXTENDED_TAG_MASK 0x20 ++#define D3F5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 ++#define D3F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0 ++#define D3F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 ++#define D3F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00 ++#define D3F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 ++#define D3F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000 ++#define D3F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf ++#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000 ++#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 ++#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000 ++#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a ++#define D3F5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000 ++#define D3F5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c ++#define D3F5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1 ++#define D3F5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 ++#define D3F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2 ++#define D3F5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 ++#define D3F5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4 ++#define D3F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 ++#define D3F5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8 ++#define D3F5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 ++#define D3F5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10 ++#define D3F5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 ++#define D3F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0 ++#define D3F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 ++#define D3F5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100 ++#define D3F5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 ++#define D3F5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200 ++#define D3F5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 ++#define D3F5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400 ++#define D3F5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa ++#define D3F5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800 ++#define D3F5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb ++#define D3F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000 ++#define D3F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc ++#define D3F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000 ++#define D3F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf ++#define D3F5_DEVICE_STATUS__CORR_ERR_MASK 0x10000 ++#define D3F5_DEVICE_STATUS__CORR_ERR__SHIFT 0x10 ++#define D3F5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000 ++#define D3F5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11 ++#define D3F5_DEVICE_STATUS__FATAL_ERR_MASK 0x40000 ++#define D3F5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12 ++#define D3F5_DEVICE_STATUS__USR_DETECTED_MASK 0x80000 ++#define D3F5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13 ++#define D3F5_DEVICE_STATUS__AUX_PWR_MASK 0x100000 ++#define D3F5_DEVICE_STATUS__AUX_PWR__SHIFT 0x14 ++#define D3F5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000 ++#define D3F5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15 ++#define D3F5_LINK_CAP__LINK_SPEED_MASK 0xf ++#define D3F5_LINK_CAP__LINK_SPEED__SHIFT 0x0 ++#define D3F5_LINK_CAP__LINK_WIDTH_MASK 0x3f0 ++#define D3F5_LINK_CAP__LINK_WIDTH__SHIFT 0x4 ++#define D3F5_LINK_CAP__PM_SUPPORT_MASK 0xc00 ++#define D3F5_LINK_CAP__PM_SUPPORT__SHIFT 0xa ++#define D3F5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000 ++#define D3F5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc ++#define D3F5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000 ++#define D3F5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf ++#define D3F5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000 ++#define D3F5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 ++#define D3F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000 ++#define D3F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 ++#define D3F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000 ++#define D3F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 ++#define D3F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000 ++#define D3F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 ++#define D3F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000 ++#define D3F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 ++#define D3F5_LINK_CAP__PORT_NUMBER_MASK 0xff000000 ++#define D3F5_LINK_CAP__PORT_NUMBER__SHIFT 0x18 ++#define D3F5_LINK_CNTL__PM_CONTROL_MASK 0x3 ++#define D3F5_LINK_CNTL__PM_CONTROL__SHIFT 0x0 ++#define D3F5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8 ++#define D3F5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 ++#define D3F5_LINK_CNTL__LINK_DIS_MASK 0x10 ++#define D3F5_LINK_CNTL__LINK_DIS__SHIFT 0x4 ++#define D3F5_LINK_CNTL__RETRAIN_LINK_MASK 0x20 ++#define D3F5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 ++#define D3F5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40 ++#define D3F5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 ++#define D3F5_LINK_CNTL__EXTENDED_SYNC_MASK 0x80 ++#define D3F5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 ++#define D3F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100 ++#define D3F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 ++#define D3F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200 ++#define D3F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 ++#define D3F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400 ++#define D3F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa ++#define D3F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800 ++#define D3F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb ++#define D3F5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000 ++#define D3F5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10 ++#define D3F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000 ++#define D3F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14 ++#define D3F5_LINK_STATUS__LINK_TRAINING_MASK 0x8000000 ++#define D3F5_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b ++#define D3F5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000 ++#define D3F5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c ++#define D3F5_LINK_STATUS__DL_ACTIVE_MASK 0x20000000 ++#define D3F5_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d ++#define D3F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000 ++#define D3F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e ++#define D3F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000 ++#define D3F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f ++#define D3F5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1 ++#define D3F5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 ++#define D3F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2 ++#define D3F5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 ++#define D3F5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4 ++#define D3F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 ++#define D3F5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8 ++#define D3F5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 ++#define D3F5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10 ++#define D3F5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 ++#define D3F5_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20 ++#define D3F5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 ++#define D3F5_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40 ++#define D3F5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 ++#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80 ++#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 ++#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000 ++#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf ++#define D3F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000 ++#define D3F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 ++#define D3F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000 ++#define D3F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 ++#define D3F5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000 ++#define D3F5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 ++#define D3F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1 ++#define D3F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 ++#define D3F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2 ++#define D3F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 ++#define D3F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4 ++#define D3F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 ++#define D3F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8 ++#define D3F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 ++#define D3F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10 ++#define D3F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 ++#define D3F5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20 ++#define D3F5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 ++#define D3F5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0 ++#define D3F5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 ++#define D3F5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300 ++#define D3F5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 ++#define D3F5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400 ++#define D3F5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa ++#define D3F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800 ++#define D3F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb ++#define D3F5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000 ++#define D3F5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc ++#define D3F5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000 ++#define D3F5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10 ++#define D3F5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000 ++#define D3F5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11 ++#define D3F5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000 ++#define D3F5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12 ++#define D3F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000 ++#define D3F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13 ++#define D3F5_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000 ++#define D3F5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14 ++#define D3F5_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000 ++#define D3F5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15 ++#define D3F5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000 ++#define D3F5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16 ++#define D3F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000 ++#define D3F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17 ++#define D3F5_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000 ++#define D3F5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18 ++#define D3F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1 ++#define D3F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 ++#define D3F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2 ++#define D3F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 ++#define D3F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4 ++#define D3F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 ++#define D3F5_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8 ++#define D3F5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 ++#define D3F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10 ++#define D3F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 ++#define D3F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000 ++#define D3F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10 ++#define D3F5_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff ++#define D3F5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 ++#define D3F5_ROOT_STATUS__PME_STATUS_MASK 0x10000 ++#define D3F5_ROOT_STATUS__PME_STATUS__SHIFT 0x10 ++#define D3F5_ROOT_STATUS__PME_PENDING_MASK 0x20000 ++#define D3F5_ROOT_STATUS__PME_PENDING__SHIFT 0x11 ++#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf ++#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 ++#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10 ++#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 ++#define D3F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20 ++#define D3F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 ++#define D3F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40 ++#define D3F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 ++#define D3F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80 ++#define D3F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 ++#define D3F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100 ++#define D3F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 ++#define D3F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200 ++#define D3F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 ++#define D3F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400 ++#define D3F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa ++#define D3F5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800 ++#define D3F5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb ++#define D3F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000 ++#define D3F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc ++#define D3F5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000 ++#define D3F5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 ++#define D3F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000 ++#define D3F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 ++#define D3F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000 ++#define D3F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 ++#define D3F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000 ++#define D3F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 ++#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf ++#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 ++#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10 ++#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 ++#define D3F5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20 ++#define D3F5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 ++#define D3F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40 ++#define D3F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 ++#define D3F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80 ++#define D3F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 ++#define D3F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100 ++#define D3F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 ++#define D3F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200 ++#define D3F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 ++#define D3F5_DEVICE_CNTL2__LTR_EN_MASK 0x400 ++#define D3F5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa ++#define D3F5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000 ++#define D3F5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd ++#define D3F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000 ++#define D3F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf ++#define D3F5_DEVICE_STATUS2__RESERVED_MASK 0xffff0000 ++#define D3F5_DEVICE_STATUS2__RESERVED__SHIFT 0x10 ++#define D3F5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe ++#define D3F5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 ++#define D3F5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100 ++#define D3F5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 ++#define D3F5_LINK_CAP2__RESERVED_MASK 0xfffffe00 ++#define D3F5_LINK_CAP2__RESERVED__SHIFT 0x9 ++#define D3F5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf ++#define D3F5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 ++#define D3F5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10 ++#define D3F5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 ++#define D3F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20 ++#define D3F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 ++#define D3F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40 ++#define D3F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 ++#define D3F5_LINK_CNTL2__XMIT_MARGIN_MASK 0x380 ++#define D3F5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 ++#define D3F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400 ++#define D3F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa ++#define D3F5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800 ++#define D3F5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb ++#define D3F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000 ++#define D3F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc ++#define D3F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000 ++#define D3F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10 ++#define D3F5_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000 ++#define D3F5_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11 ++#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000 ++#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12 ++#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000 ++#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13 ++#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000 ++#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14 ++#define D3F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000 ++#define D3F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15 ++#define D3F5_SLOT_CAP2__RESERVED_MASK 0xffffffff ++#define D3F5_SLOT_CAP2__RESERVED__SHIFT 0x0 ++#define D3F5_SLOT_CNTL2__RESERVED_MASK 0xffff ++#define D3F5_SLOT_CNTL2__RESERVED__SHIFT 0x0 ++#define D3F5_SLOT_STATUS2__RESERVED_MASK 0xffff0000 ++#define D3F5_SLOT_STATUS2__RESERVED__SHIFT 0x10 ++#define D3F5_MSI_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F5_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F5_MSI_MSG_CNTL__MSI_EN_MASK 0x10000 ++#define D3F5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10 ++#define D3F5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000 ++#define D3F5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11 ++#define D3F5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000 ++#define D3F5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14 ++#define D3F5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000 ++#define D3F5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17 ++#define D3F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000 ++#define D3F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18 ++#define D3F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc ++#define D3F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 ++#define D3F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff ++#define D3F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 ++#define D3F5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff ++#define D3F5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 ++#define D3F5_MSI_MSG_DATA__MSI_DATA_MASK 0xffff ++#define D3F5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 ++#define D3F5_SSID_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F5_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F5_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F5_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff ++#define D3F5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define D3F5_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000 ++#define D3F5_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 ++#define D3F5_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff ++#define D3F5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00 ++#define D3F5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define D3F5_MSI_MAP_CAP__EN_MASK 0x10000 ++#define D3F5_MSI_MAP_CAP__EN__SHIFT 0x10 ++#define D3F5_MSI_MAP_CAP__FIXD_MASK 0x20000 ++#define D3F5_MSI_MAP_CAP__FIXD__SHIFT 0x11 ++#define D3F5_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000 ++#define D3F5_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b ++#define D3F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000 ++#define D3F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 ++#define D3F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff ++#define D3F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 ++#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff ++#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 ++#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000 ++#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 ++#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000 ++#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 ++#define D3F5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff ++#define D3F5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 ++#define D3F5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff ++#define D3F5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 ++#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7 ++#define D3F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 ++#define D3F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70 ++#define D3F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 ++#define D3F5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300 ++#define D3F5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 ++#define D3F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00 ++#define D3F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa ++#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff ++#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 ++#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1 ++#define D3F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 ++#define D3F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe ++#define D3F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 ++#define D3F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D3F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D3F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D3F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D3F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D3F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D3F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D3F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D3F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D3F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D3F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff ++#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define D3F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000 ++#define D3F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define D3F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000 ++#define D3F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000 ++#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1 ++#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe ++#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define D3F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000 ++#define D3F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define D3F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000 ++#define D3F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000 ++#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000 ++#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++#define D3F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000 ++#define D3F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10 ++#define D3F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000 ++#define D3F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11 ++#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff ++#define D3F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 ++#define D3F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff ++#define D3F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 ++#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc ++#define D3F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd ++#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe ++#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf ++#define D3F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000 ++#define D3F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 ++#define D3F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10 ++#define D3F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 ++#define D3F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20 ++#define D3F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 ++#define D3F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc ++#define D3F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd ++#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe ++#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf ++#define D3F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 ++#define D3F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 ++#define D3F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 ++#define D3F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 ++#define D3F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 ++#define D3F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 ++#define D3F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 ++#define D3F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 ++#define D3F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 ++#define D3F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000 ++#define D3F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000 ++#define D3F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 ++#define D3F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1 ++#define D3F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 ++#define D3F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40 ++#define D3F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 ++#define D3F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80 ++#define D3F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 ++#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100 ++#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 ++#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000 ++#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc ++#define D3F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000 ++#define D3F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd ++#define D3F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000 ++#define D3F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe ++#define D3F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000 ++#define D3F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf ++#define D3F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1 ++#define D3F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 ++#define D3F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40 ++#define D3F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 ++#define D3F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80 ++#define D3F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 ++#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100 ++#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 ++#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000 ++#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc ++#define D3F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000 ++#define D3F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd ++#define D3F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000 ++#define D3F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe ++#define D3F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000 ++#define D3F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20 ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40 ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80 ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100 ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200 ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400 ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800 ++#define D3F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb ++#define D3F5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff ++#define D3F5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 ++#define D3F5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff ++#define D3F5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 ++#define D3F5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff ++#define D3F5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 ++#define D3F5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff ++#define D3F5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 ++#define D3F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1 ++#define D3F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 ++#define D3F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2 ++#define D3F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 ++#define D3F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4 ++#define D3F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 ++#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1 ++#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 ++#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2 ++#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 ++#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4 ++#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 ++#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8 ++#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 ++#define D3F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10 ++#define D3F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 ++#define D3F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20 ++#define D3F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 ++#define D3F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40 ++#define D3F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 ++#define D3F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000 ++#define D3F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b ++#define D3F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff ++#define D3F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 ++#define D3F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000 ++#define D3F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 ++#define D3F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff ++#define D3F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 ++#define D3F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff ++#define D3F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 ++#define D3F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff ++#define D3F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 ++#define D3F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff ++#define D3F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 ++#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1 ++#define D3F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 ++#define D3F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2 ++#define D3F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 ++#define D3F5_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc ++#define D3F5_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 ++#define D3F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff ++#define D3F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 ++#define D3F5_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000 ++#define D3F5_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 ++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf ++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70 ++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00 ++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000 ++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000 ++#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000 ++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10 ++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000 ++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14 ++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000 ++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18 ++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000 ++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c ++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000 ++#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f ++#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1 ++#define D3F5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 ++#define D3F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2 ++#define D3F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 ++#define D3F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4 ++#define D3F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 ++#define D3F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8 ++#define D3F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 ++#define D3F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10 ++#define D3F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 ++#define D3F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20 ++#define D3F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 ++#define D3F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40 ++#define D3F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 ++#define D3F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00 ++#define D3F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 ++#define D3F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000 ++#define D3F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10 ++#define D3F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000 ++#define D3F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11 ++#define D3F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000 ++#define D3F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12 ++#define D3F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000 ++#define D3F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13 ++#define D3F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000 ++#define D3F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14 ++#define D3F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000 ++#define D3F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15 ++#define D3F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000 ++#define D3F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16 ++#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff ++#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000 ++#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define D3F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000 ++#define D3F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++#define D3F5_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f ++#define D3F5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 ++#define D3F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000 ++#define D3F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf ++#define D3F5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000 ++#define D3F5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10 ++#define D3F5_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000 ++#define D3F5_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f ++#define D3F5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f ++#define D3F5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 ++#define D3F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000 ++#define D3F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc ++#define D3F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff ++#define D3F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 ++#define D3F5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff ++#define D3F5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 ++#define D3F5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff ++#define D3F5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 ++#define D3F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff ++#define D3F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 ++#define D3F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff ++#define D3F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 ++#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff ++#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 ++#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff ++#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 ++#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f ++#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 ++#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0 ++#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 ++#define D3F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff ++#define D3F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 ++#define C_PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff ++#define C_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 ++#define C_PCIE_DATA__PCIE_DATA_MASK 0xffffffff ++#define C_PCIE_DATA__PCIE_DATA__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK 0x2 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN__SHIFT 0x1 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN_MASK 0x4 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT 0x2 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE_MASK 0x8 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE__SHIFT 0x3 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG_MASK 0x20 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG__SHIFT 0x5 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN_MASK 0x200 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN__SHIFT 0x9 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED_MASK 0x800 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED__SHIFT 0xb ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN_MASK 0x2000 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN__SHIFT 0xd ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN_MASK 0x200000 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN__SHIFT 0x15 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN_MASK 0x800000 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN__SHIFT 0x17 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN_MASK 0x10000000 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN__SHIFT 0x1c ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED_MASK 0x20000000 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED__SHIFT 0x1d ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED_MASK 0xc0000000 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED__SHIFT 0x1e ++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG_MASK 0x1ff8 ++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG__SHIFT 0x3 ++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ_MASK 0x6000 ++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ__SHIFT 0xd ++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG_MASK 0x1f8000 ++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG__SHIFT 0xf ++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS_MASK 0x200000 ++#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS__SHIFT 0x15 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK 0x2 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT 0x1 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE_MASK 0xc ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT 0x2 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE_MASK 0x10 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE__SHIFT 0x4 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE_MASK 0x400 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE__SHIFT 0xa ++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE_MASK 0x800 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE__SHIFT 0xb ++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN_MASK 0x2000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN__SHIFT 0xd ++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN_MASK 0x4000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN__SHIFT 0xe ++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x18000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0xf ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR_MASK 0x1 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK 0x2 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT 0x1 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK 0x4 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT 0x2 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK 0x10 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT 0x4 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK 0x20 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT 0x5 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR_MASK 0x40 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT 0x6 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR_MASK 0x200 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR_MASK 0x1000 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR__SHIFT 0xc ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS_MASK 0x10000 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS__SHIFT 0x10 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN_MASK 0x20000 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN__SHIFT 0x11 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN_MASK 0x40000 ++#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN__SHIFT 0x12 ++#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE_MASK 0x4000000 ++#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE__SHIFT 0x1a ++#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL_MASK 0xc0000000 ++#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL__SHIFT 0x1e ++#define PSX80_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT_MASK 0x1 ++#define PSX80_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN_MASK 0x1 ++#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK 0x2 ++#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION__SHIFT 0x1 ++#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING_MASK 0x4 ++#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT 0x2 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3_MASK 0x1 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN_MASK 0x4 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT 0x2 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x8 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x3 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP_MASK 0x70 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP__SHIFT 0x4 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x80 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x7 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS_MASK 0x100 ++#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS__SHIFT 0x8 ++#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID_MASK 0xffff ++#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID__SHIFT 0x0 ++#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID_MASK 0xffff0000 ++#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID__SHIFT 0x10 ++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x7 ++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0 ++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x38 ++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x3 ++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_MASK 0x3c0 ++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x6 ++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_MASK 0x3c00 ++#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET__SHIFT 0xa ++#define PSX80_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG_MASK 0xf ++#define PSX80_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG__SHIFT 0x0 ++#define PSX80_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING_MASK 0x1 ++#define PSX80_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 ++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT_MASK 0xc000 ++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT__SHIFT 0xe ++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 ++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 ++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 ++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 ++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 ++#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN_MASK 0x80 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 ++#define PSX80_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB_MASK 0x1 ++#define PSX80_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB__SHIFT 0x0 ++#define PSX80_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING_MASK 0x1 ++#define PSX80_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 ++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT_MASK 0xc000 ++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT__SHIFT 0xe ++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 ++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 ++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 ++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 ++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 ++#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN_MASK 0x80 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 ++#define PSX80_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB_MASK 0x1 ++#define PSX80_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB__SHIFT 0x0 ++#define PSX80_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING_MASK 0x1 ++#define PSX80_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 ++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT_MASK 0xc000 ++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT__SHIFT 0xe ++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 ++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 ++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 ++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 ++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 ++#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN_MASK 0x80 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 ++#define PSX80_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB_MASK 0x1 ++#define PSX80_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB__SHIFT 0x0 ++#define PSX80_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING_MASK 0x1 ++#define PSX80_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 ++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT_MASK 0xc000 ++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT__SHIFT 0xe ++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 ++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 ++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 ++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 ++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 ++#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN_MASK 0x80 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 ++#define PSX80_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB_MASK 0x1 ++#define PSX80_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB__SHIFT 0x0 ++#define PSX80_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING_MASK 0x1 ++#define PSX80_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 ++#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 ++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT_MASK 0xc000 ++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT__SHIFT 0xe ++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 ++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 ++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 ++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 ++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 ++#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 ++#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN_MASK 0x80 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 ++#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 ++#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 ++#define PSX80_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB_MASK 0x1 ++#define PSX80_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB__SHIFT 0x0 ++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1 ++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0 ++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2 ++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1 ++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4 ++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2 ++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8 ++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3 ++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10 ++#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4 ++#define PSX80_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff ++#define PSX80_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0 ++#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7 ++#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0 ++#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70 ++#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4 ++#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff ++#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0 ++#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000 ++#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10 ++#define PSX80_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff ++#define PSX80_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0 ++#define PSX80_WRP_LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff ++#define PSX80_WRP_LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0 ++#define PSX80_WRP_LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff ++#define PSX80_WRP_LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0 ++#define PSX80_WRP_PCIE_EFUSE__PCIE_EFUSE_MASK 0xffffffff ++#define PSX80_WRP_PCIE_EFUSE__PCIE_EFUSE__SHIFT 0x0 ++#define PSX80_WRP_PCIE_EFUSE2__PCIE_EFUSE2_MASK 0xffffffff ++#define PSX80_WRP_PCIE_EFUSE2__PCIE_EFUSE2__SHIFT 0x0 ++#define PSX80_WRP_PCIE_EFUSE3__PCIE_EFUSE3_MASK 0xffffffff ++#define PSX80_WRP_PCIE_EFUSE3__PCIE_EFUSE3__SHIFT 0x0 ++#define PSX80_WRP_PCIE_EFUSE4__PCIE_EFUSE4_MASK 0xffffffff ++#define PSX80_WRP_PCIE_EFUSE4__PCIE_EFUSE4__SHIFT 0x0 ++#define PSX80_WRP_PCIE_EFUSE5__PCIE_EFUSE5_MASK 0xffffffff ++#define PSX80_WRP_PCIE_EFUSE5__PCIE_EFUSE5__SHIFT 0x0 ++#define PSX80_WRP_PCIE_EFUSE6__PCIE_EFUSE6_MASK 0xffffffff ++#define PSX80_WRP_PCIE_EFUSE6__PCIE_EFUSE6__SHIFT 0x0 ++#define PSX80_WRP_PCIE_EFUSE7__PCIE_EFUSE7_MASK 0xffffffff ++#define PSX80_WRP_PCIE_EFUSE7__PCIE_EFUSE7__SHIFT 0x0 ++#define PSX80_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff ++#define PSX80_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0 ++#define PSX80_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff ++#define PSX80_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0 ++#define PSX80_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1 ++#define PSX80_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0 ++#define PSX80_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1 ++#define PSX80_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0 ++#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1 ++#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0 ++#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2 ++#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1 ++#define PSX80_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK 0x2 ++#define PSX80_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY__SHIFT 0x1 ++#define PSX80_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4 ++#define PSX80_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2 ++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7 ++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0 ++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70 ++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4 ++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80 ++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7 ++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100 ++#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8 ++#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xff ++#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0 ++#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000 ++#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10 ++#define PSX80_WRP_IMPCTL_CNTL_PIF0__ArbEn0_MASK 0x1 ++#define PSX80_WRP_IMPCTL_CNTL_PIF0__ArbEn0__SHIFT 0x0 ++#define PSX80_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0_MASK 0x800 ++#define PSX80_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0__SHIFT 0xb ++#define PSX80_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1 ++#define PSX80_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0 ++#define PSX80_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1 ++#define PSX80_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0 ++#define PSX80_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1 ++#define PSX80_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0 ++#define PSX80_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1 ++#define PSX80_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0 ++#define PSX80_WRP_BIOSTIMER_CMD__Microseconds_MASK 0xffffffff ++#define PSX80_WRP_BIOSTIMER_CMD__Microseconds__SHIFT 0x0 ++#define PSX80_WRP_BIOSTIMER_CNTL__ClockRate_MASK 0xff ++#define PSX80_WRP_BIOSTIMER_CNTL__ClockRate__SHIFT 0x0 ++#define PSX80_WRP_BIOSTIMER_DEBUG__Microseconds_compare_MASK 0xffffffff ++#define PSX80_WRP_BIOSTIMER_DEBUG__Microseconds_compare__SHIFT 0x0 ++#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl_MASK 0xff ++#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl__SHIFT 0x0 ++#define PSX80_WRP_DTM_RX_BP_CNTL__Dbg_Cntl_MASK 0xf0000 ++#define PSX80_WRP_DTM_RX_BP_CNTL__Dbg_Cntl__SHIFT 0x10 ++#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue_MASK 0xf00000 ++#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue__SHIFT 0x14 ++#define PSX80_WRP_DTM_RX_BP_CNTL__td_hold_training_override_MASK 0x1f000000 ++#define PSX80_WRP_DTM_RX_BP_CNTL__td_hold_training_override__SHIFT 0x18 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy0_MASK 0x1 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy0__SHIFT 0x0 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy1_MASK 0x2 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy1__SHIFT 0x1 ++#define PSX80_WRP_DTM_CNTL__Determinism_En_DTM_MASK 0x4 ++#define PSX80_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT 0x2 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy2_MASK 0x8 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy2__SHIFT 0x3 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy3_MASK 0x10 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy3__SHIFT 0x4 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy4_MASK 0x20 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy4__SHIFT 0x5 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy5_MASK 0x40 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy5__SHIFT 0x6 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy6_MASK 0x80 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy6__SHIFT 0x7 ++#define PSX80_WRP_DTM_CNTL__TxClk1x_Cntl_MASK 0x300 ++#define PSX80_WRP_DTM_CNTL__TxClk1x_Cntl__SHIFT 0x8 ++#define PSX80_WRP_DTM_CNTL__TxClkGskt_Cntl_MASK 0xc00 ++#define PSX80_WRP_DTM_CNTL__TxClkGskt_Cntl__SHIFT 0xa ++#define PSX80_WRP_DTM_CNTL__refClk_Cntl_MASK 0x3000 ++#define PSX80_WRP_DTM_CNTL__refClk_Cntl__SHIFT 0xc ++#define PSX80_WRP_DTM_CNTL__dtmClk_Sel_Timer_MASK 0xc000 ++#define PSX80_WRP_DTM_CNTL__dtmClk_Sel_Timer__SHIFT 0xe ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy7_MASK 0x10000 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy7__SHIFT 0x10 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy8_MASK 0x20000 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy8__SHIFT 0x11 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy9_MASK 0x40000 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy9__SHIFT 0x12 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy10_MASK 0x80000 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy10__SHIFT 0x13 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy11_MASK 0x100000 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy11__SHIFT 0x14 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy12_MASK 0x200000 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy12__SHIFT 0x15 ++#define PSX80_WRP_DTM_CNTL__rxElasWidth_Cntl_MASK 0xc00000 ++#define PSX80_WRP_DTM_CNTL__rxElasWidth_Cntl__SHIFT 0x16 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy13_MASK 0x1000000 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy13__SHIFT 0x18 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy14_MASK 0x2000000 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy14__SHIFT 0x19 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy15_MASK 0x4000000 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy15__SHIFT 0x1a ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy16_MASK 0x8000000 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy16__SHIFT 0x1b ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy17_MASK 0x10000000 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy17__SHIFT 0x1c ++#define PSX80_WRP_DTM_CNTL__Warm_RstTimer_MASK 0x60000000 ++#define PSX80_WRP_DTM_CNTL__Warm_RstTimer__SHIFT 0x1d ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy18_MASK 0x80000000 ++#define PSX80_WRP_DTM_CNTL__Dtm_Dummy18__SHIFT 0x1f ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19_MASK 0x1 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19__SHIFT 0x0 ++#define PSX80_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK 0x2 ++#define PSX80_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout__SHIFT 0x1 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym_MASK 0x4 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT 0x2 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym_MASK 0x8 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym__SHIFT 0x3 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide_MASK 0x30 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide__SHIFT 0x4 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide_MASK 0xc0 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide__SHIFT 0x6 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide_MASK 0x300 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide__SHIFT 0x8 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period_MASK 0xf000 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period__SHIFT 0xc ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send_MASK 0xf0000 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send__SHIFT 0x10 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv_MASK 0xf00000 ++#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv__SHIFT 0x14 ++#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period_MASK 0x1ff ++#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period__SHIFT 0x0 ++#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send_MASK 0x3fe00 ++#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send__SHIFT 0x9 ++#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv_MASK 0x7fc0000 ++#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv__SHIFT 0x12 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x_MASK 0xff ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x__SHIFT 0x0 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x_MASK 0xff00 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x__SHIFT 0x8 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x_MASK 0xff0000 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x__SHIFT 0x10 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt_MASK 0xff ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt__SHIFT 0x0 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt_MASK 0xff00 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt__SHIFT 0x8 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt_MASK 0xff0000 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt__SHIFT 0x10 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x_MASK 0xff ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x__SHIFT 0x0 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x_MASK 0xff00 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x__SHIFT 0x8 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x_MASK 0xff0000 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x__SHIFT 0x10 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt_MASK 0xff ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt__SHIFT 0x0 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt_MASK 0xff00 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt__SHIFT 0x8 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt_MASK 0xff0000 ++#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt__SHIFT 0x10 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz_MASK 0x1 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz__SHIFT 0x0 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK 0x2 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock__SHIFT 0x1 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase_MASK 0x4 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT 0x2 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay_MASK 0x8 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay__SHIFT 0x3 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride_MASK 0xff00 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride__SHIFT 0x8 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle_MASK 0x10000 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle__SHIFT 0x10 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart_MASK 0x20000 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart__SHIFT 0x11 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart_MASK 0x40000 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart__SHIFT 0x12 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable_MASK 0x100000 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable__SHIFT 0x14 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable_MASK 0x200000 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable__SHIFT 0x15 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_spare_MASK 0xf0000000 ++#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_spare__SHIFT 0x1c ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle_MASK 0x1 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle__SHIFT 0x0 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK 0x2 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete__SHIFT 0x1 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked_MASK 0x4 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT 0x2 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld_MASK 0x8 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld__SHIFT 0x3 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld_MASK 0x10 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld__SHIFT 0x4 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue_MASK 0xff00 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue__SHIFT 0x8 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue_MASK 0xff0000 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue__SHIFT 0x10 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio_MASK 0x1f000000 ++#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio__SHIFT 0x18 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK 0x2 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN__SHIFT 0x1 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN_MASK 0x4 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT 0x2 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE_MASK 0x8 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE__SHIFT 0x3 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG_MASK 0x20 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG__SHIFT 0x5 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN_MASK 0x200 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN__SHIFT 0x9 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED_MASK 0x800 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED__SHIFT 0xb ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN_MASK 0x2000 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN__SHIFT 0xd ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN_MASK 0x200000 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN__SHIFT 0x15 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN_MASK 0x800000 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN__SHIFT 0x17 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN_MASK 0x10000000 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN__SHIFT 0x1c ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED_MASK 0x20000000 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED__SHIFT 0x1d ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED_MASK 0xc0000000 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED__SHIFT 0x1e ++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG_MASK 0x1ff8 ++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG__SHIFT 0x3 ++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ_MASK 0x6000 ++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ__SHIFT 0xd ++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG_MASK 0x1f8000 ++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG__SHIFT 0xf ++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS_MASK 0x200000 ++#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS__SHIFT 0x15 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK 0x2 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT 0x1 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE_MASK 0xc ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT 0x2 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE_MASK 0x10 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE__SHIFT 0x4 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE_MASK 0x400 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE__SHIFT 0xa ++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE_MASK 0x800 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE__SHIFT 0xb ++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN_MASK 0x2000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN__SHIFT 0xd ++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN_MASK 0x4000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN__SHIFT 0xe ++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x18000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0xf ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR_MASK 0x1 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK 0x2 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT 0x1 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK 0x4 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT 0x2 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK 0x10 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT 0x4 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK 0x20 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT 0x5 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR_MASK 0x40 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT 0x6 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR_MASK 0x200 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR_MASK 0x1000 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR__SHIFT 0xc ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS_MASK 0x10000 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS__SHIFT 0x10 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN_MASK 0x20000 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN__SHIFT 0x11 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN_MASK 0x40000 ++#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN__SHIFT 0x12 ++#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE_MASK 0x4000000 ++#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE__SHIFT 0x1a ++#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL_MASK 0xc0000000 ++#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL__SHIFT 0x1e ++#define PSX81_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT_MASK 0x1 ++#define PSX81_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN_MASK 0x1 ++#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK 0x2 ++#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION__SHIFT 0x1 ++#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING_MASK 0x4 ++#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT 0x2 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3_MASK 0x1 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN_MASK 0x4 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT 0x2 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x8 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x3 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP_MASK 0x70 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP__SHIFT 0x4 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x80 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x7 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS_MASK 0x100 ++#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS__SHIFT 0x8 ++#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID_MASK 0xffff ++#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID__SHIFT 0x0 ++#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID_MASK 0xffff0000 ++#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID__SHIFT 0x10 ++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x7 ++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0 ++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x38 ++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x3 ++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_MASK 0x3c0 ++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x6 ++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_MASK 0x3c00 ++#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET__SHIFT 0xa ++#define PSX81_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG_MASK 0xf ++#define PSX81_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG__SHIFT 0x0 ++#define PSX81_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING_MASK 0x1 ++#define PSX81_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 ++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT_MASK 0xc000 ++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT__SHIFT 0xe ++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 ++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 ++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 ++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 ++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 ++#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN_MASK 0x80 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 ++#define PSX81_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB_MASK 0x1 ++#define PSX81_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB__SHIFT 0x0 ++#define PSX81_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING_MASK 0x1 ++#define PSX81_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 ++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT_MASK 0xc000 ++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT__SHIFT 0xe ++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 ++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 ++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 ++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 ++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 ++#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN_MASK 0x80 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 ++#define PSX81_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB_MASK 0x1 ++#define PSX81_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB__SHIFT 0x0 ++#define PSX81_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING_MASK 0x1 ++#define PSX81_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 ++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT_MASK 0xc000 ++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT__SHIFT 0xe ++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 ++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 ++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 ++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 ++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 ++#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN_MASK 0x80 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 ++#define PSX81_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB_MASK 0x1 ++#define PSX81_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB__SHIFT 0x0 ++#define PSX81_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING_MASK 0x1 ++#define PSX81_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 ++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT_MASK 0xc000 ++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT__SHIFT 0xe ++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 ++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 ++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 ++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 ++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 ++#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN_MASK 0x80 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 ++#define PSX81_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB_MASK 0x1 ++#define PSX81_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB__SHIFT 0x0 ++#define PSX81_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING_MASK 0x1 ++#define PSX81_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS__SHIFT 0x10 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000 ++#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF__SHIFT 0x18 ++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT_MASK 0xc000 ++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT__SHIFT 0xe ++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000 ++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10 ++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000 ++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13 ++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000 ++#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000 ++#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN_MASK 0x80 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100 ++#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000 ++#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18 ++#define PSX81_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB_MASK 0x1 ++#define PSX81_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB__SHIFT 0x0 ++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1 ++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0 ++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2 ++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1 ++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4 ++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2 ++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8 ++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3 ++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10 ++#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4 ++#define PSX81_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff ++#define PSX81_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0 ++#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7 ++#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0 ++#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70 ++#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4 ++#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff ++#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0 ++#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000 ++#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10 ++#define PSX81_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff ++#define PSX81_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0 ++#define PSX81_WRP_LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff ++#define PSX81_WRP_LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0 ++#define PSX81_WRP_LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff ++#define PSX81_WRP_LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0 ++#define PSX81_WRP_PCIE_EFUSE__PCIE_EFUSE_MASK 0xffffffff ++#define PSX81_WRP_PCIE_EFUSE__PCIE_EFUSE__SHIFT 0x0 ++#define PSX81_WRP_PCIE_EFUSE2__PCIE_EFUSE2_MASK 0xffffffff ++#define PSX81_WRP_PCIE_EFUSE2__PCIE_EFUSE2__SHIFT 0x0 ++#define PSX81_WRP_PCIE_EFUSE3__PCIE_EFUSE3_MASK 0xffffffff ++#define PSX81_WRP_PCIE_EFUSE3__PCIE_EFUSE3__SHIFT 0x0 ++#define PSX81_WRP_PCIE_EFUSE4__PCIE_EFUSE4_MASK 0xffffffff ++#define PSX81_WRP_PCIE_EFUSE4__PCIE_EFUSE4__SHIFT 0x0 ++#define PSX81_WRP_PCIE_EFUSE5__PCIE_EFUSE5_MASK 0xffffffff ++#define PSX81_WRP_PCIE_EFUSE5__PCIE_EFUSE5__SHIFT 0x0 ++#define PSX81_WRP_PCIE_EFUSE6__PCIE_EFUSE6_MASK 0xffffffff ++#define PSX81_WRP_PCIE_EFUSE6__PCIE_EFUSE6__SHIFT 0x0 ++#define PSX81_WRP_PCIE_EFUSE7__PCIE_EFUSE7_MASK 0xffffffff ++#define PSX81_WRP_PCIE_EFUSE7__PCIE_EFUSE7__SHIFT 0x0 ++#define PSX81_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff ++#define PSX81_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0 ++#define PSX81_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff ++#define PSX81_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0 ++#define PSX81_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1 ++#define PSX81_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0 ++#define PSX81_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1 ++#define PSX81_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0 ++#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1 ++#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0 ++#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2 ++#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1 ++#define PSX81_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK 0x2 ++#define PSX81_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY__SHIFT 0x1 ++#define PSX81_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4 ++#define PSX81_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2 ++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7 ++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0 ++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70 ++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4 ++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80 ++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7 ++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100 ++#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8 ++#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xff ++#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0 ++#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000 ++#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10 ++#define PSX81_WRP_IMPCTL_CNTL_PIF0__ArbEn0_MASK 0x1 ++#define PSX81_WRP_IMPCTL_CNTL_PIF0__ArbEn0__SHIFT 0x0 ++#define PSX81_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0_MASK 0x800 ++#define PSX81_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0__SHIFT 0xb ++#define PSX81_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1 ++#define PSX81_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0 ++#define PSX81_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1 ++#define PSX81_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0 ++#define PSX81_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1 ++#define PSX81_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0 ++#define PSX81_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1 ++#define PSX81_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0 ++#define PSX81_WRP_BIOSTIMER_CMD__Microseconds_MASK 0xffffffff ++#define PSX81_WRP_BIOSTIMER_CMD__Microseconds__SHIFT 0x0 ++#define PSX81_WRP_BIOSTIMER_CNTL__ClockRate_MASK 0xff ++#define PSX81_WRP_BIOSTIMER_CNTL__ClockRate__SHIFT 0x0 ++#define PSX81_WRP_BIOSTIMER_DEBUG__Microseconds_compare_MASK 0xffffffff ++#define PSX81_WRP_BIOSTIMER_DEBUG__Microseconds_compare__SHIFT 0x0 ++#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl_MASK 0xff ++#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl__SHIFT 0x0 ++#define PSX81_WRP_DTM_RX_BP_CNTL__Dbg_Cntl_MASK 0xf0000 ++#define PSX81_WRP_DTM_RX_BP_CNTL__Dbg_Cntl__SHIFT 0x10 ++#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue_MASK 0xf00000 ++#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue__SHIFT 0x14 ++#define PSX81_WRP_DTM_RX_BP_CNTL__td_hold_training_override_MASK 0x1f000000 ++#define PSX81_WRP_DTM_RX_BP_CNTL__td_hold_training_override__SHIFT 0x18 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy0_MASK 0x1 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy0__SHIFT 0x0 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy1_MASK 0x2 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy1__SHIFT 0x1 ++#define PSX81_WRP_DTM_CNTL__Determinism_En_DTM_MASK 0x4 ++#define PSX81_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT 0x2 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy2_MASK 0x8 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy2__SHIFT 0x3 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy3_MASK 0x10 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy3__SHIFT 0x4 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy4_MASK 0x20 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy4__SHIFT 0x5 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy5_MASK 0x40 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy5__SHIFT 0x6 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy6_MASK 0x80 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy6__SHIFT 0x7 ++#define PSX81_WRP_DTM_CNTL__TxClk1x_Cntl_MASK 0x300 ++#define PSX81_WRP_DTM_CNTL__TxClk1x_Cntl__SHIFT 0x8 ++#define PSX81_WRP_DTM_CNTL__TxClkGskt_Cntl_MASK 0xc00 ++#define PSX81_WRP_DTM_CNTL__TxClkGskt_Cntl__SHIFT 0xa ++#define PSX81_WRP_DTM_CNTL__refClk_Cntl_MASK 0x3000 ++#define PSX81_WRP_DTM_CNTL__refClk_Cntl__SHIFT 0xc ++#define PSX81_WRP_DTM_CNTL__dtmClk_Sel_Timer_MASK 0xc000 ++#define PSX81_WRP_DTM_CNTL__dtmClk_Sel_Timer__SHIFT 0xe ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy7_MASK 0x10000 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy7__SHIFT 0x10 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy8_MASK 0x20000 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy8__SHIFT 0x11 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy9_MASK 0x40000 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy9__SHIFT 0x12 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy10_MASK 0x80000 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy10__SHIFT 0x13 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy11_MASK 0x100000 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy11__SHIFT 0x14 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy12_MASK 0x200000 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy12__SHIFT 0x15 ++#define PSX81_WRP_DTM_CNTL__rxElasWidth_Cntl_MASK 0xc00000 ++#define PSX81_WRP_DTM_CNTL__rxElasWidth_Cntl__SHIFT 0x16 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy13_MASK 0x1000000 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy13__SHIFT 0x18 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy14_MASK 0x2000000 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy14__SHIFT 0x19 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy15_MASK 0x4000000 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy15__SHIFT 0x1a ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy16_MASK 0x8000000 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy16__SHIFT 0x1b ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy17_MASK 0x10000000 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy17__SHIFT 0x1c ++#define PSX81_WRP_DTM_CNTL__Warm_RstTimer_MASK 0x60000000 ++#define PSX81_WRP_DTM_CNTL__Warm_RstTimer__SHIFT 0x1d ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy18_MASK 0x80000000 ++#define PSX81_WRP_DTM_CNTL__Dtm_Dummy18__SHIFT 0x1f ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19_MASK 0x1 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19__SHIFT 0x0 ++#define PSX81_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK 0x2 ++#define PSX81_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout__SHIFT 0x1 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym_MASK 0x4 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT 0x2 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym_MASK 0x8 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym__SHIFT 0x3 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide_MASK 0x30 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide__SHIFT 0x4 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide_MASK 0xc0 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide__SHIFT 0x6 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide_MASK 0x300 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide__SHIFT 0x8 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period_MASK 0xf000 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period__SHIFT 0xc ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send_MASK 0xf0000 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send__SHIFT 0x10 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv_MASK 0xf00000 ++#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv__SHIFT 0x14 ++#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period_MASK 0x1ff ++#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period__SHIFT 0x0 ++#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send_MASK 0x3fe00 ++#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send__SHIFT 0x9 ++#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv_MASK 0x7fc0000 ++#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv__SHIFT 0x12 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x_MASK 0xff ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x__SHIFT 0x0 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x_MASK 0xff00 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x__SHIFT 0x8 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x_MASK 0xff0000 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x__SHIFT 0x10 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt_MASK 0xff ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt__SHIFT 0x0 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt_MASK 0xff00 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt__SHIFT 0x8 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt_MASK 0xff0000 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt__SHIFT 0x10 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x_MASK 0xff ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x__SHIFT 0x0 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x_MASK 0xff00 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x__SHIFT 0x8 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x_MASK 0xff0000 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x__SHIFT 0x10 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt_MASK 0xff ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt__SHIFT 0x0 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt_MASK 0xff00 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt__SHIFT 0x8 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt_MASK 0xff0000 ++#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt__SHIFT 0x10 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz_MASK 0x1 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz__SHIFT 0x0 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK 0x2 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock__SHIFT 0x1 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase_MASK 0x4 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT 0x2 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay_MASK 0x8 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay__SHIFT 0x3 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride_MASK 0xff00 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride__SHIFT 0x8 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle_MASK 0x10000 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle__SHIFT 0x10 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart_MASK 0x20000 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart__SHIFT 0x11 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart_MASK 0x40000 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart__SHIFT 0x12 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable_MASK 0x100000 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable__SHIFT 0x14 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable_MASK 0x200000 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable__SHIFT 0x15 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_spare_MASK 0xf0000000 ++#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_spare__SHIFT 0x1c ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle_MASK 0x1 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle__SHIFT 0x0 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK 0x2 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete__SHIFT 0x1 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked_MASK 0x4 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT 0x2 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld_MASK 0x8 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld__SHIFT 0x3 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld_MASK 0x10 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld__SHIFT 0x4 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue_MASK 0xff00 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue__SHIFT 0x8 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue_MASK 0xff0000 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue__SHIFT 0x10 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio_MASK 0x1f000000 ++#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio__SHIFT 0x18 ++#define RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1 ++#define RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0 ++#define RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2 ++#define RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT 0x1 ++#define RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff ++#define RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0 ++#define RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000 ++#define RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e ++#define RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000 ++#define RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f ++#define RFE_IMPRST_CNTL__REG_RST_impEn_MASK 0x1 ++#define RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT 0x0 ++#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWRC_rst_MASK 0x1 ++#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWRC_rst__SHIFT 0x0 ++#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWRC_rst_MASK 0x2 ++#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWRC_rst__SHIFT 0x1 ++#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWRC_rst_MASK 0x4 ++#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWRC_rst__SHIFT 0x2 ++#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW0_rst_MASK 0x1 ++#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW0_rst__SHIFT 0x0 ++#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW1_rst_MASK 0x2 ++#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW1_rst__SHIFT 0x1 ++#define RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWRC_rst_MASK 0x4 ++#define RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWRC_rst__SHIFT 0x2 ++#define RFE_PWDN_COMMAND__REG_PCIEW0_pw_cmd_MASK 0x1 ++#define RFE_PWDN_COMMAND__REG_PCIEW0_pw_cmd__SHIFT 0x0 ++#define RFE_PWDN_COMMAND__REG_PCIEW1_pw_cmd_MASK 0x2 ++#define RFE_PWDN_COMMAND__REG_PCIEW1_pw_cmd__SHIFT 0x1 ++#define RFE_PWDN_COMMAND__REG_RWREG_RFEWRC_pw_cmd_MASK 0x4 ++#define RFE_PWDN_COMMAND__REG_RWREG_RFEWRC_pw_cmd__SHIFT 0x2 ++#define RFE_PWDN_STATUS__PCIEW0_REG_pw_status_MASK 0x1 ++#define RFE_PWDN_STATUS__PCIEW0_REG_pw_status__SHIFT 0x0 ++#define RFE_PWDN_STATUS__PCIEW1_REG_pw_status_MASK 0x2 ++#define RFE_PWDN_STATUS__PCIEW1_REG_pw_status__SHIFT 0x1 ++#define RFE_PWDN_STATUS__RWREG_RFEWRC_REG_pw_status_MASK 0x4 ++#define RFE_PWDN_STATUS__RWREG_RFEWRC_REG_pw_status__SHIFT 0x2 ++#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkGate_timer_MASK 0xff ++#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkGate_timer__SHIFT 0x0 ++#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkSetup_timer_MASK 0xf00 ++#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkSetup_timer__SHIFT 0x8 ++#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_timeout_timer_MASK 0xff0000 ++#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_timeout_timer__SHIFT 0x10 ++#define RFE_MST_PCIEW0_CMDSTATUS__PCIEW0_RFE_mstTimeout_MASK 0x1000000 ++#define RFE_MST_PCIEW0_CMDSTATUS__PCIEW0_RFE_mstTimeout__SHIFT 0x18 ++#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkGate_timer_MASK 0xff ++#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkGate_timer__SHIFT 0x0 ++#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkSetup_timer_MASK 0xf00 ++#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkSetup_timer__SHIFT 0x8 ++#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_timeout_timer_MASK 0xff0000 ++#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_timeout_timer__SHIFT 0x10 ++#define RFE_MST_PCIEW1_CMDSTATUS__PCIEW1_RFE_mstTimeout_MASK 0x1000000 ++#define RFE_MST_PCIEW1_CMDSTATUS__PCIEW1_RFE_mstTimeout__SHIFT 0x18 ++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkGate_timer_MASK 0xff ++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkGate_timer__SHIFT 0x0 ++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkSetup_timer_MASK 0xf00 ++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkSetup_timer__SHIFT 0x8 ++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_timeout_timer_MASK 0xff0000 ++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_timeout_timer__SHIFT 0x10 ++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__RWREG_RFEWRC_RFE_mstTimeout_MASK 0x1000000 ++#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__RWREG_RFEWRC_RFE_mstTimeout__SHIFT 0x18 ++#define RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1 ++#define RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0 ++#define RFE_IMPARBH_STATUS__IMPAH_REG_calDone_MASK 0x1 ++#define RFE_IMPARBH_STATUS__IMPAH_REG_calDone__SHIFT 0x0 ++#define RFE_IMPARBH_CONTROL__REG_IMPA_throttleTimer_MASK 0x3ff ++#define RFE_IMPARBH_CONTROL__REG_IMPA_throttleTimer__SHIFT 0x0 ++#define PSX80_BIF_PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff ++#define PSX80_BIF_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 ++#define PSX80_BIF_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff ++#define PSX80_BIF_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define PSX80_BIF_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define PSX80_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff ++#define PSX80_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 ++#define PSX80_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff ++#define PSX80_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 ++#define PSX80_BIF_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1 ++#define PSX80_BIF_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 ++#define PSX80_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe ++#define PSX80_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 ++#define PSX80_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80 ++#define PSX80_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 ++#define PSX80_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100 ++#define PSX80_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 ++#define PSX80_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200 ++#define PSX80_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 ++#define PSX80_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00 ++#define PSX80_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000 ++#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 ++#define PSX80_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000 ++#define PSX80_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 ++#define PSX80_BIF_PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000 ++#define PSX80_BIF_PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18 ++#define PSX80_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000 ++#define PSX80_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e ++#define PSX80_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000 ++#define PSX80_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f ++#define PSX80_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf ++#define PSX80_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 ++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000 ++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000 ++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 ++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000 ++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 ++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000 ++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 ++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000 ++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 ++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000 ++#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 ++#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff ++#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0 ++#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100 ++#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8 ++#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000 ++#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10 ++#define PSX80_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1 ++#define PSX80_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 ++#define PSX80_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e ++#define PSX80_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 ++#define PSX80_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0 ++#define PSX80_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 ++#define PSX80_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800 ++#define PSX80_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb ++#define PSX80_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000 ++#define PSX80_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc ++#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000 ++#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd ++#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000 ++#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe ++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 ++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 ++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000 ++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 ++#define PSX80_BIF_PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000 ++#define PSX80_BIF_PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 ++#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000 ++#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 ++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000 ++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 ++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000 ++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 ++#define PSX80_BIF_PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000 ++#define PSX80_BIF_PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 ++#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000 ++#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 ++#define PSX80_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000 ++#define PSX80_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 ++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000 ++#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d ++#define PSX80_BIF_PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000 ++#define PSX80_BIF_PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e ++#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000 ++#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 ++#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000 ++#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc ++#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000 ++#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd ++#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000 ++#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000 ++#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 ++#define PSX80_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000 ++#define PSX80_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3 ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30 ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0 ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300 ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00 ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000 ++#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000 ++#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc ++#define PSX80_BIF_PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40 ++#define PSX80_BIF_PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 ++#define PSX80_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80 ++#define PSX80_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 ++#define PSX80_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000 ++#define PSX80_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc ++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f ++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 ++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00 ++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 ++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000 ++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 ++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000 ++#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 ++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f ++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 ++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00 ++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 ++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000 ++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 ++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000 ++#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 ++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f ++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 ++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00 ++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 ++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000 ++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 ++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000 ++#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 ++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f ++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 ++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00 ++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 ++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000 ++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 ++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000 ++#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 ++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f ++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 ++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00 ++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 ++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000 ++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 ++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000 ++#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 ++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f ++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 ++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00 ++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 ++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000 ++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 ++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000 ++#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 ++#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1 ++#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 ++#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2 ++#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 ++#define PSX80_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c ++#define PSX80_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 ++#define PSX80_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0 ++#define PSX80_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 ++#define PSX80_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff ++#define PSX80_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 ++#define PSX80_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000 ++#define PSX80_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40 ++#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 ++#define PSX80_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff ++#define PSX80_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 ++#define PSX80_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff ++#define PSX80_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 ++#define PSX80_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff ++#define PSX80_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 ++#define PSX80_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff ++#define PSX80_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 ++#define PSX80_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff ++#define PSX80_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 ++#define PSX80_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff ++#define PSX80_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 ++#define PSX80_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff ++#define PSX80_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 ++#define PSX80_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff ++#define PSX80_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 ++#define PSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff ++#define PSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 ++#define PSX80_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff ++#define PSX80_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 ++#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1 ++#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 ++#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2 ++#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 ++#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4 ++#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 ++#define PSX80_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1 ++#define PSX80_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0 ++#define PSX80_BIF_PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1 ++#define PSX80_BIF_PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 ++#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2 ++#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 ++#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4 ++#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2 ++#define PSX80_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8 ++#define PSX80_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3 ++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10 ++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 ++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20 ++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 ++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40 ++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 ++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80 ++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 ++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100 ++#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 ++#define PSX80_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000 ++#define PSX80_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc ++#define PSX80_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000 ++#define PSX80_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd ++#define PSX80_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000 ++#define PSX80_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe ++#define PSX80_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000 ++#define PSX80_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 ++#define PSX80_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff ++#define PSX80_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 ++#define PSX80_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000 ++#define PSX80_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 ++#define PSX80_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff ++#define PSX80_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 ++#define PSX80_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff ++#define PSX80_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 ++#define PSX80_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000 ++#define PSX80_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 ++#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff ++#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 ++#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00 ++#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 ++#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1 ++#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2 ++#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 ++#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4 ++#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000 ++#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000 ++#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10 ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4 ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000 ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000 ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19 ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000 ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000 ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000 ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000 ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000 ++#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f ++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x1 ++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0 ++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2 ++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1 ++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4 ++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 ++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8 ++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3 ++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10 ++#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 ++#define PSX80_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1 ++#define PSX80_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0 ++#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000 ++#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c ++#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000 ++#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d ++#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f ++#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0 ++#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80 ++#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7 ++#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff ++#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000 ++#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10 ++#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000 ++#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18 ++#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff ++#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000 ++#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 ++#define PSX80_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff ++#define PSX80_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff ++#define PSX80_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_EN_MASK 0x1 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000 ++#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 ++#define PSX80_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff ++#define PSX80_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff ++#define PSX80_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff ++#define PSX80_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 ++#define PSX80_BIF_SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1 ++#define PSX80_BIF_SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0 ++#define PSX80_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2 ++#define PSX80_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1 ++#define PSX80_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000 ++#define PSX80_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10 ++#define PSX80_BIF_SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000 ++#define PSX80_BIF_SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000 ++#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000 ++#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16 ++#define PSX80_BIF_SWRST_COMMAND_1__SWITCHCLK_MASK 0x1 ++#define PSX80_BIF_SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETPCFG_MASK 0x2 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM0_MASK 0x10 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM1_MASK 0x20 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETLC_MASK 0x40 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETLC__SHIFT 0x6 ++#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100 ++#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8 ++#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200 ++#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETMNTR_MASK 0x2000 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd ++#define PSX80_BIF_SWRST_COMMAND_1__RESETHLTR_MASK 0x4000 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe ++#define PSX80_BIF_SWRST_COMMAND_1__RESETCPM_MASK 0x8000 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETCPM__SHIFT 0xf ++#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF0_MASK 0x10000 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF1_MASK 0x20000 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000 ++#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19 ++#define PSX80_BIF_SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000 ++#define PSX80_BIF_SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c ++#define PSX80_BIF_SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000 ++#define PSX80_BIF_SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d ++#define PSX80_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000 ++#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16 ++#define PSX80_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1 ++#define PSX80_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6 ++#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100 ++#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8 ++#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200 ++#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd ++#define PSX80_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe ++#define PSX80_BIF_SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf ++#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000 ++#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19 ++#define PSX80_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000 ++#define PSX80_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c ++#define PSX80_BIF_SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000 ++#define PSX80_BIF_SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d ++#define PSX80_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000 ++#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16 ++#define PSX80_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1 ++#define PSX80_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6 ++#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100 ++#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8 ++#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200 ++#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd ++#define PSX80_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe ++#define PSX80_BIF_SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf ++#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000 ++#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19 ++#define PSX80_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000 ++#define PSX80_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c ++#define PSX80_BIF_SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000 ++#define PSX80_BIF_SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d ++#define PSX80_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000 ++#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16 ++#define PSX80_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1 ++#define PSX80_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6 ++#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100 ++#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8 ++#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200 ++#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000 ++#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19 ++#define PSX80_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000 ++#define PSX80_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c ++#define PSX80_BIF_SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000 ++#define PSX80_BIF_SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d ++#define PSX80_BIF_SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1 ++#define PSX80_BIF_SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0 ++#define PSX80_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100 ++#define PSX80_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8 ++#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1 ++#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7 ++#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100 ++#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8 ++#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200 ++#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa ++#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb ++#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc ++#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000 ++#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd ++#define PSX80_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000 ++#define PSX80_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe ++#define PSX80_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000 ++#define PSX80_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf ++#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000 ++#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10 ++#define PSX80_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000 ++#define PSX80_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11 ++#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000 ++#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14 ++#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000 ++#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15 ++#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000 ++#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16 ++#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000 ++#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17 ++#define PSX80_BIF_CPM_CONTROL__SPARE_REGS_MASK 0xff000000 ++#define PSX80_BIF_CPM_CONTROL__SPARE_REGS__SHIFT 0x18 ++#define PSX80_BIF_LM_CONTROL__LoopbackSelect_MASK 0x1e ++#define PSX80_BIF_LM_CONTROL__LoopbackSelect__SHIFT 0x1 ++#define PSX80_BIF_LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20 ++#define PSX80_BIF_LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5 ++#define PSX80_BIF_LM_CONTROL__LoopbackHalfRate_MASK 0xc0 ++#define PSX80_BIF_LM_CONTROL__LoopbackHalfRate__SHIFT 0x6 ++#define PSX80_BIF_LM_CONTROL__LoopbackFifoPtr_MASK 0x700 ++#define PSX80_BIF_LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8 ++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE0_MASK 0xff ++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE0__SHIFT 0x0 ++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE1_MASK 0xff00 ++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE1__SHIFT 0x8 ++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE2_MASK 0xff0000 ++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE2__SHIFT 0x10 ++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE3_MASK 0xff000000 ++#define PSX80_BIF_LM_PCIETXMUX0__TXLANE3__SHIFT 0x18 ++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE4_MASK 0xff ++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE4__SHIFT 0x0 ++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE5_MASK 0xff00 ++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE5__SHIFT 0x8 ++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE6_MASK 0xff0000 ++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE6__SHIFT 0x10 ++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE7_MASK 0xff000000 ++#define PSX80_BIF_LM_PCIETXMUX1__TXLANE7__SHIFT 0x18 ++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE8_MASK 0xff ++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE8__SHIFT 0x0 ++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE9_MASK 0xff00 ++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE9__SHIFT 0x8 ++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE10_MASK 0xff0000 ++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE10__SHIFT 0x10 ++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE11_MASK 0xff000000 ++#define PSX80_BIF_LM_PCIETXMUX2__TXLANE11__SHIFT 0x18 ++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE12_MASK 0xff ++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE12__SHIFT 0x0 ++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE13_MASK 0xff00 ++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE13__SHIFT 0x8 ++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE14_MASK 0xff0000 ++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE14__SHIFT 0x10 ++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE15_MASK 0xff000000 ++#define PSX80_BIF_LM_PCIETXMUX3__TXLANE15__SHIFT 0x18 ++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE0_MASK 0xff ++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE0__SHIFT 0x0 ++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE1_MASK 0xff00 ++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE1__SHIFT 0x8 ++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE2_MASK 0xff0000 ++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE2__SHIFT 0x10 ++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE3_MASK 0xff000000 ++#define PSX80_BIF_LM_PCIERXMUX0__RXLANE3__SHIFT 0x18 ++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE4_MASK 0xff ++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE4__SHIFT 0x0 ++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE5_MASK 0xff00 ++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE5__SHIFT 0x8 ++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE6_MASK 0xff0000 ++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE6__SHIFT 0x10 ++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE7_MASK 0xff000000 ++#define PSX80_BIF_LM_PCIERXMUX1__RXLANE7__SHIFT 0x18 ++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE8_MASK 0xff ++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE8__SHIFT 0x0 ++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE9_MASK 0xff00 ++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE9__SHIFT 0x8 ++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE10_MASK 0xff0000 ++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE10__SHIFT 0x10 ++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE11_MASK 0xff000000 ++#define PSX80_BIF_LM_PCIERXMUX2__RXLANE11__SHIFT 0x18 ++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE12_MASK 0xff ++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE12__SHIFT 0x0 ++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE13_MASK 0xff00 ++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE13__SHIFT 0x8 ++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE14_MASK 0xff0000 ++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE14__SHIFT 0x10 ++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE15_MASK 0xff000000 ++#define PSX80_BIF_LM_PCIERXMUX3__RXLANE15__SHIFT 0x18 ++#define PSX80_BIF_LM_LANEENABLE__LANE_enable_MASK 0xffff ++#define PSX80_BIF_LM_LANEENABLE__LANE_enable__SHIFT 0x0 ++#define PSX80_BIF_LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff ++#define PSX80_BIF_LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0 ++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000 ++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c ++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000 ++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d ++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000 ++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e ++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000 ++#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f ++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7 ++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0 ++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38 ++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3 ++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0 ++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6 ++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700 ++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8 ++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800 ++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb ++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000 ++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe ++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000 ++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10 ++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000 ++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13 ++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000 ++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16 ++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000 ++#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18 ++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000 ++#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b ++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000 ++#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn0_MASK 0x1 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2 ++#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit0_MASK 0x20 ++#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5 ++#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40 ++#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7 ++#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph0_MASK 0x100 ++#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn1_MASK 0x200 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb ++#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000 ++#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe ++#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000 ++#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10 ++#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph1_MASK 0x20000 ++#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn2_MASK 0x40000 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14 ++#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000 ++#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17 ++#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000 ++#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000 ++#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19 ++#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000 ++#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a ++#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000 ++#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b ++#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000 ++#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d ++#define PSX80_BIF_LM_POWERCONTROL2__LMTxEn3_MASK 0x1 ++#define PSX80_BIF_LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0 ++#define PSX80_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2 ++#define PSX80_BIF_LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1 ++#define PSX80_BIF_LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c ++#define PSX80_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2 ++#define PSX80_BIF_LM_POWERCONTROL2__LMSkipBit3_MASK 0x20 ++#define PSX80_BIF_LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5 ++#define PSX80_BIF_LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40 ++#define PSX80_BIF_LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6 ++#define PSX80_BIF_LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80 ++#define PSX80_BIF_LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7 ++#define PSX80_BIF_LM_POWERCONTROL2__LMDeemph3_MASK 0x100 ++#define PSX80_BIF_LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8 ++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID2_MASK 0x600 ++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9 ++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800 ++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb ++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000 ++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd ++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000 ++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13 ++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000 ++#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19 ++#define PSX80_BIF_LM_POWERCONTROL3__TxCoeff3_MASK 0x3f ++#define PSX80_BIF_LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0 ++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0 ++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6 ++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000 ++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc ++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000 ++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12 ++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000 ++#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18 ++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum0_MASK 0x7 ++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum0__SHIFT 0x0 ++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum1_MASK 0x38 ++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum1__SHIFT 0x3 ++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum2_MASK 0x1c0 ++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum2__SHIFT 0x6 ++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum3_MASK 0xe00 ++#define PSX80_BIF_LM_POWERCONTROL4__LinkNum3__SHIFT 0x9 ++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum0_MASK 0xf000 ++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum0__SHIFT 0xc ++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum1_MASK 0xf0000 ++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum1__SHIFT 0x10 ++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum2_MASK 0xf00000 ++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum2__SHIFT 0x14 ++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum3_MASK 0xf000000 ++#define PSX80_BIF_LM_POWERCONTROL4__LaneNum3__SHIFT 0x18 ++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode0_MASK 0x10000000 ++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c ++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode1_MASK 0x20000000 ++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d ++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode2_MASK 0x40000000 ++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e ++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode3_MASK 0x80000000 ++#define PSX80_BIF_LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f ++#define PSX81_BIF_PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff ++#define PSX81_BIF_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 ++#define PSX81_BIF_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff ++#define PSX81_BIF_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define PSX81_BIF_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define PSX81_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff ++#define PSX81_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0 ++#define PSX81_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff ++#define PSX81_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0 ++#define PSX81_BIF_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1 ++#define PSX81_BIF_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 ++#define PSX81_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe ++#define PSX81_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1 ++#define PSX81_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80 ++#define PSX81_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 ++#define PSX81_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100 ++#define PSX81_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 ++#define PSX81_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200 ++#define PSX81_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9 ++#define PSX81_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00 ++#define PSX81_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000 ++#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16 ++#define PSX81_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000 ++#define PSX81_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17 ++#define PSX81_BIF_PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000 ++#define PSX81_BIF_PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18 ++#define PSX81_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000 ++#define PSX81_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e ++#define PSX81_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000 ++#define PSX81_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f ++#define PSX81_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf ++#define PSX81_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0 ++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000 ++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10 ++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000 ++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11 ++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000 ++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14 ++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000 ++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15 ++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000 ++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18 ++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000 ++#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 ++#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff ++#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0 ++#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100 ++#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8 ++#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000 ++#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10 ++#define PSX81_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1 ++#define PSX81_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0 ++#define PSX81_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e ++#define PSX81_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1 ++#define PSX81_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0 ++#define PSX81_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6 ++#define PSX81_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800 ++#define PSX81_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb ++#define PSX81_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000 ++#define PSX81_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc ++#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000 ++#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd ++#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000 ++#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe ++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 ++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10 ++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000 ++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11 ++#define PSX81_BIF_PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000 ++#define PSX81_BIF_PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12 ++#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000 ++#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13 ++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000 ++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14 ++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000 ++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15 ++#define PSX81_BIF_PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000 ++#define PSX81_BIF_PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16 ++#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000 ++#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17 ++#define PSX81_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000 ++#define PSX81_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18 ++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000 ++#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d ++#define PSX81_BIF_PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000 ++#define PSX81_BIF_PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e ++#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000 ++#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9 ++#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000 ++#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc ++#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000 ++#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd ++#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000 ++#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000 ++#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10 ++#define PSX81_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000 ++#define PSX81_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3 ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0 ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2 ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30 ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4 ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0 ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6 ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300 ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8 ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00 ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000 ++#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000 ++#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc ++#define PSX81_BIF_PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40 ++#define PSX81_BIF_PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6 ++#define PSX81_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80 ++#define PSX81_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 ++#define PSX81_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000 ++#define PSX81_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc ++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f ++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0 ++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00 ++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8 ++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000 ++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10 ++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000 ++#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18 ++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f ++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0 ++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00 ++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8 ++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000 ++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10 ++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000 ++#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18 ++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f ++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0 ++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00 ++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8 ++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000 ++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10 ++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000 ++#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18 ++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f ++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0 ++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00 ++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8 ++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000 ++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10 ++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000 ++#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18 ++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f ++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0 ++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00 ++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8 ++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000 ++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10 ++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000 ++#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18 ++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f ++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0 ++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00 ++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8 ++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000 ++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10 ++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000 ++#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18 ++#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1 ++#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0 ++#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2 ++#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1 ++#define PSX81_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c ++#define PSX81_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2 ++#define PSX81_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0 ++#define PSX81_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5 ++#define PSX81_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff ++#define PSX81_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0 ++#define PSX81_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000 ++#define PSX81_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40 ++#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6 ++#define PSX81_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff ++#define PSX81_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0 ++#define PSX81_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff ++#define PSX81_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0 ++#define PSX81_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff ++#define PSX81_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0 ++#define PSX81_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff ++#define PSX81_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0 ++#define PSX81_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff ++#define PSX81_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0 ++#define PSX81_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff ++#define PSX81_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0 ++#define PSX81_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff ++#define PSX81_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0 ++#define PSX81_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff ++#define PSX81_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0 ++#define PSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff ++#define PSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0 ++#define PSX81_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff ++#define PSX81_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0 ++#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1 ++#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 ++#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2 ++#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 ++#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4 ++#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 ++#define PSX81_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1 ++#define PSX81_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0 ++#define PSX81_BIF_PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1 ++#define PSX81_BIF_PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0 ++#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2 ++#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1 ++#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4 ++#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2 ++#define PSX81_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8 ++#define PSX81_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3 ++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10 ++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4 ++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20 ++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5 ++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40 ++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6 ++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80 ++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7 ++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100 ++#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8 ++#define PSX81_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000 ++#define PSX81_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc ++#define PSX81_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000 ++#define PSX81_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd ++#define PSX81_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000 ++#define PSX81_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe ++#define PSX81_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000 ++#define PSX81_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10 ++#define PSX81_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff ++#define PSX81_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0 ++#define PSX81_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000 ++#define PSX81_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10 ++#define PSX81_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff ++#define PSX81_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0 ++#define PSX81_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff ++#define PSX81_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0 ++#define PSX81_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000 ++#define PSX81_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10 ++#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff ++#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0 ++#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00 ++#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8 ++#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1 ++#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2 ++#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1 ++#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4 ++#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000 ++#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000 ++#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18 ++#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000 ++#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10 ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4 ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000 ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000 ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19 ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000 ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000 ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000 ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000 ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000 ++#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f ++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x1 ++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0 ++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2 ++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1 ++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4 ++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 ++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8 ++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3 ++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10 ++#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 ++#define PSX81_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1 ++#define PSX81_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0 ++#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000 ++#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c ++#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000 ++#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d ++#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f ++#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0 ++#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80 ++#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7 ++#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff ++#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000 ++#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10 ++#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000 ++#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18 ++#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff ++#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000 ++#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10 ++#define PSX81_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff ++#define PSX81_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff ++#define PSX81_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_EN_MASK 0x1 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000 ++#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10 ++#define PSX81_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff ++#define PSX81_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff ++#define PSX81_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0 ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff ++#define PSX81_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0 ++#define PSX81_BIF_SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1 ++#define PSX81_BIF_SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0 ++#define PSX81_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2 ++#define PSX81_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1 ++#define PSX81_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000 ++#define PSX81_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10 ++#define PSX81_BIF_SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000 ++#define PSX81_BIF_SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000 ++#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000 ++#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16 ++#define PSX81_BIF_SWRST_COMMAND_1__SWITCHCLK_MASK 0x1 ++#define PSX81_BIF_SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETPCFG_MASK 0x2 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM0_MASK 0x10 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM1_MASK 0x20 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETLC_MASK 0x40 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETLC__SHIFT 0x6 ++#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100 ++#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8 ++#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200 ++#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETMNTR_MASK 0x2000 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd ++#define PSX81_BIF_SWRST_COMMAND_1__RESETHLTR_MASK 0x4000 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe ++#define PSX81_BIF_SWRST_COMMAND_1__RESETCPM_MASK 0x8000 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETCPM__SHIFT 0xf ++#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF0_MASK 0x10000 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF1_MASK 0x20000 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000 ++#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19 ++#define PSX81_BIF_SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000 ++#define PSX81_BIF_SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c ++#define PSX81_BIF_SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000 ++#define PSX81_BIF_SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d ++#define PSX81_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000 ++#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16 ++#define PSX81_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1 ++#define PSX81_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6 ++#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100 ++#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8 ++#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200 ++#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd ++#define PSX81_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe ++#define PSX81_BIF_SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf ++#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000 ++#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19 ++#define PSX81_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000 ++#define PSX81_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c ++#define PSX81_BIF_SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000 ++#define PSX81_BIF_SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d ++#define PSX81_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000 ++#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16 ++#define PSX81_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1 ++#define PSX81_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6 ++#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100 ++#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8 ++#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200 ++#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd ++#define PSX81_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe ++#define PSX81_BIF_SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf ++#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000 ++#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19 ++#define PSX81_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000 ++#define PSX81_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c ++#define PSX81_BIF_SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000 ++#define PSX81_BIF_SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d ++#define PSX81_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000 ++#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16 ++#define PSX81_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1 ++#define PSX81_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6 ++#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100 ++#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8 ++#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200 ++#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000 ++#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19 ++#define PSX81_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000 ++#define PSX81_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c ++#define PSX81_BIF_SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000 ++#define PSX81_BIF_SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d ++#define PSX81_BIF_SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1 ++#define PSX81_BIF_SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0 ++#define PSX81_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100 ++#define PSX81_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8 ++#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1 ++#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7 ++#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100 ++#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8 ++#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200 ++#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa ++#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb ++#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc ++#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000 ++#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd ++#define PSX81_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000 ++#define PSX81_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe ++#define PSX81_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000 ++#define PSX81_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf ++#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000 ++#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10 ++#define PSX81_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000 ++#define PSX81_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11 ++#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000 ++#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14 ++#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000 ++#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15 ++#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000 ++#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16 ++#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000 ++#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17 ++#define PSX81_BIF_CPM_CONTROL__SPARE_REGS_MASK 0xff000000 ++#define PSX81_BIF_CPM_CONTROL__SPARE_REGS__SHIFT 0x18 ++#define PSX81_BIF_LM_CONTROL__LoopbackSelect_MASK 0x1e ++#define PSX81_BIF_LM_CONTROL__LoopbackSelect__SHIFT 0x1 ++#define PSX81_BIF_LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20 ++#define PSX81_BIF_LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5 ++#define PSX81_BIF_LM_CONTROL__LoopbackHalfRate_MASK 0xc0 ++#define PSX81_BIF_LM_CONTROL__LoopbackHalfRate__SHIFT 0x6 ++#define PSX81_BIF_LM_CONTROL__LoopbackFifoPtr_MASK 0x700 ++#define PSX81_BIF_LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8 ++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE0_MASK 0xff ++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE0__SHIFT 0x0 ++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE1_MASK 0xff00 ++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE1__SHIFT 0x8 ++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE2_MASK 0xff0000 ++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE2__SHIFT 0x10 ++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE3_MASK 0xff000000 ++#define PSX81_BIF_LM_PCIETXMUX0__TXLANE3__SHIFT 0x18 ++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE4_MASK 0xff ++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE4__SHIFT 0x0 ++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE5_MASK 0xff00 ++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE5__SHIFT 0x8 ++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE6_MASK 0xff0000 ++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE6__SHIFT 0x10 ++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE7_MASK 0xff000000 ++#define PSX81_BIF_LM_PCIETXMUX1__TXLANE7__SHIFT 0x18 ++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE8_MASK 0xff ++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE8__SHIFT 0x0 ++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE9_MASK 0xff00 ++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE9__SHIFT 0x8 ++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE10_MASK 0xff0000 ++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE10__SHIFT 0x10 ++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE11_MASK 0xff000000 ++#define PSX81_BIF_LM_PCIETXMUX2__TXLANE11__SHIFT 0x18 ++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE12_MASK 0xff ++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE12__SHIFT 0x0 ++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE13_MASK 0xff00 ++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE13__SHIFT 0x8 ++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE14_MASK 0xff0000 ++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE14__SHIFT 0x10 ++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE15_MASK 0xff000000 ++#define PSX81_BIF_LM_PCIETXMUX3__TXLANE15__SHIFT 0x18 ++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE0_MASK 0xff ++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE0__SHIFT 0x0 ++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE1_MASK 0xff00 ++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE1__SHIFT 0x8 ++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE2_MASK 0xff0000 ++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE2__SHIFT 0x10 ++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE3_MASK 0xff000000 ++#define PSX81_BIF_LM_PCIERXMUX0__RXLANE3__SHIFT 0x18 ++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE4_MASK 0xff ++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE4__SHIFT 0x0 ++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE5_MASK 0xff00 ++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE5__SHIFT 0x8 ++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE6_MASK 0xff0000 ++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE6__SHIFT 0x10 ++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE7_MASK 0xff000000 ++#define PSX81_BIF_LM_PCIERXMUX1__RXLANE7__SHIFT 0x18 ++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE8_MASK 0xff ++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE8__SHIFT 0x0 ++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE9_MASK 0xff00 ++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE9__SHIFT 0x8 ++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE10_MASK 0xff0000 ++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE10__SHIFT 0x10 ++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE11_MASK 0xff000000 ++#define PSX81_BIF_LM_PCIERXMUX2__RXLANE11__SHIFT 0x18 ++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE12_MASK 0xff ++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE12__SHIFT 0x0 ++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE13_MASK 0xff00 ++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE13__SHIFT 0x8 ++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE14_MASK 0xff0000 ++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE14__SHIFT 0x10 ++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE15_MASK 0xff000000 ++#define PSX81_BIF_LM_PCIERXMUX3__RXLANE15__SHIFT 0x18 ++#define PSX81_BIF_LM_LANEENABLE__LANE_enable_MASK 0xffff ++#define PSX81_BIF_LM_LANEENABLE__LANE_enable__SHIFT 0x0 ++#define PSX81_BIF_LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff ++#define PSX81_BIF_LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0 ++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000 ++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c ++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000 ++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d ++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000 ++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e ++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000 ++#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f ++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7 ++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0 ++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38 ++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3 ++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0 ++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6 ++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700 ++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8 ++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800 ++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb ++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000 ++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe ++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000 ++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10 ++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000 ++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13 ++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000 ++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16 ++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000 ++#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18 ++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000 ++#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b ++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000 ++#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn0_MASK 0x1 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2 ++#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit0_MASK 0x20 ++#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5 ++#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40 ++#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7 ++#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph0_MASK 0x100 ++#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn1_MASK 0x200 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb ++#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000 ++#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe ++#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000 ++#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10 ++#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph1_MASK 0x20000 ++#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn2_MASK 0x40000 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14 ++#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000 ++#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17 ++#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000 ++#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000 ++#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19 ++#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000 ++#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a ++#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000 ++#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b ++#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000 ++#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d ++#define PSX81_BIF_LM_POWERCONTROL2__LMTxEn3_MASK 0x1 ++#define PSX81_BIF_LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0 ++#define PSX81_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2 ++#define PSX81_BIF_LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1 ++#define PSX81_BIF_LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c ++#define PSX81_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2 ++#define PSX81_BIF_LM_POWERCONTROL2__LMSkipBit3_MASK 0x20 ++#define PSX81_BIF_LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5 ++#define PSX81_BIF_LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40 ++#define PSX81_BIF_LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6 ++#define PSX81_BIF_LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80 ++#define PSX81_BIF_LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7 ++#define PSX81_BIF_LM_POWERCONTROL2__LMDeemph3_MASK 0x100 ++#define PSX81_BIF_LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8 ++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID2_MASK 0x600 ++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9 ++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800 ++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb ++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000 ++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd ++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000 ++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13 ++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000 ++#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19 ++#define PSX81_BIF_LM_POWERCONTROL3__TxCoeff3_MASK 0x3f ++#define PSX81_BIF_LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0 ++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0 ++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6 ++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000 ++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc ++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000 ++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12 ++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000 ++#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18 ++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum0_MASK 0x7 ++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum0__SHIFT 0x0 ++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum1_MASK 0x38 ++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum1__SHIFT 0x3 ++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum2_MASK 0x1c0 ++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum2__SHIFT 0x6 ++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum3_MASK 0xe00 ++#define PSX81_BIF_LM_POWERCONTROL4__LinkNum3__SHIFT 0x9 ++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum0_MASK 0xf000 ++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum0__SHIFT 0xc ++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum1_MASK 0xf0000 ++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum1__SHIFT 0x10 ++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum2_MASK 0xf00000 ++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum2__SHIFT 0x14 ++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum3_MASK 0xf000000 ++#define PSX81_BIF_LM_POWERCONTROL4__LaneNum3__SHIFT 0x18 ++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode0_MASK 0x10000000 ++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c ++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode1_MASK 0x20000000 ++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d ++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode2_MASK 0x40000000 ++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e ++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode3_MASK 0x80000000 ++#define PSX81_BIF_LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_valid_MASK 0x1 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_valid__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel_MASK 0x6 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel__SHIFT 0x1 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable_MASK 0x8 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable__SHIFT 0x3 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12_MASK 0xf0 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12__SHIFT 0x4 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12_MASK 0x100 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12__SHIFT 0x8 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x600 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0x9 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x1800 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0xb ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time_MASK 0xc0000 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time__SHIFT 0x12 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_spare_MASK 0xfff00000 ++#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_spare__SHIFT 0x14 ++#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_valid_MASK 0x1 ++#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_valid__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_spare_MASK 0xfffffffe ++#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_spare__SHIFT 0x1 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_valid_MASK 0x1 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_valid__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel_MASK 0xe ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel__SHIFT 0x1 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val_MASK 0x3f0 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val__SHIFT 0x4 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val_MASK 0xfc00 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val__SHIFT 0xa ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj_MASK 0xf0000 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj__SHIFT 0x10 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj_MASK 0xf00000 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj__SHIFT 0x14 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj_MASK 0xf000000 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj__SHIFT 0x18 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en_MASK 0x10000000 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en__SHIFT 0x1c ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_spare_MASK 0xe0000000 ++#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d ++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0_MASK 0x1 ++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK 0x2 ++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal__SHIFT 0x1 ++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel_MASK 0x4 ++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT 0x2 ++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code_MASK 0x3f0 ++#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code__SHIFT 0x4 ++#define PSX80_PHY0_COM_COMMON_DFX__nelb_en_MASK 0x1 ++#define PSX80_PHY0_COM_COMMON_DFX__nelb_en__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_DFX__prbs_seed_MASK 0x7fe ++#define PSX80_PHY0_COM_COMMON_DFX__prbs_seed__SHIFT 0x1 ++#define PSX80_PHY0_COM_COMMON_DFX__force_cdr_en_MASK 0x800 ++#define PSX80_PHY0_COM_COMMON_DFX__force_cdr_en__SHIFT 0xb ++#define PSX80_PHY0_COM_COMMON_DFX__ovrd_pll_on_MASK 0x2000 ++#define PSX80_PHY0_COM_COMMON_DFX__ovrd_pll_on__SHIFT 0xd ++#define PSX80_PHY0_COM_COMMON_DFX__ovrd_clk_en_MASK 0x8000 ++#define PSX80_PHY0_COM_COMMON_DFX__ovrd_clk_en__SHIFT 0xf ++#define PSX80_PHY0_COM_COMMON_DFX__dsm_sel_MASK 0x7e0000 ++#define PSX80_PHY0_COM_COMMON_DFX__dsm_sel__SHIFT 0x11 ++#define PSX80_PHY0_COM_COMMON_DFX__dsm_en_MASK 0xf000000 ++#define PSX80_PHY0_COM_COMMON_DFX__dsm_en__SHIFT 0x18 ++#define PSX80_PHY0_COM_COMMON_DFX__hold_rdy_response_MASK 0x20000000 ++#define PSX80_PHY0_COM_COMMON_DFX__hold_rdy_response__SHIFT 0x1d ++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0xff ++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0xff00 ++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8 ++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0xff0000 ++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10 ++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xff000000 ++#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1_MASK 0xff ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2_MASK 0xff00 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2__SHIFT 0x8 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3_MASK 0xff0000 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3__SHIFT 0x10 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4_MASK 0xff000000 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4__SHIFT 0x18 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1_MASK 0xff ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2_MASK 0xff00 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2__SHIFT 0x8 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3_MASK 0xff0000 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3__SHIFT 0x10 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4_MASK 0xff000000 ++#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4__SHIFT 0x18 ++#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay_MASK 0xf ++#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask_MASK 0x3f0 ++#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber_MASK 0x7 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time_MASK 0xf0 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time__SHIFT 0x4 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time_MASK 0x1e00 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time__SHIFT 0x9 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time_MASK 0x3c000 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time__SHIFT 0xe ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time_MASK 0x780000 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time__SHIFT 0x13 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time_MASK 0x1e000000 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time__SHIFT 0x19 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel_MASK 0xe0000000 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel__SHIFT 0x1d ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain_MASK 0x3 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain_MASK 0x78 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain__SHIFT 0x3 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain_MASK 0xf00 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain__SHIFT 0x8 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain_MASK 0x1e000 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain__SHIFT 0xd ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain_MASK 0x3c0000 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain__SHIFT 0x12 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt_MASK 0x3800000 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt__SHIFT 0x17 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt_MASK 0x38000000 ++#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt__SHIFT 0x1b ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val_MASK 0x1f ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val_MASK 0x7c0 ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val__SHIFT 0x6 ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val_MASK 0xe000 ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val__SHIFT 0xd ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val_MASK 0xe0000 ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val__SHIFT 0x11 ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val_MASK 0xfc00000 ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val__SHIFT 0x16 ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val_MASK 0x3f ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val_MASK 0xf00 ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val__SHIFT 0x8 ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val_MASK 0x1e000 ++#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val__SHIFT 0xd ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val_MASK 0x1ff ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val_MASK 0xff800 ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val__SHIFT 0xb ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val_MASK 0x7fc00000 ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val__SHIFT 0x16 ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val_MASK 0x3f ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val_MASK 0x1f80 ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val__SHIFT 0x7 ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode_MASK 0x7 ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec_MASK 0x1c0 ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec__SHIFT 0x6 ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst_MASK 0x3fffc00 ++#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst__SHIFT 0xa ++#define PSX80_PHY0_COM_COMMON_LNCNTRL__clkgate_dis_MASK 0x20 ++#define PSX80_PHY0_COM_COMMON_LNCNTRL__clkgate_dis__SHIFT 0x5 ++#define PSX80_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel_MASK 0xc0 ++#define PSX80_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel__SHIFT 0x6 ++#define PSX80_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel_MASK 0x300 ++#define PSX80_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel__SHIFT 0x8 ++#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel_MASK 0x1f ++#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en_MASK 0x40 ++#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en__SHIFT 0x6 ++#define PSX80_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel_MASK 0x70 ++#define PSX80_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel__SHIFT 0x4 ++#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3_MASK 0x1 ++#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3_MASK 0x780 ++#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3__SHIFT 0x7 ++#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val_MASK 0x7e000 ++#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val__SHIFT 0xd ++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en_MASK 0x1 ++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en__SHIFT 0x0 ++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12_MASK 0x3c ++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT 0x2 ++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3_MASK 0x780 ++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3__SHIFT 0x7 ++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val_MASK 0x1ff000 ++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val__SHIFT 0xc ++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit_MASK 0xc00000 ++#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit__SHIFT 0x16 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr_MASK 0x7 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en_MASK 0x18 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en_MASK 0x20 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr_MASK 0x7 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en_MASK 0x18 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en_MASK 0x20 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr_MASK 0x7 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en_MASK 0x18 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en_MASK 0x20 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr_MASK 0x7 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en_MASK 0x18 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en_MASK 0x20 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr_MASK 0x7 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en_MASK 0x18 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en_MASK 0x20 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr_MASK 0x7 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en_MASK 0x18 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en_MASK 0x20 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr_MASK 0x7 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en_MASK 0x18 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en_MASK 0x20 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr_MASK 0x7 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en_MASK 0x18 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en_MASK 0x20 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr_MASK 0x7 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en_MASK 0x18 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en_MASK 0x20 ++#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en_MASK 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed_MASK 0x6 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2_MASK 0x8 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en_MASK 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed_MASK 0x6 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2_MASK 0x8 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en_MASK 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed_MASK 0x6 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2_MASK 0x8 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en_MASK 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed_MASK 0x6 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2_MASK 0x8 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en_MASK 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed_MASK 0x6 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2_MASK 0x8 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en_MASK 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed_MASK 0x6 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2_MASK 0x8 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en_MASK 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed_MASK 0x6 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2_MASK 0x8 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en_MASK 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed_MASK 0x6 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2_MASK 0x8 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en_MASK 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed_MASK 0x6 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2_MASK 0x8 ++#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis_MASK 0x1 ++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis__SHIFT 0x0 ++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc_MASK 0x1fe ++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc__SHIFT 0x1 ++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode_MASK 0x1800 ++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode__SHIFT 0xb ++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign_MASK 0x8000 ++#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign__SHIFT 0xf ++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis_MASK 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis__SHIFT 0x0 ++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc_MASK 0x1fe ++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc__SHIFT 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_term_mode_MASK 0x1800 ++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_term_mode__SHIFT 0xb ++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign_MASK 0x8000 ++#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign__SHIFT 0xf ++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis_MASK 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis__SHIFT 0x0 ++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc_MASK 0x1fe ++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc__SHIFT 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_term_mode_MASK 0x1800 ++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_term_mode__SHIFT 0xb ++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign_MASK 0x8000 ++#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign__SHIFT 0xf ++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis_MASK 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis__SHIFT 0x0 ++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc_MASK 0x1fe ++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc__SHIFT 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_term_mode_MASK 0x1800 ++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_term_mode__SHIFT 0xb ++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign_MASK 0x8000 ++#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign__SHIFT 0xf ++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis_MASK 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis__SHIFT 0x0 ++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc_MASK 0x1fe ++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc__SHIFT 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_term_mode_MASK 0x1800 ++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_term_mode__SHIFT 0xb ++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign_MASK 0x8000 ++#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign__SHIFT 0xf ++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis_MASK 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis__SHIFT 0x0 ++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc_MASK 0x1fe ++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc__SHIFT 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_term_mode_MASK 0x1800 ++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_term_mode__SHIFT 0xb ++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign_MASK 0x8000 ++#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign__SHIFT 0xf ++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis_MASK 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis__SHIFT 0x0 ++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc_MASK 0x1fe ++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc__SHIFT 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_term_mode_MASK 0x1800 ++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_term_mode__SHIFT 0xb ++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign_MASK 0x8000 ++#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign__SHIFT 0xf ++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis_MASK 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis__SHIFT 0x0 ++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc_MASK 0x1fe ++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc__SHIFT 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_term_mode_MASK 0x1800 ++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_term_mode__SHIFT 0xb ++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign_MASK 0x8000 ++#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign__SHIFT 0xf ++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis_MASK 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis__SHIFT 0x0 ++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc_MASK 0x1fe ++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc__SHIFT 0x1 ++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_term_mode_MASK 0x1800 ++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_term_mode__SHIFT 0xb ++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign_MASK 0x8000 ++#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign__SHIFT 0xf ++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel_MASK 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en_MASK 0x20 ++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl_MASK 0x80 ++#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl__SHIFT 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel_MASK 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en_MASK 0x20 ++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl_MASK 0x80 ++#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl__SHIFT 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel_MASK 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en_MASK 0x20 ++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl_MASK 0x80 ++#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl__SHIFT 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel_MASK 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en_MASK 0x20 ++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl_MASK 0x80 ++#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl__SHIFT 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel_MASK 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en_MASK 0x20 ++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl_MASK 0x80 ++#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl__SHIFT 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel_MASK 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en_MASK 0x20 ++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl_MASK 0x80 ++#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl__SHIFT 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel_MASK 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en_MASK 0x20 ++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl_MASK 0x80 ++#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl__SHIFT 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel_MASK 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en_MASK 0x20 ++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl_MASK 0x80 ++#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl__SHIFT 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel_MASK 0x7 ++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en_MASK 0x20 ++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl_MASK 0x80 ++#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl__SHIFT 0x7 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr_MASK 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr__SHIFT 0x0 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK 0x2 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err__SHIFT 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force_MASK 0x10 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force__SHIFT 0x4 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en_MASK 0x20 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap_MASK 0x40 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res_MASK 0x80 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res__SHIFT 0x7 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate_MASK 0x100 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out_MASK 0x400 ++#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr_MASK 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr__SHIFT 0x0 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK 0x2 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_err__SHIFT 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force_MASK 0x10 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force__SHIFT 0x4 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en_MASK 0x20 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap_MASK 0x40 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res_MASK 0x80 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res__SHIFT 0x7 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate_MASK 0x100 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out_MASK 0x400 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr_MASK 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr__SHIFT 0x0 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK 0x2 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_err__SHIFT 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force_MASK 0x10 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force__SHIFT 0x4 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en_MASK 0x20 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap_MASK 0x40 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res_MASK 0x80 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res__SHIFT 0x7 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate_MASK 0x100 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out_MASK 0x400 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr_MASK 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr__SHIFT 0x0 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK 0x2 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_err__SHIFT 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force_MASK 0x10 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force__SHIFT 0x4 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en_MASK 0x20 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap_MASK 0x40 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res_MASK 0x80 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res__SHIFT 0x7 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate_MASK 0x100 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out_MASK 0x400 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr_MASK 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr__SHIFT 0x0 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK 0x2 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_err__SHIFT 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force_MASK 0x10 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force__SHIFT 0x4 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en_MASK 0x20 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap_MASK 0x40 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res_MASK 0x80 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res__SHIFT 0x7 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate_MASK 0x100 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out_MASK 0x400 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr_MASK 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr__SHIFT 0x0 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK 0x2 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_err__SHIFT 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force_MASK 0x10 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force__SHIFT 0x4 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en_MASK 0x20 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap_MASK 0x40 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res_MASK 0x80 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res__SHIFT 0x7 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate_MASK 0x100 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out_MASK 0x400 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr_MASK 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr__SHIFT 0x0 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK 0x2 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_err__SHIFT 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force_MASK 0x10 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force__SHIFT 0x4 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en_MASK 0x20 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap_MASK 0x40 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res_MASK 0x80 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res__SHIFT 0x7 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate_MASK 0x100 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out_MASK 0x400 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr_MASK 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr__SHIFT 0x0 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK 0x2 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_err__SHIFT 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force_MASK 0x10 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force__SHIFT 0x4 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en_MASK 0x20 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap_MASK 0x40 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res_MASK 0x80 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res__SHIFT 0x7 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate_MASK 0x100 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out_MASK 0x400 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr_MASK 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr__SHIFT 0x0 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK 0x2 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_err__SHIFT 0x1 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force_MASK 0x10 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force__SHIFT 0x4 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en_MASK 0x20 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap_MASK 0x40 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res_MASK 0x80 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res__SHIFT 0x7 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate_MASK 0x100 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out_MASK 0x400 ++#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei_MASK 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei__SHIFT 0x0 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en_MASK 0x400 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en__SHIFT 0xa ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei_MASK 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei__SHIFT 0x0 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en_MASK 0x400 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en__SHIFT 0xa ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei_MASK 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei__SHIFT 0x0 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en_MASK 0x400 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en__SHIFT 0xa ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei_MASK 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei__SHIFT 0x0 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en_MASK 0x400 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en__SHIFT 0xa ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei_MASK 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei__SHIFT 0x0 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en_MASK 0x400 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en__SHIFT 0xa ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei_MASK 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei__SHIFT 0x0 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en_MASK 0x400 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en__SHIFT 0xa ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei_MASK 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei__SHIFT 0x0 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en_MASK 0x400 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en__SHIFT 0xa ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei_MASK 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei__SHIFT 0x0 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en_MASK 0x400 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en__SHIFT 0xa ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei_MASK 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei__SHIFT 0x0 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en_MASK 0x400 ++#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en__SHIFT 0xa ++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode_MASK 0x3ff ++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode_MASK 0x3ff ++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode_MASK 0x3ff ++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode_MASK 0x3ff ++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode_MASK 0x3ff ++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode_MASK 0x3ff ++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode_MASK 0x3ff ++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode_MASK 0x3ff ++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode_MASK 0x3ff ++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid_MASK 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid__SHIFT 0x0 ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom_MASK 0x1fe ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom__SHIFT 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom_MASK 0x800 ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom__SHIFT 0xb ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom_MASK 0x1000 ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom__SHIFT 0xc ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk_MASK 0x2000 ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk__SHIFT 0xd ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn_MASK 0x4000 ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn__SHIFT 0xe ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode_MASK 0x10000 ++#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode__SHIFT 0x10 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid_MASK 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid__SHIFT 0x0 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom_MASK 0x1fe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom__SHIFT 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__enable_fom_MASK 0x800 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__enable_fom__SHIFT 0xb ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_fom_MASK 0x1000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_fom__SHIFT 0xc ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trk_MASK 0x2000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trk__SHIFT 0xd ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trn_MASK 0x4000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trn__SHIFT 0xe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__response_mode_MASK 0x10000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__response_mode__SHIFT 0x10 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid_MASK 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid__SHIFT 0x0 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom_MASK 0x1fe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom__SHIFT 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__enable_fom_MASK 0x800 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__enable_fom__SHIFT 0xb ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_fom_MASK 0x1000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_fom__SHIFT 0xc ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trk_MASK 0x2000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trk__SHIFT 0xd ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trn_MASK 0x4000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trn__SHIFT 0xe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__response_mode_MASK 0x10000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__response_mode__SHIFT 0x10 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid_MASK 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid__SHIFT 0x0 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom_MASK 0x1fe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom__SHIFT 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__enable_fom_MASK 0x800 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__enable_fom__SHIFT 0xb ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_fom_MASK 0x1000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_fom__SHIFT 0xc ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trk_MASK 0x2000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trk__SHIFT 0xd ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trn_MASK 0x4000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trn__SHIFT 0xe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__response_mode_MASK 0x10000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__response_mode__SHIFT 0x10 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid_MASK 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid__SHIFT 0x0 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom_MASK 0x1fe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom__SHIFT 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__enable_fom_MASK 0x800 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__enable_fom__SHIFT 0xb ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_fom_MASK 0x1000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_fom__SHIFT 0xc ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trk_MASK 0x2000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trk__SHIFT 0xd ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trn_MASK 0x4000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trn__SHIFT 0xe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__response_mode_MASK 0x10000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__response_mode__SHIFT 0x10 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid_MASK 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid__SHIFT 0x0 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom_MASK 0x1fe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom__SHIFT 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__enable_fom_MASK 0x800 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__enable_fom__SHIFT 0xb ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_fom_MASK 0x1000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_fom__SHIFT 0xc ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trk_MASK 0x2000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trk__SHIFT 0xd ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trn_MASK 0x4000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trn__SHIFT 0xe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__response_mode_MASK 0x10000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__response_mode__SHIFT 0x10 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid_MASK 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid__SHIFT 0x0 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom_MASK 0x1fe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom__SHIFT 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__enable_fom_MASK 0x800 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__enable_fom__SHIFT 0xb ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_fom_MASK 0x1000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_fom__SHIFT 0xc ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trk_MASK 0x2000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trk__SHIFT 0xd ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trn_MASK 0x4000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trn__SHIFT 0xe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__response_mode_MASK 0x10000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__response_mode__SHIFT 0x10 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid_MASK 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid__SHIFT 0x0 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom_MASK 0x1fe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom__SHIFT 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__enable_fom_MASK 0x800 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__enable_fom__SHIFT 0xb ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_fom_MASK 0x1000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_fom__SHIFT 0xc ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trk_MASK 0x2000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trk__SHIFT 0xd ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trn_MASK 0x4000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trn__SHIFT 0xe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__response_mode_MASK 0x10000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__response_mode__SHIFT 0x10 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid_MASK 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid__SHIFT 0x0 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom_MASK 0x1fe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom__SHIFT 0x1 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__enable_fom_MASK 0x800 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__enable_fom__SHIFT 0xb ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_fom_MASK 0x1000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_fom__SHIFT 0xc ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trk_MASK 0x2000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trk__SHIFT 0xd ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trn_MASK 0x4000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trn__SHIFT 0xe ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__response_mode_MASK 0x10000 ++#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__response_mode__SHIFT 0x10 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en_MASK 0x40 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en_MASK 0x80 ++#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel_MASK 0xf ++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en_MASK 0x100000 ++#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel_MASK 0xf ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en_MASK 0x100000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel_MASK 0xf ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en_MASK 0x100000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel_MASK 0xf ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en_MASK 0x100000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel_MASK 0xf ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en_MASK 0x100000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel_MASK 0xf ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en_MASK 0x100000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel_MASK 0xf ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en_MASK 0x100000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel_MASK 0xf ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en_MASK 0x100000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel_MASK 0xf ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en_MASK 0x100000 ++#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr_MASK 0x7 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en_MASK 0x18 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x7 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x18 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x7 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x18 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x7 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x18 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x7 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x18 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr_MASK 0x7 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en_MASK 0x18 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr_MASK 0x7 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en_MASK 0x18 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr_MASK 0x7 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en_MASK 0x18 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr_MASK 0x7 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en_MASK 0x18 ++#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en__SHIFT 0x3 ++#define PSX80_PHY0_TX_DFX_BROADCAST__obs_en_MASK 0x1 ++#define PSX80_PHY0_TX_DFX_BROADCAST__obs_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_DFX_BROADCAST__obs_sel_MASK 0x4 ++#define PSX80_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT 0x2 ++#define PSX80_PHY0_TX_DFX_BROADCAST__felb_en_MASK 0x10 ++#define PSX80_PHY0_TX_DFX_BROADCAST__felb_en__SHIFT 0x4 ++#define PSX80_PHY0_TX_DFX_BROADCAST__prbs_en_MASK 0x100 ++#define PSX80_PHY0_TX_DFX_BROADCAST__prbs_en__SHIFT 0x8 ++#define PSX80_PHY0_TX_DFX_LANE0__obs_en_MASK 0x1 ++#define PSX80_PHY0_TX_DFX_LANE0__obs_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_DFX_LANE0__obs_sel_MASK 0x4 ++#define PSX80_PHY0_TX_DFX_LANE0__obs_sel__SHIFT 0x2 ++#define PSX80_PHY0_TX_DFX_LANE0__felb_en_MASK 0x10 ++#define PSX80_PHY0_TX_DFX_LANE0__felb_en__SHIFT 0x4 ++#define PSX80_PHY0_TX_DFX_LANE0__prbs_en_MASK 0x100 ++#define PSX80_PHY0_TX_DFX_LANE0__prbs_en__SHIFT 0x8 ++#define PSX80_PHY0_TX_DFX_LANE1__obs_en_MASK 0x1 ++#define PSX80_PHY0_TX_DFX_LANE1__obs_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_DFX_LANE1__obs_sel_MASK 0x4 ++#define PSX80_PHY0_TX_DFX_LANE1__obs_sel__SHIFT 0x2 ++#define PSX80_PHY0_TX_DFX_LANE1__felb_en_MASK 0x10 ++#define PSX80_PHY0_TX_DFX_LANE1__felb_en__SHIFT 0x4 ++#define PSX80_PHY0_TX_DFX_LANE1__prbs_en_MASK 0x100 ++#define PSX80_PHY0_TX_DFX_LANE1__prbs_en__SHIFT 0x8 ++#define PSX80_PHY0_TX_DFX_LANE2__obs_en_MASK 0x1 ++#define PSX80_PHY0_TX_DFX_LANE2__obs_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_DFX_LANE2__obs_sel_MASK 0x4 ++#define PSX80_PHY0_TX_DFX_LANE2__obs_sel__SHIFT 0x2 ++#define PSX80_PHY0_TX_DFX_LANE2__felb_en_MASK 0x10 ++#define PSX80_PHY0_TX_DFX_LANE2__felb_en__SHIFT 0x4 ++#define PSX80_PHY0_TX_DFX_LANE2__prbs_en_MASK 0x100 ++#define PSX80_PHY0_TX_DFX_LANE2__prbs_en__SHIFT 0x8 ++#define PSX80_PHY0_TX_DFX_LANE3__obs_en_MASK 0x1 ++#define PSX80_PHY0_TX_DFX_LANE3__obs_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_DFX_LANE3__obs_sel_MASK 0x4 ++#define PSX80_PHY0_TX_DFX_LANE3__obs_sel__SHIFT 0x2 ++#define PSX80_PHY0_TX_DFX_LANE3__felb_en_MASK 0x10 ++#define PSX80_PHY0_TX_DFX_LANE3__felb_en__SHIFT 0x4 ++#define PSX80_PHY0_TX_DFX_LANE3__prbs_en_MASK 0x100 ++#define PSX80_PHY0_TX_DFX_LANE3__prbs_en__SHIFT 0x8 ++#define PSX80_PHY0_TX_DFX_LANE4__obs_en_MASK 0x1 ++#define PSX80_PHY0_TX_DFX_LANE4__obs_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_DFX_LANE4__obs_sel_MASK 0x4 ++#define PSX80_PHY0_TX_DFX_LANE4__obs_sel__SHIFT 0x2 ++#define PSX80_PHY0_TX_DFX_LANE4__felb_en_MASK 0x10 ++#define PSX80_PHY0_TX_DFX_LANE4__felb_en__SHIFT 0x4 ++#define PSX80_PHY0_TX_DFX_LANE4__prbs_en_MASK 0x100 ++#define PSX80_PHY0_TX_DFX_LANE4__prbs_en__SHIFT 0x8 ++#define PSX80_PHY0_TX_DFX_LANE5__obs_en_MASK 0x1 ++#define PSX80_PHY0_TX_DFX_LANE5__obs_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_DFX_LANE5__obs_sel_MASK 0x4 ++#define PSX80_PHY0_TX_DFX_LANE5__obs_sel__SHIFT 0x2 ++#define PSX80_PHY0_TX_DFX_LANE5__felb_en_MASK 0x10 ++#define PSX80_PHY0_TX_DFX_LANE5__felb_en__SHIFT 0x4 ++#define PSX80_PHY0_TX_DFX_LANE5__prbs_en_MASK 0x100 ++#define PSX80_PHY0_TX_DFX_LANE5__prbs_en__SHIFT 0x8 ++#define PSX80_PHY0_TX_DFX_LANE6__obs_en_MASK 0x1 ++#define PSX80_PHY0_TX_DFX_LANE6__obs_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_DFX_LANE6__obs_sel_MASK 0x4 ++#define PSX80_PHY0_TX_DFX_LANE6__obs_sel__SHIFT 0x2 ++#define PSX80_PHY0_TX_DFX_LANE6__felb_en_MASK 0x10 ++#define PSX80_PHY0_TX_DFX_LANE6__felb_en__SHIFT 0x4 ++#define PSX80_PHY0_TX_DFX_LANE6__prbs_en_MASK 0x100 ++#define PSX80_PHY0_TX_DFX_LANE6__prbs_en__SHIFT 0x8 ++#define PSX80_PHY0_TX_DFX_LANE7__obs_en_MASK 0x1 ++#define PSX80_PHY0_TX_DFX_LANE7__obs_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_DFX_LANE7__obs_sel_MASK 0x4 ++#define PSX80_PHY0_TX_DFX_LANE7__obs_sel__SHIFT 0x2 ++#define PSX80_PHY0_TX_DFX_LANE7__felb_en_MASK 0x10 ++#define PSX80_PHY0_TX_DFX_LANE7__felb_en__SHIFT 0x4 ++#define PSX80_PHY0_TX_DFX_LANE7__prbs_en_MASK 0x100 ++#define PSX80_PHY0_TX_DFX_LANE7__prbs_en__SHIFT 0x8 ++#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1_MASK 0xff ++#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0_MASK 0x3f00 ++#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0__SHIFT 0x8 ++#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1_MASK 0xff ++#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0_MASK 0x3f00 ++#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0__SHIFT 0x8 ++#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1_MASK 0xff ++#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0_MASK 0x3f00 ++#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0__SHIFT 0x8 ++#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1_MASK 0xff ++#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0_MASK 0x3f00 ++#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0__SHIFT 0x8 ++#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1_MASK 0xff ++#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0_MASK 0x3f00 ++#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0__SHIFT 0x8 ++#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1_MASK 0xff ++#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0_MASK 0x3f00 ++#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0__SHIFT 0x8 ++#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1_MASK 0xff ++#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0_MASK 0x3f00 ++#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0__SHIFT 0x8 ++#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1_MASK 0xff ++#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0_MASK 0x3f00 ++#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0__SHIFT 0x8 ++#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1_MASK 0xff ++#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0_MASK 0x3f00 ++#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0__SHIFT 0x8 ++#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel_MASK 0x7 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel__SHIFT 0x0 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel_MASK 0x8 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel__SHIFT 0x3 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel_MASK 0x7 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel__SHIFT 0x0 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel_MASK 0x8 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel__SHIFT 0x3 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel_MASK 0x7 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel__SHIFT 0x0 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel_MASK 0x8 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel__SHIFT 0x3 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel_MASK 0x7 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel__SHIFT 0x0 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel_MASK 0x8 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel__SHIFT 0x3 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel_MASK 0x7 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel__SHIFT 0x0 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel_MASK 0x8 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel__SHIFT 0x3 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel_MASK 0x7 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel__SHIFT 0x0 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel_MASK 0x8 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel__SHIFT 0x3 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel_MASK 0x7 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel__SHIFT 0x0 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel_MASK 0x8 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel__SHIFT 0x3 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel_MASK 0x7 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel__SHIFT 0x0 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel_MASK 0x8 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel__SHIFT 0x3 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel_MASK 0x7 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel__SHIFT 0x0 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel_MASK 0x8 ++#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel__SHIFT 0x3 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary_MASK 0x1f ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary__SHIFT 0x0 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid_MASK 0x40 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid__SHIFT 0x6 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated_MASK 0x100 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated__SHIFT 0x8 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error_MASK 0x400 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error__SHIFT 0xa ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done_MASK 0x1000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done__SHIFT 0xc ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated_MASK 0x7f0000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated__SHIFT 0x10 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary_MASK 0x1f ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary__SHIFT 0x0 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid_MASK 0x40 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid__SHIFT 0x6 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated_MASK 0x100 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated__SHIFT 0x8 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error_MASK 0x400 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error__SHIFT 0xa ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done_MASK 0x1000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done__SHIFT 0xc ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated_MASK 0x7f0000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated__SHIFT 0x10 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary_MASK 0x1f ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary__SHIFT 0x0 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid_MASK 0x40 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid__SHIFT 0x6 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated_MASK 0x100 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated__SHIFT 0x8 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error_MASK 0x400 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error__SHIFT 0xa ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done_MASK 0x1000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done__SHIFT 0xc ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated_MASK 0x7f0000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated__SHIFT 0x10 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary_MASK 0x1f ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary__SHIFT 0x0 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid_MASK 0x40 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid__SHIFT 0x6 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated_MASK 0x100 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated__SHIFT 0x8 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error_MASK 0x400 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error__SHIFT 0xa ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done_MASK 0x1000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done__SHIFT 0xc ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated_MASK 0x7f0000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated__SHIFT 0x10 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary_MASK 0x1f ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary__SHIFT 0x0 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid_MASK 0x40 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid__SHIFT 0x6 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated_MASK 0x100 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated__SHIFT 0x8 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error_MASK 0x400 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error__SHIFT 0xa ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done_MASK 0x1000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done__SHIFT 0xc ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated_MASK 0x7f0000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated__SHIFT 0x10 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary_MASK 0x1f ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary__SHIFT 0x0 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid_MASK 0x40 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid__SHIFT 0x6 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated_MASK 0x100 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated__SHIFT 0x8 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error_MASK 0x400 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error__SHIFT 0xa ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done_MASK 0x1000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done__SHIFT 0xc ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated_MASK 0x7f0000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated__SHIFT 0x10 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary_MASK 0x1f ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary__SHIFT 0x0 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid_MASK 0x40 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid__SHIFT 0x6 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated_MASK 0x100 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated__SHIFT 0x8 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error_MASK 0x400 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error__SHIFT 0xa ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done_MASK 0x1000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done__SHIFT 0xc ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated_MASK 0x7f0000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated__SHIFT 0x10 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary_MASK 0x1f ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary__SHIFT 0x0 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid_MASK 0x40 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid__SHIFT 0x6 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated_MASK 0x100 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated__SHIFT 0x8 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error_MASK 0x400 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error__SHIFT 0xa ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done_MASK 0x1000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done__SHIFT 0xc ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated_MASK 0x7f0000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated__SHIFT 0x10 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary_MASK 0x1f ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary__SHIFT 0x0 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid_MASK 0x40 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid__SHIFT 0x6 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated_MASK 0x100 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated__SHIFT 0x8 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error_MASK 0x400 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error__SHIFT 0xa ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done_MASK 0x1000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done__SHIFT 0xc ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated_MASK 0x7f0000 ++#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated__SHIFT 0x10 ++#define PSX80_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response_MASK 0x800 ++#define PSX80_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response__SHIFT 0xb ++#define PSX80_PHY0_TX_TXCNTRL_LANE0__rxdetect_response_MASK 0x800 ++#define PSX80_PHY0_TX_TXCNTRL_LANE0__rxdetect_response__SHIFT 0xb ++#define PSX80_PHY0_TX_TXCNTRL_LANE1__rxdetect_response_MASK 0x800 ++#define PSX80_PHY0_TX_TXCNTRL_LANE1__rxdetect_response__SHIFT 0xb ++#define PSX80_PHY0_TX_TXCNTRL_LANE2__rxdetect_response_MASK 0x800 ++#define PSX80_PHY0_TX_TXCNTRL_LANE2__rxdetect_response__SHIFT 0xb ++#define PSX80_PHY0_TX_TXCNTRL_LANE3__rxdetect_response_MASK 0x800 ++#define PSX80_PHY0_TX_TXCNTRL_LANE3__rxdetect_response__SHIFT 0xb ++#define PSX80_PHY0_TX_TXCNTRL_LANE4__rxdetect_response_MASK 0x800 ++#define PSX80_PHY0_TX_TXCNTRL_LANE4__rxdetect_response__SHIFT 0xb ++#define PSX80_PHY0_TX_TXCNTRL_LANE5__rxdetect_response_MASK 0x800 ++#define PSX80_PHY0_TX_TXCNTRL_LANE5__rxdetect_response__SHIFT 0xb ++#define PSX80_PHY0_TX_TXCNTRL_LANE6__rxdetect_response_MASK 0x800 ++#define PSX80_PHY0_TX_TXCNTRL_LANE6__rxdetect_response__SHIFT 0xb ++#define PSX80_PHY0_TX_TXCNTRL_LANE7__rxdetect_response_MASK 0x800 ++#define PSX80_PHY0_TX_TXCNTRL_LANE7__rxdetect_response__SHIFT 0xb ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en_MASK 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed_MASK 0x6 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2_MASK 0x8 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode_MASK 0xe0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode__SHIFT 0x5 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x6 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2_MASK 0x8 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0xe0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x6 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2_MASK 0x8 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0xe0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x6 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2_MASK 0x8 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0xe0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x6 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2_MASK 0x8 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0xe0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en_MASK 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed_MASK 0x6 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2_MASK 0x8 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode_MASK 0xe0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode__SHIFT 0x5 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en_MASK 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed_MASK 0x6 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2_MASK 0x8 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode_MASK 0xe0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode__SHIFT 0x5 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en_MASK 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed_MASK 0x6 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2_MASK 0x8 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode_MASK 0xe0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode__SHIFT 0x5 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en_MASK 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en__SHIFT 0x0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed_MASK 0x6 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed__SHIFT 0x1 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2_MASK 0x8 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2__SHIFT 0x3 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode_MASK 0xe0 ++#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode__SHIFT 0x5 ++#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn_MASK 0x7 ++#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0 ++#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10 ++#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange_MASK 0xff ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange__SHIFT 0x0 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes_MASK 0x3c00 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes__SHIFT 0xa ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac_MASK 0x3fc000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac__SHIFT 0xe ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer_MASK 0x3c00000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer__SHIFT 0x16 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLock_MASK 0x4000000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLock__SHIFT 0x1a ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect_MASK 0x10000000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked_MASK 0x20000000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked__SHIFT 0x1d ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp__SHIFT 0xb ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut_MASK 0x3ffff ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut__SHIFT 0x0 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo_MASK 0x40000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo__SHIFT 0x12 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq_MASK 0x7f ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq__SHIFT 0x0 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd_MASK 0x80 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd__SHIFT 0x7 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn_MASK 0x100 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn__SHIFT 0x8 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd_MASK 0x200 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd__SHIFT 0x9 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate_MASK 0x400 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate__SHIFT 0xa ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd_MASK 0x800 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd__SHIFT 0xb ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal_MASK 0x1 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal__SHIFT 0x0 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK 0x2 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal__SHIFT 0x1 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal_MASK 0x4 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x2 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone_MASK 0x8 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone__SHIFT 0x3 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x4 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail_MASK 0x60 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail__SHIFT 0x5 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut_MASK 0x4000000 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut__SHIFT 0x1a ++#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid_MASK 0x1 ++#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid__SHIFT 0x0 ++#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj_MASK 0x1e ++#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj__SHIFT 0x1 ++#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare_MASK 0xf00 ++#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare__SHIFT 0x8 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv_MASK 0xffff ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00 ++#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8 ++#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn_MASK 0x7 ++#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0 ++#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10 ++#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange_MASK 0xff ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange__SHIFT 0x0 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin_MASK 0x700 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin__SHIFT 0x8 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes_MASK 0x3000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes__SHIFT 0xc ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0_MASK 0x3c000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0__SHIFT 0xe ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4_MASK 0x3c0000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4__SHIFT 0x12 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer_MASK 0x3c00000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer__SHIFT 0x16 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLock_MASK 0x4000000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLock__SHIFT 0x1a ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect_MASK 0x10000000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked_MASK 0x20000000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked__SHIFT 0x1d ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp__SHIFT 0xb ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut_MASK 0x3ffff ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut__SHIFT 0x0 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo_MASK 0x40000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo__SHIFT 0x12 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11 ++#define PSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI_MASK 0xff ++#define PSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI__SHIFT 0x0 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt_MASK 0x3800000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt__SHIFT 0x17 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt_MASK 0x3fff ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt__SHIFT 0x0 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone_MASK 0x8000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone__SHIFT 0xf ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x10 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail_MASK 0xe0000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail__SHIFT 0x11 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut_MASK 0x4000000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut__SHIFT 0x1a ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn_MASK 0x8000000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn__SHIFT 0x1b ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal_MASK 0x20000000 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x1d ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv_MASK 0xffff ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00 ++#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_valid_MASK 0x1 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_valid__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel_MASK 0x6 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel__SHIFT 0x1 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable_MASK 0x8 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable__SHIFT 0x3 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12_MASK 0xf0 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12__SHIFT 0x4 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12_MASK 0x100 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12__SHIFT 0x8 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x600 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0x9 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x1800 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0xb ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time_MASK 0xc0000 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time__SHIFT 0x12 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_spare_MASK 0xfff00000 ++#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_spare__SHIFT 0x14 ++#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_valid_MASK 0x1 ++#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_valid__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_spare_MASK 0xfffffffe ++#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_spare__SHIFT 0x1 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_valid_MASK 0x1 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_valid__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel_MASK 0xe ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel__SHIFT 0x1 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val_MASK 0x3f0 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val__SHIFT 0x4 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val_MASK 0xfc00 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val__SHIFT 0xa ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj_MASK 0xf0000 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj__SHIFT 0x10 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj_MASK 0xf00000 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj__SHIFT 0x14 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj_MASK 0xf000000 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj__SHIFT 0x18 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en_MASK 0x10000000 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en__SHIFT 0x1c ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_spare_MASK 0xe0000000 ++#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d ++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0_MASK 0x1 ++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK 0x2 ++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal__SHIFT 0x1 ++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel_MASK 0x4 ++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT 0x2 ++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code_MASK 0x3f0 ++#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code__SHIFT 0x4 ++#define PSX81_PHY0_COM_COMMON_DFX__nelb_en_MASK 0x1 ++#define PSX81_PHY0_COM_COMMON_DFX__nelb_en__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_DFX__prbs_seed_MASK 0x7fe ++#define PSX81_PHY0_COM_COMMON_DFX__prbs_seed__SHIFT 0x1 ++#define PSX81_PHY0_COM_COMMON_DFX__force_cdr_en_MASK 0x800 ++#define PSX81_PHY0_COM_COMMON_DFX__force_cdr_en__SHIFT 0xb ++#define PSX81_PHY0_COM_COMMON_DFX__ovrd_pll_on_MASK 0x2000 ++#define PSX81_PHY0_COM_COMMON_DFX__ovrd_pll_on__SHIFT 0xd ++#define PSX81_PHY0_COM_COMMON_DFX__ovrd_clk_en_MASK 0x8000 ++#define PSX81_PHY0_COM_COMMON_DFX__ovrd_clk_en__SHIFT 0xf ++#define PSX81_PHY0_COM_COMMON_DFX__dsm_sel_MASK 0x7e0000 ++#define PSX81_PHY0_COM_COMMON_DFX__dsm_sel__SHIFT 0x11 ++#define PSX81_PHY0_COM_COMMON_DFX__dsm_en_MASK 0xf000000 ++#define PSX81_PHY0_COM_COMMON_DFX__dsm_en__SHIFT 0x18 ++#define PSX81_PHY0_COM_COMMON_DFX__hold_rdy_response_MASK 0x20000000 ++#define PSX81_PHY0_COM_COMMON_DFX__hold_rdy_response__SHIFT 0x1d ++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0xff ++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0xff00 ++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8 ++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0xff0000 ++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10 ++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xff000000 ++#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1_MASK 0xff ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2_MASK 0xff00 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2__SHIFT 0x8 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3_MASK 0xff0000 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3__SHIFT 0x10 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4_MASK 0xff000000 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4__SHIFT 0x18 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1_MASK 0xff ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2_MASK 0xff00 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2__SHIFT 0x8 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3_MASK 0xff0000 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3__SHIFT 0x10 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4_MASK 0xff000000 ++#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4__SHIFT 0x18 ++#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay_MASK 0xf ++#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask_MASK 0x3f0 ++#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber_MASK 0x7 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time_MASK 0xf0 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time__SHIFT 0x4 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time_MASK 0x1e00 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time__SHIFT 0x9 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time_MASK 0x3c000 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time__SHIFT 0xe ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time_MASK 0x780000 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time__SHIFT 0x13 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time_MASK 0x1e000000 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time__SHIFT 0x19 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel_MASK 0xe0000000 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel__SHIFT 0x1d ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain_MASK 0x3 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain_MASK 0x78 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain__SHIFT 0x3 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain_MASK 0xf00 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain__SHIFT 0x8 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain_MASK 0x1e000 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain__SHIFT 0xd ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain_MASK 0x3c0000 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain__SHIFT 0x12 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt_MASK 0x3800000 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt__SHIFT 0x17 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt_MASK 0x38000000 ++#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt__SHIFT 0x1b ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val_MASK 0x1f ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val_MASK 0x7c0 ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val__SHIFT 0x6 ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val_MASK 0xe000 ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val__SHIFT 0xd ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val_MASK 0xe0000 ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val__SHIFT 0x11 ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val_MASK 0xfc00000 ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val__SHIFT 0x16 ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val_MASK 0x3f ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val_MASK 0xf00 ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val__SHIFT 0x8 ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val_MASK 0x1e000 ++#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val__SHIFT 0xd ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val_MASK 0x1ff ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val_MASK 0xff800 ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val__SHIFT 0xb ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val_MASK 0x7fc00000 ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val__SHIFT 0x16 ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val_MASK 0x3f ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val_MASK 0x1f80 ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val__SHIFT 0x7 ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode_MASK 0x7 ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec_MASK 0x1c0 ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec__SHIFT 0x6 ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst_MASK 0x3fffc00 ++#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst__SHIFT 0xa ++#define PSX81_PHY0_COM_COMMON_LNCNTRL__clkgate_dis_MASK 0x20 ++#define PSX81_PHY0_COM_COMMON_LNCNTRL__clkgate_dis__SHIFT 0x5 ++#define PSX81_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel_MASK 0xc0 ++#define PSX81_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel__SHIFT 0x6 ++#define PSX81_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel_MASK 0x300 ++#define PSX81_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel__SHIFT 0x8 ++#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel_MASK 0x1f ++#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en_MASK 0x40 ++#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en__SHIFT 0x6 ++#define PSX81_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel_MASK 0x70 ++#define PSX81_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel__SHIFT 0x4 ++#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3_MASK 0x1 ++#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3_MASK 0x780 ++#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3__SHIFT 0x7 ++#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val_MASK 0x7e000 ++#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val__SHIFT 0xd ++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en_MASK 0x1 ++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en__SHIFT 0x0 ++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12_MASK 0x3c ++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT 0x2 ++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3_MASK 0x780 ++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3__SHIFT 0x7 ++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val_MASK 0x1ff000 ++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val__SHIFT 0xc ++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit_MASK 0xc00000 ++#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit__SHIFT 0x16 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr_MASK 0x7 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en_MASK 0x18 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en_MASK 0x20 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr_MASK 0x7 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en_MASK 0x18 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en_MASK 0x20 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr_MASK 0x7 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en_MASK 0x18 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en_MASK 0x20 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr_MASK 0x7 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en_MASK 0x18 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en_MASK 0x20 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr_MASK 0x7 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en_MASK 0x18 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en_MASK 0x20 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr_MASK 0x7 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en_MASK 0x18 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en_MASK 0x20 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr_MASK 0x7 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en_MASK 0x18 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en_MASK 0x20 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr_MASK 0x7 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en_MASK 0x18 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en_MASK 0x20 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr_MASK 0x7 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en_MASK 0x18 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en_MASK 0x20 ++#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en_MASK 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed_MASK 0x6 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2_MASK 0x8 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en_MASK 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed_MASK 0x6 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2_MASK 0x8 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en_MASK 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed_MASK 0x6 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2_MASK 0x8 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en_MASK 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed_MASK 0x6 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2_MASK 0x8 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en_MASK 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed_MASK 0x6 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2_MASK 0x8 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en_MASK 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed_MASK 0x6 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2_MASK 0x8 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en_MASK 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed_MASK 0x6 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2_MASK 0x8 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en_MASK 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed_MASK 0x6 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2_MASK 0x8 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en_MASK 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed_MASK 0x6 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2_MASK 0x8 ++#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis_MASK 0x1 ++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis__SHIFT 0x0 ++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc_MASK 0x1fe ++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc__SHIFT 0x1 ++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode_MASK 0x1800 ++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode__SHIFT 0xb ++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign_MASK 0x8000 ++#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign__SHIFT 0xf ++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis_MASK 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis__SHIFT 0x0 ++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc_MASK 0x1fe ++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc__SHIFT 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_term_mode_MASK 0x1800 ++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_term_mode__SHIFT 0xb ++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign_MASK 0x8000 ++#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign__SHIFT 0xf ++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis_MASK 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis__SHIFT 0x0 ++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc_MASK 0x1fe ++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc__SHIFT 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_term_mode_MASK 0x1800 ++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_term_mode__SHIFT 0xb ++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign_MASK 0x8000 ++#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign__SHIFT 0xf ++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis_MASK 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis__SHIFT 0x0 ++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc_MASK 0x1fe ++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc__SHIFT 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_term_mode_MASK 0x1800 ++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_term_mode__SHIFT 0xb ++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign_MASK 0x8000 ++#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign__SHIFT 0xf ++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis_MASK 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis__SHIFT 0x0 ++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc_MASK 0x1fe ++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc__SHIFT 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_term_mode_MASK 0x1800 ++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_term_mode__SHIFT 0xb ++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign_MASK 0x8000 ++#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign__SHIFT 0xf ++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis_MASK 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis__SHIFT 0x0 ++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc_MASK 0x1fe ++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc__SHIFT 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_term_mode_MASK 0x1800 ++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_term_mode__SHIFT 0xb ++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign_MASK 0x8000 ++#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign__SHIFT 0xf ++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis_MASK 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis__SHIFT 0x0 ++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc_MASK 0x1fe ++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc__SHIFT 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_term_mode_MASK 0x1800 ++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_term_mode__SHIFT 0xb ++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign_MASK 0x8000 ++#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign__SHIFT 0xf ++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis_MASK 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis__SHIFT 0x0 ++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc_MASK 0x1fe ++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc__SHIFT 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_term_mode_MASK 0x1800 ++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_term_mode__SHIFT 0xb ++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign_MASK 0x8000 ++#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign__SHIFT 0xf ++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis_MASK 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis__SHIFT 0x0 ++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc_MASK 0x1fe ++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc__SHIFT 0x1 ++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_term_mode_MASK 0x1800 ++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_term_mode__SHIFT 0xb ++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri_MASK 0x2000 ++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri__SHIFT 0xd ++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity_MASK 0x4000 ++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity__SHIFT 0xe ++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign_MASK 0x8000 ++#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign__SHIFT 0xf ++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel_MASK 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en_MASK 0x20 ++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl_MASK 0x80 ++#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl__SHIFT 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel_MASK 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en_MASK 0x20 ++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl_MASK 0x80 ++#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl__SHIFT 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel_MASK 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en_MASK 0x20 ++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl_MASK 0x80 ++#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl__SHIFT 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel_MASK 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en_MASK 0x20 ++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl_MASK 0x80 ++#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl__SHIFT 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel_MASK 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en_MASK 0x20 ++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl_MASK 0x80 ++#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl__SHIFT 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel_MASK 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en_MASK 0x20 ++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl_MASK 0x80 ++#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl__SHIFT 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel_MASK 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en_MASK 0x20 ++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl_MASK 0x80 ++#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl__SHIFT 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel_MASK 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en_MASK 0x20 ++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl_MASK 0x80 ++#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl__SHIFT 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel_MASK 0x7 ++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel_MASK 0x10 ++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel__SHIFT 0x4 ++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en_MASK 0x20 ++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl_MASK 0x80 ++#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl__SHIFT 0x7 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr_MASK 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr__SHIFT 0x0 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK 0x2 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err__SHIFT 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force_MASK 0x10 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force__SHIFT 0x4 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en_MASK 0x20 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap_MASK 0x40 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res_MASK 0x80 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res__SHIFT 0x7 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate_MASK 0x100 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out_MASK 0x400 ++#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr_MASK 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr__SHIFT 0x0 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK 0x2 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_err__SHIFT 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force_MASK 0x10 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force__SHIFT 0x4 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en_MASK 0x20 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap_MASK 0x40 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res_MASK 0x80 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res__SHIFT 0x7 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate_MASK 0x100 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out_MASK 0x400 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr_MASK 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr__SHIFT 0x0 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK 0x2 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_err__SHIFT 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force_MASK 0x10 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force__SHIFT 0x4 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en_MASK 0x20 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap_MASK 0x40 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res_MASK 0x80 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res__SHIFT 0x7 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate_MASK 0x100 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out_MASK 0x400 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr_MASK 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr__SHIFT 0x0 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK 0x2 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_err__SHIFT 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force_MASK 0x10 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force__SHIFT 0x4 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en_MASK 0x20 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap_MASK 0x40 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res_MASK 0x80 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res__SHIFT 0x7 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate_MASK 0x100 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out_MASK 0x400 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr_MASK 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr__SHIFT 0x0 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK 0x2 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_err__SHIFT 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force_MASK 0x10 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force__SHIFT 0x4 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en_MASK 0x20 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap_MASK 0x40 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res_MASK 0x80 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res__SHIFT 0x7 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate_MASK 0x100 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out_MASK 0x400 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr_MASK 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr__SHIFT 0x0 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK 0x2 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_err__SHIFT 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force_MASK 0x10 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force__SHIFT 0x4 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en_MASK 0x20 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap_MASK 0x40 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res_MASK 0x80 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res__SHIFT 0x7 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate_MASK 0x100 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out_MASK 0x400 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr_MASK 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr__SHIFT 0x0 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK 0x2 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_err__SHIFT 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force_MASK 0x10 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force__SHIFT 0x4 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en_MASK 0x20 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap_MASK 0x40 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res_MASK 0x80 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res__SHIFT 0x7 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate_MASK 0x100 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out_MASK 0x400 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr_MASK 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr__SHIFT 0x0 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK 0x2 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_err__SHIFT 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force_MASK 0x10 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force__SHIFT 0x4 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en_MASK 0x20 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap_MASK 0x40 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res_MASK 0x80 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res__SHIFT 0x7 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate_MASK 0x100 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out_MASK 0x400 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr_MASK 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr__SHIFT 0x0 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK 0x2 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_err__SHIFT 0x1 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force_MASK 0x10 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force__SHIFT 0x4 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en_MASK 0x20 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap_MASK 0x40 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap__SHIFT 0x6 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res_MASK 0x80 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res__SHIFT 0x7 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate_MASK 0x100 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate__SHIFT 0x8 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out_MASK 0x400 ++#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out__SHIFT 0xa ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei_MASK 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei__SHIFT 0x0 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en_MASK 0x400 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en__SHIFT 0xa ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei_MASK 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei__SHIFT 0x0 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en_MASK 0x400 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en__SHIFT 0xa ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei_MASK 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei__SHIFT 0x0 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en_MASK 0x400 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en__SHIFT 0xa ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei_MASK 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei__SHIFT 0x0 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en_MASK 0x400 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en__SHIFT 0xa ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei_MASK 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei__SHIFT 0x0 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en_MASK 0x400 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en__SHIFT 0xa ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei_MASK 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei__SHIFT 0x0 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en_MASK 0x400 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en__SHIFT 0xa ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei_MASK 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei__SHIFT 0x0 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en_MASK 0x400 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en__SHIFT 0xa ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei_MASK 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei__SHIFT 0x0 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en_MASK 0x400 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en__SHIFT 0xa ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei_MASK 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei__SHIFT 0x0 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out__SHIFT 0x1 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds_MASK 0x4 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT 0x2 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj_MASK 0x1f8 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj__SHIFT 0x3 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en_MASK 0x400 ++#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en__SHIFT 0xa ++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode_MASK 0x3ff ++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode_MASK 0x3ff ++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode_MASK 0x3ff ++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode_MASK 0x3ff ++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode_MASK 0x3ff ++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode_MASK 0x3ff ++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode_MASK 0x3ff ++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode_MASK 0x3ff ++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode_MASK 0x3ff ++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel_MASK 0xe000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel__SHIFT 0xd ++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off_MASK 0x20000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off__SHIFT 0x11 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel_MASK 0x180000 ++#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel__SHIFT 0x13 ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid_MASK 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid__SHIFT 0x0 ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom_MASK 0x1fe ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom__SHIFT 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom_MASK 0x800 ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom__SHIFT 0xb ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom_MASK 0x1000 ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom__SHIFT 0xc ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk_MASK 0x2000 ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk__SHIFT 0xd ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn_MASK 0x4000 ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn__SHIFT 0xe ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode_MASK 0x10000 ++#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode__SHIFT 0x10 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid_MASK 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid__SHIFT 0x0 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom_MASK 0x1fe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom__SHIFT 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__enable_fom_MASK 0x800 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__enable_fom__SHIFT 0xb ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_fom_MASK 0x1000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_fom__SHIFT 0xc ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trk_MASK 0x2000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trk__SHIFT 0xd ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trn_MASK 0x4000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trn__SHIFT 0xe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__response_mode_MASK 0x10000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__response_mode__SHIFT 0x10 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid_MASK 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid__SHIFT 0x0 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom_MASK 0x1fe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom__SHIFT 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__enable_fom_MASK 0x800 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__enable_fom__SHIFT 0xb ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_fom_MASK 0x1000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_fom__SHIFT 0xc ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trk_MASK 0x2000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trk__SHIFT 0xd ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trn_MASK 0x4000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trn__SHIFT 0xe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__response_mode_MASK 0x10000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__response_mode__SHIFT 0x10 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid_MASK 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid__SHIFT 0x0 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom_MASK 0x1fe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom__SHIFT 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__enable_fom_MASK 0x800 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__enable_fom__SHIFT 0xb ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_fom_MASK 0x1000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_fom__SHIFT 0xc ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trk_MASK 0x2000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trk__SHIFT 0xd ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trn_MASK 0x4000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trn__SHIFT 0xe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__response_mode_MASK 0x10000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__response_mode__SHIFT 0x10 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid_MASK 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid__SHIFT 0x0 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom_MASK 0x1fe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom__SHIFT 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__enable_fom_MASK 0x800 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__enable_fom__SHIFT 0xb ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_fom_MASK 0x1000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_fom__SHIFT 0xc ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trk_MASK 0x2000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trk__SHIFT 0xd ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trn_MASK 0x4000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trn__SHIFT 0xe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__response_mode_MASK 0x10000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__response_mode__SHIFT 0x10 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid_MASK 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid__SHIFT 0x0 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom_MASK 0x1fe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom__SHIFT 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__enable_fom_MASK 0x800 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__enable_fom__SHIFT 0xb ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_fom_MASK 0x1000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_fom__SHIFT 0xc ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trk_MASK 0x2000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trk__SHIFT 0xd ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trn_MASK 0x4000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trn__SHIFT 0xe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__response_mode_MASK 0x10000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__response_mode__SHIFT 0x10 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid_MASK 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid__SHIFT 0x0 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom_MASK 0x1fe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom__SHIFT 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__enable_fom_MASK 0x800 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__enable_fom__SHIFT 0xb ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_fom_MASK 0x1000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_fom__SHIFT 0xc ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trk_MASK 0x2000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trk__SHIFT 0xd ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trn_MASK 0x4000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trn__SHIFT 0xe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__response_mode_MASK 0x10000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__response_mode__SHIFT 0x10 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid_MASK 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid__SHIFT 0x0 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom_MASK 0x1fe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom__SHIFT 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__enable_fom_MASK 0x800 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__enable_fom__SHIFT 0xb ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_fom_MASK 0x1000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_fom__SHIFT 0xc ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trk_MASK 0x2000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trk__SHIFT 0xd ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trn_MASK 0x4000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trn__SHIFT 0xe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__response_mode_MASK 0x10000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__response_mode__SHIFT 0x10 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid_MASK 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid__SHIFT 0x0 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom_MASK 0x1fe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom__SHIFT 0x1 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__enable_fom_MASK 0x800 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__enable_fom__SHIFT 0xb ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_fom_MASK 0x1000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_fom__SHIFT 0xc ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trk_MASK 0x2000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trk__SHIFT 0xd ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trn_MASK 0x4000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trn__SHIFT 0xe ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__response_mode_MASK 0x10000 ++#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__response_mode__SHIFT 0x10 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en_MASK 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en__SHIFT 0x0 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en__SHIFT 0x1 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en_MASK 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT 0x2 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en_MASK 0x40 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en__SHIFT 0x6 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en_MASK 0x80 ++#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en__SHIFT 0x7 ++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel_MASK 0xf ++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en_MASK 0x100000 ++#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel_MASK 0xf ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en_MASK 0x100000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel_MASK 0xf ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en_MASK 0x100000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel_MASK 0xf ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en_MASK 0x100000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel_MASK 0xf ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en_MASK 0x100000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel_MASK 0xf ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en_MASK 0x100000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel_MASK 0xf ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en_MASK 0x100000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel_MASK 0xf ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en_MASK 0x100000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel_MASK 0xf ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel__SHIFT 0x0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out_MASK 0x1ffc0 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out__SHIFT 0x6 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst_MASK 0x80000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst__SHIFT 0x13 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en_MASK 0x100000 ++#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en__SHIFT 0x14 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr_MASK 0x7 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en_MASK 0x18 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x7 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x18 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x7 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x18 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x7 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x18 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x7 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x18 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr_MASK 0x7 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en_MASK 0x18 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr_MASK 0x7 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en_MASK 0x18 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr_MASK 0x7 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en_MASK 0x18 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr_MASK 0x7 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en_MASK 0x18 ++#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en__SHIFT 0x3 ++#define PSX81_PHY0_TX_DFX_BROADCAST__obs_en_MASK 0x1 ++#define PSX81_PHY0_TX_DFX_BROADCAST__obs_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_DFX_BROADCAST__obs_sel_MASK 0x4 ++#define PSX81_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT 0x2 ++#define PSX81_PHY0_TX_DFX_BROADCAST__felb_en_MASK 0x10 ++#define PSX81_PHY0_TX_DFX_BROADCAST__felb_en__SHIFT 0x4 ++#define PSX81_PHY0_TX_DFX_BROADCAST__prbs_en_MASK 0x100 ++#define PSX81_PHY0_TX_DFX_BROADCAST__prbs_en__SHIFT 0x8 ++#define PSX81_PHY0_TX_DFX_LANE0__obs_en_MASK 0x1 ++#define PSX81_PHY0_TX_DFX_LANE0__obs_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_DFX_LANE0__obs_sel_MASK 0x4 ++#define PSX81_PHY0_TX_DFX_LANE0__obs_sel__SHIFT 0x2 ++#define PSX81_PHY0_TX_DFX_LANE0__felb_en_MASK 0x10 ++#define PSX81_PHY0_TX_DFX_LANE0__felb_en__SHIFT 0x4 ++#define PSX81_PHY0_TX_DFX_LANE0__prbs_en_MASK 0x100 ++#define PSX81_PHY0_TX_DFX_LANE0__prbs_en__SHIFT 0x8 ++#define PSX81_PHY0_TX_DFX_LANE1__obs_en_MASK 0x1 ++#define PSX81_PHY0_TX_DFX_LANE1__obs_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_DFX_LANE1__obs_sel_MASK 0x4 ++#define PSX81_PHY0_TX_DFX_LANE1__obs_sel__SHIFT 0x2 ++#define PSX81_PHY0_TX_DFX_LANE1__felb_en_MASK 0x10 ++#define PSX81_PHY0_TX_DFX_LANE1__felb_en__SHIFT 0x4 ++#define PSX81_PHY0_TX_DFX_LANE1__prbs_en_MASK 0x100 ++#define PSX81_PHY0_TX_DFX_LANE1__prbs_en__SHIFT 0x8 ++#define PSX81_PHY0_TX_DFX_LANE2__obs_en_MASK 0x1 ++#define PSX81_PHY0_TX_DFX_LANE2__obs_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_DFX_LANE2__obs_sel_MASK 0x4 ++#define PSX81_PHY0_TX_DFX_LANE2__obs_sel__SHIFT 0x2 ++#define PSX81_PHY0_TX_DFX_LANE2__felb_en_MASK 0x10 ++#define PSX81_PHY0_TX_DFX_LANE2__felb_en__SHIFT 0x4 ++#define PSX81_PHY0_TX_DFX_LANE2__prbs_en_MASK 0x100 ++#define PSX81_PHY0_TX_DFX_LANE2__prbs_en__SHIFT 0x8 ++#define PSX81_PHY0_TX_DFX_LANE3__obs_en_MASK 0x1 ++#define PSX81_PHY0_TX_DFX_LANE3__obs_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_DFX_LANE3__obs_sel_MASK 0x4 ++#define PSX81_PHY0_TX_DFX_LANE3__obs_sel__SHIFT 0x2 ++#define PSX81_PHY0_TX_DFX_LANE3__felb_en_MASK 0x10 ++#define PSX81_PHY0_TX_DFX_LANE3__felb_en__SHIFT 0x4 ++#define PSX81_PHY0_TX_DFX_LANE3__prbs_en_MASK 0x100 ++#define PSX81_PHY0_TX_DFX_LANE3__prbs_en__SHIFT 0x8 ++#define PSX81_PHY0_TX_DFX_LANE4__obs_en_MASK 0x1 ++#define PSX81_PHY0_TX_DFX_LANE4__obs_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_DFX_LANE4__obs_sel_MASK 0x4 ++#define PSX81_PHY0_TX_DFX_LANE4__obs_sel__SHIFT 0x2 ++#define PSX81_PHY0_TX_DFX_LANE4__felb_en_MASK 0x10 ++#define PSX81_PHY0_TX_DFX_LANE4__felb_en__SHIFT 0x4 ++#define PSX81_PHY0_TX_DFX_LANE4__prbs_en_MASK 0x100 ++#define PSX81_PHY0_TX_DFX_LANE4__prbs_en__SHIFT 0x8 ++#define PSX81_PHY0_TX_DFX_LANE5__obs_en_MASK 0x1 ++#define PSX81_PHY0_TX_DFX_LANE5__obs_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_DFX_LANE5__obs_sel_MASK 0x4 ++#define PSX81_PHY0_TX_DFX_LANE5__obs_sel__SHIFT 0x2 ++#define PSX81_PHY0_TX_DFX_LANE5__felb_en_MASK 0x10 ++#define PSX81_PHY0_TX_DFX_LANE5__felb_en__SHIFT 0x4 ++#define PSX81_PHY0_TX_DFX_LANE5__prbs_en_MASK 0x100 ++#define PSX81_PHY0_TX_DFX_LANE5__prbs_en__SHIFT 0x8 ++#define PSX81_PHY0_TX_DFX_LANE6__obs_en_MASK 0x1 ++#define PSX81_PHY0_TX_DFX_LANE6__obs_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_DFX_LANE6__obs_sel_MASK 0x4 ++#define PSX81_PHY0_TX_DFX_LANE6__obs_sel__SHIFT 0x2 ++#define PSX81_PHY0_TX_DFX_LANE6__felb_en_MASK 0x10 ++#define PSX81_PHY0_TX_DFX_LANE6__felb_en__SHIFT 0x4 ++#define PSX81_PHY0_TX_DFX_LANE6__prbs_en_MASK 0x100 ++#define PSX81_PHY0_TX_DFX_LANE6__prbs_en__SHIFT 0x8 ++#define PSX81_PHY0_TX_DFX_LANE7__obs_en_MASK 0x1 ++#define PSX81_PHY0_TX_DFX_LANE7__obs_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_DFX_LANE7__obs_sel_MASK 0x4 ++#define PSX81_PHY0_TX_DFX_LANE7__obs_sel__SHIFT 0x2 ++#define PSX81_PHY0_TX_DFX_LANE7__felb_en_MASK 0x10 ++#define PSX81_PHY0_TX_DFX_LANE7__felb_en__SHIFT 0x4 ++#define PSX81_PHY0_TX_DFX_LANE7__prbs_en_MASK 0x100 ++#define PSX81_PHY0_TX_DFX_LANE7__prbs_en__SHIFT 0x8 ++#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1_MASK 0xff ++#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0_MASK 0x3f00 ++#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0__SHIFT 0x8 ++#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1_MASK 0xff ++#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0_MASK 0x3f00 ++#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0__SHIFT 0x8 ++#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1_MASK 0xff ++#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0_MASK 0x3f00 ++#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0__SHIFT 0x8 ++#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1_MASK 0xff ++#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0_MASK 0x3f00 ++#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0__SHIFT 0x8 ++#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1_MASK 0xff ++#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0_MASK 0x3f00 ++#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0__SHIFT 0x8 ++#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1_MASK 0xff ++#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0_MASK 0x3f00 ++#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0__SHIFT 0x8 ++#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1_MASK 0xff ++#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0_MASK 0x3f00 ++#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0__SHIFT 0x8 ++#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1_MASK 0xff ++#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0_MASK 0x3f00 ++#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0__SHIFT 0x8 ++#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1_MASK 0xff ++#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1__SHIFT 0x0 ++#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0_MASK 0x3f00 ++#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0__SHIFT 0x8 ++#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1_MASK 0xff0000 ++#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1__SHIFT 0x10 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel_MASK 0x7 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel__SHIFT 0x0 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel_MASK 0x8 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel__SHIFT 0x3 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel_MASK 0x7 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel__SHIFT 0x0 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel_MASK 0x8 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel__SHIFT 0x3 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel_MASK 0x7 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel__SHIFT 0x0 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel_MASK 0x8 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel__SHIFT 0x3 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel_MASK 0x7 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel__SHIFT 0x0 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel_MASK 0x8 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel__SHIFT 0x3 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel_MASK 0x7 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel__SHIFT 0x0 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel_MASK 0x8 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel__SHIFT 0x3 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel_MASK 0x7 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel__SHIFT 0x0 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel_MASK 0x8 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel__SHIFT 0x3 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel_MASK 0x7 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel__SHIFT 0x0 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel_MASK 0x8 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel__SHIFT 0x3 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel_MASK 0x7 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel__SHIFT 0x0 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel_MASK 0x8 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel__SHIFT 0x3 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel_MASK 0x7 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel__SHIFT 0x0 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel_MASK 0x8 ++#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel__SHIFT 0x3 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary_MASK 0x1f ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary__SHIFT 0x0 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid_MASK 0x40 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid__SHIFT 0x6 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated_MASK 0x100 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated__SHIFT 0x8 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error_MASK 0x400 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error__SHIFT 0xa ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done_MASK 0x1000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done__SHIFT 0xc ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated_MASK 0x7f0000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated__SHIFT 0x10 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary_MASK 0x1f ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary__SHIFT 0x0 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid_MASK 0x40 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid__SHIFT 0x6 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated_MASK 0x100 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated__SHIFT 0x8 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error_MASK 0x400 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error__SHIFT 0xa ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done_MASK 0x1000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done__SHIFT 0xc ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated_MASK 0x7f0000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated__SHIFT 0x10 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary_MASK 0x1f ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary__SHIFT 0x0 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid_MASK 0x40 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid__SHIFT 0x6 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated_MASK 0x100 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated__SHIFT 0x8 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error_MASK 0x400 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error__SHIFT 0xa ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done_MASK 0x1000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done__SHIFT 0xc ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated_MASK 0x7f0000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated__SHIFT 0x10 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary_MASK 0x1f ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary__SHIFT 0x0 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid_MASK 0x40 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid__SHIFT 0x6 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated_MASK 0x100 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated__SHIFT 0x8 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error_MASK 0x400 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error__SHIFT 0xa ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done_MASK 0x1000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done__SHIFT 0xc ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated_MASK 0x7f0000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated__SHIFT 0x10 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary_MASK 0x1f ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary__SHIFT 0x0 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid_MASK 0x40 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid__SHIFT 0x6 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated_MASK 0x100 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated__SHIFT 0x8 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error_MASK 0x400 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error__SHIFT 0xa ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done_MASK 0x1000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done__SHIFT 0xc ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated_MASK 0x7f0000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated__SHIFT 0x10 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary_MASK 0x1f ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary__SHIFT 0x0 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid_MASK 0x40 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid__SHIFT 0x6 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated_MASK 0x100 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated__SHIFT 0x8 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error_MASK 0x400 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error__SHIFT 0xa ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done_MASK 0x1000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done__SHIFT 0xc ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated_MASK 0x7f0000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated__SHIFT 0x10 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary_MASK 0x1f ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary__SHIFT 0x0 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid_MASK 0x40 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid__SHIFT 0x6 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated_MASK 0x100 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated__SHIFT 0x8 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error_MASK 0x400 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error__SHIFT 0xa ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done_MASK 0x1000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done__SHIFT 0xc ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated_MASK 0x7f0000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated__SHIFT 0x10 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary_MASK 0x1f ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary__SHIFT 0x0 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid_MASK 0x40 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid__SHIFT 0x6 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated_MASK 0x100 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated__SHIFT 0x8 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error_MASK 0x400 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error__SHIFT 0xa ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done_MASK 0x1000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done__SHIFT 0xc ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated_MASK 0x7f0000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated__SHIFT 0x10 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary_MASK 0x1f ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary__SHIFT 0x0 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid_MASK 0x40 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid__SHIFT 0x6 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated_MASK 0x100 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated__SHIFT 0x8 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error_MASK 0x400 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error__SHIFT 0xa ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done_MASK 0x1000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done__SHIFT 0xc ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated_MASK 0x7f0000 ++#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated__SHIFT 0x10 ++#define PSX81_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response_MASK 0x800 ++#define PSX81_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response__SHIFT 0xb ++#define PSX81_PHY0_TX_TXCNTRL_LANE0__rxdetect_response_MASK 0x800 ++#define PSX81_PHY0_TX_TXCNTRL_LANE0__rxdetect_response__SHIFT 0xb ++#define PSX81_PHY0_TX_TXCNTRL_LANE1__rxdetect_response_MASK 0x800 ++#define PSX81_PHY0_TX_TXCNTRL_LANE1__rxdetect_response__SHIFT 0xb ++#define PSX81_PHY0_TX_TXCNTRL_LANE2__rxdetect_response_MASK 0x800 ++#define PSX81_PHY0_TX_TXCNTRL_LANE2__rxdetect_response__SHIFT 0xb ++#define PSX81_PHY0_TX_TXCNTRL_LANE3__rxdetect_response_MASK 0x800 ++#define PSX81_PHY0_TX_TXCNTRL_LANE3__rxdetect_response__SHIFT 0xb ++#define PSX81_PHY0_TX_TXCNTRL_LANE4__rxdetect_response_MASK 0x800 ++#define PSX81_PHY0_TX_TXCNTRL_LANE4__rxdetect_response__SHIFT 0xb ++#define PSX81_PHY0_TX_TXCNTRL_LANE5__rxdetect_response_MASK 0x800 ++#define PSX81_PHY0_TX_TXCNTRL_LANE5__rxdetect_response__SHIFT 0xb ++#define PSX81_PHY0_TX_TXCNTRL_LANE6__rxdetect_response_MASK 0x800 ++#define PSX81_PHY0_TX_TXCNTRL_LANE6__rxdetect_response__SHIFT 0xb ++#define PSX81_PHY0_TX_TXCNTRL_LANE7__rxdetect_response_MASK 0x800 ++#define PSX81_PHY0_TX_TXCNTRL_LANE7__rxdetect_response__SHIFT 0xb ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en_MASK 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed_MASK 0x6 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2_MASK 0x8 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode_MASK 0xe0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode__SHIFT 0x5 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x6 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2_MASK 0x8 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0xe0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x6 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2_MASK 0x8 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0xe0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x6 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2_MASK 0x8 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0xe0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x6 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2_MASK 0x8 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0xe0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en_MASK 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed_MASK 0x6 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2_MASK 0x8 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode_MASK 0xe0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode__SHIFT 0x5 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en_MASK 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed_MASK 0x6 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2_MASK 0x8 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode_MASK 0xe0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode__SHIFT 0x5 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en_MASK 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed_MASK 0x6 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2_MASK 0x8 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode_MASK 0xe0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode__SHIFT 0x5 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en_MASK 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en__SHIFT 0x0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed_MASK 0x6 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed__SHIFT 0x1 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2_MASK 0x8 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2__SHIFT 0x3 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode_MASK 0xe0 ++#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode__SHIFT 0x5 ++#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn_MASK 0x7 ++#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0 ++#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10 ++#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange_MASK 0xff ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange__SHIFT 0x0 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes_MASK 0x3c00 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes__SHIFT 0xa ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac_MASK 0x3fc000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac__SHIFT 0xe ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer_MASK 0x3c00000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer__SHIFT 0x16 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLock_MASK 0x4000000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLock__SHIFT 0x1a ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect_MASK 0x10000000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked_MASK 0x20000000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked__SHIFT 0x1d ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp__SHIFT 0xb ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut_MASK 0x3ffff ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut__SHIFT 0x0 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo_MASK 0x40000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo__SHIFT 0x12 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq_MASK 0x7f ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq__SHIFT 0x0 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd_MASK 0x80 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd__SHIFT 0x7 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn_MASK 0x100 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn__SHIFT 0x8 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd_MASK 0x200 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd__SHIFT 0x9 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate_MASK 0x400 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate__SHIFT 0xa ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd_MASK 0x800 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd__SHIFT 0xb ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal_MASK 0x1 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal__SHIFT 0x0 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK 0x2 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal__SHIFT 0x1 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal_MASK 0x4 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x2 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone_MASK 0x8 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone__SHIFT 0x3 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x4 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail_MASK 0x60 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail__SHIFT 0x5 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut_MASK 0x4000000 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut__SHIFT 0x1a ++#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid_MASK 0x1 ++#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid__SHIFT 0x0 ++#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj_MASK 0x1e ++#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj__SHIFT 0x1 ++#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare_MASK 0xf00 ++#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare__SHIFT 0x8 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv_MASK 0xffff ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00 ++#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8 ++#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn_MASK 0x7 ++#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0 ++#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10 ++#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange_MASK 0xff ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange__SHIFT 0x0 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin_MASK 0x700 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin__SHIFT 0x8 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes_MASK 0x3000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes__SHIFT 0xc ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0_MASK 0x3c000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0__SHIFT 0xe ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4_MASK 0x3c0000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4__SHIFT 0x12 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer_MASK 0x3c00000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer__SHIFT 0x16 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLock_MASK 0x4000000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLock__SHIFT 0x1a ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect_MASK 0x10000000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked_MASK 0x20000000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked__SHIFT 0x1d ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp__SHIFT 0xb ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut_MASK 0x3ffff ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut__SHIFT 0x0 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo_MASK 0x40000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo__SHIFT 0x12 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11 ++#define PSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI_MASK 0xff ++#define PSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI__SHIFT 0x0 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt_MASK 0x3800000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt__SHIFT 0x17 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt_MASK 0x3fff ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt__SHIFT 0x0 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone_MASK 0x8000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone__SHIFT 0xf ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x10 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail_MASK 0xe0000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail__SHIFT 0x11 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut_MASK 0x4000000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut__SHIFT 0x1a ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn_MASK 0x8000000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn__SHIFT 0x1b ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal_MASK 0x20000000 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x1d ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv_MASK 0xffff ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00 ++#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8 ++#define PSX80_PIF0_SCRATCH__PIF_SCRATCH_MASK 0xffffffff ++#define PSX80_PIF0_SCRATCH__PIF_SCRATCH__SHIFT 0x0 ++#define PSX80_PIF0_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define PSX80_PIF0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define PSX80_PIF0_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define PSX80_PIF0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define PSX80_PIF0_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define PSX80_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define PSX80_PIF0_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define PSX80_PIF0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define PSX80_PIF0_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define PSX80_PIF0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define PSX80_PIF0_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define PSX80_PIF0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define PSX80_PIF0_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define PSX80_PIF0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define PSX80_PIF0_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define PSX80_PIF0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define PSX80_PIF0_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define PSX80_PIF0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define PSX80_PIF0_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define PSX80_PIF0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define PSX80_PIF0_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define PSX80_PIF0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define PSX80_PIF0_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define PSX80_PIF0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define PSX80_PIF0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define PSX80_PIF0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define PSX80_PIF0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define PSX80_PIF0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define PSX80_PIF0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define PSX80_PIF0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define PSX80_PIF0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define PSX80_PIF0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define PSX80_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2 ++#define PSX80_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1 ++#define PSX80_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4 ++#define PSX80_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2 ++#define PSX80_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8 ++#define PSX80_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3 ++#define PSX80_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10 ++#define PSX80_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4 ++#define PSX80_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20 ++#define PSX80_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5 ++#define PSX80_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0 ++#define PSX80_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6 ++#define PSX80_PIF0_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300 ++#define PSX80_PIF0_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8 ++#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400 ++#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa ++#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800 ++#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb ++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000 ++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc ++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000 ++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd ++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000 ++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe ++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000 ++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf ++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000 ++#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10 ++#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1 ++#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0 ++#define PSX80_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2 ++#define PSX80_PIF0_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1 ++#define PSX80_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4 ++#define PSX80_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2 ++#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8 ++#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3 ++#define PSX80_PIF0_CTRL__PHY_RST_PWROK_VDD_MASK 0x10 ++#define PSX80_PIF0_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4 ++#define PSX80_PIF0_CTRL__PIF_PLL_STATUS_MASK 0xc0 ++#define PSX80_PIF0_CTRL__PIF_PLL_STATUS__SHIFT 0x6 ++#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100 ++#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8 ++#define PSX80_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200 ++#define PSX80_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9 ++#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400 ++#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa ++#define PSX80_PIF0_CTRL__PIF_PG_EXIT_MODE_MASK 0x800 ++#define PSX80_PIF0_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb ++#define PSX80_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000 ++#define PSX80_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc ++#define PSX80_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000 ++#define PSX80_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd ++#define PSX80_PIF0_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000 ++#define PSX80_PIF0_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_S2_MASK 0x7 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000 ++#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16 ++#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000 ++#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17 ++#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000 ++#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18 ++#define PSX80_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7 ++#define PSX80_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0 ++#define PSX80_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38 ++#define PSX80_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3 ++#define PSX80_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0 ++#define PSX80_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6 ++#define PSX80_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200 ++#define PSX80_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 ++#define PSX80_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 ++#define PSX80_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa ++#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000 ++#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10 ++#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000 ++#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11 ++#define PSX80_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000 ++#define PSX80_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15 ++#define PSX80_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000 ++#define PSX80_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16 ++#define PSX80_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000 ++#define PSX80_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19 ++#define PSX80_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000 ++#define PSX80_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a ++#define PSX80_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000 ++#define PSX80_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d ++#define PSX80_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000 ++#define PSX80_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_S2_MASK 0x7 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000 ++#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16 ++#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000 ++#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17 ++#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000 ++#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18 ++#define PSX80_PIF0_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000 ++#define PSX80_PIF0_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19 ++#define PSX80_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000 ++#define PSX80_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a ++#define PSX80_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7 ++#define PSX80_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0 ++#define PSX80_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38 ++#define PSX80_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3 ++#define PSX80_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0 ++#define PSX80_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6 ++#define PSX80_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200 ++#define PSX80_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 ++#define PSX80_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 ++#define PSX80_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa ++#define PSX80_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000 ++#define PSX80_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10 ++#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000 ++#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11 ++#define PSX80_PIF0_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000 ++#define PSX80_PIF0_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13 ++#define PSX80_PIF0_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000 ++#define PSX80_PIF0_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15 ++#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000 ++#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18 ++#define PSX80_PIF0_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000 ++#define PSX80_PIF0_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19 ++#define PSX80_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000 ++#define PSX80_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000 ++#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80 ++#define PSX80_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7 ++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100 ++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8 ++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200 ++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9 ++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400 ++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa ++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800 ++#define PSX80_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb ++#define PSX80_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000 ++#define PSX80_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10 ++#define PSX80_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000 ++#define PSX80_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11 ++#define PSX80_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000 ++#define PSX80_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80 ++#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7 ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100 ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8 ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200 ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9 ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400 ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800 ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000 ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000 ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000 ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000 ++#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000 ++#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f ++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3 ++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0 ++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc ++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2 ++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10 ++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4 ++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60 ++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5 ++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80 ++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7 ++#define PSX80_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100 ++#define PSX80_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8 ++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200 ++#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000 ++#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17 ++#define PSX80_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1 ++#define PSX80_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0 ++#define PSX80_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2 ++#define PSX80_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1 ++#define PSX80_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4 ++#define PSX80_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2 ++#define PSX80_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8 ++#define PSX80_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3 ++#define PSX80_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10 ++#define PSX80_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4 ++#define PSX80_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20 ++#define PSX80_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5 ++#define PSX80_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40 ++#define PSX80_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6 ++#define PSX80_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80 ++#define PSX80_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7 ++#define PSX80_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100 ++#define PSX80_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8 ++#define PSX80_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200 ++#define PSX80_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9 ++#define PSX80_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400 ++#define PSX80_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa ++#define PSX80_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800 ++#define PSX80_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb ++#define PSX80_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000 ++#define PSX80_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc ++#define PSX80_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000 ++#define PSX80_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd ++#define PSX80_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000 ++#define PSX80_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe ++#define PSX80_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000 ++#define PSX80_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf ++#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000 ++#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10 ++#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000 ++#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11 ++#define PSX80_PIF0_LANE0_OVRD2__GANGMODE_0_MASK 0x7 ++#define PSX80_PIF0_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0 ++#define PSX80_PIF0_LANE0_OVRD2__FREQDIV_0_MASK 0x18 ++#define PSX80_PIF0_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3 ++#define PSX80_PIF0_LANE0_OVRD2__LINKSPEED_0_MASK 0x60 ++#define PSX80_PIF0_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5 ++#define PSX80_PIF0_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80 ++#define PSX80_PIF0_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7 ++#define PSX80_PIF0_LANE0_OVRD2__TXPWR_0_MASK 0x700 ++#define PSX80_PIF0_LANE0_OVRD2__TXPWR_0__SHIFT 0x8 ++#define PSX80_PIF0_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800 ++#define PSX80_PIF0_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb ++#define PSX80_PIF0_LANE0_OVRD2__RXPWR_0_MASK 0xe000 ++#define PSX80_PIF0_LANE0_OVRD2__RXPWR_0__SHIFT 0xd ++#define PSX80_PIF0_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000 ++#define PSX80_PIF0_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10 ++#define PSX80_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000 ++#define PSX80_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12 ++#define PSX80_PIF0_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000 ++#define PSX80_PIF0_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13 ++#define PSX80_PIF0_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000 ++#define PSX80_PIF0_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14 ++#define PSX80_PIF0_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000 ++#define PSX80_PIF0_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15 ++#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000 ++#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16 ++#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000 ++#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17 ++#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000 ++#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18 ++#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000 ++#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a ++#define PSX80_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1 ++#define PSX80_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0 ++#define PSX80_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2 ++#define PSX80_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1 ++#define PSX80_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4 ++#define PSX80_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2 ++#define PSX80_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8 ++#define PSX80_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3 ++#define PSX80_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10 ++#define PSX80_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4 ++#define PSX80_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20 ++#define PSX80_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5 ++#define PSX80_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40 ++#define PSX80_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6 ++#define PSX80_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80 ++#define PSX80_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7 ++#define PSX80_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100 ++#define PSX80_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8 ++#define PSX80_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200 ++#define PSX80_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9 ++#define PSX80_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400 ++#define PSX80_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa ++#define PSX80_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800 ++#define PSX80_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb ++#define PSX80_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000 ++#define PSX80_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc ++#define PSX80_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000 ++#define PSX80_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd ++#define PSX80_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000 ++#define PSX80_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe ++#define PSX80_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000 ++#define PSX80_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf ++#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000 ++#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10 ++#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000 ++#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11 ++#define PSX80_PIF0_LANE1_OVRD2__GANGMODE_1_MASK 0x7 ++#define PSX80_PIF0_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0 ++#define PSX80_PIF0_LANE1_OVRD2__FREQDIV_1_MASK 0x18 ++#define PSX80_PIF0_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3 ++#define PSX80_PIF0_LANE1_OVRD2__LINKSPEED_1_MASK 0x60 ++#define PSX80_PIF0_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5 ++#define PSX80_PIF0_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80 ++#define PSX80_PIF0_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7 ++#define PSX80_PIF0_LANE1_OVRD2__TXPWR_1_MASK 0x700 ++#define PSX80_PIF0_LANE1_OVRD2__TXPWR_1__SHIFT 0x8 ++#define PSX80_PIF0_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800 ++#define PSX80_PIF0_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb ++#define PSX80_PIF0_LANE1_OVRD2__RXPWR_1_MASK 0xe000 ++#define PSX80_PIF0_LANE1_OVRD2__RXPWR_1__SHIFT 0xd ++#define PSX80_PIF0_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000 ++#define PSX80_PIF0_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10 ++#define PSX80_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000 ++#define PSX80_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12 ++#define PSX80_PIF0_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000 ++#define PSX80_PIF0_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13 ++#define PSX80_PIF0_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000 ++#define PSX80_PIF0_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14 ++#define PSX80_PIF0_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000 ++#define PSX80_PIF0_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15 ++#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000 ++#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16 ++#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000 ++#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17 ++#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000 ++#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18 ++#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000 ++#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a ++#define PSX80_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1 ++#define PSX80_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0 ++#define PSX80_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2 ++#define PSX80_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1 ++#define PSX80_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4 ++#define PSX80_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2 ++#define PSX80_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8 ++#define PSX80_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3 ++#define PSX80_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10 ++#define PSX80_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4 ++#define PSX80_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20 ++#define PSX80_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5 ++#define PSX80_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40 ++#define PSX80_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6 ++#define PSX80_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80 ++#define PSX80_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7 ++#define PSX80_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100 ++#define PSX80_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8 ++#define PSX80_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200 ++#define PSX80_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9 ++#define PSX80_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400 ++#define PSX80_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa ++#define PSX80_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800 ++#define PSX80_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb ++#define PSX80_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000 ++#define PSX80_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc ++#define PSX80_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000 ++#define PSX80_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd ++#define PSX80_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000 ++#define PSX80_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe ++#define PSX80_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000 ++#define PSX80_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf ++#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000 ++#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10 ++#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000 ++#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11 ++#define PSX80_PIF0_LANE2_OVRD2__GANGMODE_2_MASK 0x7 ++#define PSX80_PIF0_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0 ++#define PSX80_PIF0_LANE2_OVRD2__FREQDIV_2_MASK 0x18 ++#define PSX80_PIF0_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3 ++#define PSX80_PIF0_LANE2_OVRD2__LINKSPEED_2_MASK 0x60 ++#define PSX80_PIF0_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5 ++#define PSX80_PIF0_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80 ++#define PSX80_PIF0_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7 ++#define PSX80_PIF0_LANE2_OVRD2__TXPWR_2_MASK 0x700 ++#define PSX80_PIF0_LANE2_OVRD2__TXPWR_2__SHIFT 0x8 ++#define PSX80_PIF0_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800 ++#define PSX80_PIF0_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb ++#define PSX80_PIF0_LANE2_OVRD2__RXPWR_2_MASK 0xe000 ++#define PSX80_PIF0_LANE2_OVRD2__RXPWR_2__SHIFT 0xd ++#define PSX80_PIF0_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000 ++#define PSX80_PIF0_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10 ++#define PSX80_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000 ++#define PSX80_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12 ++#define PSX80_PIF0_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000 ++#define PSX80_PIF0_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13 ++#define PSX80_PIF0_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000 ++#define PSX80_PIF0_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14 ++#define PSX80_PIF0_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000 ++#define PSX80_PIF0_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15 ++#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000 ++#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16 ++#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000 ++#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17 ++#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000 ++#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18 ++#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000 ++#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a ++#define PSX80_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1 ++#define PSX80_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0 ++#define PSX80_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2 ++#define PSX80_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1 ++#define PSX80_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4 ++#define PSX80_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2 ++#define PSX80_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8 ++#define PSX80_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3 ++#define PSX80_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10 ++#define PSX80_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4 ++#define PSX80_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20 ++#define PSX80_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5 ++#define PSX80_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40 ++#define PSX80_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6 ++#define PSX80_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80 ++#define PSX80_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7 ++#define PSX80_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100 ++#define PSX80_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8 ++#define PSX80_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200 ++#define PSX80_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9 ++#define PSX80_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400 ++#define PSX80_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa ++#define PSX80_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800 ++#define PSX80_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb ++#define PSX80_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000 ++#define PSX80_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc ++#define PSX80_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000 ++#define PSX80_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd ++#define PSX80_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000 ++#define PSX80_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe ++#define PSX80_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000 ++#define PSX80_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf ++#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000 ++#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10 ++#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000 ++#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11 ++#define PSX80_PIF0_LANE3_OVRD2__GANGMODE_3_MASK 0x7 ++#define PSX80_PIF0_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0 ++#define PSX80_PIF0_LANE3_OVRD2__FREQDIV_3_MASK 0x18 ++#define PSX80_PIF0_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3 ++#define PSX80_PIF0_LANE3_OVRD2__LINKSPEED_3_MASK 0x60 ++#define PSX80_PIF0_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5 ++#define PSX80_PIF0_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80 ++#define PSX80_PIF0_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7 ++#define PSX80_PIF0_LANE3_OVRD2__TXPWR_3_MASK 0x700 ++#define PSX80_PIF0_LANE3_OVRD2__TXPWR_3__SHIFT 0x8 ++#define PSX80_PIF0_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800 ++#define PSX80_PIF0_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb ++#define PSX80_PIF0_LANE3_OVRD2__RXPWR_3_MASK 0xe000 ++#define PSX80_PIF0_LANE3_OVRD2__RXPWR_3__SHIFT 0xd ++#define PSX80_PIF0_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000 ++#define PSX80_PIF0_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10 ++#define PSX80_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000 ++#define PSX80_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12 ++#define PSX80_PIF0_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000 ++#define PSX80_PIF0_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13 ++#define PSX80_PIF0_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000 ++#define PSX80_PIF0_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14 ++#define PSX80_PIF0_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000 ++#define PSX80_PIF0_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15 ++#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000 ++#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16 ++#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000 ++#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17 ++#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000 ++#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18 ++#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000 ++#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a ++#define PSX80_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1 ++#define PSX80_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0 ++#define PSX80_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2 ++#define PSX80_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1 ++#define PSX80_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4 ++#define PSX80_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2 ++#define PSX80_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8 ++#define PSX80_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3 ++#define PSX80_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10 ++#define PSX80_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4 ++#define PSX80_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20 ++#define PSX80_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5 ++#define PSX80_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40 ++#define PSX80_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6 ++#define PSX80_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80 ++#define PSX80_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7 ++#define PSX80_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100 ++#define PSX80_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8 ++#define PSX80_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200 ++#define PSX80_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9 ++#define PSX80_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400 ++#define PSX80_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa ++#define PSX80_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800 ++#define PSX80_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb ++#define PSX80_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000 ++#define PSX80_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc ++#define PSX80_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000 ++#define PSX80_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd ++#define PSX80_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000 ++#define PSX80_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe ++#define PSX80_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000 ++#define PSX80_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf ++#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000 ++#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10 ++#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000 ++#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11 ++#define PSX80_PIF0_LANE4_OVRD2__GANGMODE_4_MASK 0x7 ++#define PSX80_PIF0_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0 ++#define PSX80_PIF0_LANE4_OVRD2__FREQDIV_4_MASK 0x18 ++#define PSX80_PIF0_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3 ++#define PSX80_PIF0_LANE4_OVRD2__LINKSPEED_4_MASK 0x60 ++#define PSX80_PIF0_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5 ++#define PSX80_PIF0_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80 ++#define PSX80_PIF0_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7 ++#define PSX80_PIF0_LANE4_OVRD2__TXPWR_4_MASK 0x700 ++#define PSX80_PIF0_LANE4_OVRD2__TXPWR_4__SHIFT 0x8 ++#define PSX80_PIF0_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800 ++#define PSX80_PIF0_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb ++#define PSX80_PIF0_LANE4_OVRD2__RXPWR_4_MASK 0xe000 ++#define PSX80_PIF0_LANE4_OVRD2__RXPWR_4__SHIFT 0xd ++#define PSX80_PIF0_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000 ++#define PSX80_PIF0_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10 ++#define PSX80_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000 ++#define PSX80_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12 ++#define PSX80_PIF0_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000 ++#define PSX80_PIF0_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13 ++#define PSX80_PIF0_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000 ++#define PSX80_PIF0_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14 ++#define PSX80_PIF0_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000 ++#define PSX80_PIF0_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15 ++#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000 ++#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16 ++#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000 ++#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17 ++#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000 ++#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18 ++#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000 ++#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a ++#define PSX80_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1 ++#define PSX80_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0 ++#define PSX80_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2 ++#define PSX80_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1 ++#define PSX80_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4 ++#define PSX80_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2 ++#define PSX80_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8 ++#define PSX80_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3 ++#define PSX80_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10 ++#define PSX80_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4 ++#define PSX80_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20 ++#define PSX80_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5 ++#define PSX80_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40 ++#define PSX80_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6 ++#define PSX80_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80 ++#define PSX80_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7 ++#define PSX80_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100 ++#define PSX80_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8 ++#define PSX80_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200 ++#define PSX80_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9 ++#define PSX80_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400 ++#define PSX80_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa ++#define PSX80_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800 ++#define PSX80_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb ++#define PSX80_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000 ++#define PSX80_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc ++#define PSX80_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000 ++#define PSX80_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd ++#define PSX80_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000 ++#define PSX80_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe ++#define PSX80_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000 ++#define PSX80_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf ++#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000 ++#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10 ++#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000 ++#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11 ++#define PSX80_PIF0_LANE5_OVRD2__GANGMODE_5_MASK 0x7 ++#define PSX80_PIF0_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0 ++#define PSX80_PIF0_LANE5_OVRD2__FREQDIV_5_MASK 0x18 ++#define PSX80_PIF0_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3 ++#define PSX80_PIF0_LANE5_OVRD2__LINKSPEED_5_MASK 0x60 ++#define PSX80_PIF0_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5 ++#define PSX80_PIF0_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80 ++#define PSX80_PIF0_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7 ++#define PSX80_PIF0_LANE5_OVRD2__TXPWR_5_MASK 0x700 ++#define PSX80_PIF0_LANE5_OVRD2__TXPWR_5__SHIFT 0x8 ++#define PSX80_PIF0_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800 ++#define PSX80_PIF0_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb ++#define PSX80_PIF0_LANE5_OVRD2__RXPWR_5_MASK 0xe000 ++#define PSX80_PIF0_LANE5_OVRD2__RXPWR_5__SHIFT 0xd ++#define PSX80_PIF0_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000 ++#define PSX80_PIF0_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10 ++#define PSX80_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000 ++#define PSX80_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12 ++#define PSX80_PIF0_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000 ++#define PSX80_PIF0_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13 ++#define PSX80_PIF0_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000 ++#define PSX80_PIF0_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14 ++#define PSX80_PIF0_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000 ++#define PSX80_PIF0_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15 ++#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000 ++#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16 ++#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000 ++#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17 ++#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000 ++#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18 ++#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000 ++#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a ++#define PSX80_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1 ++#define PSX80_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0 ++#define PSX80_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2 ++#define PSX80_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1 ++#define PSX80_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4 ++#define PSX80_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2 ++#define PSX80_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8 ++#define PSX80_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3 ++#define PSX80_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10 ++#define PSX80_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4 ++#define PSX80_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20 ++#define PSX80_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5 ++#define PSX80_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40 ++#define PSX80_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6 ++#define PSX80_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80 ++#define PSX80_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7 ++#define PSX80_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100 ++#define PSX80_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8 ++#define PSX80_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200 ++#define PSX80_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9 ++#define PSX80_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400 ++#define PSX80_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa ++#define PSX80_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800 ++#define PSX80_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb ++#define PSX80_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000 ++#define PSX80_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc ++#define PSX80_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000 ++#define PSX80_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd ++#define PSX80_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000 ++#define PSX80_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe ++#define PSX80_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000 ++#define PSX80_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf ++#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000 ++#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10 ++#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000 ++#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11 ++#define PSX80_PIF0_LANE6_OVRD2__GANGMODE_6_MASK 0x7 ++#define PSX80_PIF0_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0 ++#define PSX80_PIF0_LANE6_OVRD2__FREQDIV_6_MASK 0x18 ++#define PSX80_PIF0_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3 ++#define PSX80_PIF0_LANE6_OVRD2__LINKSPEED_6_MASK 0x60 ++#define PSX80_PIF0_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5 ++#define PSX80_PIF0_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80 ++#define PSX80_PIF0_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7 ++#define PSX80_PIF0_LANE6_OVRD2__TXPWR_6_MASK 0x700 ++#define PSX80_PIF0_LANE6_OVRD2__TXPWR_6__SHIFT 0x8 ++#define PSX80_PIF0_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800 ++#define PSX80_PIF0_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb ++#define PSX80_PIF0_LANE6_OVRD2__RXPWR_6_MASK 0xe000 ++#define PSX80_PIF0_LANE6_OVRD2__RXPWR_6__SHIFT 0xd ++#define PSX80_PIF0_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000 ++#define PSX80_PIF0_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10 ++#define PSX80_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000 ++#define PSX80_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12 ++#define PSX80_PIF0_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000 ++#define PSX80_PIF0_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13 ++#define PSX80_PIF0_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000 ++#define PSX80_PIF0_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14 ++#define PSX80_PIF0_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000 ++#define PSX80_PIF0_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15 ++#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000 ++#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16 ++#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000 ++#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17 ++#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000 ++#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18 ++#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000 ++#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a ++#define PSX80_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1 ++#define PSX80_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0 ++#define PSX80_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2 ++#define PSX80_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1 ++#define PSX80_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4 ++#define PSX80_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2 ++#define PSX80_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8 ++#define PSX80_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3 ++#define PSX80_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10 ++#define PSX80_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4 ++#define PSX80_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20 ++#define PSX80_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5 ++#define PSX80_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40 ++#define PSX80_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6 ++#define PSX80_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80 ++#define PSX80_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7 ++#define PSX80_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100 ++#define PSX80_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8 ++#define PSX80_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200 ++#define PSX80_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9 ++#define PSX80_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400 ++#define PSX80_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa ++#define PSX80_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800 ++#define PSX80_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb ++#define PSX80_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000 ++#define PSX80_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc ++#define PSX80_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000 ++#define PSX80_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd ++#define PSX80_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000 ++#define PSX80_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe ++#define PSX80_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000 ++#define PSX80_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf ++#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000 ++#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10 ++#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000 ++#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11 ++#define PSX80_PIF0_LANE7_OVRD2__GANGMODE_7_MASK 0x7 ++#define PSX80_PIF0_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0 ++#define PSX80_PIF0_LANE7_OVRD2__FREQDIV_7_MASK 0x18 ++#define PSX80_PIF0_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3 ++#define PSX80_PIF0_LANE7_OVRD2__LINKSPEED_7_MASK 0x60 ++#define PSX80_PIF0_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5 ++#define PSX80_PIF0_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80 ++#define PSX80_PIF0_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7 ++#define PSX80_PIF0_LANE7_OVRD2__TXPWR_7_MASK 0x700 ++#define PSX80_PIF0_LANE7_OVRD2__TXPWR_7__SHIFT 0x8 ++#define PSX80_PIF0_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800 ++#define PSX80_PIF0_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb ++#define PSX80_PIF0_LANE7_OVRD2__RXPWR_7_MASK 0xe000 ++#define PSX80_PIF0_LANE7_OVRD2__RXPWR_7__SHIFT 0xd ++#define PSX80_PIF0_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000 ++#define PSX80_PIF0_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10 ++#define PSX80_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000 ++#define PSX80_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12 ++#define PSX80_PIF0_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000 ++#define PSX80_PIF0_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13 ++#define PSX80_PIF0_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000 ++#define PSX80_PIF0_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14 ++#define PSX80_PIF0_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000 ++#define PSX80_PIF0_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15 ++#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000 ++#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16 ++#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000 ++#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17 ++#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000 ++#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18 ++#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000 ++#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a ++#define PSX81_PIF0_SCRATCH__PIF_SCRATCH_MASK 0xffffffff ++#define PSX81_PIF0_SCRATCH__PIF_SCRATCH__SHIFT 0x0 ++#define PSX81_PIF0_HW_DEBUG__HW_00_DEBUG_MASK 0x1 ++#define PSX81_PIF0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0 ++#define PSX81_PIF0_HW_DEBUG__HW_01_DEBUG_MASK 0x2 ++#define PSX81_PIF0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1 ++#define PSX81_PIF0_HW_DEBUG__HW_02_DEBUG_MASK 0x4 ++#define PSX81_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2 ++#define PSX81_PIF0_HW_DEBUG__HW_03_DEBUG_MASK 0x8 ++#define PSX81_PIF0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3 ++#define PSX81_PIF0_HW_DEBUG__HW_04_DEBUG_MASK 0x10 ++#define PSX81_PIF0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4 ++#define PSX81_PIF0_HW_DEBUG__HW_05_DEBUG_MASK 0x20 ++#define PSX81_PIF0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5 ++#define PSX81_PIF0_HW_DEBUG__HW_06_DEBUG_MASK 0x40 ++#define PSX81_PIF0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6 ++#define PSX81_PIF0_HW_DEBUG__HW_07_DEBUG_MASK 0x80 ++#define PSX81_PIF0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7 ++#define PSX81_PIF0_HW_DEBUG__HW_08_DEBUG_MASK 0x100 ++#define PSX81_PIF0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8 ++#define PSX81_PIF0_HW_DEBUG__HW_09_DEBUG_MASK 0x200 ++#define PSX81_PIF0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9 ++#define PSX81_PIF0_HW_DEBUG__HW_10_DEBUG_MASK 0x400 ++#define PSX81_PIF0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa ++#define PSX81_PIF0_HW_DEBUG__HW_11_DEBUG_MASK 0x800 ++#define PSX81_PIF0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb ++#define PSX81_PIF0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000 ++#define PSX81_PIF0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc ++#define PSX81_PIF0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000 ++#define PSX81_PIF0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd ++#define PSX81_PIF0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000 ++#define PSX81_PIF0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe ++#define PSX81_PIF0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000 ++#define PSX81_PIF0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf ++#define PSX81_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2 ++#define PSX81_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1 ++#define PSX81_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4 ++#define PSX81_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2 ++#define PSX81_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8 ++#define PSX81_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3 ++#define PSX81_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10 ++#define PSX81_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4 ++#define PSX81_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20 ++#define PSX81_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5 ++#define PSX81_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0 ++#define PSX81_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6 ++#define PSX81_PIF0_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300 ++#define PSX81_PIF0_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8 ++#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400 ++#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa ++#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800 ++#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb ++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000 ++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc ++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000 ++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd ++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000 ++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe ++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000 ++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf ++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000 ++#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10 ++#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1 ++#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0 ++#define PSX81_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2 ++#define PSX81_PIF0_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1 ++#define PSX81_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4 ++#define PSX81_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2 ++#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8 ++#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3 ++#define PSX81_PIF0_CTRL__PHY_RST_PWROK_VDD_MASK 0x10 ++#define PSX81_PIF0_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4 ++#define PSX81_PIF0_CTRL__PIF_PLL_STATUS_MASK 0xc0 ++#define PSX81_PIF0_CTRL__PIF_PLL_STATUS__SHIFT 0x6 ++#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100 ++#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8 ++#define PSX81_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200 ++#define PSX81_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9 ++#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400 ++#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa ++#define PSX81_PIF0_CTRL__PIF_PG_EXIT_MODE_MASK 0x800 ++#define PSX81_PIF0_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb ++#define PSX81_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000 ++#define PSX81_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc ++#define PSX81_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000 ++#define PSX81_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd ++#define PSX81_PIF0_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000 ++#define PSX81_PIF0_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_S2_MASK 0x7 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000 ++#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16 ++#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000 ++#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17 ++#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000 ++#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18 ++#define PSX81_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7 ++#define PSX81_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0 ++#define PSX81_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38 ++#define PSX81_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3 ++#define PSX81_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0 ++#define PSX81_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6 ++#define PSX81_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200 ++#define PSX81_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 ++#define PSX81_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 ++#define PSX81_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa ++#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000 ++#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10 ++#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000 ++#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11 ++#define PSX81_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000 ++#define PSX81_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15 ++#define PSX81_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000 ++#define PSX81_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16 ++#define PSX81_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000 ++#define PSX81_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19 ++#define PSX81_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000 ++#define PSX81_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a ++#define PSX81_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000 ++#define PSX81_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d ++#define PSX81_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000 ++#define PSX81_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_S2_MASK 0x7 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000 ++#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16 ++#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000 ++#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17 ++#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000 ++#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18 ++#define PSX81_PIF0_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000 ++#define PSX81_PIF0_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19 ++#define PSX81_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000 ++#define PSX81_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a ++#define PSX81_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7 ++#define PSX81_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0 ++#define PSX81_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38 ++#define PSX81_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3 ++#define PSX81_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0 ++#define PSX81_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6 ++#define PSX81_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200 ++#define PSX81_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9 ++#define PSX81_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400 ++#define PSX81_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa ++#define PSX81_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000 ++#define PSX81_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10 ++#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000 ++#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11 ++#define PSX81_PIF0_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000 ++#define PSX81_PIF0_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13 ++#define PSX81_PIF0_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000 ++#define PSX81_PIF0_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15 ++#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000 ++#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18 ++#define PSX81_PIF0_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000 ++#define PSX81_PIF0_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19 ++#define PSX81_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000 ++#define PSX81_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000 ++#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80 ++#define PSX81_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7 ++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100 ++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8 ++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200 ++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9 ++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400 ++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa ++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800 ++#define PSX81_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb ++#define PSX81_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000 ++#define PSX81_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10 ++#define PSX81_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000 ++#define PSX81_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11 ++#define PSX81_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000 ++#define PSX81_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80 ++#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7 ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100 ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8 ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200 ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9 ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400 ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800 ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000 ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000 ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000 ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000 ++#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000 ++#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f ++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3 ++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0 ++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc ++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2 ++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10 ++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4 ++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60 ++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5 ++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80 ++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7 ++#define PSX81_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100 ++#define PSX81_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8 ++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200 ++#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000 ++#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17 ++#define PSX81_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1 ++#define PSX81_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0 ++#define PSX81_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2 ++#define PSX81_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1 ++#define PSX81_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4 ++#define PSX81_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2 ++#define PSX81_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8 ++#define PSX81_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3 ++#define PSX81_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10 ++#define PSX81_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4 ++#define PSX81_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20 ++#define PSX81_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5 ++#define PSX81_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40 ++#define PSX81_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6 ++#define PSX81_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80 ++#define PSX81_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7 ++#define PSX81_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100 ++#define PSX81_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8 ++#define PSX81_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200 ++#define PSX81_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9 ++#define PSX81_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400 ++#define PSX81_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa ++#define PSX81_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800 ++#define PSX81_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb ++#define PSX81_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000 ++#define PSX81_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc ++#define PSX81_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000 ++#define PSX81_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd ++#define PSX81_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000 ++#define PSX81_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe ++#define PSX81_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000 ++#define PSX81_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf ++#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000 ++#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10 ++#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000 ++#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11 ++#define PSX81_PIF0_LANE0_OVRD2__GANGMODE_0_MASK 0x7 ++#define PSX81_PIF0_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0 ++#define PSX81_PIF0_LANE0_OVRD2__FREQDIV_0_MASK 0x18 ++#define PSX81_PIF0_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3 ++#define PSX81_PIF0_LANE0_OVRD2__LINKSPEED_0_MASK 0x60 ++#define PSX81_PIF0_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5 ++#define PSX81_PIF0_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80 ++#define PSX81_PIF0_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7 ++#define PSX81_PIF0_LANE0_OVRD2__TXPWR_0_MASK 0x700 ++#define PSX81_PIF0_LANE0_OVRD2__TXPWR_0__SHIFT 0x8 ++#define PSX81_PIF0_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800 ++#define PSX81_PIF0_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb ++#define PSX81_PIF0_LANE0_OVRD2__RXPWR_0_MASK 0xe000 ++#define PSX81_PIF0_LANE0_OVRD2__RXPWR_0__SHIFT 0xd ++#define PSX81_PIF0_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000 ++#define PSX81_PIF0_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10 ++#define PSX81_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000 ++#define PSX81_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12 ++#define PSX81_PIF0_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000 ++#define PSX81_PIF0_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13 ++#define PSX81_PIF0_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000 ++#define PSX81_PIF0_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14 ++#define PSX81_PIF0_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000 ++#define PSX81_PIF0_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15 ++#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000 ++#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16 ++#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000 ++#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17 ++#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000 ++#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18 ++#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000 ++#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a ++#define PSX81_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1 ++#define PSX81_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0 ++#define PSX81_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2 ++#define PSX81_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1 ++#define PSX81_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4 ++#define PSX81_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2 ++#define PSX81_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8 ++#define PSX81_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3 ++#define PSX81_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10 ++#define PSX81_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4 ++#define PSX81_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20 ++#define PSX81_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5 ++#define PSX81_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40 ++#define PSX81_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6 ++#define PSX81_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80 ++#define PSX81_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7 ++#define PSX81_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100 ++#define PSX81_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8 ++#define PSX81_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200 ++#define PSX81_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9 ++#define PSX81_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400 ++#define PSX81_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa ++#define PSX81_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800 ++#define PSX81_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb ++#define PSX81_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000 ++#define PSX81_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc ++#define PSX81_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000 ++#define PSX81_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd ++#define PSX81_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000 ++#define PSX81_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe ++#define PSX81_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000 ++#define PSX81_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf ++#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000 ++#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10 ++#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000 ++#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11 ++#define PSX81_PIF0_LANE1_OVRD2__GANGMODE_1_MASK 0x7 ++#define PSX81_PIF0_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0 ++#define PSX81_PIF0_LANE1_OVRD2__FREQDIV_1_MASK 0x18 ++#define PSX81_PIF0_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3 ++#define PSX81_PIF0_LANE1_OVRD2__LINKSPEED_1_MASK 0x60 ++#define PSX81_PIF0_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5 ++#define PSX81_PIF0_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80 ++#define PSX81_PIF0_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7 ++#define PSX81_PIF0_LANE1_OVRD2__TXPWR_1_MASK 0x700 ++#define PSX81_PIF0_LANE1_OVRD2__TXPWR_1__SHIFT 0x8 ++#define PSX81_PIF0_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800 ++#define PSX81_PIF0_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb ++#define PSX81_PIF0_LANE1_OVRD2__RXPWR_1_MASK 0xe000 ++#define PSX81_PIF0_LANE1_OVRD2__RXPWR_1__SHIFT 0xd ++#define PSX81_PIF0_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000 ++#define PSX81_PIF0_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10 ++#define PSX81_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000 ++#define PSX81_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12 ++#define PSX81_PIF0_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000 ++#define PSX81_PIF0_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13 ++#define PSX81_PIF0_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000 ++#define PSX81_PIF0_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14 ++#define PSX81_PIF0_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000 ++#define PSX81_PIF0_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15 ++#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000 ++#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16 ++#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000 ++#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17 ++#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000 ++#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18 ++#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000 ++#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a ++#define PSX81_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1 ++#define PSX81_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0 ++#define PSX81_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2 ++#define PSX81_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1 ++#define PSX81_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4 ++#define PSX81_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2 ++#define PSX81_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8 ++#define PSX81_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3 ++#define PSX81_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10 ++#define PSX81_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4 ++#define PSX81_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20 ++#define PSX81_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5 ++#define PSX81_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40 ++#define PSX81_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6 ++#define PSX81_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80 ++#define PSX81_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7 ++#define PSX81_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100 ++#define PSX81_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8 ++#define PSX81_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200 ++#define PSX81_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9 ++#define PSX81_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400 ++#define PSX81_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa ++#define PSX81_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800 ++#define PSX81_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb ++#define PSX81_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000 ++#define PSX81_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc ++#define PSX81_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000 ++#define PSX81_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd ++#define PSX81_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000 ++#define PSX81_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe ++#define PSX81_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000 ++#define PSX81_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf ++#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000 ++#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10 ++#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000 ++#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11 ++#define PSX81_PIF0_LANE2_OVRD2__GANGMODE_2_MASK 0x7 ++#define PSX81_PIF0_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0 ++#define PSX81_PIF0_LANE2_OVRD2__FREQDIV_2_MASK 0x18 ++#define PSX81_PIF0_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3 ++#define PSX81_PIF0_LANE2_OVRD2__LINKSPEED_2_MASK 0x60 ++#define PSX81_PIF0_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5 ++#define PSX81_PIF0_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80 ++#define PSX81_PIF0_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7 ++#define PSX81_PIF0_LANE2_OVRD2__TXPWR_2_MASK 0x700 ++#define PSX81_PIF0_LANE2_OVRD2__TXPWR_2__SHIFT 0x8 ++#define PSX81_PIF0_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800 ++#define PSX81_PIF0_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb ++#define PSX81_PIF0_LANE2_OVRD2__RXPWR_2_MASK 0xe000 ++#define PSX81_PIF0_LANE2_OVRD2__RXPWR_2__SHIFT 0xd ++#define PSX81_PIF0_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000 ++#define PSX81_PIF0_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10 ++#define PSX81_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000 ++#define PSX81_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12 ++#define PSX81_PIF0_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000 ++#define PSX81_PIF0_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13 ++#define PSX81_PIF0_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000 ++#define PSX81_PIF0_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14 ++#define PSX81_PIF0_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000 ++#define PSX81_PIF0_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15 ++#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000 ++#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16 ++#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000 ++#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17 ++#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000 ++#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18 ++#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000 ++#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a ++#define PSX81_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1 ++#define PSX81_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0 ++#define PSX81_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2 ++#define PSX81_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1 ++#define PSX81_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4 ++#define PSX81_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2 ++#define PSX81_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8 ++#define PSX81_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3 ++#define PSX81_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10 ++#define PSX81_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4 ++#define PSX81_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20 ++#define PSX81_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5 ++#define PSX81_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40 ++#define PSX81_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6 ++#define PSX81_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80 ++#define PSX81_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7 ++#define PSX81_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100 ++#define PSX81_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8 ++#define PSX81_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200 ++#define PSX81_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9 ++#define PSX81_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400 ++#define PSX81_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa ++#define PSX81_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800 ++#define PSX81_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb ++#define PSX81_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000 ++#define PSX81_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc ++#define PSX81_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000 ++#define PSX81_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd ++#define PSX81_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000 ++#define PSX81_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe ++#define PSX81_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000 ++#define PSX81_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf ++#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000 ++#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10 ++#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000 ++#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11 ++#define PSX81_PIF0_LANE3_OVRD2__GANGMODE_3_MASK 0x7 ++#define PSX81_PIF0_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0 ++#define PSX81_PIF0_LANE3_OVRD2__FREQDIV_3_MASK 0x18 ++#define PSX81_PIF0_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3 ++#define PSX81_PIF0_LANE3_OVRD2__LINKSPEED_3_MASK 0x60 ++#define PSX81_PIF0_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5 ++#define PSX81_PIF0_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80 ++#define PSX81_PIF0_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7 ++#define PSX81_PIF0_LANE3_OVRD2__TXPWR_3_MASK 0x700 ++#define PSX81_PIF0_LANE3_OVRD2__TXPWR_3__SHIFT 0x8 ++#define PSX81_PIF0_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800 ++#define PSX81_PIF0_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb ++#define PSX81_PIF0_LANE3_OVRD2__RXPWR_3_MASK 0xe000 ++#define PSX81_PIF0_LANE3_OVRD2__RXPWR_3__SHIFT 0xd ++#define PSX81_PIF0_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000 ++#define PSX81_PIF0_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10 ++#define PSX81_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000 ++#define PSX81_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12 ++#define PSX81_PIF0_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000 ++#define PSX81_PIF0_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13 ++#define PSX81_PIF0_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000 ++#define PSX81_PIF0_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14 ++#define PSX81_PIF0_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000 ++#define PSX81_PIF0_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15 ++#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000 ++#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16 ++#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000 ++#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17 ++#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000 ++#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18 ++#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000 ++#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a ++#define PSX81_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1 ++#define PSX81_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0 ++#define PSX81_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2 ++#define PSX81_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1 ++#define PSX81_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4 ++#define PSX81_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2 ++#define PSX81_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8 ++#define PSX81_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3 ++#define PSX81_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10 ++#define PSX81_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4 ++#define PSX81_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20 ++#define PSX81_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5 ++#define PSX81_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40 ++#define PSX81_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6 ++#define PSX81_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80 ++#define PSX81_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7 ++#define PSX81_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100 ++#define PSX81_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8 ++#define PSX81_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200 ++#define PSX81_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9 ++#define PSX81_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400 ++#define PSX81_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa ++#define PSX81_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800 ++#define PSX81_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb ++#define PSX81_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000 ++#define PSX81_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc ++#define PSX81_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000 ++#define PSX81_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd ++#define PSX81_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000 ++#define PSX81_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe ++#define PSX81_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000 ++#define PSX81_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf ++#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000 ++#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10 ++#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000 ++#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11 ++#define PSX81_PIF0_LANE4_OVRD2__GANGMODE_4_MASK 0x7 ++#define PSX81_PIF0_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0 ++#define PSX81_PIF0_LANE4_OVRD2__FREQDIV_4_MASK 0x18 ++#define PSX81_PIF0_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3 ++#define PSX81_PIF0_LANE4_OVRD2__LINKSPEED_4_MASK 0x60 ++#define PSX81_PIF0_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5 ++#define PSX81_PIF0_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80 ++#define PSX81_PIF0_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7 ++#define PSX81_PIF0_LANE4_OVRD2__TXPWR_4_MASK 0x700 ++#define PSX81_PIF0_LANE4_OVRD2__TXPWR_4__SHIFT 0x8 ++#define PSX81_PIF0_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800 ++#define PSX81_PIF0_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb ++#define PSX81_PIF0_LANE4_OVRD2__RXPWR_4_MASK 0xe000 ++#define PSX81_PIF0_LANE4_OVRD2__RXPWR_4__SHIFT 0xd ++#define PSX81_PIF0_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000 ++#define PSX81_PIF0_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10 ++#define PSX81_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000 ++#define PSX81_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12 ++#define PSX81_PIF0_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000 ++#define PSX81_PIF0_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13 ++#define PSX81_PIF0_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000 ++#define PSX81_PIF0_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14 ++#define PSX81_PIF0_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000 ++#define PSX81_PIF0_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15 ++#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000 ++#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16 ++#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000 ++#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17 ++#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000 ++#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18 ++#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000 ++#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a ++#define PSX81_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1 ++#define PSX81_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0 ++#define PSX81_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2 ++#define PSX81_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1 ++#define PSX81_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4 ++#define PSX81_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2 ++#define PSX81_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8 ++#define PSX81_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3 ++#define PSX81_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10 ++#define PSX81_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4 ++#define PSX81_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20 ++#define PSX81_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5 ++#define PSX81_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40 ++#define PSX81_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6 ++#define PSX81_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80 ++#define PSX81_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7 ++#define PSX81_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100 ++#define PSX81_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8 ++#define PSX81_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200 ++#define PSX81_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9 ++#define PSX81_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400 ++#define PSX81_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa ++#define PSX81_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800 ++#define PSX81_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb ++#define PSX81_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000 ++#define PSX81_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc ++#define PSX81_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000 ++#define PSX81_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd ++#define PSX81_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000 ++#define PSX81_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe ++#define PSX81_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000 ++#define PSX81_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf ++#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000 ++#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10 ++#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000 ++#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11 ++#define PSX81_PIF0_LANE5_OVRD2__GANGMODE_5_MASK 0x7 ++#define PSX81_PIF0_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0 ++#define PSX81_PIF0_LANE5_OVRD2__FREQDIV_5_MASK 0x18 ++#define PSX81_PIF0_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3 ++#define PSX81_PIF0_LANE5_OVRD2__LINKSPEED_5_MASK 0x60 ++#define PSX81_PIF0_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5 ++#define PSX81_PIF0_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80 ++#define PSX81_PIF0_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7 ++#define PSX81_PIF0_LANE5_OVRD2__TXPWR_5_MASK 0x700 ++#define PSX81_PIF0_LANE5_OVRD2__TXPWR_5__SHIFT 0x8 ++#define PSX81_PIF0_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800 ++#define PSX81_PIF0_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb ++#define PSX81_PIF0_LANE5_OVRD2__RXPWR_5_MASK 0xe000 ++#define PSX81_PIF0_LANE5_OVRD2__RXPWR_5__SHIFT 0xd ++#define PSX81_PIF0_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000 ++#define PSX81_PIF0_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10 ++#define PSX81_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000 ++#define PSX81_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12 ++#define PSX81_PIF0_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000 ++#define PSX81_PIF0_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13 ++#define PSX81_PIF0_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000 ++#define PSX81_PIF0_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14 ++#define PSX81_PIF0_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000 ++#define PSX81_PIF0_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15 ++#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000 ++#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16 ++#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000 ++#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17 ++#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000 ++#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18 ++#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000 ++#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a ++#define PSX81_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1 ++#define PSX81_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0 ++#define PSX81_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2 ++#define PSX81_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1 ++#define PSX81_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4 ++#define PSX81_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2 ++#define PSX81_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8 ++#define PSX81_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3 ++#define PSX81_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10 ++#define PSX81_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4 ++#define PSX81_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20 ++#define PSX81_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5 ++#define PSX81_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40 ++#define PSX81_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6 ++#define PSX81_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80 ++#define PSX81_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7 ++#define PSX81_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100 ++#define PSX81_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8 ++#define PSX81_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200 ++#define PSX81_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9 ++#define PSX81_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400 ++#define PSX81_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa ++#define PSX81_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800 ++#define PSX81_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb ++#define PSX81_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000 ++#define PSX81_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc ++#define PSX81_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000 ++#define PSX81_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd ++#define PSX81_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000 ++#define PSX81_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe ++#define PSX81_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000 ++#define PSX81_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf ++#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000 ++#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10 ++#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000 ++#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11 ++#define PSX81_PIF0_LANE6_OVRD2__GANGMODE_6_MASK 0x7 ++#define PSX81_PIF0_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0 ++#define PSX81_PIF0_LANE6_OVRD2__FREQDIV_6_MASK 0x18 ++#define PSX81_PIF0_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3 ++#define PSX81_PIF0_LANE6_OVRD2__LINKSPEED_6_MASK 0x60 ++#define PSX81_PIF0_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5 ++#define PSX81_PIF0_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80 ++#define PSX81_PIF0_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7 ++#define PSX81_PIF0_LANE6_OVRD2__TXPWR_6_MASK 0x700 ++#define PSX81_PIF0_LANE6_OVRD2__TXPWR_6__SHIFT 0x8 ++#define PSX81_PIF0_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800 ++#define PSX81_PIF0_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb ++#define PSX81_PIF0_LANE6_OVRD2__RXPWR_6_MASK 0xe000 ++#define PSX81_PIF0_LANE6_OVRD2__RXPWR_6__SHIFT 0xd ++#define PSX81_PIF0_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000 ++#define PSX81_PIF0_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10 ++#define PSX81_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000 ++#define PSX81_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12 ++#define PSX81_PIF0_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000 ++#define PSX81_PIF0_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13 ++#define PSX81_PIF0_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000 ++#define PSX81_PIF0_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14 ++#define PSX81_PIF0_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000 ++#define PSX81_PIF0_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15 ++#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000 ++#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16 ++#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000 ++#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17 ++#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000 ++#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18 ++#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000 ++#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a ++#define PSX81_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1 ++#define PSX81_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0 ++#define PSX81_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2 ++#define PSX81_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1 ++#define PSX81_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4 ++#define PSX81_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2 ++#define PSX81_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8 ++#define PSX81_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3 ++#define PSX81_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10 ++#define PSX81_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4 ++#define PSX81_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20 ++#define PSX81_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5 ++#define PSX81_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40 ++#define PSX81_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6 ++#define PSX81_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80 ++#define PSX81_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7 ++#define PSX81_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100 ++#define PSX81_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8 ++#define PSX81_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200 ++#define PSX81_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9 ++#define PSX81_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400 ++#define PSX81_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa ++#define PSX81_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800 ++#define PSX81_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb ++#define PSX81_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000 ++#define PSX81_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc ++#define PSX81_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000 ++#define PSX81_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd ++#define PSX81_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000 ++#define PSX81_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe ++#define PSX81_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000 ++#define PSX81_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf ++#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000 ++#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10 ++#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000 ++#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11 ++#define PSX81_PIF0_LANE7_OVRD2__GANGMODE_7_MASK 0x7 ++#define PSX81_PIF0_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0 ++#define PSX81_PIF0_LANE7_OVRD2__FREQDIV_7_MASK 0x18 ++#define PSX81_PIF0_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3 ++#define PSX81_PIF0_LANE7_OVRD2__LINKSPEED_7_MASK 0x60 ++#define PSX81_PIF0_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5 ++#define PSX81_PIF0_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80 ++#define PSX81_PIF0_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7 ++#define PSX81_PIF0_LANE7_OVRD2__TXPWR_7_MASK 0x700 ++#define PSX81_PIF0_LANE7_OVRD2__TXPWR_7__SHIFT 0x8 ++#define PSX81_PIF0_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800 ++#define PSX81_PIF0_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb ++#define PSX81_PIF0_LANE7_OVRD2__RXPWR_7_MASK 0xe000 ++#define PSX81_PIF0_LANE7_OVRD2__RXPWR_7__SHIFT 0xd ++#define PSX81_PIF0_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000 ++#define PSX81_PIF0_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10 ++#define PSX81_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000 ++#define PSX81_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12 ++#define PSX81_PIF0_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000 ++#define PSX81_PIF0_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13 ++#define PSX81_PIF0_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000 ++#define PSX81_PIF0_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14 ++#define PSX81_PIF0_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000 ++#define PSX81_PIF0_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15 ++#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000 ++#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16 ++#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000 ++#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17 ++#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000 ++#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18 ++#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000 ++#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a ++ ++#endif /* BIF_5_1_SH_MASK_H */ +-- +cgit v0.10.2 + |