diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-MCE-decoding-for-F15h-M60h.patch')
| -rw-r--r-- | meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-MCE-decoding-for-F15h-M60h.patch | 121 |
1 files changed, 121 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-MCE-decoding-for-F15h-M60h.patch b/meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-MCE-decoding-for-F15h-M60h.patch new file mode 100644 index 00000000..dc25affe --- /dev/null +++ b/meta-amdfalconx86/recipes-kernel/linux/files/0003-yocto-amd-MCE-decoding-for-F15h-M60h.patch @@ -0,0 +1,121 @@ +EDAC, MCE, AMD: Add MCE decoding for F15h M60h +Add decoding logic for new Fam15h model 60h. + +Tested using mce_amd_inj module and works fine. + +Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> +Signed-off-by: Borislav Petkov <bp@suse.de> +Signed-off-by: Sanjay Mehta <sanju.mehta@amd.com> +diff -Naur a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c +--- a/drivers/edac/mce_amd.c 2015-03-25 14:39:54.692737985 +0530 ++++ b/drivers/edac/mce_amd.c 2015-03-25 14:43:37.872742361 +0530 +@@ -79,7 +79,8 @@ + "uop queue", + "insn buffer", + "predecode buffer", +- "fetch address FIFO" ++ "fetch address FIFO", ++ "dispatch uop queue" + }; + + static const char * const f15h_mc2_mce_desc[] = { +@@ -268,6 +269,11 @@ + pr_cont("System Read Data Error.\n"); + else + pr_cont(" Internal error condition type %d.\n", xec); ++ } else if (INT_ERROR(ec)) { ++ if (xec <= 0x1f) ++ pr_cont("Hardware Assert.\n"); ++ else ++ ret = false; + } else + ret = false; + +@@ -374,7 +380,7 @@ + pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]); + break; + +- case 0x11 ... 0x14: ++ case 0x11 ... 0x15: + pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]); + break; + +@@ -398,10 +404,21 @@ + bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58))); + + pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read")); ++ } else if (INT_ERROR(ec)) { ++ if (xec <= 0x3f) ++ pr_cont("Hardware Assert.\n"); ++ else ++ goto wrong_mc1_mce; + } else if (fam_ops->mc1_mce(ec, xec)) + ; + else +- pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n"); ++ goto wrong_mc1_mce; ++ ++ return; ++ ++wrong_mc1_mce: ++ pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n"); ++ + } + + static bool k8_mc2_mce(u16 ec, u8 xec) +@@ -469,6 +486,12 @@ + default: + ret = false; + } ++ ++ } else if (INT_ERROR(ec)) { ++ if (xec <= 0x3f) ++ pr_cont("Hardware Assert.\n"); ++ else ++ ret = false; + } + + return ret; +@@ -616,6 +639,7 @@ + static void decode_mc5_mce(struct mce *m) + { + struct cpuinfo_x86 *c = &boot_cpu_data; ++ u16 ec = EC(m->status); + u8 xec = XEC(m->status, xec_mask); + + if (c->x86 == 0xf || c->x86 == 0x11) +@@ -623,6 +647,14 @@ + + pr_emerg(HW_ERR "MC5 Error: "); + ++ if (INT_ERROR(ec)) { ++ if (xec <= 0x1f) { ++ pr_cont("Hardware Assert.\n"); ++ return; ++ } else ++ goto wrong_mc5_mce; ++ } ++ + if (xec == 0x0 || xec == 0xc) + pr_cont("%s.\n", mc5_mce_desc[xec]); + else if (xec <= 0xd) +@@ -643,6 +675,10 @@ + pr_emerg(HW_ERR "MC6 Error: "); + + switch (xec) { ++ case 0x0: ++ pr_cont("Hardware Assertion"); ++ break; ++ + case 0x1: + pr_cont("Free List"); + break; +@@ -858,7 +894,7 @@ + break; + + case 0x15: +- xec_mask = 0x1f; ++ xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f; + fam_ops->mc0_mce = f15h_mc0_mce; + fam_ops->mc1_mce = f15h_mc1_mce; + fam_ops->mc2_mce = f15h_mc2_mce; |