diff options
Diffstat (limited to 'meta-amdfalconx86/recipes-graphics/mesa/mesa/0030-radeonsi-properly-set-the-raster_config-for-KV.patch')
-rw-r--r-- | meta-amdfalconx86/recipes-graphics/mesa/mesa/0030-radeonsi-properly-set-the-raster_config-for-KV.patch | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/meta-amdfalconx86/recipes-graphics/mesa/mesa/0030-radeonsi-properly-set-the-raster_config-for-KV.patch b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0030-radeonsi-properly-set-the-raster_config-for-KV.patch new file mode 100644 index 00000000..9ed40181 --- /dev/null +++ b/meta-amdfalconx86/recipes-graphics/mesa/mesa/0030-radeonsi-properly-set-the-raster_config-for-KV.patch @@ -0,0 +1,53 @@ +From 7f720fc229da2b75b60ddc9824f19ebd1acc42df Mon Sep 17 00:00:00 2001 +From: Arindam Nath <arindam.nath@amd.com> +Date: Thu, 11 Jun 2015 14:07:38 +0530 +Subject: [PATCH 1/2] radeonsi: properly set the raster_config for KV + +This enables the second RB on asics that support it which +should boost performance. + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Cc: mesa-stable@lists.freedesktop.org +Signed-off-by: Arindam Nath <arindam.nath@amd.com> +--- + src/gallium/drivers/radeonsi/si_state.c | 14 +++++++++----- + 1 file changed, 9 insertions(+), 5 deletions(-) + +diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c +index b35fbd5..b3e77ec 100644 +--- a/src/gallium/drivers/radeonsi/si_state.c ++++ b/src/gallium/drivers/radeonsi/si_state.c +@@ -3040,6 +3040,7 @@ si_write_harvested_raster_configs(struct si_context *sctx, + + void si_init_config(struct si_context *sctx) + { ++ unsigned num_rb = sctx->screen->b.info.r600_num_backends; + struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); + + if (pm4 == NULL) +@@ -3097,14 +3098,17 @@ void si_init_config(struct si_context *sctx) + si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000); + break; + case CHIP_KAVERI: +- /* XXX todo */ ++ if (num_rb > 1) ++ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000002); ++ else ++ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); ++ si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000); ++ break; + case CHIP_KABINI: +- /* XXX todo */ + case CHIP_MULLINS: +- /* XXX todo */ + default: +- si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0); +- si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0); ++ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); ++ si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000); + break; + } + } else { +-- +1.9.1 + |