diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4617-drm-amdgpu-fix-GFX10-missing-CSIB-set-v3.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4617-drm-amdgpu-fix-GFX10-missing-CSIB-set-v3.patch | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4617-drm-amdgpu-fix-GFX10-missing-CSIB-set-v3.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4617-drm-amdgpu-fix-GFX10-missing-CSIB-set-v3.patch new file mode 100644 index 00000000..785a0841 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4617-drm-amdgpu-fix-GFX10-missing-CSIB-set-v3.patch @@ -0,0 +1,89 @@ +From 34d7f239a288a1195c3b802a5851f493c6dce4e4 Mon Sep 17 00:00:00 2001 +From: Monk Liu <Monk.Liu@amd.com> +Date: Tue, 26 Nov 2019 19:33:38 +0800 +Subject: [PATCH 4617/4736] drm/amdgpu: fix GFX10 missing CSIB set(v3) + +still need to init csb even for SRIOV + +v2: +drop init_pg() for gfx10 at all since +PG and GFX off feature will be fully controled +by RLC and SMU fw for gfx10 + +v3: +drop the flush_gpu_tlb lines since we consider +it is only usefull in emulation + +Signed-off-by: Monk Liu <Monk.Liu@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 33 ++++---------------------- + 1 file changed, 5 insertions(+), 28 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +index fd7ae21eb540..ed630d37c32c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -1769,22 +1769,6 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev) + return 0; + } + +-static int gfx_v10_0_init_pg(struct amdgpu_device *adev) +-{ +- int i; +- int r; +- +- r = gfx_v10_0_init_csb(adev); +- if (r) +- return r; +- +- for (i = 0; i < adev->num_vmhubs; i++) +- amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); +- +- /* TODO: init power gating */ +- return 0; +-} +- + void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) + { + u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); +@@ -1877,21 +1861,16 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) + { + int r; + +- if (amdgpu_sriov_vf(adev)) +- return 0; +- + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { +- r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); +- if (r) +- return r; + +- r = gfx_v10_0_init_pg(adev); ++ r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); + if (r) + return r; + +- /* enable RLC SRM */ +- gfx_v10_0_rlc_enable_srm(adev); ++ gfx_v10_0_init_csb(adev); + ++ if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ ++ gfx_v10_0_rlc_enable_srm(adev); + } else { + adev->gfx.rlc.funcs->stop(adev); + +@@ -1913,9 +1892,7 @@ static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) + return r; + } + +- r = gfx_v10_0_init_pg(adev); +- if (r) +- return r; ++ gfx_v10_0_init_csb(adev); + + adev->gfx.rlc.funcs->start(adev); + +-- +2.17.1 + |