diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4560-drm-amdgpu-refine-query-function-of-mmhub-EDC-counte.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4560-drm-amdgpu-refine-query-function-of-mmhub-EDC-counte.patch | 769 |
1 files changed, 769 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4560-drm-amdgpu-refine-query-function-of-mmhub-EDC-counte.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4560-drm-amdgpu-refine-query-function-of-mmhub-EDC-counte.patch new file mode 100644 index 00000000..6fec2621 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4560-drm-amdgpu-refine-query-function-of-mmhub-EDC-counte.patch @@ -0,0 +1,769 @@ +From 2a45b43ad84392eafa5b6b974534ad0358e6ca88 Mon Sep 17 00:00:00 2001 +From: Dennis Li <Dennis.Li@amd.com> +Date: Tue, 19 Nov 2019 16:02:28 +0800 +Subject: [PATCH 4560/4736] drm/amdgpu: refine query function of mmhub EDC + counter in vg20 + +Add codes to print the detail EDC info for the subblock of mmhub + +v2: Move the EDC_CNT registers' defintion from mmhub_9_4 header +files to mmhub_1_0 ones. Add mmhub_v1_0_ prefix for the local +static variable and function. + +Change-Id: I1d5b3df38caa8f0b437c96b78091662aaeaf264b +Signed-off-by: Dennis Li <Dennis.Li@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Reviewed-by: Tao Zhou <tao.zhou1@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 232 ++++++++++++---- + .../include/asic_reg/mmhub/mmhub_1_0_offset.h | 16 ++ + .../asic_reg/mmhub/mmhub_1_0_sh_mask.h | 122 +++++++++ + .../asic_reg/mmhub/mmhub_9_4_0_offset.h | 53 ---- + .../asic_reg/mmhub/mmhub_9_4_0_sh_mask.h | 257 ------------------ + 5 files changed, 318 insertions(+), 362 deletions(-) + delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h + delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h + +diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +index 41c340bfc953..c0041d74df09 100644 +--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +@@ -27,17 +27,13 @@ + #include "mmhub/mmhub_1_0_offset.h" + #include "mmhub/mmhub_1_0_sh_mask.h" + #include "mmhub/mmhub_1_0_default.h" +-#include "mmhub/mmhub_9_4_0_offset.h" + #include "vega10_enum.h" +- ++#include "soc15.h" + #include "soc15_common.h" + + #define mmDAGB0_CNTL_MISC2_RV 0x008f + #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0 + +-#define EA_EDC_CNT_MASK 0x3 +-#define EA_EDC_CNT_SHIFT 0x2 +- + u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) + { + u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); +@@ -562,59 +558,191 @@ void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) + *flags |= AMD_CG_SUPPORT_MC_LS; + } + ++static const struct soc15_ras_field_entry mmhub_v1_0_ras_fields[] = { ++ { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT), ++ }, ++ { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT), ++ }, ++ { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT), ++ }, ++ { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT), ++ }, ++ { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT), ++ }, ++ { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT), ++ 0, 0, ++ }, ++ { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT), ++ 0, 0, ++ }, ++ { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT), ++ 0, 0, ++ }, ++ { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT), ++ 0, 0, ++ }, ++ { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT), ++ 0, 0, ++ }, ++ { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT), ++ }, ++ { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT), ++ }, ++ { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT), ++ }, ++ { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT), ++ 0, 0, ++ }, ++ { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), ++ SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT), ++ 0, 0, ++ }, ++ { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT), ++ }, ++ { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT), ++ }, ++ { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT), ++ }, ++ { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT), ++ }, ++ { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT), ++ }, ++ { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT), ++ 0, 0, ++ }, ++ { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT), ++ 0, 0, ++ }, ++ { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT), ++ 0, 0, ++ }, ++ { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT), ++ 0, 0, ++ }, ++ { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT), ++ 0, 0, ++ }, ++ { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT), ++ }, ++ { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT), ++ }, ++ { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT), ++ }, ++ { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT), ++ 0, 0, ++ }, ++ { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), ++ SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT), ++ 0, 0, ++ } ++}; ++ ++static const struct soc15_reg_entry mmhub_v1_0_edc_cnt_regs[] = { ++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 0, 0, 0}, ++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 0, 0, 0}, ++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 0, 0, 0}, ++ { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 0, 0, 0}, ++}; ++ ++static int mmhub_v1_0_get_ras_error_count(const struct soc15_reg_entry *reg, ++ uint32_t value, uint32_t *sec_count, uint32_t *ded_count) ++{ ++ uint32_t i; ++ uint32_t sec_cnt, ded_cnt; ++ ++ for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_ras_fields); i++) { ++ if(mmhub_v1_0_ras_fields[i].reg_offset != reg->reg_offset) ++ continue; ++ ++ sec_cnt = (value & ++ mmhub_v1_0_ras_fields[i].sec_count_mask) >> ++ mmhub_v1_0_ras_fields[i].sec_count_shift; ++ if (sec_cnt) { ++ DRM_INFO("MMHUB SubBlock %s, SEC %d\n", ++ mmhub_v1_0_ras_fields[i].name, ++ sec_cnt); ++ *sec_count += sec_cnt; ++ } ++ ++ ded_cnt = (value & ++ mmhub_v1_0_ras_fields[i].ded_count_mask) >> ++ mmhub_v1_0_ras_fields[i].ded_count_shift; ++ if (ded_cnt) { ++ DRM_INFO("MMHUB SubBlock %s, DED %d\n", ++ mmhub_v1_0_ras_fields[i].name, ++ ded_cnt); ++ *ded_count += ded_cnt; ++ } ++ } ++ ++ return 0; ++} ++ + static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev, + void *ras_error_status) + { +- int i; +- uint32_t ea0_edc_cnt, ea0_edc_cnt2; +- uint32_t ea1_edc_cnt, ea1_edc_cnt2; + struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; +- +- /* EDC CNT will be cleared automatically after read */ +- ea0_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT_VG20); +- ea0_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20); +- ea1_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT_VG20); +- ea1_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20); +- +- /* error count of each error type is recorded by 2 bits, +- * ce and ue count in EDC_CNT +- */ +- for (i = 0; i < 5; i++) { +- err_data->ce_count += (ea0_edc_cnt & EA_EDC_CNT_MASK); +- err_data->ce_count += (ea1_edc_cnt & EA_EDC_CNT_MASK); +- ea0_edc_cnt >>= EA_EDC_CNT_SHIFT; +- ea1_edc_cnt >>= EA_EDC_CNT_SHIFT; +- err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK); +- err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK); +- ea0_edc_cnt >>= EA_EDC_CNT_SHIFT; +- ea1_edc_cnt >>= EA_EDC_CNT_SHIFT; +- } +- /* successive ue count in EDC_CNT */ +- for (i = 0; i < 5; i++) { +- err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK); +- err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK); +- ea0_edc_cnt >>= EA_EDC_CNT_SHIFT; +- ea1_edc_cnt >>= EA_EDC_CNT_SHIFT; ++ uint32_t sec_count = 0, ded_count = 0; ++ uint32_t i; ++ uint32_t reg_value; ++ ++ err_data->ue_count = 0; ++ err_data->ce_count = 0; ++ ++ for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++) { ++ reg_value = ++ RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i])); ++ if (reg_value) ++ mmhub_v1_0_get_ras_error_count(&mmhub_v1_0_edc_cnt_regs[i], ++ reg_value, &sec_count, &ded_count); + } + +- /* ce and ue count in EDC_CNT2 */ +- for (i = 0; i < 3; i++) { +- err_data->ce_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK); +- err_data->ce_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK); +- ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT; +- ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT; +- err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK); +- err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK); +- ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT; +- ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT; +- } +- /* successive ue count in EDC_CNT2 */ +- for (i = 0; i < 6; i++) { +- err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK); +- err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK); +- ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT; +- ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT; +- } ++ err_data->ce_count += sec_count; ++ err_data->ue_count += ded_count; + } + + const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = { +diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h +index 352ffae7a7ca..2c3ce243861a 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h +@@ -1964,4 +1964,20 @@ + #define mmATC_L2_PERFCOUNTER_RSLT_CNTL 0x084a + #define mmATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 + ++/* MMEA */ ++#define mmMMEA0_EDC_CNT_VG20 0x0206 ++#define mmMMEA0_EDC_CNT_VG20_BASE_IDX 0 ++#define mmMMEA0_EDC_CNT2_VG20 0x0207 ++#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX 0 ++#define mmMMEA1_EDC_CNT_VG20 0x0346 ++#define mmMMEA1_EDC_CNT_VG20_BASE_IDX 0 ++#define mmMMEA1_EDC_CNT2_VG20 0x0347 ++#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX 0 ++ ++// addressBlock: mmhub_utcl2_vmsharedpfdec ++// base address: 0x6a040 ++#define mmMC_VM_XGMI_LFB_CNTL 0x0823 ++#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 ++#define mmMC_VM_XGMI_LFB_SIZE 0x0824 ++#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 + #endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h +index 34278ef2aa1b..198f5f93ed1a 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h +@@ -10124,4 +10124,126 @@ + #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L + #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + ++//MMEA0_EDC_CNT ++#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 ++#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 ++#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 ++#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 ++#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 ++#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa ++#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc ++#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT__SHIFT 0xe ++#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 ++#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 ++#define MMEA0_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 ++#define MMEA0_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 ++#define MMEA0_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 ++#define MMEA0_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a ++#define MMEA0_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c ++#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L ++#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL ++#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L ++#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L ++#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L ++#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L ++#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L ++#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L ++#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L ++#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L ++#define MMEA0_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L ++#define MMEA0_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L ++#define MMEA0_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L ++#define MMEA0_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L ++#define MMEA0_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L ++//MMEA0_EDC_CNT2 ++#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 ++#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 ++#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 ++#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 ++#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 ++#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa ++#define MMEA0_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc ++#define MMEA0_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe ++#define MMEA0_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT__SHIFT 0x10 ++#define MMEA0_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT__SHIFT 0x12 ++#define MMEA0_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT__SHIFT 0x14 ++#define MMEA0_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT__SHIFT 0x16 ++#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L ++#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL ++#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L ++#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L ++#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L ++#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L ++#define MMEA0_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L ++#define MMEA0_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L ++#define MMEA0_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT_MASK 0x00030000L ++#define MMEA0_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L ++#define MMEA0_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT_MASK 0x00300000L ++#define MMEA0_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L ++//MMEA1_EDC_CNT ++#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 ++#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 ++#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 ++#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 ++#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 ++#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa ++#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc ++#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT__SHIFT 0xe ++#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 ++#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 ++#define MMEA1_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 ++#define MMEA1_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 ++#define MMEA1_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 ++#define MMEA1_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a ++#define MMEA1_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c ++#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L ++#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL ++#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L ++#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L ++#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L ++#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L ++#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L ++#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L ++#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L ++#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L ++#define MMEA1_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L ++#define MMEA1_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L ++#define MMEA1_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L ++#define MMEA1_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L ++#define MMEA1_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L ++//MMEA1_EDC_CNT2 ++#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 ++#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 ++#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 ++#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 ++#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 ++#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa ++#define MMEA1_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc ++#define MMEA1_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe ++#define MMEA1_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT__SHIFT 0x10 ++#define MMEA1_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT__SHIFT 0x12 ++#define MMEA1_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT__SHIFT 0x14 ++#define MMEA1_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT__SHIFT 0x16 ++#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L ++#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL ++#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L ++#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L ++#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L ++#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L ++#define MMEA1_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L ++#define MMEA1_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L ++#define MMEA1_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT_MASK 0x00030000L ++#define MMEA1_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L ++#define MMEA1_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT_MASK 0x00300000L ++#define MMEA1_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L ++ ++// addressBlock: mmhub_utcl2_vmsharedpfdec ++//MC_VM_XGMI_LFB_CNTL ++#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 ++#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 ++#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L ++#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000070L ++//MC_VM_XGMI_LFB_SIZE ++#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 ++#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL + #endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h +deleted file mode 100644 +index f2ae3a58949e..000000000000 +--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h ++++ /dev/null +@@ -1,53 +0,0 @@ +-/* +- * Copyright (C) 2018 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included +- * in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- */ +-#ifndef _mmhub_9_4_0_OFFSET_HEADER +-#define _mmhub_9_4_0_OFFSET_HEADER +- +-/* MMEA */ +-#define mmMMEA0_SDP_ARB_FINAL_VG20 0x01ee +-#define mmMMEA0_SDP_ARB_FINAL_VG20_BASE_IDX 0 +-#define mmMMEA0_EDC_CNT_VG20 0x0206 +-#define mmMMEA0_EDC_CNT_VG20_BASE_IDX 0 +-#define mmMMEA0_EDC_CNT2_VG20 0x0207 +-#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX 0 +-#define mmMMEA0_EDC_MODE_VG20 0x0210 +-#define mmMMEA0_EDC_MODE_VG20_BASE_IDX 0 +-#define mmMMEA0_ERR_STATUS_VG20 0x0211 +-#define mmMMEA0_ERR_STATUS_VG20_BASE_IDX 0 +-#define mmMMEA1_SDP_ARB_FINAL_VG20 0x032e +-#define mmMMEA1_SDP_ARB_FINAL_VG20_BASE_IDX 0 +-#define mmMMEA1_EDC_CNT_VG20 0x0346 +-#define mmMMEA1_EDC_CNT_VG20_BASE_IDX 0 +-#define mmMMEA1_EDC_CNT2_VG20 0x0347 +-#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX 0 +-#define mmMMEA1_EDC_MODE_VG20 0x0350 +-#define mmMMEA1_EDC_MODE_VG20_BASE_IDX 0 +-#define mmMMEA1_ERR_STATUS_VG20 0x0351 +-#define mmMMEA1_ERR_STATUS_VG20_BASE_IDX 0 +- +-// addressBlock: mmhub_utcl2_vmsharedpfdec +-// base address: 0x6a040 +-#define mmMC_VM_XGMI_LFB_CNTL 0x0823 +-#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0 +-#define mmMC_VM_XGMI_LFB_SIZE 0x0824 +-#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0 +- +-#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h +deleted file mode 100644 +index c24259ed12a1..000000000000 +--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h ++++ /dev/null +@@ -1,257 +0,0 @@ +-/* +- * Copyright (C) 2018 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included +- * in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- */ +-#ifndef _mmhub_9_4_0_SH_MASK_HEADER +-#define _mmhub_9_4_0_SH_MASK_HEADER +- +-//MMEA0_SDP_ARB_FINAL +-#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +-#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +-#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +-#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +-#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +-#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +-#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +-#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +-#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +-#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +-#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +-#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +-#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +-//MMEA0_EDC_CNT +-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +-#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +-#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +-#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +-#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +-#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +-#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +-#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +-#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +-#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +-#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +-#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +-#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +-#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +-#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +-#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +-#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +-#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +-#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +-#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +-#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +-#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +-//MMEA0_EDC_CNT2 +-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +-#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +-#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +-#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 +-#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 +-#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 +-#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 +-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +-#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +-#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +-#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +-#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +-#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +-#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L +-#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L +-#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L +-#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L +-//MMEA0_EDC_MODE +-#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +-#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 +-#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 +-#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d +-#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f +-#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +-#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L +-#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L +-#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L +-#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L +-//MMEA0_ERR_STATUS +-#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +-#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +-#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +-#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +-#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd +-#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +-#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +-#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +-#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +-#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +-#define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +-//MMEA1_SDP_ARB_FINAL +-#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +-#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +-#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +-#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +-#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +-#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +-#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +-#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +-#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +-#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +-#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +-#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +-#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +-//MMEA1_EDC_CNT +-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +-#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +-#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +-#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +-#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +-#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +-#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +-#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +-#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +-#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +-#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +-#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +-#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +-#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +-#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +-#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +-#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +-#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +-#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +-#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +-#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +-#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +-//MMEA1_EDC_CNT2 +-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +-#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +-#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +-#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 +-#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 +-#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 +-#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 +-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +-#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +-#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +-#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +-#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +-#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +-#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L +-#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L +-#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L +-#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L +-//MMEA1_EDC_MODE +-#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +-#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 +-#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 +-#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d +-#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f +-#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +-#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L +-#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L +-#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L +-#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L +-//MMEA1_ERR_STATUS +-#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +-#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +-#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +-#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +-#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd +-#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +-#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +-#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +-#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +-#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +-#define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +- +-// addressBlock: mmhub_utcl2_vmsharedpfdec +-//MC_VM_XGMI_LFB_CNTL +-#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 +-#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 +-#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L +-#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000070L +-//MC_VM_XGMI_LFB_SIZE +-#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 +-#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL +- +-#endif +-- +2.17.1 + |