diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4556-drm-amdgpu-gfx10-explicitly-wait-for-cp-idle-after-h.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4556-drm-amdgpu-gfx10-explicitly-wait-for-cp-idle-after-h.patch | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4556-drm-amdgpu-gfx10-explicitly-wait-for-cp-idle-after-h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4556-drm-amdgpu-gfx10-explicitly-wait-for-cp-idle-after-h.patch new file mode 100644 index 00000000..55f28921 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4556-drm-amdgpu-gfx10-explicitly-wait-for-cp-idle-after-h.patch @@ -0,0 +1,50 @@ +From 38eb1b45802cde565f6d4b708cb5e00bb7529119 Mon Sep 17 00:00:00 2001 +From: Xiaojie Yuan <xiaojie.yuan@amd.com> +Date: Thu, 14 Nov 2019 16:56:08 +0800 +Subject: [PATCH 4556/4736] drm/amdgpu/gfx10: explicitly wait for cp idle after + halt/unhalt + +50us is not enough to wait for cp ready after gpu reset on some navi asics. + +Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> +Suggested-by: Jack Xiao <Jack.Xiao@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +index 678ad1b26535..5403567683b7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -2404,7 +2404,7 @@ static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) + return 0; + } + +-static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) ++static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) + { + int i; + u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); +@@ -2417,7 +2417,17 @@ static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) + adev->gfx.gfx_ring[i].sched.ready = false; + } + WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); +- udelay(50); ++ ++ for (i = 0; i < adev->usec_timeout; i++) { ++ if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) ++ break; ++ udelay(1); ++ } ++ ++ if (i >= adev->usec_timeout) ++ DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); ++ ++ return 0; + } + + static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) +-- +2.17.1 + |