diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4469-drm-amd-powerplay-avoid-DPM-reenable-process-on-Navi.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4469-drm-amd-powerplay-avoid-DPM-reenable-process-on-Navi.patch | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4469-drm-amd-powerplay-avoid-DPM-reenable-process-on-Navi.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4469-drm-amd-powerplay-avoid-DPM-reenable-process-on-Navi.patch new file mode 100644 index 00000000..9e104fd6 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/4469-drm-amd-powerplay-avoid-DPM-reenable-process-on-Navi.patch @@ -0,0 +1,90 @@ +From a1a63a29b5717b05ea6b8e9a9a3982adfade96d4 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Mon, 11 Nov 2019 17:15:02 +0800 +Subject: [PATCH 4469/4736] drm/amd/powerplay: avoid DPM reenable process on + Navi1x ASICs V2 + +Otherwise, without RLC reinitialization, the DPM reenablement +will fail. That affects the custom pptable uploading. + +V2: setting/clearing uploading_custom_pp_table in + smu_sys_set_pp_table() + +Change-Id: I6fe2ed5ce23f2a5b66f371c0b6d1f924837e5af6 +Reported-by: Matt Coffin <mcoffin13@gmail.com> +Signed-off-by: Evan Quan <evan.quan@amd.com> +Tested-by: Matt Coffin <mcoffin13@gmail.com> +Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> +--- + drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 31 ++++++++++++++++--- + .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 + + 2 files changed, 28 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +index d66db86836a1..9483f5ff64e7 100644 +--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +@@ -594,10 +594,18 @@ int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size) + smu_table->power_play_table = smu_table->hardcode_pptable; + smu_table->power_play_table_size = size; + ++ /* ++ * Special hw_fini action(for Navi1x, the DPMs disablement will be ++ * skipped) may be needed for custom pptable uploading. ++ */ ++ smu->uploading_custom_pp_table = true; ++ + ret = smu_reset(smu); + if (ret) + pr_info("smu reset failed, ret = %d\n", ret); + ++ smu->uploading_custom_pp_table = false; ++ + failed: + mutex_unlock(&smu->mutex); + return ret; +@@ -1302,10 +1310,25 @@ static int smu_hw_fini(void *handle) + return ret; + } + +- ret = smu_stop_dpms(smu); +- if (ret) { +- pr_warn("Fail to stop Dpms!\n"); +- return ret; ++ /* ++ * For custom pptable uploading, skip the DPM features ++ * disable process on Navi1x ASICs. ++ * - As the gfx related features are under control of ++ * RLC on those ASICs. RLC reinitialization will be ++ * needed to reenable them. That will cost much more ++ * efforts. ++ * ++ * - SMU firmware can handle the DPM reenablement ++ * properly. ++ */ ++ if (!smu->uploading_custom_pp_table || ++ !((adev->asic_type >= CHIP_NAVI10) && ++ (adev->asic_type <= CHIP_NAVI12))) { ++ ret = smu_stop_dpms(smu); ++ if (ret) { ++ pr_warn("Fail to stop Dpms!\n"); ++ return ret; ++ } + } + + kfree(table_context->driver_pptable); +diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +index cdd46cdaffb8..5bac7efcd6ee 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +@@ -391,6 +391,7 @@ struct smu_context + + uint32_t smc_if_version; + ++ bool uploading_custom_pp_table; + }; + + struct i2c_adapter; +-- +2.17.1 + |